5 2008 Semtech Corp. www.semtech.com
PROTECTION PRODUCTS
RClamp0504N
PIN Descriptions
Therefore, the voltage overshoot due to 1nH of series
inductance is:
V = LP diESD/dt = 1X10-9 (30 / 1X10-9) = 30V
Example:
Consider a VCC = 5V, a typical VF of 30V (at 30A) for the
steering diode and a series trace inductance of 10nH.
The clamping voltage seen by the protected IC for a
positive 8kV (30A) ESD pulse will be:
VC = 5V + 30V + (10nH X 30V/nH) = 335V
This does not take into account that the ESD current is
directed into the supply rail, potentially damaging any
components that are attached to that rail. Also note
that it is not uncommon for the VF of discrete diodes to
exceed the damage threshold of the protected IC. This
is due to the relatively small junction area of typical
discrete components. It is also possible that the
power dissipation capability of the discrete diode will
be exceeded, thus destroying the device.
The RailClamp is designed to overcome the inherent
disadvantages of using discrete signal diodes for ESD
suppression. The RailClamp’s integrated TVS diode
helps to mitigate the effects of parasitic inductance in
the power supply connection. During an ESD event,
the current will be directed through the integrated TVS
diode to ground. The maximum voltage seen by the
protected IC due to this path will be the clamping
voltage of the device.
Applications Information (continued)
Figure 2 - The Effects of Parasitic InductanceFigure 2 - The Effects of Parasitic Inductance
Figure 2 - The Effects of Parasitic InductanceFigure 2 - The Effects of Parasitic Inductance
Figure 2 - The Effects of Parasitic Inductance
When Using Discrete Components to ImplementWhen Using Discrete Components to Implement
When Using Discrete Components to ImplementWhen Using Discrete Components to Implement
When Using Discrete Components to Implement
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ETHERNET PROTECTION
Ethernet ICs are vulnerable to damage from electro-
static discharge (ESD), lightning, and cable discharge
events (CDE). The internal protection in the PHY chip,
if any, often is not enough due to the high energy of
these disturbances. The fatal discharge can occur
differentially across the transmit or receive line pair or
between any line and ground (common mode).
Common mode and differential mode protection
against ESD and CDE discharges can be achieved by
connecting the RClamp0504N on the PHY side of the
Ethernet circuit as shown in Figure 4. Pins 1, 3, 4, and
6 are connected to the transmit and receive line pairs.
Since there is no Vcc connection at the connector, pin
5 of the RClamp0504N should not be connected. Pin
2 is connected to ground. This connection should be
made directly to the ground plane. All path lengths
should be kept as short as possible to minimize para-
sitic inductance. This configuration can be used to
meet the ESD immunity requirements of IEC 61000-4-
2 and cable discharge events.