1
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
14-Bit, 125Msps/105Msps/
80Msps Low Power Dual ADCs
n Communications
n Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multi-Channel Data Acquisition
n Nondestructive Testing
n Two-Channel Simultaneously Sampling ADC
n 73.1dB SNR
n 90dB SFDR
n Low Power: 189mW/149mW/113mW Total
95mW/75mW/57mW per Channel
n Single 1.8V Supply
n CMOS, DDR CMOS, or DDR LVDS Outputs
n Selectable Input Ranges: 1VP-P to 2VP-P
n 750MHz Full Power Bandwidth S/H
n Optional Data Output Randomizer
n Optional Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Serial SPI Port for Configuration
n 64-Pin (9mm × 9mm) QFN Package
The LTC
®
2145-14/LTC2144-14/LTC2143-14 are 2-channel
simultaneous sampling 14-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 73.1dB SNR and
90dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.08psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.2LSBRMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
64k Point 2-Tone FFT, fIN = 69MHz,
70MHz, –1dBFS, 125Msps
CMOS,
DDR CMOS
OR DDR LVDS
OUTPUTS
1.8V
VDD
1.8V
OVDD
CLOCK
CONTROL
D1_13
D1_0
21454314 TA01a
CH 1
ANALOG
INPUT
OUTPUT
DRIVERS
t
t
t
GND OGND
S/H 14-BIT
ADC CORE
CH 2
ANALOG
INPUT
S/H 14-BIT
ADC CORE
D2_13
D2_0
t
t
t
125MHz
CLOCK FREQUENCY (MHz)
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
21454314 TA03b
010 20 30 40 50 60
LTC2145-14/
LTC2144-14/LTC2143-14
2
21454314fa
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (VDD, OVDD) ....................... –0.3V to 2V
Analog Input Voltage (AIN+, AIN–,
PAR/SER, SENSE) (Note 3) .......... –0.3V to (VDD + 0.2V)
Digital Input Voltage (ENC+, ENC–, CS,
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
(Notes 1, 2)
PIN CONFIGURATIONS
Digital Output Voltage ................–0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2145C, LTC2144C, LTC2143C............. 0°C to 70°C
LTC2145I, LTC2144I, LTC2143I ............–40°C to 85°C
Storage Temperature Range ...................–65°C to 150°C
FULL RATE CMOS OUTPUT MODE DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
UP PACKAGE
64-LEAD (9mm s 9mm) PLASTIC QFN
VDD 1
VCM1 2
GND 3
AIN1+ 4
AIN1– 5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
AIN2+ 12
AIN2– 13
GND 14
VCM2 15
VDD 16
48 D1_3
47 D1_2
46 D1_1
45 D1_0
44 DNC
43 DNC
42 OVDD
41 OGND
40 CLKOUT+
39 CLKOUT–
38 D2_13
37 D2_12
36 D2_11
35 D2_10
34 D2_9
33 D2_8
65
GND
64 VDD
63 SENSE
62 VREF
61 SDO
60 OF1
59 OF2
58 D1_13
57 D1_12
56 D1_11
55 D1_10
54 D1_9
53 D1_8
52 D1_7
51 D1_6
50 D1_5
49 D1_4
VDD 17
ENC+ 18
ENC– 19
CS 20
SCK 21
SDI 22
DNC 23
DNC 24
D2_0 25
D2_1 26
D2_2 27
D2_3 28
D2_4 29
D2_5 30
D2_6 31
D2_7 32
TJMAX = 150°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
TOP VIEW
UP PACKAGE
64-LEAD (9mm s 9mm) PLASTIC QFN
VDD 1
VCM1 2
GND 3
AIN1+ 4
AIN1– 5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
AIN2+ 12
AIN2– 13
GND 14
VCM2 15
VDD 16
48 D1_2_3
47 DNC
46 D1_0_1
45 DNC
44 DNC
43 DNC
42 OVDD
41 OGND
40 CLKOUT+
39 CLKOUT–
38 D2_12_13
37 DNC
36 D2_10_11
35 DNC
34 D2_8_9
33 DNC
65
GND
64 VDD
63 SENSE
62 VREF
61 SDO
60 OF2_1
59 DNC
58 D1_12_13
57 DNC
56 D1_10_11
55 DNC
54 D1_8_9
53 DNC
52 D1_6_7
51 DNC
50 D1_4_5
49 DNC
VDD 17
ENC+ 18
ENC– 19
CS 20
SCK 21
SDI 22
DNC 23
DNC 24
DNC 25
D2_0_1 26
DNC 27
D2_2_3 28
DNC 29
D2_4_5 30
DNC 31
D2_6_7 32
TJMAX = 150°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
3
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2145CUP-14#PBF LTC2145CUP-14#TRPBF LTC2145UP-14 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C
LTC2145IUP-14#PBF LTC2145IUP-14#TRPBF LTC2145UP-14 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C
LTC2144CUP-14#PBF LTC2144CUP-14#TRPBF LTC2144UP-14 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C
LTC2144IUP-14#PBF LTC2144IUP-14#TRPBF LTC2144UP-14 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C
LTC2143CUP-14#PBF LTC2143CUP-14#TRPBF LTC2143UP-14 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C
LTC2143IUP-14#PBF LTC2143IUP-14#TRPBF LTC2143UP-14 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
UP PACKAGE
64-LEAD (9mm s 9mm) PLASTIC QFN
VDD 1
VCM1 2
GND 3
AIN1+ 4
AIN1– 5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
AIN2+ 12
AIN2– 13
GND 14
VCM2 15
VDD 16
48 D1_2_3+
47 D1_2_3–
46 D1_0_1+
45 D1_0_1–
44 DNC
43 DNC
42 OVDD
41 OGND
40 CLKOUT+
39 CLKOUT–
38 D2_12_13+
37 D2_12_13–
36 D2_10_11+
35 D2_10_11–
34 D2_8_9+
33 D2_8_9–
65
GND
64 VDD
63 SENSE
62 VREF
61 SDO
60 OF2_1+
59 OF2_1–
58 D1_12_13+
57 D1_12_13–
56 D1_10_11+
55 D1_10_11–
54 D1_8_9+
53 D1_8_9–
52 D1_6_7+
51 D1_6_7–
50 D1_4_5+
49 D1_4_5–
VDD 17
ENC+ 18
ENC– 19
CS 20
SCK 21
SDI 22
DNC 23
DNC 24
D2_0_1– 25
D2_0_1+ 26
D2_2_3– 27
D2_2_3+ 28
D2_4_5– 29
D2_4_5+ 30
D2_6_7– 31
D2_6_7+ 32
TJMAX = 150°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
PIN CONFIGURATIONS
LTC2145-14/
LTC2144-14/LTC2143-14
4
21454314fa
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ – AIN–) 1.7V < VDD < 1.9V l1 to 2 VP-P
VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) l0.7 VCM 1.25 V
VSENSE External Voltage Reference Applied to SENSE External Reference Mode l0.625 1.250 1.300 V
IINCM Analog Input Common Mode Current Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
155
130
100
µA
µA
µA
IIN1 Analog Input Leakage Current (No Encode) 0 < AIN+, AIN– < VDD l–1.5 1.5 µA
IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l–3 3 µA
IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l–3 3 µA
tAP Sample-and-Hold Acquisition Delay Time 0 ns
tJITTER Sample-and-Hold Acquisition Delay Jitter Single-Ended Encode
Differential Encode
0.08
0.10
psRMS
psRMS
CMRR Analog Input Common Mode Rejection Ratio 80 dB
BW-3B Full-Power Bandwidth Figure 6 Test Circuit 750 MHz
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS
LTC2145-14 LTC2144-14 LTC2143-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Resolution (No Missing Codes) l14 14 14 Bits
Integral Linearity Error Differential Analog Input (Note 6) l–2.6 ±1 2.6 –2.6 ±1 2.6 –2.6 ±1 2.6 LSB
Differential Linearity Error Differential Analog Input l–0.9 ±0.3 0.9 –0.9 ±0.3 0.9 –0.8 ±0.3 0.8 LSB
Offset Error (Note 7) l–9 ±1.5 9 –9 ±1.5 9 –9 ±1.5 9 mV
Gain Error Internal Reference
External Reference l–1.8
±1.5
–0.4 0.9 –1.5
±1.5
–0.3 1.1 –1.5
±1.5
–0.3 1.1
%FS
%FS
Offset Drift ±10 ±10 ±10 µV/°C
Full-Scale Drift Internal Reference
External Reference
±30
±10
±30
±10
±30
±10
ppm/°C
ppm/°C
Gain Matching ±0.2 ±0.2 ±0.2 %FS
Offset Matching ±1.5 ±1.5 ±1.5 mV
Transition Noise 1.25 1.28 1.20 LSBRMS
5
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 0.5 • VDD – 25mV 0.5 • VDD 0.5 • VDD + 25mV V
VCM Output Temperature Drift ±25 ppm/°C
VCM Output Resistance –600µA < IOUT < 1mA 4
VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V
VREF Output Temperature Drift ±25 ppm/°C
VREF Output Resistance –400µA < IOUT < 1mA 7
VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2145-14 LTC2144-14 LTC2143-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
SNR Signal-to-Noise Ratio 5MHz Input
70MHz Input
140MHz Input
l71.4
73.1
73
72.6
71.2
72.9
72.8
72.4
71.7
73.4
73.3
72.9
dBFS
dBFS
dBFS
SFDR Spurious Free Dynamic Range
2nd Harmonic
5MHz Input
70MHz Input
140MHz Input
l76
90
89
84
77
90
89
84
78
90
89
84
dBFS
dBFS
dBFS
Spurious Free Dynamic Range
3rd Harmonic
5MHz Input
70MHz Input
140MHz Input
l79
90
89
84
79
90
89
84
81
90
89
84
dBFS
dBFS
dBFS
Spurious Free Dynamic Range
4th Harmonic or Higher
5MHz Input
70MHz Input
140MHz Input
l86
95
95
95
86
95
95
95
86
95
95
95
dBFS
dBFS
dBFS
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
l70.8
73
72.8
72.2
70.8
72.8
72.6
72
71.4
73.2
73.1
72.4
dBFS
dBFS
dBFS
Crosstalk 10MHz Input –110 –110 –110 dBc
LTC2145-14/
LTC2144-14/LTC2143-14
6
21454314fa
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC– )
Differential Encode Mode (ENC– Not Tied to GND)
VID Differential Input Voltage (Note 8) l0.2 V
VICM Common Mode Input Voltage Internally Set
Externally Set (Note 8) l1.1
1.2
1.6
V
V
VIN Input Voltage Range ENC+, ENC– to GND l0.2 3.6 V
RIN Input Resistance (See Figure 10) 10 k
CIN Input Capacitance (Note 8) 3.5 pF
Single-Ended Encode Mode (ENC– Tied to GND)
VIH High Level Input Voltage VDD = 1.8V l1.2 V
VIL Low Level Input Voltage VDD = 1.8V l0.6 V
VIN Input Voltage Range ENC+ to GND l0 3.6 V
RIN Input Resistance (See Figure 11) 30 k
CIN Input Capacitance (Note 8) 3.5 pF
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH High Level Input Voltage VDD = 1.8V l1.3 V
VIL Low Level Input Voltage VDD = 1.8V l0.6 V
IIN Input Current VIN = 0V to 3.6V l–10 10 µA
CIN Input Capacitance (Note 8) 3 pF
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200
IOH Logic High Output Leakage Current SDO = 0V to 3.6V l–10 10 µA
COUT Output Capacitance (Note 8) 3 pF
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
OVDD = 1.8V
VOH High Level Output Voltage IO = –500µA l1.750 1.790 V
VOL Low Level Output Voltage IO = 500µA l0.010 0.050 V
OVDD = 1.5V
VOH High Level Output Voltage IO = –500µA 1.488 V
VOL Low Level Output Voltage IO = 500µA 0.010 V
OVDD = 1.2V
VOH High Level Output Voltage IO = –500µA 1.185 V
VOL Low Level Output Voltage IO = 500µA 0.010 V
DIGITAL DATA OUTPUTS (LVDS MODE)
VOD Differential Output Voltage 100 Differential Load, 3.5mA Mode
100 Differential Load, 1.75mA Mode
l247 350
175
454 mV
mV
VOS Common Mode Output Voltage 100 Differential Load, 3.5mA Mode
100 Differential Load, 1.75mA Mode
l1.125 1.250
1.250
1.375 V
V
RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100
7
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS
LTC2145-14 LTC2144-14 LTC2143-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD Analog Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OVDD Output Supply Voltage (Note 10) l1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V
IVDD Analog Supply Current DC Input
Sine Wave Input
l105.2
105.9
116 82.8
83.3
92 62.8
63.2
70 mA
mA
IOVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V 8.5 7.1 5.4 mA
PDISS Power Dissipation DC Input
Sine Wave Input, OVDD = 1.2V
l189
201
209 149
159
166 113
120
126 mW
mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OVDD Output Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
IVDD Analog Supply Current Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode l
107.3
108.7 123
84.7
86.1 97
64.6
66.1 75
mA
mA
IOVDD Digital Supply Current
(0VDD = 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode l
35.1
66.3 77
34.8
66 76
34.5
65.7 76
mA
mA
PDISS Power Dissipation Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode l
256
315 360
215
274 312
178
237 272
mW
mW
All Output Modes
PSLEEP Sleep Mode Power 1 1 1 mW
PNAP Nap Mode Power 16 16 16 mW
PDIFFCLK Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
20 20 20 mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2145-14 LTC2144-14 LTC2143-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
fSSampling Frequency (Note 10) l1 125 1 105 1 80 MHz
tLENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
4
4
500
500
4.52
2
4.76
4.76
500
500
5.93
2
6.25
6.25
500
500
ns
ns
tHENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
4
4
500
500
4.52
2
4.76
4.76
500
500
5.93
2
6.25
6.25
500
500
ns
ns
tAP Sample-and-Hold
Acquisition Delay Time
000ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tDENC to Data Delay CL = 5pF (Note 8) l1.1 1.7 3.1 ns
tCENC to CLKOUT Delay CL = 5pF (Note 8) l1 1.4 2.6 ns
tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l0 0.3 0.6 ns
Pipeline Latency Full Data Rate Mode
Double Data Rate Mode
6
6.5
Cycles
Cycles
LTC2145-14/
LTC2144-14/LTC2143-14
8
21454314fa
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Data Outputs (LVDS Mode)
tDENC to Data Delay CL = 5pF (Note 8) l1.1 1.8 3.2 ns
tCENC to CLKOUT Delay CL = 5pF (Note 8) l1 1.5 2.7 ns
tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l0 0.3 0.6 ns
Pipeline Latency 6.5 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode
Readback Mode, CSDO = 20pF, RPULLUP = 2k
l
l
40
250
ns
ns
tSCS to SCK Setup Time l5ns
tHSCK to CS Setup Time l5ns
tDS SDI Setup Time l5ns
tDH SDI Hold Time l5ns
tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l125 ns
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2145), 105MHz
(LTC2144), or 80MHz (LTC2143), LVDS outputs, differential ENC+/ENC–
= 2VP-P sine wave, input range = 2VP-P with differential drive, unless
otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and 11 1111 1111
1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = 1.8V, fSAMPLE = 125MHz (LTC2145), 105MHz (LTC2144),
or 80MHz (LTC2143), CMOS outputs, ENC+ = single-ended 1.8V square
wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on
each digital output unless otherwise noted. The supply current and power
dissipation specifications are totals for the entire IC, not per channel.
Note 10: Recommended operating conditions.
9
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2145-14: Integral
Nonlinearity (INL)
LTC2145-14: Differential
Nonlinearity (DNL)
LTC2145-14: 64k Point FFT,
fIN = 5MHz, –1dBFS, 125Msps
LTC2145-14: 64k Point FFT,
fIN = 30MHz, –1dBFS, 125Msps
LTC2145-14: 64k Point FFT,
fIN = 70MHz, –1dBFS, 125Msps
LTC2145-14: 64k Point FFT,
fIN = 140MHz, –1dBFS, 125Msps
LTC2145-14: 64k Point 2-Tone
FFT, fIN = 69MHz, 70MHz,
–1dBFS, 125Msps
LTC2145-14: Shorted Input
Histogram
LTC2145-14: SNR vs Input
Frequency, –1dBFS, 125Msps,
2V Range
OUTPUT CODE
–2.0
–1.0
–0.5
–1.5
INL ERROR (LSB)
0.5
0
1.0
1.5
2.0
21454314 G01
04096 8192 12288 16384
OUTPUT CODE
–1.0
–0.4
–0.2
–0.6
–0.8
DNL ERROR (LSB)
0
0.4
0.2
0.6
0.8
1.0
21454314 G02
04096 8192 12288 16384
FREQUENCY (MHz)
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
21454314 G03
010 20 30 40 50 60
FREQUENCY (MHz)
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
21454314 G04
010 20 30 40 50 60
FREQUENCY (MHz)
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
21454314 G05
010 20 30 40 50 60
FREQUENCY (MHz)
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
21454314 G06
010 20 30 40 50 60
FREQUENCY (MHz)
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
21454314 G07
010 20 30 40 50 60
OUTPUT CODE
8183
0
COUNT
3000
4000
5000
8185 8187 8189
6000
2000
1000
8191
21454314 G08 INPUT FREQUENCY (MHz)
0
72
71
70
74
73
SNR (dBFS)
50 100 150 200 250 300
21454314 G09
SINGLE-ENDED
ENCODE
DIFFERENTIAL
ENCODE
LTC2145-14/
LTC2144-14/LTC2143-14
10
21454314fa
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2145-14: SFDR vs Input Level,
fIN = 70MHz, 125Msps, 2V Range
LTC2145-14: IVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
Input on Each Channel
LTC2145-14: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
125Msps, 2V Range
LTC2145-14: IOVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
on Each Input
LTC2145-14: SNR vs SENSE,
fIN = 5MHz, –1dBFS
LTC2144-14: Integral
Nonlinearity (INL)
LTC2144-14: Differential
Nonlinearity (DNL)
LTC2144-14: 64k Point FFT,
fIN = 5MHz, –1dBFS, 105Msps
LTC2145-14: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
125Msps, 1V Range
0 50 100 150 200 250 300
INPUT FREQUENCY (MHz)
90
85
80
75
70
65
100
95
2ND AND 3RD HARMONIC (dBFS)
21454314 G10
2ND
3RD
0 50 100 150 200 250 300
INPUT FREQUENCY (MHz)
90
85
80
75
70
65
100
95
2ND AND 3RD HARMONIC (dBFS)
218543 G11
2ND
3RD
INPUT LEVEL (dBFS)
120
90
80
100
110
SFDR (dBc AND dBFS)
70
50
60
40
30
21454314 G12
–80 –70 –60 –50 –40 –30 –20 –10 0
dBc
dBFS
SAMPLE RATE (Msps)
0
75
80
85
110
105
100
95
90
IVDD (mA)
25 50 75 125100
21454314 G13
CMOS OUTPUTS
LVDS OUTPUTS
SAMPLE RATE (Msps)
0
10
0
20
30
70
60
50
40
IOVDD (mA)
25 50 75 125100
21454314 G14
3.5mA LVDS
1.75mA LVDS
1.8V CMOS
SENSE PIN (V)
0.6
71
72
69
70
68
67
66
74
73
SNR (dBFS)
0.8 10.7 0.9 1.1 1.2 1.3
21454314 G15
OUTPUT CODE
–2.0
–1.0
–0.5
–1.5
INL ERROR (LSB)
0.5
0
1.0
1.5
2.0
21454314 G16
04096 8192 12288 16384
OUTPUT CODE
–1.0
–0.4
–0.2
–0.6
–0.8
DNL ERROR (LSB)
0
0.4
0.2
0.6
0.8
1.0
21454314 G17
04096 8192 12288 16384
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
21454314 G1
11
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
LTC2144-14: 64k Point FFT,
fIN = 140MHz, –1dBFS, 105Msps
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2144-14: 64k Point FFT,
fIN = 30MHz, –1dBFS, 105Msps
LTC2144-14: 64k Point FFT,
fIN = 70MHz, –1dBFS, 105Msps
LTC2144-14: 64k Point 2-Tone
FFT, fIN = 69MHz, 70MHz,
–1dBFS, 105Msps
LTC2144-14: Shorted Input
Histogram
LTC2144-14: SNR vs Input
Frequency, –1dBFS, 105Msps,
2V Range
LTC2144-14: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
105Msps, 2V Range
LTC2144-14: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
105Msps, 1V Range
LTC2144-14: SFDR vs Input Level,
fIN = 70MHz, 105Msps, 2V Range
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
21454314 G19 FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
21454314 G20 FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
21454314 G21
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
21454314 G22 OUTPUT CODE
8190
0
COUNT
3000
4000
5000
8192 8194 8196
6000
2000
1000
8198
21454314 G23 INPUT FREQUENCY (MHz)
0
72
71
70
74
73
SNR (dBFS)
50 100 150 200 250 300
21454314 G24
SINGLE-ENDED
ENCODE
DIFFERENTIAL
ENCODE
0 50 100 150 200 250 300
INPUT FREQUENCY (MHz)
90
85
80
75
70
65
100
95
2ND AND 3RD HARMONIC (dBFS)
21454314 G25
2ND
3RD
0 50 100 150 200 250 300
INPUT FREQUENCY (MHz)
90
85
80
75
70
65
100
95
2ND AND 3RD HARMONIC (dBFS)
218543 G26
2ND
3RD
INPUT LEVEL (dBFS)
120
90
80
100
110
SFDR (dBc AND dBFS)
70
50
60
40
30
21454314 G27
–80 –70 –60 –50 –40 –30 –20 –10 0
dBc
dBFS
LTC2145-14/
LTC2144-14/LTC2143-14
12
21454314fa
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2143-14: 64k Point FFT,
fIN = 70MHz, –1dBFS, 80Msps
LTC2143-14: 64k Point FFT,
fIN = 140MHz, –1dBFS, 80Msps
LTC2143-14: 64k Point FFT,
fIN = 30MHz, –1dBFS, 80Msps
LTC2144-14: IVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
Input on Each Channel
LTC2144-14: IOVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
on Each Input
LTC2144-14: SNR vs SENSE,
fIN = 5MHz, –1dBFS
LTC2143-14: Integral
Nonlinearity (INL)
LTC2143-14: Differential
Nonlinearity (DNL)
LTC2143-14: 64k Point FFT,
fIN = 5MHz, –1dBFS, 80Msps
SAMPLE RATE (Msps)
0
55
60
65
90
85
80
75
70
IVDD (mA)
25 50 75 100
21454314 G28
CMOS OUTPUTS
LVDS OUTPUTS
SAMPLE RATE (Msps)
0
10
0
20
30
70
60
50
40
IOVDD (mA)
25 50 75 100
21454314 G29
3.5mA LVDS
1.75mA LVDS
1.8V CMOS
SENSE PIN (V)
0.6
71
72
69
70
68
67
66
74
73
SNR (dBFS)
0.8 10.7 0.9 1.1 1.2 1.3
21454314 G30
OUTPUT CODE
INL ERROR (LSB)
21454314 G31
04096 8192 12288 16384
–2.0
–1.0
–0.5
–1.5
0.5
0
1.0
1.5
2.0
OUTPUT CODE
–1.0
–0.4
–0.2
–0.6
–0.8
DNL ERROR (LSB)
0
0.4
0.2
0.6
0.8
1.0
21454314 G32
04096 8192 12288 16384
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
21454314 G33
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
21454314 G34 FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
21454314 G35
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
21454314 G36
13
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2143-14: Shorted Input
Histogram
LTC2143-14: 64k Point 2-Tone FFT,
fIN = 69MHz, 70MHz, –1dBFS,
80Msps
LTC2143-14: SNR vs Input
Frequency, –1dBFS, 80Msps,
2V Range
LTC2143-14: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 80Msps,
2V Range
LTC2143-14: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 80Msps,
1V Range
LTC2143-14: SFDR vs Input Level,
fIN = 70MHz, 80Msps, 2V Range
LTC2143-14: IVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
Input on Each Channel
LTC2143-14: IOVDD vs Sample
Rate, 5MHz, –1dBFS, Sine Wave
on Each Input
LTC2143-14: SNR vs SENSE,
fIN = 5MHz, –1dBFS
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
21454314 G37 OUTPUT CODE
8183
0
COUNT
3000
4000
5000
8185 8187 8189
6000
2000
1000
8191
21454314 G38 INPUT FREQUENCY (MHz)
0
72
71
70
74
73
SNR (dBFS)
50 100 150 200 250 300
21454314 G39
SINGLE-ENDED
ENCODE
DIFFERENTIAL
ENCODE
0 50 100 150 200 250 300
INPUT FREQUENCY (MHz)
90
85
80
75
70
65
100
95
2ND AND 3RD HARMONIC (dBFS)
21454314 G40
2ND
3RD
0 50 100 150 200 250 300
INPUT FREQUENCY (MHz)
90
85
80
75
70
65
100
95
2ND AND 3RD HARMONIC (dBFS)
218543 G41
2ND
3RD
INPUT LEVEL (dBFS)
120
90
80
100
110
SFDR (dBc AND dBFS)
70
50
60
40
30
21454314 G42
–80 –70 –60 –50 –40 –30 –20 –10 0
dBc
dBFS
SAMPLE RATE (Msps)
0
40
45
70
65
60
55
50
IVDD (mA)
20 40 60 80
21454314 G43
CMOS OUTPUTS
LVDS OUTPUTS
SAMPLE RATE (Msps)
0
10
0
20
30
70
60
50
40
IOVDD (mA)
20 40 60 80
21454314 G44
3.5mA LVDS
1.75mA LVDS
1.8V CMOS
SENSE PIN (V)
0.6
71
72
69
70
68
67
66
74
73
SNR (dBFS)
0.8 10.7 0.9 1.1 1.2 1.3
21454314 G45
LTC2145-14/
LTC2144-14/LTC2143-14
14
21454314fa
PINS THAT ARE THE SAME FOR ALL DIGITAL
OUTPUT MODES
VDD (Pins 1, 16, 17, 64): Analog Power Supply, 1.7V to
1.9V. Bypass to ground with 0.1µF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
VCM1 (Pin 2): Common Mode Bias Output, Nominally Equal
to VDD/2. VCM1 should be used to bias the common mode
of the analog inputs to channel 1. Bypass to ground with
a 0.1µF ceramic capacitor.
GND (Pins 3, 6, 14): ADC Power Ground.
AIN1+ (Pin 4): Channel 1 Positive Differential Analog Input.
AIN1– (Pin 5): Channel 1 Negative Differential Analog Input.
REFH (Pins 7, 9): ADC High Reference. See the Applica-
tions Information section for recommended bypassing
circuits for REFH and REFL.
REFL (Pins 8, 10): ADC Low Reference. See the Applica-
tions Information section for recommended bypassing
circuits for REFH and REFL.
PAR/SER (Pin 11): Programming Mode Selection Pin.
Connect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or VDD and not be driven by a logic signal.
AIN2+ (Pin 12): Channel 2 Positive Differential Analog Input.
AIN2– (Pin 13): Channel 2 Negative Differential Analog Input.
VCM2 (Pin 15): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM2 should be used to bias the common
mode of the analog inputs to channel 2. Bypass to ground
with a 0.1µF ceramic capacitor.
ENC+ (Pin 18): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 19): Encode Complement Input. Conversion
starts on the falling edge. Tie to GND for single-ended
encode mode.
CS (Pin 20): In Serial Programming Mode, (PAR/SER =
0V), CS Is the Serial Interface Chip Select Input. When
CS is low, SCK is enabled for shifting data on SDI into the
mode control registers. In the parallel programming mode
(PAR/SER = VDD), CS controls the clock duty cycle stabilizer
(See Table 2). CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 21): In Serial Programming Mode, (PAR/SER =
0V), SCK Is the Serial Interface Clock Input. In the parallel
programming mode (PAR/SER = VDD), SCK controls the
digital output mode (see Table 2). SCK can be driven with
1.8V to 3.3V logic.
SDI (Pin 22): In Serial Programming Mode, (PAR/SER =
0V), SDI Is the Serial Interface Data Input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In the parallel programming mode (PAR/
SER = VDD), SDI can be used together with SDO to power
down the part (see Table 2). SDI can be driven with 1.8V
to 3.3V logic.
OGND (Pin 41): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
OVDD (Pin 42): Output Driver Supply. Bypass to ground
with a 0.1µF ceramic capacitor.
SDO (Pin 61): In Serial Programming Mode, (PAR/SER
= 0V), SDO Is the Optional Serial Interface Data Output.
Data on SDO is read back from the mode control regis-
ters and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V – 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode (PAR/SER = VDD), SDO can
be used together with SDI to power down the part (see
Table 2). When used as an input, SDO can be driven with
1.8V to 3.3V logic through a 1k series resistor.
VREF (Pin 62): Reference Voltage Output. Bypass to
ground with a 2.2µF ceramic capacitor. The output voltage
is nominally 1.25V.
PIN FUNCTIONS
15
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
PIN FUNCTIONS
SENSE (Pin 63): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • VSENSE.
Ground (Exposed Pad Pin 65): The exposed pad must be
soldered to the PCB ground.
FULL RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels
(OGND to OVDD)
D2_0 to D2_13 (Pins 25, 26, 27, 28, 29, 30, 31, 32, 33,
34, 35, 36, 37, 38): Channel 2 Digital Outputs. D2_13 is
the MSB.
DNC (Pins 23, 24, 43, 44): Do not connect these pins.
CLKOUT– (Pin 39): Inverted Version of CLKOUT+.
CLKOUT+ (Pin 40): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the Digital Outputs by programming the mode
control registers.
D1_0 to D1_13 (Pins 45, 46, 47, 48, 49, 50, 51, 52, 53,
54, 55, 56, 57, 58): Channel 1 Digital Outputs. D1_13 is
the MSB.
OF2 (Pin 59): Channel 2 Over/Underflow Digital Output.
OF2 is high when an overflow or underflow has occurred.
OF1 (Pin 60): Channel 1 Over/Underflow Digital Output.
OF1 is high when an overflow or underflow has occurred.
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels
(OGND to OVDD)
D2_0_1 to D2_12_13 (Pins 26, 28, 30, 32, 34, 36, 38):
Channel 2 Double Data Rate Digital Outputs. Two data bits
are multiplexed onto each output pin. The even data bits
(D0, D2, D4, D6, D8, D10, D12) appear when CLKOUT+
is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13)
appear when CLKOUT+ is high.
DNC (Pins 23, 24, 25, 27, 29, 31, 33, 35, 37, 43, 44, 45,
47, 49, 51, 53, 55, 57, 59): Do not connect these pins.
CLKOUT– (Pin 39): Inverted Version of CLKOUT+.
CLKOUT+ (Pin 40): Data Output Clock. The Digital Outputs
normally transition at the same time as the falling and ris-
ing edges of CLKOUT+. The phase of CLKOUT+ can also
be delayed relative to the Digital Outputs by programming
the mode control registers.
D1_0_1 to D1_12_13 (Pins 46, 48, 50, 52, 54, 56, 58):
Channel 1 Double Data Rate Digital Outputs. Two data bits
are multiplexed onto each output pin. The even data bits
(D0, D2, D4, D6, D8, D10, D12) appear when CLKOUT+
is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13)
appear when CLKOUT+ is high.
OF2_1 (Pin 60): Over/Underflow Digital Output. OF2_1 is
high when an overflow or underflow has occurred. The
over/under flow for both channels are multiplexed onto
this pin. Channel 2 appears when CLKOUT+ is low, and
Channel 1 appears when CLKOUT+ is high.
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level Is Programmable. There Is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D2_0_1–/D2_0_1+ to D2_12_13–/D2_12_13+ (Pins 25/26,
27/28, 29/30, 31/32, 33/34, 35/36, 37/38): Channel
2 Double Data Rate Digital Outputs. Two data bits are
multiplexed onto each differential output pair. The even
data bits (D0, D2, D4, D6, D8, D10, D12) appear when
CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9,
D11, D13) appear when CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 39/40): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
LTC2145-14/
LTC2144-14/LTC2143-14
16
21454314fa
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
DNC (Pins 23, 24, 43, 44): Do not connect these pins.
D1_0_1–/D1_0_1+ to D1_12_13–/D1_12_13+ (Pins
45/46, 47/48, 49/50, 51/52, 53/54, 55/56, 57/58):
Channel 1 Double Data Rate Digital Outputs. Two data
bits are multiplexed onto each differential output pair.
The even data bits (D0, D2, D4, D6, D8, D10, D12) ap-
pear when CLKOUT+ is low. The odd data bits (D1, D3,
D5, D7, D9, D11, D13) appear when CLKOUT+ is high.
OF2_1–/OF2_1+ (Pins 59/60): Over/Underflow Digital
Output. OF2_1+ is high when an overflow or underflow
has occurred. The over/under flow for both channels
are multiplexed onto this pin. Channel 2 appears when
CLKOUT+ is low, and Channel 1 appears when CLKOUT+
is high.
DIFF
REF
AMP
REF
BUF
2.2µF
0.1µF 0.1µF
INTERNAL CLOCK SIGNALSREFH REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.25V
REFERENCE
ENC+
REFH REFL ENC–
CORRECTION
LOGIC
SDOCS
OGND
OF1
OVDD
D1_13
CLKOUT
–
CLKOUT
+
D1_0
21454314 F01
SENSE
VREF
CH 1
ANALOG
INPUT
2.2µF
VCM1
0.1µF
VDD/2
OUTPUT
DRIVERS
MODE
CONTROL
REGISTERS
SCKPAR/SER SDI
t
t
t
GND
S/H 14-BIT
ADC CORE
CH 2
ANALOG
INPUT
S/H 14-BIT
ADC CORE
VCM2
0.1µF
OF2
D2_13
D2_0
t
t
t
VDD
PIN FUNCTIONS
17
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
Full Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
TIMING DIAGRAMS
tH
tD
tC
tL
B – 6 B – 5 B – 4 B – 3 B – 2
tAP
A + 1
A + 2 A + 4
A + 3
A
CH 1
ANALOG
INPUT
ENC–
ENC+
CLKOUT+
CLKOUT–
D2_0 - D2_13, OF2
tAP
B + 1
B + 2 B + 4
B + 3
B
CH 2
ANALOG
INPUT
A – 6 A – 5 A – 4 A – 3 A – 2
D1_0 - D1_13, OF1
21454314 TD01
LTC2145-14/
LTC2144-14/LTC2143-14
18
21454314fa
TIMING DIAGRAMS
Double Data Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tD
t
t
t
tD
tCtC
tL
BIT 0
A-6
BIT 1
A-6
BIT 0
A-5
BIT 1
A-5
BIT 0
A-4
BIT 1
A-4
BIT 0
A-3
BIT 1
A-3
BIT 0
A-2
BIT 12
A-6
BIT 13
A-6
BIT 12
A-5
BIT 13
A-5
BIT 12
A-4
BIT 13
A-4
BIT 12
A-3
BIT 13
A-3
BIT 12
A-2
ENC–
ENC+
D1_0_1
D1_12_13
t
t
t
BIT 0
B-6
BIT 1
B-6
BIT 0
B-5
BIT 1
B-5
BIT 0
B-4
BIT 1
B-4
BIT 0
B-3
BIT 1
B-3
BIT 0
B-2
BIT 12
B-6
BIT 13
B-6
BIT 12
B-5
BIT 13
B-5
BIT 12
B-4
BIT 13
B-4
BIT 12
B-3
BIT 13
B-3
BIT 12
B-2
OF
B-6
OF
A-6
OF
B-5
OF
A-5
OF
B-4
OF
A-4
OF
B-3
OF
A-3
OF
B-2
D2_0_1
D2_12_13
CLKOUT+
CLKOUT–
OF2_1
21454314 TD02
tH
tAP
A + 1
A + 2 A + 4
A + 3
A
CH 1
ANALOG
INPUT
tAP
B + 1
B + 2 B + 4
B + 3
B
CH 2
ANALOG
INPUT
19
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
TIMING DIAGRAMS
Double Data Rate LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
tD
t
t
t
tD
tCtC
tL
BIT 0
A-6
BIT 1
A-6
BIT 0
A-5
BIT 1
A-5
BIT 0
A-4
BIT 1
A-4
BIT 0
A-3
BIT 1
A-3
BIT 0
A-2
BIT 12
A-6
BIT 13
A-6
BIT 12
A-5
BIT 13
A-5
BIT 12
A-4
BIT 13
A-4
BIT 12
A-3
BIT 13
A-3
BIT 12
A-2
ENC–
ENC+
D1_0_1+
D1_12_13+
t
t
t
BIT 0
B-6
BIT 1
B-6
BIT 0
B-5
BIT 1
B-5
BIT 0
B-4
BIT 1
B-4
BIT 0
B-3
BIT 1
B-3
BIT 0
B-2
BIT 12
B-6
BIT 13
B-6
BIT 12
B-5
BIT 13
B-5
BIT 12
B-4
BIT 13
B-4
BIT 12
B-3
BIT 13
B-3
BIT 12
B-2
OF
B-6
OF
A-6
OF
B-5
OF
A-5
OF
B-4
OF
A-4
OF
B-3
OF
A-3
OF
B-2
D2_0_1+
D2_12_13+
CLKOUT+
CLKOUT–
OF2_1+
D1_0_1–
D1_12_13–
D2_0_1–
D2_12_13–
OF2_1–
21454314 TD03
tH
tAP
A + 1
A + 2 A + 4
A + 3
A
CH 1
ANALOG
INPUT
tAP
B + 1
B + 2 B + 4
B + 3
B
CH 2
ANALOG
INPUT
A6
tStDS
A5 A4 A3 A2 A1 A0 XX
D7 D6 D5 D4 D3 D2 D1 D0
XX XX XX XX XX XX XX
CS
SCK
SDI R/W
SDO
HIGH IMPEDANCE
SPI Port Timing (Readback Mode)
SPI Port Timing (Write Mode)
tDH
tDO
tSCK tH
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
21454314 TD04
CS
SCK
SDI R/W
SDO
HIGH IMPEDANCE
LTC2145-14/
LTC2144-14/LTC2143-14
20
21454314fa
CONVERTER OPERATION
The LTC2145-14/LTC2144-14/LTC2143-14 are low power,
two-channel, 14-bit, 125Msps/105Msps/80Msps A/D
converters that are powered by a single 1.8V supply. The
analog inputs should be driven differentially. The encode
input can be driven differentially, or single ended for lower
power consumption. The digital outputs can be CMOS,
double data rate CMOS (to halve the number of output
lines), or double data rate LVDS (to reduce digital noise
in the system.) Many additional features can be chosen
by programming the mode control registers through a
serial SPI port.
ANALOG INPUT
The analog inputs are differential CMOS sample-and-hold
circuits (Figure 2). The inputs should be driven differen-
tially around a common mode voltage set by the VCM1 or
VCM2 output pins, which are nominally VDD/2. For the 2V
input range, the inputs should swing from VCM – 0.5V
to VCM + 0.5V. There should be 180° phase difference
between the inputs.
The two channels are simultaneously sampled by a shared
encode circuit (Figure 2).
Single-Ended Input
For applications less sensitive to harmonic distortion, the
AIN+ input can be driven single-ended with a 1VP-P signal
centered around VCM. The AIN– input should be connected
to VCM and the VCM bypass capacitor should be increased
to 2.2µF. With a single-ended input, the harmonic distortion
and INL will degrade, but the noise and DNL will remain
unchanged.
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
also limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with VCM, setting the A/D input at its optimal
DC level. At higher input frequencies a transmission line
balun transformer (Figure 4 to Figure 6) has better balance,
resulting in lower A/D distortion.
CSAMPLE
5pF
RON
15
RON
15
VDD
VDD
LTC2145-14
AIN+
21454314 F02
CSAMPLE
5pF
VDD
AIN–
ENC–
ENC+
1.2V
10k
1.2V
10k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
10
10Ω
25
25 25
25
50
0.1µF
AIN+
AIN–
12pF
0.1µF
VCM
LTC2145-14
ANALOG
INPUT
0.1µF T1
1:1
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
21454314 F03
Figure 2. Equivalent Input Circuit. Only One of the Two
Analog Channels Is Shown
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
APPLICATIONS INFORMATION
21
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
Figure 5. Recommended Front-End Circuit for Input
Frequencies from 150MHz to 250MHz
Figure 6. Recommended Front-End Circuit for Input
Frequencies Above 250MHz
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC-coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figure 4
to Figure 6) should convert the signal to differential before
driving the A/D.
Figure 4. Recommended Front-End Circuit for Input
Frequencies from 5MHz to 150MHz
Reference
The LTC2145-14/LTC2144-14/LTC2143-14 has an internal
1.25V voltage reference. For a 2V input range using the
internal reference, connect SENSE to VDD. For a 1V input
range using the internal reference, connect SENSE to
ground. For a 2V input range with an external reference,
apply a 1.25V reference voltage to SENSE (Figure 9).
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • VSENSE.
The VREF, REFH and REFL pins should be bypassed as
shown in Figure 8. A low inductance 2.2µF interdigitated
capacitor is recommended for the bypass between REFH
and REFL. This type of capacitor is available at a low cost
from multiple suppliers.
25
12
12
25
50
0.1µF
AIN+
AIN–
8.2pF
0.1µF
VCM
ANALOG
INPUT
0.1µF
0.1µF
T1
T2
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
21454314 F04
LTC2145-14
25
25
50
0.1µF
AIN+
AIN–
1.8pF
0.1µF
VCM
ANALOG
INPUT
0.1µF
0.1µF
T1
T2
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
21454314 F05
LTC2145-14
25
25
50
0.1µF
4.7nH
4.7nH
AIN+
AIN–
0.1µF
VCM
ANALOG
INPUT
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
21454314 F06
LTC2145-14
T1
0.1µF
0.1µF
25
25
200
200
0.1µF AIN+
AIN–
0.1µF
12pF
12pF
VCM
LTC2145-14
21454314 F07
––
++
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1µF
Figure 7. Front-End Circuit Using a High Speed
Differential Amplifier
LTC2145-14/
LTC2144-14/LTC2143-14
22
21454314fa
APPLICATIONS INFORMATION
VREF
REFH
REFH
SENSE
C1
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
3"/(&t7SENSE FOR
0.625V < VSENSE < 1.300V
1.25V
REFL
REFL
INTERNAL ADC
HIGH REFERENCE
BUFFER
21454314 F08a
LTC2145-14
5
0.8x
DIFF AMP
INTERNAL ADC
LOW REFERENCE
C1: 2.2µF LOW INDUCTANCE
INTERDIGITATED CAPACITOR
TDK CLLE1AX7S0G225M
MURATA LLA219C70G225M
AVX W2L14Z225M
OR EQUIVALENT
1.25V BANDGAP
REFERENCE
0.625V
RANGE
DETECT
AND
CONTROL
2.2µF
C2
0.1µF
C3
0.1µF
+
+
–
–
–
–
+
+
Figure 8a. Reference Circuit
SENSE
1.25V
EXTERNAL
REFERENCE
2.2µF
1µF
VREF
21454314 F09
LTC2145-14
Figure 9. Using an External 1.25V Reference
REFH
REFH
REFL
REFL
21454314 F08b
LTC2145-14
CAPACITORS ARE 0402 PACKAGE SIZE
C3
0.1µF
C1
2.2µF
C2
0.1µF
Figure 8b. Alternative REFH/REFL Bypass Circuit
Figure 8c. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8a
Alternatively, C1 can be replaced by a standard 2.2µF
capacitor between REFH and REFL (see Figure 8b). The
capacitors should be as close to the pins as possible (not
on the back side of the circuit board).
Figure 8c and Figure 8d show the recommended circuit
board layout for the REFH/REFL bypass capacitors. Note
that in Figure 8c, every pin of the interdigitated capacitor
(C1) is connected since the pins are not internally connected
Figure 8d. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8b
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals – do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for si-
nusoidal, PECL, or LVDS encode inputs (Figure 12 and
Figure 13). The encode inputs are internally biased to 1.2V
in some vendors’ capacitors. In Figure 8d the REFH and
REFL pins are connected by short jumpers in an internal
layer. To minimize the inductance of these jumpers they
can be placed in a small hole in the GND plane on the
second board layer.
23
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
50Ω
100Ω
0.1µF
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50Ω
LTC2145-14
21454314 F12
ENC–
ENC+
T1
0.1µF
0.1µF
Figure 12. Sinusoidal Encode Drive
ENC+
ENC–
PECL OR
LVDS
CLOCK
0.1µF
0.1µF
21454314 F13
LTC2145-14
Figure 13. PECL or LVDS Encode Drive
VDD
LTC2145-14
21454314 F10
ENC–
ENC+
15k
VDD
DIFFERENTIAL
COMPARATOR
30k
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
30k
ENC+
ENC–
21454314 F11
0V
1.8V TO 3.3V
LTC2145-14
CMOS LOGIC
BUFFER
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
through 10kΩ equivalent resistance. The encode inputs
can be taken above VDD (up to 3.6V), and the common
mode range is from 1.1V to 1.6V. In the differential encode
mode, ENC– should stay at least 200mV above ground to
avoid falsely triggering the single ended encode mode.
For good jitter performance ENC+ and ENC– should have
fast rise and fall times.
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC– is connected to
ground and ENC+ is driven with a square wave encode input.
ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V
CMOS logic levels can be used. The ENC+ threshold is 0.9V.
For good jitter performance ENC+ should have fast rise
and fall times. If the encode signal is turned off or drops
below approximately 500kHz, the A/D enters nap mode.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency, the duty cycle stabilizer circuit
requires one hundred clock cycles to lock onto the input
clock. The duty cycle stabilizer is enabled by mode control
register A2 (serial programming mode), or by CS (parallel
programming mode).
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
to make the sampling clock have a 50% (±5%) duty cycle.
The duty cycle stabilizer should not be used below 5Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2145-14/LTC2144-14/LTC2143-14 can operate in
three digital output modes: full rate CMOS, double data
rate CMOS (to halve the number of output lines), or double
data rate LVDS (to reduce digital noise in the system.) The
output mode is set by mode control register A3 (serial
programming mode), or by SCK (parallel programming
APPLICATIONS INFORMATION
LTC2145-14/
LTC2144-14/LTC2143-14
24
21454314fa
APPLICATIONS INFORMATION
mode). Note that double data rate CMOS cannot be selected
in the parallel programming mode.
Full Rate CMOS Mode
In full rate CMOS mode the data outputs (D1_0 to D1_13
and D2_0 to D2_13), overflow (OF2, OF1), and the data
output clocks (CLKOUT+, CLKOUT–) have CMOS output
levels. The outputs are powered by OVDD and OGND which
are isolated from the A/D core power and ground. OVDD
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double Data Rate CMOS Mode
In double data rate CMOS mode, two data bits are
multiplexed and output on each data pin. This reduces
the number of digital lines by fifteen, simplifying board
routing and reducing the number of input pins needed
to receive the data. The data outputs (D1_0_1, D1_2_3,
D1_4_5, D1_6_7, D1_8_9, D1_10_11, D1_12_13, D2_0_1,
D2_2_3, D2_4_5, D2_6_7, D2_8_9, D2_10_11,
D2_12_13), overflow (OF2_1), and the data output clocks
(CLKOUT+, CLKOUT–) have CMOS output levels. The out-
puts are powered by OVDD and OGND which are isolated
from the A/D core power and ground. OVDD can range
from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS logic
outputs. Note that the overflow for both ADC channels is
multiplexed onto the OF2_1 pin.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
When using double data rate CMOS at sample rates above
100Msps the SNR may degrade slightly, about 0.1dB to
0.3dB depending on load capacitance and board layout.
Double Data Rate LVDS Mode
In double data rate LVDS mode, two data bits are multi-
plexed and output on each differential output pair. There
are seven LVDS output pairs per ADC channel (D1_0_1+/
D1_0_1– through D1_12_13+/D1_12_13– and D2_0_1+/
D2_0_1– through D2_12_13+/D2_12_13–) for the digital
output data. Overflow (OF2_1+/OF2_1–) and the data
output clock (CLKOUT+/CLKOUT–) each have an LVDS
output pair. Note that the overflow for both ADC channels
is multiplexed onto the OF2_1+/OF2_1– output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground. In LVDS
mode, OVDD must be 1.8V.
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by serially programming mode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
Overflow Bit
The overflow output bit outputs a logic high when the analog
input is either overranged or underranged. The overflow
bit has the same pipeline latency as the data bits. In full
rate CMOS mode each ADC channel has its own overflow
pin (OF1 for channel 1, OF2 for channel 2). In DDR CMOS
or DDR LVDS mode the overflow for both ADC channels
is multiplexed onto the OF2_1 output.
25
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
Phase Shifting the Output Clock
In full rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
set-up and hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2145-14/LTC2144-14/LTC2143-14 can also phase
shift the CLKOUT+/CLKOUT– signals by serially program-
ming mode control register A2. The output clock can be
shifted by 0°, 45°, 90°, or 135°. To use the phase shift-
ing feature the clock duty cycle stabilizer must be turned
on. Another control register bit can invert the polarity of
CLKOUT+ and CLKOUT–, independently of the phase shift.
The combination of these two features enables phase shifts
of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range) OF
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
>1.000000V
+0.999878V
+0.999756V
1
0
0
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
+0.000122V
+0.000000V
–0.000122V
–0.000244V
0
0
0
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
–0.999878V
–1.000000V
≤–1.000000V
0
0
1
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
CLKOUT+
D0-D13, OF
PHASE
SHIFT
0°
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
0
0
0
1
1
1
1
CLKPHASE1
MODE CONTROL BITS
0
0
1
1
0
0
1
1
CLKPHASE0
0
1
0
1
0
1
0
1
21454314 F14
ENC+
Figure 14. Phase Shifting CLKOUT
LTC2145-14/
LTC2144-14/LTC2143-14
26
21454314fa
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclusive-
OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
an exclusive-OR operation is applied between the LSB
and all other bits. The LSB, OF and CLKOUT outputs are
not affected. The output randomizer is enabled by serially
programming mode control register A4.
Alternate Bit Polarity
Another feature that reduces digital feedback on the circuit
board is the alternate bit polarity mode. When this mode
is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11,
D13) are inverted before the output buffers. The even bits
(D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are not
affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
When there is a very small signal at the input of the A/D
that is centered around mid-scale, the digital outputs toggle
between mostly 1’s and mostly 0’s. This simultaneous
switching of most of the bits will cause large currents in the
ground plane. By inverting every other bit, the alternate bit
polarity mode makes half of the bits transition high while
half of the bits transition low. This cancels current flow in
the ground plane, reducing the digital noise.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13). The alternate
bit polarity mode is independent of the digital output ran-
domizer – either, both or neither function can be on at the
same time. The alternate bit polarity mode is enabled by
serially programming mode control register A4.
APPLICATIONS INFORMATION
CLKOUT CLKOUT
OF
D13/D0
D12/D0
t
t
t
D2/D0
D1/D0
D0
21454314 F15
OF
D13
D12
D2
D1
D0
RANDOMIZER
ON
D13
FPGA
PC BOARD
D12
t
t
t
D2
D1
D0
21454314 F16
D0
D1/D0
D2/D0
D12/D0
D13/D0
OF
CLKOUT
LTC2145-14
Figure 15. Functional Equivalent of Digital Output Randomizer
Figure 16. Unrandomizing a Randomized Digital
Output Signal
27
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
allowed so the on-chip references can settle from the slight
temperature shift caused by the change in supply current
as the A/D leaves nap mode. Either channel 2 or both chan-
nels can be placed in nap mode; it is not possible to have
channel 1 in nap mode and channel 2 operating normally.
Sleep mode and nap mode are enabled by mode control
register A1 (serial programming mode), or by SDI and
SDO (parallel programming mode).
DEVICE PROGRAMMING MODES
The operating modes of the LTC2145-14/LTC2144-14/
LTC2143-14 can be programmed by either a parallel in-
terface or a simple serial interface. The serial interface has
more flexibility and can program all available modes. The
parallel interface is more limited and can only program
some of the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK, SDI and SDO pins are binary
logic inputs that set certain operating modes. These pins
can be tied to VDD or ground, or driven by 1.8V, 2.5V, or
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 2 shows the
modes set by CS, SCK, SDI and SDO.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN DESCRIPTION
CS Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK Digital Output Mode Control Bit
0 = Full Rate CMOS Output Mode
1 = Double Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
SDI/SDO Power Down Control Bit
00 = Normal Operation
01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode
10 = Channel 1 and Channel 2 in Nap Mode
11 = Sleep Mode (Entire Device Powered Down)
APPLICATIONS INFORMATION
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13-D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples.
Checkerboard: Outputs change from
101010101010101 to 010101010101010 on alternat-
ing samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the Test Patterns override all other formatting modes: 2’s
complement, randomizer, alternate bit polarity.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs including
OF and CLKOUT are disabled. The high-impedance disabled
state is intended for in-circuit testing or long periods of
inactivity – it is too slow to multiplex a data bus between
multiple converters at full speed. When the outputs are
disabled both channels should be put into either sleep or
nap mode.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire device is powered down,
resulting in 1mW power consumption. The amount of time
required to recover from sleep mode depends on the size
of the bypass capacitors on VREF, REFH, and REFL. For the
suggested values in Fig. 8, the A/D will stabilize after 2ms.
In nap mode the A/D core is powered down while the internal
reference circuits stay active, allowing faster wakeup than
from sleep mode. Recovering from nap mode requires at
least 100 clock cycles. If the application demands very
accurate DC settling then an additional 50µs should be
LTC2145-14/
LTC2144-14/LTC2143-14
28
21454314fa
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become a
serial interface that program the A/D mode control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the timing
diagrams). During a read back command the register is
not updated and data on SDI is ignored.
The SDO pin is an open drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required. If
serial data is only written and read back is not needed, then
SDO can be left floating and no pull-up resistor is needed.
Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
GROUNDING AND BYPASSING
The LTC2145-14/LTC2144-14/LTC2143-14 requires a
printed circuit board with a clean unbroken ground plane.
A multilayer board with an internal ground plane in the
first layer beneath the ADC is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass
capacitors must be located as close to the pins as pos-
sible. Size 0402 ceramic capacitors are recommended. The
traces connecting the pins and bypass capacitors must
be kept short and should be made as wide as possible.
Of particular importance is the capacitor between REFH
and REFL. This capacitor should be on the same side of
the circuit board as the A/D, and as close to the device
as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC2145-14/LTC2144-
14/LTC2143-14 is transferred from the die through the
bottom-side exposed pad and package leads onto the
printed circuit board. For good electrical and thermal
performance, the exposed pad must be soldered to a large
grounded pad on the PC board. This pad should be con-
nected to the internal ground planes by an array of vias.
APPLICATIONS INFORMATION
29
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
APPLICATIONS INFORMATION
Table 3. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7 D6 D5 D4 D3 D2 D1 D0
RESETXXXXXXX
Bit 7 RESET Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC is momentarily placed in SLEEP mode. This bit is
automatically set back to zero at the end of the SPI write command. The reset register is write only. Data read back from the reset
register will be random.
Bits 6-0 Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7 D6 D5 D4 D3 D2 D1 D0
XXXXXXPWROFF1 PWROFF0
Bits 7-2 Unused, Don’t Care Bits.
Bits 1-0 PWROFF1:PWROFF0 Power Down Control Bits
00 = Normal Operation
01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode
10 = Channel 1 and Channel 2 in Nap Mode
11 = Sleep Mode
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7 D6 D5 D4 D3 D2 D1 D0
XXXXCLKINV CLKPHASE1 CLKPHASE0 DCS
Bits 7-4 Unused, Don’t Care Bits.
Bit 3 CLKINV Output Clock Invert Bit
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1 CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– Delayed by 45° (Clock Period • 1/8)
10 = CLKOUT+/CLKOUT– Delayed by 90° (Clock Period • 1/4)
11 = CLKOUT+/CLKOUT– Delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT Phase Delay Feature Is Used, the Clock Duty Cycle Stabilizer Must Also Be Turned On
Bit 0 DCS Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
LTC2145-14/
LTC2144-14/LTC2143-14
30
21454314fa
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7 D6 D5 D4 D3 D2 D1 D0
X ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE1 OUTMODE0
Bit 7 Unused, Don’t Care Bit.
Bits 6-4 ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 3 TERMON LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 2× the Current Set by ILVDS2:ILVDS0
Bit 2 OUTOFF Output Disable Bit
0 = Digital Outputs Are Enabled
1 = Digital Outputs Are Disabled and Have High Output Impedance
Note: If the Digital Outputs Are Disabled the Part Should Also Be Put in Sleep or Nap Mode (Both Channels).
Bits 1-0 OUTMODE1:OUTMODE0 Digital Output Mode Control Bits
00 = Full Rate CMOS Output Mode
01 = Double Data Rate LVDS Output Mode
10 = Double Data Rate CMOS Output Mode
11 = Not Used
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7 D6 D5 D4 D3 D2 D1 D0
X X OUTTEST2 OUTTEST1 OUTTEST0 ABP RAND TWOSCOMP
Bit 7-6 Unused, Don’t Care Bits.
Bits 5-3 OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits
000 = Digital Output Test Patterns Off
001 = All Digital Outputs = 0
011 = All Digital Outputs = 1
101 = Checkerboard Output Pattern. OF, D13-D0 Alternate Between 1 01 0101 0101 0101 and 0 10 1010 1010 1010
111 = Alternating Output Pattern. OF, D13-D0 Alternate Between 0 00 0000 0000 0000 and 1 11 1111 1111 1111
Note: Other Bit Combinations Are not Used
Bit 2 ABP Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On. Forces the Output Format to Be Offset Binary
Bit 1 RAND Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 0 TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
APPLICATIONS INFORMATION
31
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
Silkscreen Top
TYPICAL APPLICATIONS
Top Side
LTC2145-14/
LTC2144-14/LTC2143-14
32
21454314fa
TYPICAL APPLICATIONS
Inner Layer 2 GND
Inner Layer 3
33
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5 Power
LTC2145-14/
LTC2144-14/LTC2143-14
34
21454314fa
TYPICAL APPLICATIONS
Bottom Side
35
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D1_2_3+
D1_2_3–
D1_0_1+
D1_0_1–
DNC
DNC
OVDD
OGND
CLKOUT+
CLKOUT–
D2_12_13+
D2_12_13–
D2_10_11+
D2_10_11–
D2_8_9+
D2_8_9–
65
PAD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDD
SENSE
VREF
SDO
OF2_1+
OF2_1–
D1_12_13+
D1_12_13–
D1_10_11+
D1_10_11–
D1_8_9+
D1_8_9–
D1_6_7+
D1_6_7–
D1_4_5+
D1_4_5–
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD
ENC+
ENC–
CS
SCK
SDI
DNC
DNC
D2_0_1–
D2_0_1+
D2_2_3–
D2_2_3+
D2_4_5–
D2_4_5+
D2_6_7–
D2_6_7+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
C19
0.1µF
SDO
SENSE
VDD
VDD
VCM1
GND
AIN1+
AIN1–
GND
REFH
REFL
REFH
REFL
PAR/SER
AIN2+
AIN2–
GND
VCM2
VDD
C20
0.1µF
C18
0.1µF
VDD
PAR/SER
C17
1µF
C23
2.2µF
C37
0.1µF
DIGITAL
OUTPUTS
DIGITAL
OUTPUTS
OVDD
SPI BUS
C67
0.1µF
C78
0.1µF
C79
0.1µF
R51
100
LTC2145-14
ENCODE
CLOCK
CN1
AIN2+
AIN2–
AIN1+
AIN1–
C15
0.1µF
C21
0.1µF
+
+
–
–
–
–
+
+
21454314 TA02
TYPICAL APPLICATIONS
LTC2145-14 Schematic
LTC2145-14/
LTC2144-14/LTC2143-14
36
21454314fa
PACKAGE DESCRIPTION
9 .00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
PIN 1 TOP MARK
(SEE NOTE 5)
0.40 ±0.10
6463
1
2
BOTTOM VIEW—EXPOSED PAD
7.15 ±0.10
7.15 ±0.10
7.50 REF
(4-SIDES)
0.75 ±0.05
R = 0.10
TYP
R = 0.115
TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UP64) QFN 0406 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
7.50 REF
(4 SIDES)
7.15 ±0.05
7.15 ±0.05
8.10 ±0.05 9.50 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
PIN 1
CHAMFER
C = 0.35
UP Package
64-Lead Plastic QFN (9mm w 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
37
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 07/12 Corrected Channel 1 Data Bus (D1_*) Pin Description to state “Channel 1” 16
LTC2145-14/
LTC2144-14/LTC2143-14
38
21454314fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2011
LT 0712 REV A • PRINTED IN USA
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D1_13
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21454314 TA03a
CH 1
ANALOG
INPUT
OUTPUT
DRIVERS
t
t
t
GND OGND
S/H 14-BIT
ADC CORE
CH 2
ANALOG
INPUT
S/H 14-BIT
ADC CORE
D2_13
D2_0
t
t
t
125MHz
CLOCK
CMOS,
DDR CMOS
OR DDR LVDS
OUTPUTS
TYPICAL APPLICATIONS
FREQUENCY (MHz)
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
21454314 TA03b
010 20 30 40 50 60
64k Point 2-Tone FFT, fIN = 69MHz,
70MHz, –1dBFS, 125Msps