2011 Microchip Technology Inc. DS31037B-page 1
PIC24F16KL402 FAMILY
Power Management Modes:
• Run – CPU, Flash, SRAM and Peripherals on
• Doze – CPU Clock Runs Slower than Peripherals
• Idle – CPU Off, SRAM and Peripherals on
• Sleep – CPU, Flash and Peripherals Off and SRAM on
• Low-Power Consumption:
- Run mode currents under 350 µA/MHz at 1.8V
- Idle mode currents under 80 µA/MHz at 1.8V
- Sleep mode currents as low as 30 nA at 25°C
- Watchdog Timer as low as 210 nA at 25°C
High-Performance CPU:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator:
- 4x PLL option
- Multiple divide options
• 17-Bit x 17-Bit Single-Cycle Hardware
Fractional/integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16 x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set
Architecture (ISA):
- 76 base instructions
- Flexible addressing modes
• Linear Program Memory Addressing
• Linear Data Memory Addressing
• Two Address Generation Units (AGU) for Separate
Read and Write Addressing of Data Memory
Peripheral Feat ures:
• High-Current Sink/Source (18 mA/18 mA) on All
I/O Pins
• Configurable Open-Drain Outputs on Digital I/O Pins
• Up to Three External Interrupt Sources
• Two 16-Bit Timer/Counters with Selectable Clock
Sources
• Up to Two 8-Bit Timers/Counters with Programmable
Prescalers
• Two Capture/Compare/PWM (CCP) modules:
- Modules automatically configure and drive I/O
- 16-bit Capture with max. resolution 40 ns
- 16-bit Compare with max. resolution 83.3 ns
- 1-bit to 10-bit PWM resolution
• Up to One Enhanced CCP module:
- Backward compatible with CCP
- 1, 2 or 4 PWM outputs
- Programmable dead time
- Auto-shutdown on external event
• Up to Two Master Synchronous Serial Port modules
(MSSPs) with Two Modes of Operation:
- 3-wire SPI (all four modes)
-I
2C™ Master, Multi-Master and Slave modes and
7-Bit/10-Bit Addressing
• Up to Two UART modules:
- Supports RS-485, RS-232 and LIN/J2602
- On-chip hardware encoder/decoder for IrDA®
- Auto-wake-up on Start bit
- Auto-Baud Detect (ABD)
- Two-byte transmit and receive FIFO buffers
Device Pins
Memory Peripherals
Ultra Low-Power
W ake-up
Flash
Program
(bytes)
Data
(bytes)
Data
EEPROM
(bytes)
10-Bi t A/ D (ch)
Comparators
8/16-Bit
Timers
CCP/ECCP
MSSP
UART w/IrDA®
PIC24F16KL402 28 16K 1024 512 12 2 2/2 2/1 2 2 Y
PIC24F08KL402 28 8K 1024 512 12 2 2/2 2/1 2 2 Y
PIC24F16KL401 20 16K 1024 512 12 2 2/2 2/1 2 2 Y
PIC24F08KL401 20 8K 1024 512 12 2 2/2 2/1 2 2 Y
PIC24F08KL302 28 8K 1024 256 — 2 2/2 2/1 2 2 Y
PIC24F08KL301 20 8K 1024 256 — 2 2/2 2/1 2 2 Y
PIC24F08KL201 20 8K 512 — 12 1 1/2 2/0 1 1 Y
PIC24F08KL200 14 8K 512 — 7 1 1/2 2/0 1 1 Y
PIC24F04KL101 20 4K 512 — — 1 1/2 2/0 1 1 Y
PIC24F04KL100 14 4K 512 — — 1 1/2 2/0 1 1 Y
Low-Power, Low-Cost, General Purpose
16-Bit Flash Microcontrollers with nanoWatt XLP Technology
PIC24F16KL402 FAMILY
DS31037B-page 2 2011 Microchip Technology Inc.
Analog Features:
• 10-Bit, up to 12-Channel Analog-to-Digital (A/D)
Converter:
- 500 ksps conversion rate
- Conversion available during Sleep and Idle
• Dual Rail-to-Rail Analog Comparators with
Programmable Input/Output Configuration
• On-Chip Voltage Reference
S pecial Microcontroller Features:
• Operating Voltage Range of 1.8V to 3.6V
• 10,000 Erase/Write Cycle Endurance Flash Program
Memory, Typical
• 100,000 Erase/Write Cycle Endurance Data
EEPROM, Typical
• Flash and Data EEPROM Data Retention:
40 Years Minimum
• Self-Programmable under Software Control
• Programmable Reference Clock Output
• Fail-Safe Clock Monitor (FSCM) Operation:
- Detects clock failure and switches to on-chip,
low-power RC oscillator
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT):
- Uses its own low-power RC oscillator
- Windowed operating modes
- Programmable period of 2 ms to 131s
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via 2 Pins
• Programmable High/Low-Voltage Detect (HLVD)
• Programmable Brown-out Reset (BOR):
- Configurable for software controlled operation and
shutdown in Sleep mode
- Selectable trip points (1.8V, 2.7V and 3.0V)
- Low-power 2.0V POR re-arm
2011 Microchip Technology Inc. DS31037B-page 3
PIC24F16KL402 FAMILY
Pin Diagrams: PIC24FXXKL302/402
Note 1: Analog features (indicated in red) are not available on PIC24FXXKL302 devices.
2: Alternate location for I2C™ functionality of MSSP1, as determined by the I2C1SEL Configuration bit.
28-Pin SPDIP/SSOP/SOIC(1)
PIC24FXXKL402
MCLR/VPP/RA5
VSS
VDD
VREF+/CVREF+/AN0/SDA2/CN2/RA0
CVREF-/VREF-/AN1/CN3/RA1
VDD
VSS
PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/CN4/RB0
PGEC3/ASCL1(2)/SDO2/CN24/RB6
SOSCO/SCLKI/U2CTS/CN0/RA4
SOSCI/AN15/U2RTS/CN1/RB4
SDI2/CCP3/CN9/RA7
OSCO/AN14/CLKO/CN29/RA3
OSCI/AN13/CLKI/CN30/RA2 C2OUT/CCP1/P1A/INT2/CN8/RA6
U1TX/INT0/CN23/RB7
SDA1/T1CK/U1RTS/P1D/CN21/RB9
SCL1/U1CTS/CN22/RB8
C1INA/C2INC/SCL2/CN7/RB3
AN4/C1INB/C2IND/T3G/U1RX/CN6/RB2
PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AN9/T3CK/REFO/SS1/CN11/RB15
CVREF/AN10/C1OUT/FLT0/INT1/CN12/RB14
AN11/SDO1/CN13/RB13
AN12/HLVDIN/SS2/CCP2/CN14/RB12
PGED2/SDI1/P1B/CN16/RB10
PGEC2/SCK1/P1C/CN15/RB11
PGED3/ASDA1(2)/SCK2/CN27/RB5
PIC24FXXKL302(2)
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
24FXXKL402
5
4
MCLR/ VPP/RA5
VSS
VDD
VREF+/CVREF+/AN0/SDA2/CN2/RA0
CVREF-/VREF-/AN1/CN3/RA1
VDD
VSS
PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/CN4/RB0
PGEC3/ASCL1(2)/SDO2/CN24/RB6
SOSCO/SCLKI/U2CTS/CN0/RA4
SOSCI/AN15/U2RTS/CN1/RB4
SDI2/CCP3/CN9/RA7
OSCO/AN14/CLKO/CN29/RA3
OSCI/AN13/CLKI/CN30/RA2
C2OUT/CCP1/P1A/INT2/CN8/RA6
U1TX/INT0/CN23/RB7
SDA1/T1CK/U1RTS/P1D/CN21/RB9
SCL1/U1CTS/CN22/RB8
C1INA/C2INC/SCL2/CN7/RB3
AN4/C1INB/C2IND/T3G/U1RX/CN6/RB2
PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
AN9/T3CK/REFO/SS1/CN11/RB15
CVREF/AN10/C1OUT/FLT0/INT1/CN12/RB14
AN11/SDO1/CN13/RB13
AN12/HLVDIN/SS2/CCP2/CN14/RB12
PGED2/SDI1/P1B/CN16/RB10
PGEC2/SCK1/P1C/CN15/RB11
PGED3/ASDA1(2)/SCK2/CN27/RB5
24FXXKL302(2)
28-Pin QFN(1)
Contact your Microchip sales team for Chip Scale Package (CSP) availability.
PIC24F16KL402 FAMILY
DS31037B-page 4 2011 Microchip Technology Inc.
Pin Diagrams: PIC24FXXKL301/401
Note 1: Analog features (indicated in red) are not available on PIC24FXXKL301 devices.
20-Pin QFN(1)
89
2
3
1
12
13
14
15
106
11
1617181920
7
5
4
OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3
PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/P1C/CN4/RB0
OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2
AN4/T3G/U1RX/CN6/RB2
PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
U1TX/INT0/CN23/RB7
SDA1/T1CK/U1RTS/CCP3/CN21/RB9
PGEC3/SOSCO/SCLKI/U2CTS/CN0/RA4
PGED3/SOSCI/AN15/U2RTS/CN1/RB4
SCL1/U1CTS/SS1/CN22/RB8
AN12/HLVDIN/SCK1/SS2/CCP2/CN14/RB12
AN11/SDO1/P1D/CN13/RB13
C2OUT/CCP1/P1A/INT2/CN8/RA6
CVREF/AN10/SDI1/C1OUT/FLT0/INT1/CN12/RB14
AN9/SCL2/T3CK/REFO/SCK2/CN11/RB15
PGED2/CVREF-/VREF-/AN1/SDO2/CN3/RA1
PGEC2/VREF+/CVREF+/AN0/SDA2/SDI2/CN2/RA0
MCLR/VPP/RA5
VDD
VSS
20-Pin SPDIP/SSOP/SOIC(1)
PIC24FXXKL301(2)
MCLR/VPP/RA5
OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3
PGEC2/VREF+/CVREF+/AN0/SDA2/SDI2/CN2/RA0
PGED2/CVREF-/VREF-/AN1/SDO2/CN3/RA1
VDD
VSS
PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/P1C/CN4/RB0
U1TX/INT0/CN23/RB7
PGEC3/SOSCO/SCLKI/U2CTS/CN0/RA4
PGED3/SOSCI/AN15/U2RTS/CN1/RB4 SCL1/U1CTS/SS1/CN22/RB8
OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2
AN4/T3G/U1RX/CN6/RB2
PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AN9/SCL2/T3CK/REFO/SCK2/CN11/RB15
CVREF/AN10/SDI1/C1OUT/FLT0/INT1/CN12/RB14
AN11/SDO1/P1D/CN13/RB13
AN12/HLVDIN/SCK1/SS2/CCP2/CN14/RB12
SDA1/T1CK/U1RTS/CCP3/CN21/RB9
C2OUT/CCP1/P1A/INT2/CN8/RA6
PIC24FXXKL401
PIC24FXXKL301
(2)
PIC24FXXKL401
2011 Microchip Technology Inc. DS31037B-page 5
PIC24F16KL402 FAMILY
Pin Diagrams: PIC24FXXKL10X/20X
20-Pin QFN(1)
89
2
3
1
12
13
14
15
106
11
1617181920
7
5
4
OSCO/AN14/C1INA/CLKO/CN29/RA3
PGED1/AN2/ULPWU/C1IND/CN4/RB0
OSCI/AN13/C1INB/CLKI/CN30/RA2
AN4/T3G/U1RX/CN6/RB2
PGEC1/AN3/C1INC/CN5/RB1
U1TX/INT0/CN23/RB7
SDA1/T1CK/U1RTS/CN21/RB9
PGEC3/SOSCO/SCLKI/CN0/RA4
PGED3/SOSCI/AN15/CN1/RB4
SCL1/U1CTS/SS1/CN22/RB8
AN12/HLVDIN/SCK1/CCP2/CN14/RB12
AN11/SDO1/CN13/RB13
CCP1/INT2/CN8/RA6
CVREF/AN10/SDI1/C1OUT/INT1/CN12/RB14
AN9/T3CK/REFO/CN11/RB15
PGED2/CVREF-/VREF-/AN1/CN3/RA1
PGEC2/VREF+/CVREF+/AN0/CN2/RA0
MCLR/VPP/RA5
VDD
VSS
Note 1: Analog features (indicated in red) are not available on PIC24FXXKL100/101 devices.
20-Pin SPDIP/SSOP/SOIC(1)
PIC24FXXKL101(2)
MCLR/VPP/RA5
OSCO/AN14/C1INA/CLKO/CN29/RA3
PGEC2/VREF+/CVREF+/AN0/CN2/RA0
PGED2/CVREF-/VREF-/AN1/CN3/RA1
VDD
VSS
PGED1/AN2/ULPWU/C1IND/CN4/RB0
U1TX/INT0/CN23/RB7
PGEC3/SOSCO/SCLKI/CN0/RA4
PGED3/SOSCI/AN15/CN1/RB4 SCL1/U1CTS/SS1/CN22/RB8
OSCI/AN13/C1INB/CLKI/CN30/RA2
AN4/T3G/U1RX/CN6/RB2
PGEC1/AN3/C1INC/CN5/RB1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AN9/T3CK/REFO/CN11/RB15
CVREF/AN10/SDI1/C1OUT/INT1/CN12/RB14
AN11/SDO1/CN13/RB13
AN12/HLVDIN/SCK1/CCP2/CN14/RB12
SDA1/T1CK/U1RTS/CN21/RB9
CCP1/INT2/CN8/RA6
PIC24FXXKL201
MCLR/VPP/RA5
PGEC2/VREF+/CVREF+/AN0/CN2/RA0
PGED2/CVREF-/VREF-/AN1/ULPWU/CN3/RA1
VDD
VSS
OSCI/AN13/C1INB/CLKI/CN30/RA2
PGEC3/SOSCO/SCLKI/CN0/RA4
PGED3/SOSCI/AN15/HLVDIN/CN1/RB4
OSCO/AN14/C1INA/CLKO/CN29/RA3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
AN9/T3CK/REFO/U1RX/SS1/INT0/CN11/RB15
CVREF/AN10/T3G/U1TX/SDI1/C1OUT/INT1/CN12/RB14
CCP1/INT2/CN8/RA6
SDA1/T1CK/U1RTS/SDO1/CCP2/CN21/RB9
SCL1/U1CTS/SCK1/CN22/RB8
14-Pin PDIP(1)
PIC24FXXKL101
(2)
PIC24FXXKL201
PIC24FXXKL100(2)
PIC24FXXKL200
PIC24F16KL402 FAMILY
DS31037B-page 6 2011 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 21
3.0 CPU ........................................................................................................................................................................................... 25
4.0 Memory Organization ................................................................................................................................................................. 31
5.0 Flash Program Memory.............................................................................................................................................................. 47
6.0 Data EEPROM Memory ............................................................................................................................................................. 53
7.0 Resets ........................................................................................................................................................................................ 59
8.0 Interrupt Controller ..................................................................................................................................................................... 65
9.0 Oscillator Configuration .............................................................................................................................................................. 95
10.0 Power-Saving Features............................................................................................................................................................ 105
11.0 I/O Ports ................................................................................................................................................................................... 111
12.0 Timer1 ..................................................................................................................................................................................... 115
13.0 Timer2 Module ......................................................................................................................................................................... 117
14.0 Timer3 Module ......................................................................................................................................................................... 119
15.0 Timer4 Module ......................................................................................................................................................................... 123
16.0 Capture/Compare/PWM (CCP) and Enhanced CCP Modules................................................................................................. 125
17.0 Master Synchronous Serial Port (MSSP) ................................................................................................................................. 135
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 149
19.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 157
20.0 Comparator Module.................................................................................................................................................................. 167
21.0 Comparator Voltage Reference................................................................................................................................................ 171
22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 173
23.0 Special Features ...................................................................................................................................................................... 175
24.0 Development Support............................................................................................................................................................... 187
25.0 Instruction Set Summary .......................................................................................................................................................... 191
26.0 Electrical Characteristics .......................................................................................................................................................... 199
27.0 Packaging Information.............................................................................................................................................................. 225
Appendix A: Revision History............................................................................................................................................................. 249
Index .................................................................................................................................................................................................. 251
The Microchip Web Site ..................................................................................................................................................................... 255
Customer Change Notification Service .............................................................................................................................................. 255
Customer Support .............................................................................................................................................................................. 255
Reader Response .............................................................................................................................................................................. 256
Product Identification System............................................................................................................................................................. 257
2011 Microchip Technology Inc. DS31037B-page 7
PIC24F16KL402 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer No tific atio n Syst em
Register on our web site at www.microchip.com to receive the most current information on all of our products.
PIC24F16KL402 FAMILY
DS31037B-page 8 2011 Microchip Technology Inc.
NOTES:
2011 Microchip Technology Inc. DS31037B-page 9
PIC24F16KL402 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
The PIC24F16KL402 family adds an entire range of
economical, low pin count and low-power devices to
Microchip’s portfolio of 16-bit microcontrollers. Aimed
at applications that require low-power consumption but
more computational ability than an 8-bit platform can
provide, these devices offer a range of tailored
peripheral sets that allow the designer to optimize both
price point and features with no sacrifice of
functionality.
1.1 Core Features
1.1.1 16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® digital signal controllers. The PIC24F CPU core
offers a wide range of enhancements, such as:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 64 Kbytes (data)
• A 16-element working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32-bit by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as C
• Operational performance up to 16 MIPS
1.1.2 POWER-SAVING TECHNOLOGY
All of the devices in the PIC24F16KL402 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
features include:
•On-the-Fly Clock Switching: The device clock
can be changed under software control to the
Timer1 source, or the internal, low-power RC
oscillator during operation, allowing the user to
incorporate power-saving ideas into their software
designs.
•Doze Mode Operation: When timing-sensitive
applications, such as serial communications,
require the uninterrupted operation of peripherals,
the CPU clock speed can be selectively reduced,
allowing incremental power savings without
missing a beat.
•Instruction-Bas ed Pow er-Saving Mod es: The
microcontroller can suspend all operations, or
selectively shut down its core while leaving its
peripherals active, with a single instruction in
software.
1.1.3 OSCILLATOR OPTIONS AND
FEATURES
The PIC24F16KL402 family offers five different
oscillator options, allowing users a range of choices in
developing application hardware. These include:
• Two Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of a
divide-by-2 clock output.
• Two Fast Internal Oscillators (FRCs): One with a
nominal 8 MHz output and the other with a
nominal 500 kHz output. These outputs can also
be divided under software control to provide clock
speed as low as 31 kHz or 2 kHz.
• A Phase Locked Loop (PLL) frequency multiplier,
available to the External Oscillator modes and the
8 MHz FRC Oscillator, which allows clock speeds
of up to 32 MHz.
• A separate Internal RC Oscillator (LPRC) with a
fixed 31 kHz output, which provides a low-power
option for timing-insensitive applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the
internal oscillator and enables the controller to switch to
the internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
1.1.4 EASY MIGRATION
Regardless of the memory size, all the devices share
the same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also helps in migrating to the next larger
device. This is true when moving between devices with
the same pin count, or even jumping from 20-pin or
28-pin devices to 44-pin/48-pin devices.
The PIC24F family is pin compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow, from the relatively
simple, to the powerful and complex.
• PIC24F04KL100 • PIC24F04KL101
• PIC24F08KL200 • PIC24F08KL201
• PIC24F08KL301 • PIC24F08KL302
• PIC24F08KL401 • PIC24F16KL401
• PIC24F08KL402 • PIC24F16KL402
PIC24F16KL402 FAMILY
DS31037B-page 10 2011 Microchip Technology Inc.
1.2 Other Special Features
•Communications: The PIC24F16KL402 family
incorporates multiple serial communication
peripherals to handle a range of application
requirements. The MSSP module implements
both SPI and I2C™ protocols, and supports both
Master and Slave modes of operation for each.
Devices also include one of two UARTs with
built-in IrDA® encoders/decoders.
•Analog Features: Select members of the
PIC24F16KL402 family include a 10-bit A/D
Converter module. The A/D module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, as
well as faster sampling speeds.
The comparator modules are configurable for a
wide range of operations and can be used as
either a single or double comparator module.
1.3 Details on Individual Family
Members
Devices in the PIC24F16KL402 family are available in
14-pin, 20-pin and 28-pin packages. The general block
diagram for all devices is shown in Figure 1-1.
The PIC24F16KL402 family may be thought of as four
different device groups, each offering a slightly different
set of features. These differ from each other in multiple
ways:
• The size of the Flash program memory
• The presence and size of data EEPROM
• The presence of an A/D Converter and the
number of external analog channels available
• The number of analog comparators
• The number of general purpose timers
• The number and type of CCP modules
(i.e., CCP vs. ECCP)
• The number of serial communications modules
(both MMSPs and UARTs)
The general differences between the different
sub-families is shown in Ta bl e 1 - 1 . The feature sets for
specific devices are summarized in Ta b l e 1 - 2 and
Table 1-3.
A list of the individual pin features available on the
PIC24F16KL402 family devices, sorted by function, is
provided in Tab le 1 -4 (for PIC24FXXKL40X/30X
devices) and Tab le 1- 5 (for PIC24FXXKL20X/10X
devices). Note that this table shows the pin location of
individual peripheral features and not how they are
multiplexed on the same pin. This information is
provided in the pinout diagrams in the beginning of this
data sheet. Multiplexed features are sorted by the
priority given to a feature, with the highest priority
peripheral being listed first.
TABLE 1-1: FEATURE COMPARISON FOR PIC24F16KL402 FAMILY GROUPS
Device Group Program
Memory
(bytes)
Data
EEPROM
(bytes)
Timers
(8/16-bit) CCP and
ECCP
Serial
(MSSP/
UART)
A/D
(channels) Comparators
PIC24FXXKL10X 4K — 1/2 2/0 1/1 — 1
PIC24FXXKL20X 8K — 1/2 2/0 1/1 7 or 12 1
PIC24FXXKL30X 8K 256 2/2 2/1 2/2 — 2
PIC24FXXKL40X 8K or 16K 512 2/2 2/1 2/2 12 2
2011 Microchip Technology Inc. DS31037B-page 11
PIC24F16KL402 FAMILY
TABLE 1-2: DEVICE FEATURES FOR PIC24F16KL40X/30X DEVICES
Features
PIC24F16KL402
PIC24F08KL402
PIC24F08KL302
PIC24F16KL401
PIC24F08KL401
PIC24F08KL301
Operating Frequency DC – 32 MHz
Program Memory (bytes) 16K 8K 8K 16K 8K 8K
Program Memory (instructions) 5632 2816 2816 5632 2816 2816
Data Memory (bytes) 1024 1024 1024 1024 1024 1024
Data EEPROM Memory (bytes) 512 512 256 512 512 256
Interrupt Sources
(soft vectors/NMI traps)
31 (27/4) 31 (27/4) 30 (26/4) 31 (27/4) 31 (27/4) 30 (26/4)
I/O Ports PORTA<7:0>
PORTB<15:0>
PORTA<6:0>
PORTB<15:12,9:7,4,2:0>
Total I/O Pins 24 18
Timers (8/16-bit) 2/2 2/2 2/2 2/2 2/2 2/2
Capture/Compare/PWM modules:
Total 333333
Enhanced CCP 111111
Input Change Notification Interrupt 23 23 23 17 17 17
Serial Communications:
UART 222222
MSSP 222222
10-Bit Analog-to-Digital Module
(input channels)
12 12 — 12 12 —
Analog Comparators 2 2 2 2 2 2
Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode,
REPEAT Instruction, Hardware Traps, Configuration Word Mismatch
( P W RT, O S T, PL L L oc k)
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 28-Pin PDIP/SSOP/SOIC/QFN 20-Pin SPDIP/SSOP/SOIC/QFN
PIC24F16KL402 FAMILY
DS31037B-page 12 2011 Microchip Technology Inc.
TABLE 1-3: DEVICE FEATURES FOR THE PIC24F16KL20X/10X DEVICES
Features
PIC24F08KL201
PIC24F04KL101
PIC24F08KL200
PIC24F04KL100
Operating Frequency DC – 32 MHz
Program Memory (bytes) 8K4K8K4K
Program Memory (instructions) 2816 1408 2816 1408
Data Memory (bytes) 512 512 512 512
Data EEPROM Memory (bytes) — — — —
Interrupt Sources
(soft vectors/NMI traps)
27 (23/4) 26 (22/4) 27 (23/4) 26 (22/4)
I/O Ports PORTA<6:0>
PORTB<15:12,9:7,4,2:0>
PORTA<5:0>
PORTB<15:14,9:8,4,0>
Total I/O Pins 17 12
Timers (8/16-bit) 1/2 1/2 1/2 1/2
Capture/Compare/PWM modules:
Total 2 2 2 2
Enhanced CCP 0 0 0 0
Input Change Notification Interrupt 17 17 11 11
Serial Communications:
UART 1 1 1 1
MSSP 1 1 1 1
10-Bit Analog-to-Digital Module
(input channels)
12 — 7 —
Analog Comparators 1 1 1 1
Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode,
REPEAT Instruction, Hardware Traps, Configuration Word Mismatch
(PWRT, OST, PLL Lock)
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 20-Pin SPDIP/SSOP/SOIC/QFN 14-Pin PDIP/TSSOP
2011 Microchip Technology Inc. DS31037B-page 13
PIC24F16KL402 FAMILY
FIGURE 1-1: PIC24F16 KL402 FAMILY GENERAL BLOCK DIAGRAM
Instruction
Decode and
Control
16
PCH PCL
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
16
Divide
Support
Inst Latch
16
EA MUX
Read AGU
Write AGU
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Program Memory
Data Latch
16
Address Bus
Literal Data
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
PORTA(1)
RA<0:7>
PORTB(1)
RB<0:15>
Note 1: All pins or features are not implemented on all device pinout configurations. See Table 1-4 and Table 1-5 for
I/O port pin descriptions.
ComparatorsTimer4
Timer3
CCP2
A/D
10-Bit
CCP3(1) MSSP CN1-23(1)
UART
Data EEPROM
OSCI/CLKI
OSCO/CLKO
VDD,
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR
FRC/LPRC
Oscillators
Timer2Timer1
CCP1/ HLVD
Precision
Reference
Band Gap
ECCP1(1)
ULPWU
VSS
ULPWU
1/2(1) 1/2(1)
PIC24F16KL402 FAMILY
DS31037B-page 14 2011 Microchip Technology Inc.
TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS
Function
Pin Number
I/O Buffer Description
20-Pin
PDIP/
SSOP/
SOIC
20-Pin
QFN
28-Pin
SPDIP/
SSOP/
SOIC
28-Pin
QFN
AN0 2 19 2 27 I ANA A/D Analog Inputs. Not available on PIC24F16KL30X
family devices.
AN1 3 20 3 28 I ANA
AN2 4141IANA
AN3 5252IANA
AN4 6363IANA
AN5 — — 7 4 I ANA
AN9 18 15 26 23 I ANA
AN10 17 14 25 22 I ANA
AN11 16 13 24 21 I ANA
AN12 15 12 23 20 I ANA
AN13 7496IANA
AN14 8 5 10 7 I ANA
AN15 9 6 11 8 I ANA
ASCL1 — — 15 12 I/O I2C™ Alternate MSSP1 I2C Clock Input/Output
ASDA1 — — 14 11 I/O I2C Alternate MSSP1 I2C Data Input/Output
AVDD 20 17 28 25 I ANA Positive Supply for Analog modules
AVSS 19 16 27 24 I ANA Ground Reference for Analog modules
CCP1 14 11 20 17 I/O ST CCP1/ECCP1 Capture Input/Compare and PWM
Output
CCP2 15 12 23 20 I/O ST CCP2 Capture Input/Compare and PWM Output
CCP3 13 10 19 16 I/O ST CCP3 Capture Input/Compare and PWM Output
C1INA 8574IANAComparator 1 Input A (+)
C1INB 7463IANAComparator 1 Input B (-)
C1INC 5252IANAComparator 1 Input C (+)
C1IND 4141IANAComparator 1 Input D (-)
C1OUT 17 14 25 22 O — Comparator 1 Output
C2INA 5252IANAComparator 2 Input A (+)
C2INB 4141IANAComparator 2 Input B (-)
C2INC 8574IANAComparator 2 Input C (+)
C2IND 7463IANAComparator 2 Input D (-)
C2OUT 14 11 20 17 O — Comparator 2 Output
CLK I 7496IANAMain Clock Input
CLKO 8 5 10 7 O — System Clock Output
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C™/SMBus input buffer
2011 Microchip Technology Inc. DS31037B-page 15
PIC24F16KL402 FAMILY
CN0 10 7 12 9 I ST Interrupt-on-Change Inputs
CN1 9 6 11 8 I ST
CN2 2 19 2 27 I ST
CN3 3 20 3 28 I ST
CN4 4141IST
CN5 5252IST
CN6 6363IST
CN7 — — 7 4 I ST
CN8 14 11 20 17 I ST
CN9 — — 19 16 I ST
CN11 18 15 26 23 I ST
CN12 17 14 25 22 I ST
CN13 16 13 24 21 I ST
CN14 15 12 23 20 I ST
CN15 — — 22 19 I ST
CN16 — — 21 18 I ST
CN21 13 10 18 15 I ST
CN22 12 9 17 14 I ST
CN23 11 8 16 13 I ST
CN24 — — 15 12 I ST
CN27 — — 14 11 I ST
CN29 8 5 10 7 I ST
CN30 7496IST
CVREF 17 14 25 22 I ANA Comparator Voltage Reference Output
CVREF+ 2 19 2 27 I ANA Comparator Reference Positive Input Voltage
CVREF- 3 20 3 28 I ANA Comparator Reference Negative Input Voltage
FLT0 17 14 25 22 I ST ECCP1 Enhanced PWM Fault Input
HLVDIN 15 12 23 20 I ST High/Low-Voltage Detect Input
INT0 11 8 16 13 I ST Interrupt 0 Input
INT1 17 14 25 22 I ST Interrupt 1 Input
INT2 14 11 20 17 I ST Interrupt 2 Input
MCLR 1 18 1 26 I ST Master Clear (device Reset) Input. This line is
brought low to cause a Reset.
OSCI 7496IANAMain Oscillator Input
OSCO 8 5 10 7 O ANA Main Oscillator Output
P1A 14 11 20 17 O — ECCP1 Output A (Enhanced PWM Mode)
P1B 5 2 21 18 O — ECCP1 Output B (Enhanced PWM Mode)
P1C 4 1 22 19 O — ECCP1 Output C (Enhanced PWM Mode)
P1D 16 13 18 15 O — ECCP1 Output D (Enhanced PWM Mode)
TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O Buffer Description
20-Pin
PDIP/
SSOP/
SOIC
20-Pin
QFN
28-Pin
SPDIP/
SSOP/
SOIC
28-Pin
QFN
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C™/SMBus input buffer
PIC24F16KL402 FAMILY
DS31037B-page 16 2011 Microchip Technology Inc.
PGEC1 5252I/OSTICSP™ Clock 1
PCED1 4141I/OSTICSP Data 1
PGEC2 2 19 22 19 I/O ST ICSP Clock 2
PGED2 3 20 21 18 I/O ST ICSP Data 2
PGEC3 10 7 15 12 I/O ST ICSP Clock 3
PGED3 9 6 14 11 I/O ST ICSP Data 3
RA0 2 19 2 27 I/O ST PORTA Pins
RA1 320328I/OST
RA2 7496I/OST
RA3 8 5 10 7 I/O ST
RA4 10 7 12 9 I/O ST
RA5 118126IST
RA6 14 11 20 17 I/O ST
RA7 — — 19 16 I/O ST
RB0 4141I/OSTPORTB Pins
RB1 5252I/OST
RB2 6363I/OST
RB3 — — 7 4 I/O ST
RB4 9 6 11 8 I/O ST
RB5 — — 14 11 I/O ST
RB6 — — 15 12 I/O ST
RB7 11 8 16 13 I/O ST
RB8 12 9 17 14 I/O ST
RB9 13 10 18 15 I/O ST
RB10 — — 21 18 I/O ST
RB11 — — 22 19 I/O ST
RB12 15 12 23 20 I/O ST
RB13 16 13 24 21 I/O ST
RB14 17 14 25 22 I/O ST
RB15 18 15 26 23 I/O ST
REFO 18 15 26 23 O — Reference Clock Output
SCK1 15 12 22 19 I/O ST MSSP1 SPI Serial Input/Output Clock
SCK2 18 15 14 11 I/O ST MSSP2 SPI Serial Input/Output Clock
SCL1 12 9 17 14 I/O I2C MSSP1 I2C Clock Input/Output
SCL2 18 15 7 4 I/O I2C MSSP2 I2C Clock Input/Output
SCLKI 10 7 12 9 I ST Digital Secondary Clock Input
SDA1 13 10 18 15 I/O I2C MSSP1 I2C Data Input/Output
SDA2 219227I/OI
2C MSSP2 I2C Data Input/Output
SDI1 17 14 21 18 I ST MSSP1 SPI Serial Data Input
SDI2 2 19 19 16 I ST MSSP2 SPI Serial Data Input
SDO1 16 13 24 21 O — MSSP1 SPI Serial Data Output
SDO2 3 20 15 12 O — MSSP2 SPI Serial Data Output
TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O Buffer Description
20-Pin
PDIP/
SSOP/
SOIC
20-Pin
QFN
28-Pin
SPDIP/
SSOP/
SOIC
28-Pin
QFN
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C™/SMBus input buffer
2011 Microchip Technology Inc. DS31037B-page 17
PIC24F16KL402 FAMILY
SOSCI 9 6 11 8 I ANA Secondary Oscillator Input
SOSCO 10 7 12 9 O ANA Secondary Oscillator Output
SS1 12 9 26 23 O — SPI1 Slave Select
SS2 15 12 23 20 O — SPI2 Slave Select
T1CK 13 10 18 15 I ST Timer1 Clock
T3CK 18 15 26 23 I ST Timer3 Clock
T3G 6363ISTTimer3 External Gate Input
U1CTS 12 9 17 14 I ST UART1 Clear-to-Send Input
U1RTS 13 10 18 15 O — UART1 Request-to-Send Output
U1RX 6363ISTUART1 Receive
U1TX 11 8 16 13 O — UART1 Transmit
U2CTS 10 7 12 9 I ST UART2 Clear-to-Send Input
U2RTS 9 6 11 8 O — UART2 Request-to-Send Output
U2RX 5252ISTUART2 Receive
U2TX 4141O—UART2 Transmit
ULPWU 4141IANAUltra Low-Power Wake-up Input
VDD 20 17 13, 28 10, 25 P — Positive Supply for Peripheral Digital Logic and
I/O Pins
VREF+ 2 19 2 27 I ANA A/D Reference Voltage Input (+)
VREF- 3 20 3 28 I ANA A/D Reference Voltage Input (-)
VSS 19 16 8, 27 5, 24 P — Ground Reference for Logic and I/O Pins
TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O Buffer Description
20-Pin
PDIP/
SSOP/
SOIC
20-Pin
QFN
28-Pin
SPDIP/
SSOP/
SOIC
28-Pin
QFN
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C™/SMBus input buffer
PIC24F16KL402 FAMILY
DS31037B-page 18 2011 Microchip Technology Inc.
TABLE 1-5: PIC24F16KL20X/10X FAMILY PINOUT DESCRIPTIONS
Function
Pin Nu mber
I/O Buffer Description
20-Pin
PDIP/
SSOP/
SOIC
20-Pin
QFN
14-Pin
PDIP/
TSSOP
AN0 2 19 2 I ANA A/D Analog Inputs. Not available on PIC24F16KL10X
family devices.
AN1 3 20 3 I ANA
AN2 4 1 — I ANA
AN3 5 2 — I ANA
AN4 6 3 — I ANA
AN9 18 15 12 I ANA
AN10 17 14 11 I ANA
AN11 16 13 — I ANA
AN12 15 12 — I ANA
AN13 7 4 4 I ANA
AN14 8 5 5 I ANA
AN15 9 6 6 I ANA
AVDD 20 17 14 I ANA Positive Supply for Analog modules
AVSS 19 16 13 I ANA Ground Reference for Analog modules
CCP1 14 11 10 I/O ST CCP1 Capture Input/Compare and PWM Output
CCP2 15 12 9 I/O ST CCP2 Capture Input/Compare and PWM Output
C1INA 8 5 5 I ANA Comparator 1 Input A (+)
C1INB 7 4 4 I ANA Comparator 1 Input B (-)
C1INC 5 2 — I ANA Comparator 1 Input C (+)
C1IND 4 1 — I ANA Comparator 1 Input D (-)
C1OUT 17 14 11 O — Comparator 1 Output
CLK I 7 4 9 I ANA Main Clock Input
CLKO 8 5 10 O — System Clock Output
CN0 10 7 7 I ST Interrupt-on-Change Inputs
CN1 9 6 6 I ST
CN2 2 19 2 I ST
CN3 3 20 3 I ST
CN4 4 1 –- I ST
CN5 5 2 –- I ST
CN6 6 3 –- I ST
CN8 14 11 10 I ST
CN9 –- –- –- I ST
CN11 18 15 12 I ST
CN12 17 14 11 I ST
CN13 16 13 –- I ST
CN14 15 12 –- I ST
CN21 13 10 9 I ST
CN22 12 9 8 I ST
CN23 11 8 –- I ST
CN29 8 5 5 I ST
CN30 7 4 4 I ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C™/SMBus input buffer
2011 Microchip Technology Inc. DS31037B-page 19
PIC24F16KL402 FAMILY
CVREF 17 14 11 I ANA Comparator Voltage Reference Output
CVREF+ 2 19 2 I ANA Comparator Reference Positive Input Voltage
CVREF- 3 20 3 I ANA Comparator Reference Negative Input Voltage
HLVDIN 15 12 6 I ST High/Low-Voltage Detect Input
INT0 11 8 12 I ST Interrupt 0 Input
INT1 17 14 11 I ST Interrupt 1 Input
INT2 14 11 10 I ST Interrupt 2 Input
MCLR 1 18 1 I ST Master Clear (device Reset) Input. This line is brought
low to cause a Reset.
OSCI 7 4 4 I ANA Main Oscillator Input
OSCO 8 5 5 O ANA Main Oscillator Output
PGEC1 5 2 — I/O ST ICSP™