YAV4CL2TC14FX - FCI ELECTRONICS

1. General description

The LPC2212/2214 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation

and embedded trace support, together with 128/256 kB of embedded high-speed ﬂash

memory. A 128-bit wide memory interface and a unique accelerator architecture enable

32-bit code execution at maximum clock rate. For critical code size applications, the

alternative 16-bit Thumb mode reduces code by more than 30 % with minimal

performance penalty.

With their 144-pin package, low power consumption, various 32-bit timers, 8-channel

10-bit ADC, PWM channels and up to nine external interrupt pins these microcontrollers

are particularly suitable for industrial control, medical systems, access control and

point-of-sale. Number of available fast GPIOs ranges from up to 76 pins (with external

memory) through up to 112 pins (single-chip). With a wide range of serial communications

interfaces, they are also very well suited for communication gateways, protocol converters

and embedded soft modems as well as many other general-purpose applications.

Remark: Throughout the data sheet, the term LPC2212/2214 will apply to devices with

and without the /00 or /01 sufﬁxes. The /00 or the /01 sufﬁx will be used to differentiate

from other devices only when necessary.

2. Features

2.1 Key features brought by LPC2212/2214/01 devices

nFast GPIO ports enable port pin toggling up to 3.5 times faster than the original device.

They also allow for a port pin to be read at any time regardless of its function.

nDedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are

5 V tolerant when conﬁgured for digital I/O function(s).

nUART0/1 include fractional baud rate generator, auto-bauding capabilities and

handshake ﬂow-control fully implemented in hardware.

nBuffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.

nSPI programmable data length and master mode enhancement.

nDiversiﬁed Code Read Protection (CRP) enables different security levels to be

implemented. This feature is available in LPC2212/2214/00 devices as well.

nGeneral purpose timers can operate as external event counters.

2.2 Key features common for all devices

n16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package.

LPC2212/2214

16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP ﬂash with

10-bit ADC and external memory interface

Rev. 04 — 3 January 2008 Product data sheet

Product data sheet Rev. 04 — 3 January 2008 2 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

n16 kB on-chip static RAM and 128/256 kB on-chip ﬂash program memory. 128-bit wide

interface/accelerator enables high speed 60 MHz operation.

nIn-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or

full chip erase takes 400 ms.

nEmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the

on-chip RealMonitor software as well as high speed real-time tracing of instruction

execution.

nEight-channel 10-bit ADC with conversion time as low as 2.44 µs.

nTwo 32-bit timers (with four capture and four compare channels), PWM unit (six

outputs), Real-Time Clock and Watchdog.

nMultiple serial interfaces including two UARTs (16C550), Fast I2C-bus (400 kbit/s) and

two SPIs.

nVectored Interrupt Controller with conﬁgurable priorities and vector addresses.

nConﬁgurable external memory interface with up to four banks, each up to 16 MB and

8/16/32-bit data width.

nUp to 112 general purpose I/O pins (5 V tolerant). Up to nine edge or level sensitive

external interrupt pins available.

n60 MHz maximum CPU clock available from programmable on-chip Phase-Locked

Loop with settling time of 100 µs.

nOn-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.

nTwo low power modes, Idle and Power-down.

nProcessor wake-up from Power-down mode via external interrupt.

nIndividual enable/disable of peripheral functions for power optimization.

nDual power supply:

uCPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 0.15 V).

uI/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.

3. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

LPC2212FBD144 LQFP144 plastic low proﬁle quad ﬂat package; 144 leads;

body 20 ×20 ×1.4 mm SOT486-1

LPC2212FBD144/00 LQFP144 plastic low proﬁle quad ﬂat package; 144 leads;

body 20 ×20 ×1.4 mm SOT486-1

LPC2212FBD144/01 LQFP144 plastic low proﬁle quad ﬂat package; 144 leads;

body 20 ×20 ×1.4 mm SOT486-1

LPC2214FBD144 LQFP144 plastic low proﬁle quad ﬂat package; 144 leads;

body 20 ×20 ×1.4 mm SOT486-1

LPC2214FBD144/00 LQFP144 plastic low proﬁle quad ﬂat package; 144 leads;

body 20 ×20 ×1.4 mm SOT486-1

LPC2214FBD144/01 LQFP144 plastic low proﬁle quad ﬂat package; 144 leads;

body 20 ×20 ×1.4 mm SOT486-1

Product data sheet Rev. 04 — 3 January 2008 3 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

3.1 Ordering options

Table 2. Ordering options

Type number Flash memory RAM Fast GPIO/

SSP/

Enhanced

UART, ADC,

Timer

Temperature range

LPC2212FBD144 128 kB 16 kB no −40 °C to +85 °C

LPC2212FBD144/00 128 kB 16 kB no −40 °C to +85 °C

LPC2212FBD144/01 128 kB 16 kB yes −40 °C to +85 °C

LPC2214FBD144 256 kB 16 kB no −40 °C to +85 °C

LPC2214FBD144/00 256 kB 16 kB no −40 °C to +85 °C

LPC2214FBD144/01 256 kB 16 kB yes −40 °C to +85 °C

Product data sheet Rev. 04 — 3 January 2008 4 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

4. Block diagram

(1) Shared with GPIO.

(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.

(3) SSP interface and high-speed GPIO are available on LPC2212/01 and LPC2214/01 only.

Fig 1. Block diagram

SCL(1)

P0[30:27],

P0[25:0]

TRST(2)

TMS(2)

TCK(2)

TDI(2)

TDO(2) XTAL2

XTAL1

EINT[3:0](1)

AIN[3:0](1)

AIN[7:4](1)

PWM[6:1](1)

AHB BRIDGE

PLL

PWM0

ARM7TDMI-S

LPC2212

LPC2214

RESET

4 × CAP0(1)

4 × CAP1(1)

4 × MAT0(1)

4 × MAT1(1)

P1[31:16],

P1[1:0]

P2[31:0]

P3[31:0]

SDA(1)

DSR1(1), CTS1(1),

RTS1(1), DTR1(1),

DCD1(1), RI1(1)

RTCK

ARM7 LOCAL BUS

INTERNAL

SRAM

CONTROLLER

INTERNAL

FLASH

CONTROLLER

16 kB

SRAM 128/256 kB

FLASH

EXTERNAL

INTERRUPTS

CAPTURE/

COMPARE

TIMER 0/TIMER 1

A/D CONVERTER

GENERAL

PURPOSE I/O

TEST/DEBUG

INTERFACE

EMULATION

TRACE MODULE

system

clock

SYSTEM

FUNCTIONS

VECTORED

INTERRUPT

CONTROLLER

AHB

DECODER

I2C-BUS SERIAL

INTERFACE

AHB T O APB

BRIDGE APB

DIVIDER

SPI1/SSP(3) SERIAL

INTERFACE

UART0/UART1

WATCHDOG

TIMER

SYSTEM CONTROL

REAL-TIME CLOCK

002aad181

VDD(3V3)

VSS

VDD(1V8)

SCK1(1)

MOSI1(1)

MISO1(1)

SSEL1(1)

SPI0 SERIAL

INTERFACE

SCK0(1)

MOSI0(1)

MISO0(1)

SSEL0(1)

EXTERNAL MEMORY

CONTROLLER BLS[3:0](1)

OE, WE(1)

CS[3:0](1)

A[23:0](1)

D[31:0](1)

RXD[1:0](1)

TXD[1:0](1)

AMBA Advanced High-performance

Bus (AHB)

P0, P1 HIGH-SPEED

GPI/O(3)

48 PINS TOTAL

Product data sheet Rev. 04 — 3 January 2008 5 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

5. Pinning information

5.1 Pinning

(1) Pin conﬁguration is identical for devices with and without /00 and /01 sufﬁxes.

Fig 2. Pin conﬁguration (LQFP144)

LPC2212

LPC2214(1)

108

144

109

002aad182

Product data sheet Rev. 04 — 3 January 2008 6 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

5.2 Pin description

Table 3. Pin description

Symbol Pin Type Description

P0[0] to P0[31] I/O Port 0 is a 32-bit bidirectional I/O port with individual direction controls for

each bit. The operation of port 0 pins depends upon the pin function selected

via the Pin Connect Block.

Pins 26 and 31 of port 0 are not available.

P0[0]/TXD0/PWM1 42 O TXD0 — Transmitter output for UART0.

OPWM1 — Pulse Width Modulator output 1.

P0[1]/RXD0/PWM3/

EINT0 49 I RXD0 — Receiver input for UART0.

OPWM3 — Pulse Width Modulator output 3.

IEINT0 — External interrupt 0 input

P0[2]/SCL/CAP0[0] 50 I/O SCL — I2C-bus clock input/output. Open-drain output (for I2C-bus

compliance).

ICAP0[0] — Capture input for Timer 0, channel 0.

P0[3]/SDA/MAT0[0]/

EINT1 58 I/O SDA — I2C-bus data input/output. Open-drain output (for I2C-bus

compliance).

OMAT0[0] — Match output for Timer 0, channel 0.

IEINT1 — External interrupt 1 input.

P0[4]/SCK0/CAP0[1] 59 I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.

ICAP0[1] — Capture input for Timer 0, channel 1.

P0[5]/MISO0/MAT0[1] 61 I/O MISO0 — Master In Slave OUT for SPI0. Data input to SPI master or data

output from SPI slave.

OMAT0[1] — Match output for Timer 0, channel 1.

P0[6]/MOSI0/CAP0[2] 68 I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data

input to SPI slave.

ICAP0[2] — Capture input for Timer 0, channel 2.

P0[7]/SSEL0/PWM2/

EINT2 69 I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.

OPWM2 — Pulse Width Modulator output 2.

IEINT2 — External interrupt 2 input.

P0[8]/TXD1/PWM4 75 O TXD1 — Transmitter output for UART1.

OPWM4 — Pulse Width Modulator output 4.

P0[9]/RXD1/PWM6/

EINT3 76 I RXD1 — Receiver input for UART1.

OPWM6 — Pulse Width Modulator output 6.

IEINT3 — External interrupt 3 input.

P0[10]/RTS1/CAP1[0] 78 O RTS1 — Request to Send output for UART1.

ICAP1[0] — Capture input for Timer 1, channel 0.

P0[11]/CTS1/CAP1[1] 83 I CTS1 — Clear to Send input for UART1.

ICAP1[1] — Capture input for Timer 1, channel 1.

P0[12]/DSR1/MAT1[0] 84 I DSR1 — Data Set Ready input for UART1.

OMAT1[0] — Match output for Timer 1, channel 0.

P0[13]/DTR1/MAT1[1] 85 O DTR1 — Data Terminal Ready output for UART1.

OMAT1[1] — Match output for Timer 1, channel 1.

Product data sheet Rev. 04 — 3 January 2008 7 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

P0[14]/DCD1/EINT1 92 I DCD1 — Data Carrier Detect input for UART1.

IEINT1 — External interrupt 1 input.

Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take

over control of the part after reset.

P0[15]/RI1/EINT2 99 I RI1 — Ring Indicator input for UART1.

IEINT2 — External interrupt 2 input.

P0[16]/EINT0/MAT0[2]/

CAP0[2] 100 I EINT0 — External interrupt 0 input.

OMAT0[2] — Match output for Timer 0, channel 2.

ICAP0[2] — Capture input for Timer 0, channel 2.

P0[17]/CAP1[2]/SCK1/

MAT1[2] 101 I CAP1[2] — Capture input for Timer 1, channel 2.

I/O SCK1 — Serial Clock for SPI1/SSP[1]. SPI clock output from master or input

to slave.

OMAT1[2] — Match output for Timer 1, channel 2.

P0[18]/CAP1[3]/MISO1/

MAT1[3] 121 I CAP1[3] — Capture input for Timer 1, channel 3.

I/O MISO1 — Master In Slave Out for SPI1/SSP[1]. Data input to SPI master or

data output from SPI slave.

OMAT1[3] — Match output for Timer 1, channel 3.

P0[19]/MAT1[2]/MOSI1/

CAP1[2] 122 O MAT1[2] — Match output for Timer 1, channel 2.

I/O MOSI1 — Master Out Slave In for SPI1/SSP[1]. Data output from SPI master

or data input to SPI slave.

ICAP1[2] — Capture input for Timer 1, channel 2.

P0[20]/MAT1[3]/SSEL1/

EINT3 123 O MAT1[3] — Match output for Timer 1, channel 3.

ISSEL1 — Slave Select for SPI1/SSP[1]. Selects the SPI interface as a slave.

IEINT3 — External interrupt 3 input.

P0[21]/PWM5/CAP1[3] 4 O PWM5 — Pulse Width Modulator output 5.

ICAP1[3] — Capture input for Timer 1, channel 3.

P0[22]/CAP0[0]/MAT0[0] 5 I CAP0[0] — Capture input for Timer 0, channel 0.

OMAT0[0] — Match output for Timer 0, channel 0.

P0[23] 6 I/O General purpose bidirectional digital port only.

P0[24] 8 I/O General purpose bidirectional digital port only.

P0[25] 21 I/O General purpose bidirectional digital port only.

P0[27]/AIN0/CAP0[1]/

MAT0[1] 23 I AIN0 — ADC, input 0. This analog input is always connected to its pin.

ICAP0[1] — Capture input for Timer 0, channel 1.

OMAT0[1] — Match output for Timer 0, channel 1.

P0[28]/AIN1/CAP0[2]/

MAT0[2] 25 I AIN1 — ADC, input 1. This analog input is always connected to its pin.

ICAP0[2] — Capture input for Timer 0, channel 2.

OMAT0[2] — Match output for Timer 0, channel 2.

P0[29]/AIN2/CAP0[3]/

MAT0[3] 32 I AIN2 — ADC, input 2. This analog input is always connected to its pin.

ICAP0[3] — Capture input for Timer 0, Channel 3.

OMAT0[3] — Match output for Timer 0, channel 3.

Table 3. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 04 — 3 January 2008 8 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

P0[30]/AIN3/EINT3/

CAP0[0] 33 I AIN3 — ADC, input 3. This analog input is always connected to its pin.

IEINT3 — External interrupt 3 input.

ICAP0[0] — Capture input for Timer 0, channel 0.

P1[0] to P1[31] I/O Port 1 is a 32-bit bidirectional I/O port with individual direction controls for

each bit. The operation of port 1 pins depends upon the pin function selected

via the Pin Connect Block.

Pins 2 through 15 of port 1 are not available.

P1[0]/CS0 91 O LOW-active Chip Select 0 signal.

(Bank 0 addresses range 0x8000 0000 to 0x80FF FFFF)

P1[1]/OE 90 O LOW-active Output Enable signal.

P1[16]/TRACEPKT0 34 O Trace Packet, bit 0. Standard I/O port with internal pull-up.

P1[17]/TRACEPKT1 24 O Trace Packet, bit 1. Standard I/O port with internal pull-up.

P1[18]/TRACEPKT2 15 O Trace Packet, bit 2. Standard I/O port with internal pull-up.

P1[19]/TRACEPKT3 7 O Trace Packet, bit 3. Standard I/O port with internal pull-up.

P1[20]/TRACESYNC 102 O Trace Synchronization; standard I/O port with internal pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1[25:16] to

operate as Trace port after reset.

P1[21]/PIPESTAT0 95 O Pipeline Status, bit 0. Standard I/O port with internal pull-up.

P1[22]/PIPESTAT1 86 O Pipeline Status, bit 1. Standard I/O port with internal pull-up.

P1[23]/PIPESTAT2 82 O Pipeline Status, bit 2. Standard I/O port with internal pull-up.

P1[24]/TRACECLK 70 O Trace Clock. Standard I/O port with internal pull-up.

P1[25]/EXTIN0 60 I External Trigger Input. Standard I/O with internal pull-up.

P1[26]/RTCK 52 I/O Returned Test Clock output. Extra signal added to the JTAG port. Assists

debugger synchronization when processor frequency varies. Bidirectional pin

with internal pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1[31:26] to

operate as Debug port after reset.

P1[27]/TDO 144 O Test Data out for JTAG interface.

P1[28]/TDI 140 I Test Data in for JTAG interface.

P1[29]/TCK 126 I Test Clock for JTAG interface. This clock must be slower than 1⁄6 of the CPU

clock (CCLK) for the JTAG interface to operate.

P1[30]/TMS 113 I Test Mode Select for JTAG interface.

P1[31]/TRST 43 I Test Reset for JTAG interface.

P2[0] to P2[31] I/O Port 2 is a 32-bit bidirectional I/O port with individual direction controls for

each bit. The operation of port 2 pins depends upon the pin function selected

via the Pin Connect Block.

P2[0]/D0 98 I/O External memory data line 0.

P2[1]/D1 105 I/O External memory data line 1.

P2[2]/D2 106 I/O External memory data line 2.

P2[3]/D3 108 I/O External memory data line 3.

P2[4]/D4 109 I/O External memory data line 4.

P2[5]/D5 114 I/O External memory data line 5.

P2[6]/D6 115 I/O External memory data line 6.

Table 3. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 04 — 3 January 2008 9 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

P2[7]/D7 116 I/O External memory data line 7.

P2[8]/D8 117 I/O External memory data line 8.

P2[9]/D9 118 I/O External memory data line 9.

P2[10]/D10 120 I/O External memory data line 10.

P2[11]/D11 124 I/O External memory data line 11.

P2[12]/D12 125 I/O External memory data line 12.

P2[13]/D13 127 I/O External memory data line 13.

P2[14]/D14 129 I/O External memory data line 14.

P2[15]/D15 130 I/O External memory data line 15.

P2[16]/D16 131 I/O External memory data line 16.

P2[17]/D17 132 I/O External memory data line 17.

P2[18]/D18 133 I/O External memory data line 18.

P2[19]/D19 134 I/O External memory data line 19.

P2[20]/D20 136 I/O External memory data line 20.

P2[21]/D21 137 I/O External memory data line 21.

P2[22]/D22 1 I/O External memory data line 22.

P2[23]/D23 10 I/O External memory data line 23.

P2[24]/D24 11 I/O External memory data line 24.

P2[25]/D25 12 I/O External memory data line 25.

P2[26]/D26/BOOT0 13 I/O D26 — External memory data line 26.

IBOOT0 — While RESET is LOW, together with BOOT1 controls booting and

internal operation. Internal pull-up ensures HIGH state if pin is left

unconnected.

P2[27]/D27/BOOT1 16 I/O D27 — External memory data line 27.

IBOOT1 — While RESET is LOW, together with BOOT0 controls booting and

internal operation. Internal pull-up ensures HIGH state if pin is left

unconnected.

BOOT1:0 = 00 selects 8-bit memory on CS0 for boot.

BOOT1:0 = 01 selects 16-bit memory on CS0 for boot.

BOOT1:0 = 10 selects 32-bit memory on CS0 for boot.

BOOT1:0 = 11 selects internal ﬂash memory.

P2[28]/D28 17 I/O External memory data line 28.

P2[29]/D29 18 I/O External memory data line 29.

P2[30]/D30/AIN4 19 I/O D30 — External memory data line 30.

IAIN4 — ADC, input 4. This analog input is always connected to its pin.

P2[31]/D31/AIN5 20 I/O D31 — External memory data line 31.

IAIN5 — ADC, input 5. This analog input is always connected to its pin.

P3[0] to P3[31] I/O Port 3 is a 32-bit bidirectional I/O port with individual direction controls for

each bit. The operation of port 3 pins depends upon the pin function selected

via the Pin Connect Block.

P3[0]/A0 89 O External memory address line 0.

P3[1]/A1 88 O External memory address line 1.

P3[2]/A2 87 O External memory address line 2.

Table 3. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 04 — 3 January 2008 10 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

P3[3]/A3 81 O External memory address line 3.

P3[4]/A4 80 O External memory address line 4.

P3[5]/A5 74 O External memory address line 5.

P3[6]/A6 73 O External memory address line 6.

P3[7]/A7 72 O External memory address line 7.

P3[8]/A8 71 O External memory address line 8.

P3[9]/A9 66 O External memory address line 9.

P3[10]/A10 65 O External memory address line 10.

P3[11]/A11 64 O External memory address line 11.

P3[12]/A12 63 O External memory address line 12.

P3[13]/A13 62 O External memory address line 13.

P3[14]/A14 56 O External memory address line 14.

P3[15]/A15 55 O External memory address line 15.

P3[16]/A16 53 O External memory address line 16.

P3[17]/A17 48 O External memory address line 17.

P3[18]/A18 47 O External memory address line 18.

P3[19]/A19 46 O External memory address line 19.

P3[20]/A20 45 O External memory address line 20.

P3[21]/A21 44 O External memory address line 21.

P3[22]/A22 41 O External memory address line 22.

P3[23]/A23/XCLK 40 O A23 — External memory address line 23.

OXCLK — Clock output.

P3[24]/CS3 36 O LOW-active Chip Select 3 signal.

(Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF)

P3[25]/CS2 35 O LOW-active Chip Select 2 signal.

(Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF)

P3[26]/CS1 30 O LOW-active Chip Select 1 signal.

(Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF)

P3[27]/WE 29 O LOW-active Write enable signal.

P3[28]/BLS3/AIN7 28 O BLS3 — LOW-active Byte Lane Select signal (Bank 3).

IAIN7 — ADC, input 7. This analog input is always connected to its pin.

P3[29]/BLS2/AIN6 27 O BLS2 — LOW-active Byte Lane Select signal (Bank 2).

IAIN6 — ADC, input 6. This analog input is always connected to its pin.

P3[30]/BLS1 97 O LOW-active Byte Lane Select signal (Bank 1).

P3[31]/BLS0 96 O LOW-active Byte Lane Select signal (Bank 0).

n.c. 22 Pin not connected.

RESET 135 I external reset input; a LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1 142 I input to the oscillator circuit and internal clock generator circuits.

XTAL2 141 O output from the oscillator ampliﬁer.

Table 3. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 04 — 3 January 2008 11 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

[1] SSP interface is available on LPC2212/01 and LPC2214/01 only.

VSS 3, 9, 26,

38, 54, 67,

79, 93,

103, 107,

111, 128

I ground: 0 V reference

VSSA 139 I analog ground; 0 V reference. This should nominally be the same voltage as

VSS, but should be isolated to minimize noise and error.

VSSA(PLL) 138 I PLL analog ground; 0 V reference. This should nominally be the same voltage

as VSS, but should be isolated to minimize noise and error.

VDD(1V8) 37, 110 I 1.8 V core power supply; this is the power supply voltage for internal circuitry.

VDDA(1V8) 143 I analog 1.8 V core power supply; this is the power supply voltage for internal

circuitry. This should be nominally the same voltage as VDD(1V8) but should be

isolated to minimize noise and error.

VDD(3V3) 2, 31, 39,

51, 57, 77,

94, 104,

112, 119

I 3.3 V pad power supply; this is the power supply voltage for the I/O ports

VDDA(3V3) 14 I analog 3.3 V pad power supply; this should be nominally the same voltage as

VDD(3V3) but should be isolated to minimize noise and error

Table 3. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 04 — 3 January 2008 12 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

6. Functional description

Details of the LPC2212/2214 systems and peripheral functions are described in the

following sections.

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers. This simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

•The standard 32-bit ARM set.

•A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-chip ﬂash program memory

The LPC2212/2214 incorporate a 128 kB and 256 kB ﬂash memory system respectively.

This memory may be used for both code and data storage. Programming of the ﬂash

memory may be accomplished in several ways. It may be programmed In System via the

serial port. The application program may also erase and/or program the ﬂash while the

application is running, allowing a great degree of ﬂexibility for data storage ﬁeld ﬁrmware

upgrades, etc. When on-chip bootloader is used, 120/248 kB of ﬂash memory is available

for user code.

The LPC2212/2214 ﬂash memory provides a minimum of 100000 erase/write cycles and

20 years of data retention.

On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the

LPC2212/2214 on-chip ﬂash memory. When the CRP is enabled, the JTAG debug port,

external memory boot and ISP commands accessing either the on-chip RAM or ﬂash

memory are disabled. However, the ISP ﬂash erase command can be executed at any

Product data sheet Rev. 04 — 3 January 2008 13 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

time (no matter whether the CRP is on or off). Removal of CRP is achieved by erasure of

full on-chip user ﬂash. With the CRP off, full access to the chip via the JTAG and/or ISP is

restored.

6.3 On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The SRAM may be

accessed as 8 bit, 16 bit, and 32 bit. The LPC2212/2214 provide 16 kB of static RAM.

6.4 Memory map

The LPC2212/2214 memory maps incorporate several distinct regions, as shown in the

following ﬁgures.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either

ﬂash memory (the default) or on-chip static RAM. This is described in Section 6.18

“System control”.

Product data sheet Rev. 04 — 3 January 2008 14 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

6.5 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and

categorizes them as Fast Interrupt reQuest (FIQ), vectored Interrupt Request (IRQ), and

non-vectored IRQ as deﬁned by programmable settings. The programmable assignment

scheme means that priorities of interrupts from the various peripherals can be dynamically

assigned and adjusted.

The FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC

combines the requests to produce the FIQ signal to the ARM processor. The fastest

possible FIQ latency is achieved when only one request is classiﬁed as FIQ, because then

the FIQ service routine can simply start dealing with that device. But if more than one

request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC

that identiﬁes which FIQ source(s) is (are) requesting an interrupt.

Fig 3. LPC2212/2214 memory map

AHB PERIPHERALS

APB PERIPHERALS

RESERVED ADDRESS SPACE

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP FLASH MEMORY)

RESERVED ADDRESS SPACE

16 kB ON-CHIP STATIC RAM

RESERVED ADDRESS SPACE

256 kB ON-CHIP FLASH MEMORY (LPC2214)

0xFFFF FFFF

0xF000 0000

0xEFFF FFFF

0xE000 0000

0xC000 0000

0xDFFF FFFF

0x8000 0000

0x7FFF FFFF

0x7FFF E000

0x7FFF DFFF

0x4000 4000

0x4000 3FFF

0x4000 0000

0x3FFF FFFF

0x0004 0000

0x0003 FFFF

0x0002 0000

4.0 GB

3.75 GB

3.5 GB

3.0 GB

2.0 GB

1.0 GB

128 kB ON-CHIP FLASH MEMORY (LPC2212) 0x0001 FFFF

0x0000 0000

0.0 GB

002aad183

Product data sheet Rev. 04 — 3 January 2008 15 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned

to this category. Any of the interrupt requests can be assigned to any of the 16 vectored

IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

VIC provides the address of the highest-priority requesting IRQs service routine,

otherwise it provides the address of a default routine that is shared by all the non-vectored

IRQs. The default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has

one interrupt line connected to the Vectored Interrupt Controller, but may have several

internal interrupt ﬂags. Individual interrupt ﬂags may also represent more than one

interrupt source.

Table 4. Interrupt sources

Block Flag(s) VIC channel #

WDT Watchdog Interrupt (WDINT) 0

- Reserved for software interrupts only 1

ARM Core EmbeddedICE, DbgCommRx 2

ARM Core EmbeddedICE, DbgCommTx 3

Timer 0 Match 0 to 3 (MR0, MR1, MR2, MR3) 4

Timer 1 Match 0 to 3 (MR0, MR1, MR2, MR3) 5

UART0 Rx Line Status (RLS)

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

UART1 Rx Line Status (RLS)

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

Modem Status Interrupt (MSI)

PWM0 Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) 8

I2C-bus SI (state change) 9

SPI0 SPIF, MODF 10

SPI1 and SSP[1] SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS 11

PLL PLL Lock (PLOCK) 12

RTC RTCCIF (Counter Increment), RTCALF (Alarm) 13

System Control External Interrupt 0 (EINT0) 14

External Interrupt 1 (EINT1) 15

External Interrupt 2 (EINT2) 16

External Interrupt 3 (EINT3) 17

ADC ADC 18

Product data sheet Rev. 04 — 3 January 2008 16 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

[1] SSP interface available on LPC2212/01 and LPC2214/01 only.

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undeﬁned.

6.7 External memory controller

The external Static Memory Controller (SMC) is a module which provides an interface

between the system bus and external (off-chip) memory devices. It provides support for

up to four independently conﬁgurable memory banks (16 MB each with byte lane enable

control) simultaneously. Each memory bank is capable of supporting SRAM, ROM, ﬂash

EPROM, burst ROM memory, or some external I/O devices.

Each memory bank may be 8-bit, 16-bit, or 32-bit wide.

6.8 General purpose parallel I/O (GPIO) and Fast I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

parallel I/O registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

6.8.1 Features

•Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

•Direction control of individual bits.

•Separate control of output set and clear.

•All I/O default to inputs after reset.

6.8.2 Features added with the Fast GPIO set of registers available on

LPC2212/2214/01 only

•Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O

timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.

•Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

•All Fast GPIO registers are byte addressable.

•Entire port value can be written in one instruction.

•Ports are accessible via either the legacy group of registers (GPIOs) or the group of

registers providing accelerated port access (Fast GPIOs).

Product data sheet Rev. 04 — 3 January 2008 17 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

6.9 10-bit ADC

The LPC2212/2214 each contain a single 10-bit successive approximation ADC with four

multiplexed channels.

6.9.1 Features

•Measurement range of 0 V to 3 V.

•Capable of performing more than 400000 10-bit samples per second.

•Burst conversion mode for single or multiple inputs.

•Optional conversion on transition on input pin or Timer Match signal.

6.9.2 ADC features available in LPC2212/2214/01 only

•Every analog input has a dedicated result register to reduce interrupt overhead.

•Every analog input can generate an interrupt once the conversion is completed.

•The ADC pads are 5 V tolerant when conﬁgured for digital I/O function(s).

6.10 UARTs

The LPC2212/2214 each contain two UARTs. In addition to standard transmit and receive

data lines, the UART1 also provides a full modem control handshake interface.

6.10.1 Features

•16 B Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

•Transmission FIFO control enables implementation of software (XON/XOFF) ﬂow

control on both UARTs.

•UART1 is equipped with standard modem interface signals. This module also

provides full support for hardware ﬂow control (auto-CTS/RTS).

6.10.2 UART features available in LPC2212/2214/01 only

Compared to previous LPC2000 microcontrollers, UARTs in LPC2212/2214/01 introduce

a fractional baud rate generator for both UARTs, enabling these microcontrollers to

achieve standard baud rates such as 115200 Bd with any crystal frequency above 2 MHz.

In addition, auto-CTS/RTS ﬂow-control functions are fully implemented in hardware.

•Fractional baud rate generator enables standard baud rates such as 115200 Bd to be

achieved with any crystal frequency above 2 MHz.

•Auto-bauding.

•Auto-CTS/RTS ﬂow-control fully implemented in hardware.

Product data sheet Rev. 04 — 3 January 2008 18 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

6.11 I2C-bus serial I/O controller

The I2C-bus is a bidirectional bus for inter-IC control using only two wires: a serial clock

line (SCL), and a serial data line (SDA). Each device is recognized by a unique address

and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with

the capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus; it can be

controlled by more than one bus master connected to it.

The I2C-bus implemented in LPC2212/2214 supports a bit rate up to 400 kbit/s (Fast

I2C-bus).

6.11.1 Features

•Standard I2C-bus compliant interface.

•Easy to conﬁgure as Master, Slave, or Master/Slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

•The I2C-bus may be used for test and diagnostic purposes.

6.12 SPI serial I/O controller

The LPC2212/2214 each contain two SPIs. The SPI is a full duplex serial interface,

designed to be able to handle multiple masters and slaves connected to a given bus. Only

a single master and a single slave can communicate on the interface during a given data

transfer. During a data transfer the master always sends a byte of data to the slave, and

the slave always sends a byte of data to the master.

6.12.1 Features

•Compliant with Serial Peripheral Interface (SPI) speciﬁcation.

•Synchronous, Serial, Full Duplex communication.

•Combined SPI master and slave.

•Maximum data bit rate of 1⁄8 of the input clock rate.

6.12.2 Features available in LPC2212/2214/01 only

•Eight to 16 bits per frame.

Product data sheet Rev. 04 — 3 January 2008 19 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

•When the SPI interface is used in Master mode, the SSEL pin is not needed (can be

used for a different function).

6.13 SSP controller (LPC2212/2214/01 only)

The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. Data transfers are in

principle full duplex, with frames of four to 16 bits of data ﬂowing from the master to the

slave and from the slave to the master.

While the SSP and SPI1 peripherals share the same physical pins, it is not possible to

have both of these two peripherals active at the same time. Application can switch on the

ﬂy from SPI1 to SSP and back.

6.13.1 Features

•Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National

Semiconductor’s Microwire buses.

•Synchronous serial communication.

•Master or slave operation.

•8-frame FIFOs for both transmit and receive.

•Four to 16 bits per frame.

6.14 General purpose timers

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

speciﬁed timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

6.14.1 Features

•A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

•Timer or external event counter operation

•Four 32-bit capture channels per timer that can take a snapshot of the timer value

when an input signal transitions. A capture event may also optionally generate an

interrupt.

•Four 32-bit match registers that allow:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Four external outputs per timer corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

Product data sheet Rev. 04 — 3 January 2008 20 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

–Toggle on match.

–Do nothing on match.

6.14.2 Features available in LPC2212/2214/01 only

The LPC2212/2214/01 can count external events on one of the capture inputs if the

external pulse lasts at least one half of the period of the PCLK. In this conﬁguration,

unused capture lines can be selected as regular timer capture inputs, or used as external

interrupts.

•Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied

clock.

•When counting cycles of an externally supplied clock, only one of the timer’s capture

inputs can be selected as the timer’s clock. The rate of such a clock is limited to

PCLK / 4. Duration of high/low levels on the selected CAP input cannot be shorter

than 1 / (2PCLK).

6.15 Watchdog timer

The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the Watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the Watchdog within a predetermined

amount of time.

6.15.1 Features

•Internally resets chip if not periodically reloaded.

•Debug mode.

•Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

•Incorrect/incomplete feed sequence causes reset/interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 32-bit timer with internal prescaler.

•Selectable time period from (Tcy(PCLK) ×256 ×4) to (Tcy(PCLK) ×232 ×4) in multiples of

Tcy(PCLK) × 4.

6.16 Real-time clock

The RTC is designed to provide a set of counters to measure time when normal or idle

operating mode is selected. The RTC has been designed to use little power, making it

suitable for battery powered systems where the CPU is not running continuously (Idle

mode).

6.16.1 Features

•Measures the passage of time to maintain a calendar and clock.

•Ultra low power design to support battery powered systems.

Product data sheet Rev. 04 — 3 January 2008 21 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

•Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

•Programmable reference clock divider allows adjustment of the RTC to match various

crystal frequencies.

6.17 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2212/2214. The Timer is designed to

count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform

other actions when speciﬁed timer values occur, based on seven match registers. The

PWM function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires three

non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (MR0) controls the PWM cycle rate, by resetting the count upon match.

The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a

rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, the MR0 match register controls the PWM cycle rate. The other match registers

control the two PWM edge positions. Additional double edge controlled PWM outputs

require only two match registers each, since the repetition rate is the same for all PWM

outputs.

With double edge controlled PWM outputs, speciﬁc match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

6.17.1 Features

•Seven match registers allow up to six single edge controlled or three double edge

controlled PWM outputs, or a mix of both types.

•The match registers also allow:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the

output is a constant LOW. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

Product data sheet Rev. 04 — 3 January 2008 22 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

•Pulse period and width can be any number of timer counts. This allows complete

ﬂexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

•Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

•Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must ‘release’ new match values before they can become

effective.

•May be used as a standard timer if the PWM mode is not enabled.

•A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

6.18 System control

6.18.1 Crystal oscillator

The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output

frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for

purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is

running and connected. Refer to Section 6.18.2 “PLL” for additional information.

6.18.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled

Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the

multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper

frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so

there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desired output frequency. The output divider may be set to divide

by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and

bypassed following a chip Reset and may be enabled by software. The program must

conﬁgure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a

clock source. The PLL settling time is 100 µs.

6.18.3 Reset and wake-up timer

Reset has two sources on the LPC2212/2214: the RESET pin and Watchdog Reset. The

RESET pin is a Schmitt trigger input pin with an additional glitch ﬁlter. Assertion of chip

Reset by any source starts the Wake-up Timer (see Wake-up Timer description below),

causing the internal chip reset to remain asserted until the external Reset is de-asserted,

the oscillator is running, a ﬁxed number of clocks have passed, and the on-chip ﬂash

controller has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is the Reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

The Wake-up Timer ensures that the oscillator and other analog functions required for

chip operation are fully functional before the processor is allowed to execute instructions.

This is important at power on, all types of Reset, and whenever any of the aforementioned

Product data sheet Rev. 04 — 3 January 2008 23 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the Wake-up Timer.

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of VDD ramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.18.4 Code security (Code Read Protection - CRP)

This feature of the LPC2212/2214 allows the user to enable different levels of security in

the system so that access to the on-chip ﬂash and use of the JTAG and ISP can be

restricted. When needed, CRP is invoked by programming a speciﬁc pattern into a

dedicated ﬂash location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial ﬂash update (excluding

ﬂash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and ﬂash ﬁeld updates are needed but all sectors can not be erased.

CRP2 disables access to chip via the JTAG and only allows full ﬂash erase and update

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too. It

is up to the user’s application to provide (if needed) ﬂash update mechanism using IAP

calls or call reinvoke ISP command to enable ﬂash update via UART0.

Remark: Devices without the sufﬁx /00 or /01 have only a security level equivalent to

CRP2 available.

6.18.5 External interrupt inputs

The LPC2212/2214 include up to nine edge or level sensitive External Interrupt Inputs as

selectable pin functions. When the pins are combined, external events can be processed

as four independent interrupt signals. The External Interrupt Inputs can optionally be used

to wake up the processor from Power-down mode.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 04 — 3 January 2008 24 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

6.18.6 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

ﬂash memory, or to the on-chip static RAM. This allows code running in different memory

spaces to have control of the interrupts.

6.18.7 Power control

The LPC2212/2214 support two reduced power modes: Idle mode and Power-down

mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt

occurs. Peripheral functions continue operation during Idle mode and may generate

interrupts to cause the processor to resume execution. Idle mode eliminates power used

by the processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a Reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

6.18.8 APB

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The ﬁrst

is to provide peripherals with the desired PCLK via APB so that they can operate at the

speed chosen for the ARM processor. In order to achieve this, the APB may be slowed

down to 1⁄2to 1⁄4of the processor clock rate. Because the APB bus must work properly at

power-up (and its timing cannot be altered if it does not work since the APB divider control

registers reside on the APB), the default condition at reset is for the APB to run at 1⁄4of the

processor clock rate. The second purpose of the APB divider is to allow power savings

when an application does not require any peripherals to run at the full processor rate.

Because the APB divider is connected to the PLL output, the PLL remains active (if it was

running) during Idle mode.

6.19 Emulation and debugging

The LPC2212/2214 support emulation and debugging via a JTAG serial port. A trace port

allows tracing program execution. Debugging and trace functions are multiplexed only with

GPIOs on Port 1. This means that all communication, timer and interface peripherals

residing on Port 0 are available during the development and debugging phase as they are

when the application is run in the embedded system itself.

6.19.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote

Debug Protocol commands to the JTAG data needed to access the ARM core.

Product data sheet Rev. 04 — 3 January 2008 25 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with the

host debugger or another separate host without stopping the program ﬂow or even

entering the debug state. The debug communication channel is accessed as a

co-processor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving data

without affecting the normal program ﬂow. The debug communication channel data and

control registers are mapped in to addresses in the EmbeddedICE logic.

The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG

interface to operate.

6.19.2 Embedded trace macrocell

Since the LPC2212/2214 have signiﬁcant amounts of on-chip memory, it is not possible to

determine how the processor core is operating simply by observing the external pins. The

Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply

embedded processor cores. It outputs information about processor execution to the trace

port.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

trace port analyzer must capture the trace information under software debugger control.

Instruction trace (or PC trace) shows the ﬂow of execution of the processor and provides a

list of all the instructions that were executed. Instruction trace is signiﬁcantly compressed

by only broadcasting branch addresses as well as a set of status signals that indicate the

pipeline status on a cycle by cycle basis. Trace information generation can be controlled

by selecting the trigger resource. Trigger resources include address comparators,

counters and sequencers. Since trace information is compressed the software debugger

requires a static image of the code being executed. Self-modifying code can not be traced

because of this restriction.

6.19.3 RealMonitor

RealMonitor is a conﬁgurable software module, developed by ARM Inc., which enables

real time debug. It is a lightweight debug monitor that runs in the background while users

debug their foreground application. It communicates with the host using the DCC (Debug

Communications Channel), which is present in the EmbeddedICE logic. The

LPC2212/2214 contain a speciﬁc conﬁguration of RealMonitor software programmed into

the on-chip ﬂash memory.

Product data sheet Rev. 04 — 3 January 2008 26 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

7. Limiting values

[1] The following applies to Table 5:

a) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to VSS unless

otherwise noted.

[2] Internal rail.

[3] External rail.

[4] Including voltage on outputs in 3-state mode.

[5] Only valid when the VDD(3V3) supply voltage is present.

[6] Not to exceed 4.6 V.

[7] Per supply pin.

[8] The peak current is limited to 25 times the corresponding maximum current.

[9] Per ground pin.

[10] Dependent on package type.

[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

[12] Machine model: equivalent to discharging a 200 pF capacitor through a 0.75 µH coil and a 10 Ω series resistor.

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol Parameter Conditions Min Max Unit

VDD(1V8) supply voltage (1.8 V) [2] −0.5 +2.5 V

VDD(3V3) supply voltage (3.3 V) [3] −0.5 +3.6 V

VDDA(3V3) analog supply voltage (3.3 V) −0.5 +4.6 V

VIA analog input voltage −0.5 +5.1 V

VIinput voltage 5 V tolerant I/O pins [4][5] −0.5 +6.0 V

other I/O pins [4][6] −0.5 VDD(3V3) + 0.5 V

IDD supply current [7][8] - 100 mA

ISS ground current [8][9] - 100 mA

Tjjunction temperature - 150 °C

Tstg storage temperature [10] −65 +150 °C

Ptot(pack) total power dissipation (per

package) based on package heat

transfer,notdevice power

consumption

- 1.5 W

Vesd electrostatic discharge voltage human body model [11]

all pins −2000 +2000 V

machine model [12]

all pins −200 +200 V

Product data sheet Rev. 04 — 3 January 2008 27 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

8. Static characteristics

Table 6. Static characteristics

amb

−

C to +85

C for industrial applications, unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD(1V8) supply voltage (1.8 V) [2] 1.65 1.8 1.95 V

VDD(3V3) supply voltage (3.3 V) [3] 3.0 3.3 3.6 V

VDDA(3V3) analog supply voltage

(3.3 V) 2.5 3.3 3.6 V

Standard port pins, RESET, RTCK

IIL LOW-level input current VI= 0 V; no pull-up - - 3 µA

IIH HIGH-level input current VI=V

DD(3V3); no pull-down - - 3 µA

IOZ OFF-state output current VO=0V; V

O=V

DD(3V3);

no pull-up/down --3µA

Ilatch I/O latch-up current −(0.5VDD(3V3)) < VI <

(1.5VDD(3V3)); Tj < 125 °C100 - - mA

VIinput voltage [4][5][6] 0 - 5.5 V

VOoutput voltage output active 0 - VDD(3V3) V

VIH HIGH-level input voltage 2.0 - - V

VIL LOW-level input voltage - - 0.8 V

Vhys hysteresis voltage - 0.4 - V

VOH HIGH-level output voltage IOH =−4 mA [7] VDD(3V3) − 0.4 - - V

VOL LOW-level output voltage IOL = 4 mA [7] - - 0.4 V

IOH HIGH-level output current VOH =V

DD(3V3) −0.4 V [7] −4--mA

IOL LOW-level output current VOL = 0.4 V [7] 4--mA

IOHS HIGH-level short-circuit

output current VOH =0V [8] --−45 mA

IOLS LOW-level short-circuit

output current VOL =V

DD(3V3) [8] - - 50 mA

Ipd pull-down current VI=5V [9] 10 50 150 µA

Ipu pull-up current VI=0V [10] −15 −50 −85 µA

VDD(3V3) < VI < 5 V [9] 000µA

Power consumption LPC2212, LPC2212/00, LPC2214, LPC2214/00

IDD(act) active mode supply current VDD(1V8) = 1.8 V;

CCLK = 60 MHz;

Tamb =25°C; code

while(1){}

executed from ﬂash; all

peripherals enabled via

PCONP[11] register but not

conﬁgured to run

-60-mA

IDD(pd) Power-down mode supply

current VDD(1V8) = 1.8 V;

Tamb =25°C-10-µA

VDD(1V8) = 1.8 V;

Tamb =85°C- 110 500 µA

Product data sheet Rev. 04 — 3 January 2008 28 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[2] Internal rail.

[3] External rail.

[4] Including voltage on outputs in 3-state mode.

[5] VDD(3V3) supply voltages must be present.

[6] 3-state outputs go into 3-state mode when VDD(3V3) is grounded.

[7] Accounts for 100 mV voltage drop in all supply lines.

[8] Only allowed for a short time period.

[9] Minimum condition for VI= 4.5 V, maximum condition for VI= 5.5 V.

[10] Applies to P1[25:16].

[11] See the

LPC2114/2124/2212/2214 User Manual

[12] To VSS.

Power consumption LPC2212/01 and LPC2214/01

IDD(act) active mode supply current VDD(1V8) = 1.8 V;

CCLK = 60 MHz;

Tamb =25°C; code

while(1){}

executed from ﬂash; all

peripherals enabled via

PCONP[11] register but not

conﬁgured to run

-41-mA

IDD(idle) Idle mode supply current VDD(1V8) = 1.8 V;

CCLK = 60 MHz;

Tamb =25°C;

executed from ﬂash; all

peripherals enabled via

PCONP[11] register but not

conﬁgured to run

- 6.5 - mA

IDD(pd) Power-down mode supply

current VDD(1V8) = 1.8 V;

Tamb =25°C-10-µA

VDD(1V8) = 1.8 V;

Tamb =85°C- - 180 µA

I2C-bus pins

VIH HIGH-level input voltage 0.7VDD(3V3) --V

VIL LOW-level input voltage - - 0.3VDD(3V3) V

Vhys hysteresis voltage - 0.5VDD(3V3) -V

VOL LOW-level output voltage IOLS = 3 mA [7] - - 0.4 V

ILI input leakage current VI=V

DD(3V3) [12] -24µA

VI=5V - 10 22 µA

Oscillator pins

Vi(XTAL1) input voltage on pin XTAL1 0 - 1.8 V

Vo(XTAL2) output voltage on pin

XTAL2 0 - 1.8 V

Table 6. Static characteristics

…continued

amb

−

C to +85

C for industrial applications, unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 04 — 3 January 2008 29 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

[1] Conditions: VSSA =0V, V

DDA = 3.3 V.

[2] The ADC is monotonic, there are no missing codes.

[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 4.

[4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 4.

[5] The offset error (EO) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 4.

[6] The gain error (EG) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 4.

[7] The absolute voltage error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the

non-calibrated ADC and the ideal transfer curve. See Figure 4.

Table 7. ADC static characteristics

DDA

= 2.5 V to 3.6 V unless otherwise speciﬁed; T

amb

−

C to +85

C unless otherwise speciﬁed. ADC frequency

4.5 MHz.

Symbol Parameter Conditions Min Typ Max Unit

VIA analog input voltage 0 - VDDA V

Cia analog input

capacitance --1pF

EDdifferential linearity

error [1][2][3] --±1 LSB

EL(adj) integral non-linearity [1][4] --±2 LSB

EOoffset error [1][5] --±3 LSB

EGgain error [1][6] --±0.5 %

ETabsolute error [1][7] --±4 LSB

Product data sheet Rev. 04 — 3 January 2008 30 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 4. ADC characteristics

002aaa668

1023

1022

1021

1020

1019

(2)

(1)

10241018 1019 1020 1021 1022 1023

7123456

1018

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VDDA − VSSA

1024

offset

error

gain

error

offset

error

VIA (LSBideal)

1 LSB =

Product data sheet Rev. 04 — 3 January 2008 31 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

8.1 Power consumption measurements for LPC2212/01 and LPC2214/01

The power consumption measurements represent typical values for the given conditions.

The peripherals were enabled through the PCONP register, but for these measurements,

the peripherals were not conﬁgured to run. Peripherals were disabled through the PCONP

LPC2114/2124/2212/2214

User Manual

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4;

Tamb =25°C; core voltage 1.8 V.

Fig 5. Typical LPC2212/01 and LPC2214/01 IDD(act) measured at different frequencies

002aad140

12 20 28 36 44 52 60

all peripherals disabl ed

all peripherals enabled

frequency (M H z)

IDD(act)

(mA)

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4;

Tamb = 25 °C; core voltage 1.8 V; all peripherals enabled.

Fig 6. Typical LPC2212/01 and LPC2214/01 IDD(act) measured at different voltages

002aad142

1.65 1.80 1.95

12 MHz

48 MHz

60 MHz

voltage (V)

IDD(act)

(mA)

Product data sheet Rev. 04 — 3 January 2008 32 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4;

Temp = 25 °C; core voltage 1.8 V; all peripherals disabled.

Fig 7. Typical LPC2212/01 and LPC2214/01 IDD(act) measured at different voltages

002aad141

1.65 1.80 1.95

12 MHz

48 MHz

60 MHz

voltage (V)

IDD(act)

(mA)

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4;

Tamb = 25 °C; core voltage 1.8 V.

Fig 8. Typical LPC2212/01 and LPC2214/01 IDD(idle) measured at different frequencies

002aad143

12 20 28 36 44 52 60

all peripherals disabl ed

all peripherals enabled

frequency (M H z)

IDD(idle)

(mA)

Product data sheet Rev. 04 — 3 January 2008 33 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4;

Tamb =25°C; core voltage 1.8 V; all peripherals enabled.

Fig 9. Typical LPC2212/01 and LPC2214/01 IDD(idle) measured at different voltages

002aad145

1.65 1.80 1.95

12 MHz

48 MHz

60 MHz

voltage (V)

IDD(idle)

(mA)

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4;

Temp = 25 °C; core voltage 1.8 V; all peripherals disabled.

Fig 10. Typical LPC2212/01 and LPC2214/01 IDD(idle) measured at different voltages

002aad144

1.65 1.80 1.95

12 MHz

48 MH z

60 MHz

voltage (V)

IDD(idle)

(mA)

Product data sheet Rev. 04 — 3 January 2008 34 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4;

core voltage 1.8 V; all peripherals disabled.

Fig 11. Typical LPC2212/01 and LPC2214/01 IDD(act) measured at different temperatures

002aad146

-40 -15 10 35 60 85

12 MHz

48 MHz

60 MHz

tem perature (°C)

IDD(act)

(mA)

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4;

core voltage 1.8 V; all peripherals disabled.

Fig 12. Typical LPC2212/01 and LPC2214/01 IDD(idle) measured at different temperatures

002aad147

-40 -15 10 35 60 85

12 MHz

48 MHz

60 MH z

1.0

2.0

3.0

4.0

5.0

6.0

tem perature (°C)

IDD(idle)

(mA)

Product data sheet Rev. 04 — 3 January 2008 35 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

Test conditions: Power-down mode entered executing code from on-chip ﬂash.

Fig 13. Typical LPC2212/01 and LPC2214/01 core power-down current IDD(pd) measured at different temperatures

120

160

200

1. 65 V

1. 8 V

1. 95 V

002aad148

-40 -15 10 35 60 85

temperature (°C)

IDD(pd)

(µA)

Table 8. Typical LPC2212/01 and LPC2214/01 peripheral power consumption in active

mode

Core voltage 1.8 V; T

amb

=25

C; all measurements in

A; PCLK =

CCLK

⁄

Peripheral CCLK = 12 MHz CCLK = 48 MHz CCLK = 60 MHz

Timer0 43 141 184

Timer1 46 150 180

UART0 98 320 398

UART1 103 351 421

PWM0 103 341 407

I2C-bus 9 37 53

SPI0/1 6 27 29

RTC165578

ADC 33 128 167

EMC 306 994 1205

Product data sheet Rev. 04 — 3 January 2008 36 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

9. Dynamic characteristics

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Bus capacitance Cb in pF, from 10 pF to 400 pF.

Table 9. Dynamic characteristics

amb

−

C to +85

C for industrial applications; V

DD(1V8)

, V

DD(3V3)

over speciﬁed ranges.

[1]

Symbol Parameter Conditions Min Typ Max Unit

External clock

fosc oscillator frequency supplied by an external

oscillator (signal generator) 1 - 50 MHz

external clock frequency

supplied by an external

crystal oscillator

1 - 30 MHz

external clock frequency if

on-chip PLL is used 10 - 25 MHz

external clock frequency if

on-chip bootloader is used

for initial code download

10 - 25 MHz

Tcy(clk) clock cycle time 20 - 1000 ns

tCHCX clock HIGH time Tcy(clk) ×0.4 - - ns

tCLCX clock LOW time Tcy(clk) ×0.4 - - ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Port pins (except P0[2] and P0[3])

trrise time - 10 - ns

tffall time - 10 - ns

I2C-bus pins (P0[2] and P0[3])

tffall time VIH to VIL [2] 20 + 0.1 ×Cb--ns

Product data sheet Rev. 04 — 3 January 2008 37 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

Table 10. External memory interface dynamic characteristics

= 25 pF; T

amb

=40

Symbol Parameter Conditions Min Typ Max Unit

Common to read and write cycles

tCHAV XCLK HIGH to address valid

time - - 10 ns

tCHCSL XCLK HIGH to CS LOW time - - 10 ns

tCHCSH XCLK HIGH to CS HIGH

time - - 10 ns

tCHANV XCLK HIGH to address

invalid time - - 10 ns

Read cycle parameters

tCSLAV CS LOW to address valid

time [1] −5 - +10 ns

tOELAV OE LOW to address valid

time [1] −5 - +10 ns

tCSLOEL CS LOW to OE LOW time −5 - +5 ns

tam memory access time [2][3] (Tcy(CCLK) ×(2 + WST1)) +

(−20) -- ns

tam(ibr) memory access time (initial

burst-ROM) [2][3] (Tcy(CCLK) × (2 + WST1)) +

(−20) -- ns

tam(sbr) memory access time

(subsequent burst-ROM) [2][4] Tcy(CCLK) +(−20) - - ns

th(D) data hold time [5] 0--ns

tCSHOEH CS HIGH to OE HIGH time −5 - +5 ns

tOEHANV OE HIGH to address invalid

time −5 - +5 ns

tCHOEL XCLK HIGH to OE LOW time −5 - +5 ns

tCHOEH XCLK HIGH to OE HIGH

time −5 - +5 ns

Write cycle parameters

tAVCSL address valid to CS LOW

time [1] Tcy(CCLK) −10 - - ns

tCSLDV CS LOW to data valid time −5 - +5 ns

tCSLWEL CS LOW to WE LOW time −5 - +5 ns

tCSLBLSL CS LOW to BLS LOW time −5 - +5 ns

tWELDV WE LOW to data valid time −5 - +5 ns

tCSLDV CS LOW to data valid time −5 - +5 ns

tWELWEH WE LOW to WE HIGH time [2] Tcy(CCLK) × (1 + WST2) − 5- T

cy(CCLK) × (1 +

WST2) + 5 ns

tBLSLBLSH BLS LOW to BLS HIGH time [2] Tcy(CCLK) × (1 + WST2) − 5- T

cy(CCLK) ×

(1 + WST2) + 5 ns

tWEHANV WE HIGH to address invalid

time [2] Tcy(CCLK) − 5-T

cy(CCLK) +5 ns

tWEHDNV WE HIGH to data invalid time [2] (2 ×Tcy(CCLK))− 5 - (2 ×Tcy(CCLK))+5 ns

tBLSHANV BLS HIGH to address invalid

time [2] Tcy(CCLK) − 5-T

cy(CCLK) +5 ns

Product data sheet Rev. 04 — 3 January 2008 38 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

[1] Except on initial access, in which case the address is set up Tcy(CCLK) earlier.

[2] Tcy(CCLK) = 1⁄CCLK.

[3] Latest of address valid, CS LOW, OE LOW to data valid.

[4] Address valid to data valid.

[5] Earliest of CS HIGH, OE HIGH, address change to data invalid.

[1] See the

LPC2114/2124/2212/2214 User Manual

for a description of the WSTn bits.

tBLSHDNV BLS HIGH to data invalid

time [2] (2 ×Tcy(CCLK))− 5 - (2 ×Tcy(CCLK))+5 ns

tCHDV XCLK HIGH to data valid

time - - 10 ns

tCHWEL XCLK HIGH to WE LOW

time - - 10 ns

tCHBLSL XCLK HIGH to BLS LOW

time - - 10 ns

tCHWEH XCLK HIGH to WE HIGH

time - - 10 ns

tCHBLSH XCLK HIGH to BLS HIGH

time - - 10 ns

tCHDNV XCLK HIGH to data invalid

time - - 10 ns

Table 10. External memory interface dynamic characteristics

…continued

= 25 pF; T

amb

=40

Symbol Parameter Conditions Min Typ Max Unit

Table 11. Standard read access speciﬁcations

Access cycle Max frequency WST[1] setting

WST ≥ 0; round up to

integer

Memory access time requirement

standard read

standard write

burst read - initial

burst read - subsequent 3×N/A

MAX 2 WST1+

tRAM 20 ns+

--------------------------------

≤WST1 tRAM 20 ns+

tcy CCLK()

--------------------------------

≥2–tRAM tcy CCLK()

2 WST1+()×20 ns–≤

MAX 1WST2+

tWRITE 5ns+

----------------------------------

≤WST2 tWRITE tCYC 5+–

tcy CCLK()

--------------------------------------------

≥tWRITE tcy CCLK()

1 WST2+()×5ns–≤

MAX 2 WST1+

tINIT 20 ns+

--------------------------------

≤

ST1 tINIT 20 ns+

tcy CCLK()

--------------------------------

≥2–tINIT tcy CCLK()

2 WST1+()×20 ns–≤

MAX 1

tROM 20 ns+

---------------------------------

≤tROM tcy CCLK()

20 ns–≤

Product data sheet Rev. 04 — 3 January 2008 39 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

9.1 Timing

Fig 14. External memory read access

XCLK

addr

data

tCSLAV

tOELAV

tCSLOEL

tam th(D)

tCSHOEH

tOEHANV

tCHOEH

tCHOEL

002aaa749

Fig 15. External memory write access

XCLK

addr

data

BLS/WE

tCSLWEL

tCSLBLSL tWELDV

tCSLDV

tWELWEH

tBLSLBLSH

tWEHANV

tBLSHANV

tWEHDNV

tBLSHDNV

002aaa750

tCSLDV

tAVCSL

Product data sheet Rev. 04 — 3 January 2008 40 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

VDD = 1.8 V.

Fig 16. External clock timing

tCHCL tCLCX tCHCX

Tcy(clk)

tCLCH

002aaa907

0.2VDD + 0.9 V

0.2VDD − 0.1 V

VDD − 0.5 V

0.45 V

Product data sheet Rev. 04 — 3 January 2008 41 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

10. Package outline

Fig 17. Package outline SOT486-1 (LQFP144)

UNIT A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 1.45

1.35 0.25 0.27

0.17 0.20

0.09 20.1

19.9 0.5 22.15

21.85 1.4

1.1 7

0.080.2 0.081

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT486-1 136E23 MS-026 00-03-14

03-02-20

D(1) (1)(1)

20.1

19.9

22.15

21.85

1.4

1.1

0 5 10 mm

scale

EA1

detail X

(A )

HA2

HvMB

vMA

max.

1.6

LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1

108

109

pin 1 index

144 36

Product data sheet Rev. 04 — 3 January 2008 42 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

11. Abbreviations

Table 12. Abbreviations

Acronym Description

ADC Analog-to-Digital Converter

AMBA Advanced Microcontroller Bus Architecture

APB Advanced Peripheral Bus

CPU Central Processing Unit

DCC Debug Communications Channel

EMC External Memory Controller

FIFO First In, First Out

GPIO General Purpose Input/Output

JTAG Joint Test Action Group

PLL Phase-Locked Loop

POR Power-On Reset

PWM Pulse Width Modulator

RAM Random Access Memory

SPI Serial Peripheral Interface

SRAM Static Random Access Memory

SSI Synchronous Serial Interface

SSP Synchronous Serial Port

TTL Transistor-Transistor Logic

UART Universal Asynchronous Receiver/Transmitter

Product data sheet Rev. 04 — 3 January 2008 43 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

12. Revision history

Table 13. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC2212_2214_4 20080103 Product data sheet - LPC2212_2214_3

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Type number LPC2212FBD144/01 has been added.

•Type number LPC2214FBD144/01 has been added.

•Details introduced with /01 devices on new peripherals/features (Fast I/O Ports, SSP, CRP)

and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) added.

•Power consumption measurements for LPC2212/01 and LPC2214/01 added.

•Description of JTAG pin TCK has been updated.

LPC2212_2214_3 20060719 Product data sheet - LPC2212_2214-02

LPC2212_2214-02 20041223 Product data - LPC2212_2214-01

LPC2212_2214-01 20040202 Preliminary data - -

Product data sheet Rev. 04 — 3 January 2008 44 of 45

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

13. Legal information

13.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

13.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

14. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors LPC2212/2214

16/32-bit ARM microcontrollers

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 January 2008

Document identifier: LPC2212_2214_4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

15. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 Key features brought by LPC2212/2214/01

devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Key features common for all devices . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Functional description . . . . . . . . . . . . . . . . . . 12

6.1 Architectural overview. . . . . . . . . . . . . . . . . . . 12

6.2 On-chip ﬂash program memory . . . . . . . . . . . 12

6.3 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 13

6.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 14

6.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 15

6.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 16

6.7 External memory controller. . . . . . . . . . . . . . . 16

6.8 General purpose parallel I/O (GPIO)

and Fast I/O . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.8.2 Features added with the Fast GPIO set of

registers available on LPC2212/2214/01 only 16

6.9 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.9.2 ADC features available in LPC2212/2214/01

only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.10 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.10.2 UART features available in LPC2212/2214/01

only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.11 I2C-bus serial I/O controller . . . . . . . . . . . . . . 18

6.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.12 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 18

6.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.12.2 Features available in LPC2212/2214/01 only . 18

6.13 SSP controller (LPC2212/2214/01 only). . . . . 19

6.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.14 General purpose timers . . . . . . . . . . . . . . . . . 19

6.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.14.2 Features available in LPC2212/2214/01 only . 20

6.15 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 20

6.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.16 Real-time clock. . . . . . . . . . . . . . . . . . . . . . . . 20

6.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.17 Pulse width modulator . . . . . . . . . . . . . . . . . . 21

6.17.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.18 System control . . . . . . . . . . . . . . . . . . . . . . . . 22

6.18.1 Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 22

6.18.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.18.3 Reset and wake-up timer . . . . . . . . . . . . . . . . 22

6.18.4 Code security

(Code Read Protection - CRP). . . . . . . . . . . . 23

6.18.5 External interrupt inputs. . . . . . . . . . . . . . . . . 23

6.18.6 Memory mapping control . . . . . . . . . . . . . . . . 24

6.18.7 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.18.8 APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.19 Emulation and debugging. . . . . . . . . . . . . . . . 24

6.19.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 24

6.19.2 Embedded trace macrocell . . . . . . . . . . . . . . 25

6.19.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Static characteristics . . . . . . . . . . . . . . . . . . . 27

8.1 Power consumption measurements for

LPC2212/01 and LPC2214/01. . . . . . . . . . . . 31

9 Dynamic characteristics. . . . . . . . . . . . . . . . . 36

9.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 41

11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 42

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . 43

13 Legal information . . . . . . . . . . . . . . . . . . . . . . 44

13.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 44

13.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

13.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 44

13.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 44

14 Contact information . . . . . . . . . . . . . . . . . . . . 44

15 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45