Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 Counter function modes 7.2 Alarm function modes 7.3 Control/status register 7.4 Counter registers 75 Alarm control register 7.6 Alarm registers 7.7 Timer 7.8 Event counter mode 7.9 Interrupt output 7.10 Oscillator and divider 7.11 Initialization 8 CHARACTERISTICS OF THE I?C-BUS 8.1 Bit transfer 8.2 Start and stop conditions 8.3 System configuration 8.4 Acknowledge 9 l2C-BUS PROTOCOL 9.1 Addressing 9.2 Clock/calendar READ/WRITE cycles 1997 Jul 15 10 11 12 13 14 14.1 14.1.1 14.1.2 14.1.3 15 16 16.1 16.2 16.2.1 16.2.2 16.3 16.3.1 16.3.2 16.3.3 17 18 19 LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION Quartz frequency adjustment Method 1: fixed osci capacitor Method 2: OSCI Trimmer Method 3: PACKAGE OUTLINES SOLDERING Introduction DIP Soldering by dipping or by wave Repairing soldered joints SO Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I?C COMPONENTSPhilips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 1 FEATURES e |2C-bus interface operating supply voltage: 2.5 V to 6 V Clock operating supply voltage (0 to +70 C): 1.0Vto6.0V 240 x 8-bit low-voltage RAM e Data retention voltage: 1.0 V to6 V Operating current (at fgco_ = 0 Hz): max. 50 pA Clock function with four year calendar e Universal timer with alarm and overflow indication 24 or 12 hour format 32.768 kHz or 50 Hz time base Serial input/output bus (I?C) Automatic word address incrementing Programmable alarm, timer and interrupt function Slave address: READ: A1 or A3 WRITE: AO or A2. 3 QUICK REFERENCE DATA 2 GENERAL DESCRIPTION The PCF8583 is a clock/calendar circuit based on a 2048-bit static CMOS RAM organized as 256 words by 8 bits. Addresses and data are transferred serially via the two-line bidirectional I2@C-bus. The built-in word address register is incremented automatically after each written or read data byte. Address pin AO is used for programming the hardware address, allowing the connection of two devices to the bus without additional hardware. The built-in 32.768 kHz oscillator circuit and the first 8 bytes of the RAM are used for the clock/calendar and counter functions. The next 8 bytes may be programmed as alarm registers or used as free RAM space. The remaining 240 bytes are free RAM locations. SYMBOL PARAMETER CONDITION MIN. | TYP. | MAX. | UNIT Vpp supply voltage operating mode l2C-bus active 2.5 - 6.0 Vv l2C-bus inactive 1.0 - 6.0 Vv Ipp supply current operating mode fgc_ = 100 kHz - - 200 LA Ippo supply current clock mode fgc_ = O HZ; Vpp = 5 V - 10 50 HA fgc. = 0 HZ; Vpp = 1 V - 2 10 HA Tamb operating ambient temperature range 40 - +85 C Tstg storage temperature range 65 - +150 |C 4 ORDERING INFORMATION TYPE PACKAGE NUMBER NAME DESCRIPTION VERSION PCF8583P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 PCF8583T SO8 plastic small outline package; 8 leads; body width 7.5 mm SOT176-1 1997 Jul 15Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 5 BLOCK DIAGRAM OSCI 1, PCF8583 DIVIDER 100 Hz control/status 00 2 OSCILLATOR > 1 on > hundredth of a second 01 OSCO 32.768 kHz 100 : 128 seconds _ 7 - minutes INT < | hours Vpp 8 year/date 4 Poe CONTROL weekdays/months Vs RESET LOGIC timer 07 | ___alarmcontrol _| 08 a YW 3 alarm registers AO > or RAM 6 eepus | [J] PTT TTTT HF SCL INTERFACE . ADDRESS = oF SDA 5 REGISTER RAM * (240 x 8) | FF AN < p. MRBo01 Fig.1 Block diagram. 6 PINNING SYMBOL | PIN DESCRIPTION OSCI 1 | oscillator input, 50 Hz or event-pulse input oscl [7 | U 18] Yop OSCO 2 | oscillator output AO 3 | address input osco [2] PCF8583P HA ins Vss 4 | negative supply ; : Voc | 4 5 | SDA SDA 5 | serial data line ss 4] 5 | SCL 6 | serial clock line MNBON4 INT 7 | open drain interrupt output (active LOW) Fig.2 Pinning diagram. Vpp 8 | positive supply 1997 Jul 15 4Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 7 FUNCTIONAL DESCRIPTION The PCF8583 contains a 256 by 8-bit RAM with an 8-bit auto-increment address register, an on-chip 32.768 KHz oscillator circuit, a frequency divider, a serial two-line bidirectional I@C-bus interface and a power-on reset circuit. The first 16 bytes of the RAM (memory addresses 00 to OF) are designed as addressable 8-bit parallel special function registers. The first register (memory address 00) is used as a control/status register. The memory addresses 01 to 07 are used as counters for the clock function. The memory addresses 08 to OF may be programmed as alarm registers or used as free RAM locations, when the alarm is disabled. 7.1 Counter function modes When the control/status register is programmed, a 32.768 kHz clock mode, a 50 Hz clock mode or an event-counter mode can be selected. In the clock modes the hundredths of a second, seconds, minutes, hours, date, month (four year calendar) and weekday are stored in a BCD format. The timer register stores up to 99 days. The event counter mode is used to count pulses applied to the oscillator input (OSCO left open-circuit). The event counter stores up to 6 digits of data. When one of the counters is read (memory locations 01 to 07), the contents of all counters are strobed into capture latches at the beginning of a read cycle. Therefore, faulty reading of the count during a carry condition is prevented. When a counter is written, other counters are not affected. 7.2 Alarm function modes By setting the alarm enable bit of the control/status register the alarm control register (address 08) is activated. By setting the alarm control register a dated alarm, a daily alarm, a weekday alarm or a timer alarm may be programmed. In the clock modes, the timer register (address 07) may be programmed to count hundredths of a second, seconds, minutes, hours or days. Days are counted when an alarm is not programmed. 1997 Jul 15 Whenever an alarm event occurs the alarm flag of the control/status register is set. A timer alarm event will set the alarm flag and an overflow condition of the timer will set the timer flag. The open drain interrupt output is switched on (active LOW) when the alarm or timer flag is set (enabled). The flags remain set until directly reset by a write operation. When the alarm is disabled (Bit 2 of control/status register = 0) the alarm registers at addresses 08 to OF may be used as free RAM. 7.3. Control/status register The control/status register is defined as the memory location 00 with free access for reading and writing via the l2C-bus. All functions and options are controlled by the contents of the control/status register (see Fig.3). 7.4 Counter registers In the clock modes 24 h or 12 h format can be selected by setting the most significant bit of the hours counter register. The format of the hours counter is shown in Fig.5. The year and date are packed into memory location 05 (see Fig.6). The weekdays and months are packed into memory location 06 (see Fig.7). When reading these memory locations the year and weekdays are masked out when the mask flag of the control/status register is set. This allows the user to read the date and month count directly. In the event-counter mode events are stored in BCD format. D5 is the most significant and DO the least significant digit. The divider is by-passed. In the different modes the counter registers are programmed and arranged as shown in Fig.4. Counter cycles are listed in Table 1.Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 MSB LSB memory location 00 7 6 5 4) 3 2 1 0 | reset state: 0000 0000 L timer flag (50% duty factor seconds flag if alarm enable bit is 0) alarm flag (50% duty factor minutes flag if alarm enable bit is 0) alarm enable bit: 0 alarm disabled: flags toggle alarm control register disabled (memory locations 08 to OF are free RAM space) 1 enable alarm control register (memory location 08 is the alarm control register) mask flag: 0 read locations 05 to 06 unmasked 1 read date and month count directly function mode : 00 clock mode 32.768 kHz 01. clock mode 50 Hz 10 event-counter mode 11. test modes hold last count flag : 0 count 1 store and hold last count in capture latches stop counting flag : 0 count pulses 1 stop counting, reset divider MRBO17 Fig.3 Control/status register. 1997 Jul 15Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 control/status hundredth of a second 110s | _1/100s control/status seconds 10s | 1s minutes 10min | 1 min hours 10h | 1h year/date 10 day | 1 day weekday/month 10 month | 1 month timer 10 day | 1 day alarm control D1 Do D3 D2 D5 D4 free free free timer T1 | hundredth of a second 140s | 100s alarm control alarm seconds alarm alarm Di bo alarm minutes D3 D2 alarm hours D5 D4 alarm date free alarm month free alarm timer free free RAM alarm timer free RAM i CLOCK MODES EVENT COUNTER Fig.4 Register arrangement. i en 00 01 02 03 04 05 06 07 08 og 0A 0B 0c oD OE OF 1997 Jul 15Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 MSB LSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | memory location 04 (hours counter) reset state: 0000 0000 Lf | unit hours BCD ten hours (0 to 2 binary) AM/PM flag: 0 AM 1 PM format: 0 24h format, AM/PM flag remains unchanged 1 12h format, AM/PM flag will be updated MRB002 Fig.5 Format of the hours counter. MSB LSB | 7 | | 4 | 3 | 2 | 1 | 0 | memory location 05 (year/date) reset state: 0000 0001 a a unit days BCD ten days (0 to 3 binary) year (0 to 3 binary, read as 0 if the mask flag is set) MRBOO3 Fig.6 Format of the year/date counter. MSB LSB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | memory location 06 (weekdays/months) reset state: 0000 0001 Lf unit months BCD ten months weekdays (0 to 6 binary, read as 0 if the mask flag is set) MRBO04 Fig.7 Format of the weekdays/month counter. 1997 Jul 15 8Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 Table 1 Cycle length of the time counters, clock modes CONTENTS OF THE UNIT COUNTING CYCLE CARRY TO NEXT UNIT MONTH COUNTER Hundredths of a second 00 to 99 99 to 00 - Seconds 00 to 59 59 to 00 - Minutes 00 to 59 59 to 00 - Hours (24 h) 00 to 23 23 to 00 - Hours (12 h) 12 AM - - 01 AM to 11 AM - - 12 PM - - 01 PM to 11 PM 11 PM to 12 AM - Date 01 to 31 31 to 01 1,3, 5, 7, 8, 10 and 12 01 to 30 30 to 01 4,6, 9 and 11 01 to 29 29 to 01 2, year =0 01 to 28 28 to 01 2, year=1,2and3 Months 01 to 12 12 to 01 - Year 0to3 - - Weekdays Oto6 6 to0 - Timer 00 to 99 no carry - 7.5 Alarm control register When the alarm enable bit of the control/status register is set (address 00, bit 2) the alarm control register (address 08) is activated. All alarm, timer, and interrupt output functions are controlled by the contents of the alarm control register (see Fig.8). 7.6 Alarm registers All alarm registers are allocated with a constant address offset of hexadecimal 08 to the corresponding counter registers (see Fig.4, Register arrangement). 1997 Jul 15 An alarm signal is generated when the contents of the alarm registers matches bit-by-bit the contents of the involved counter registers. The year and weekday bits are ignored in a dated alarm. A daily alarm ignores the month and date bits. When a weekday alarm is selected, the contents of the alarm weekday/month register will select the weekdays on which an alarm is activated (see Fig.9). Remark: In the 12 h mode, bits 6 and 7 of the alarm hours register must be the same as the hours counter.Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 MSB LSB L7te]s}+{s]2{+]o] MRBOOS memory location 08 reset state: 0000 0000 timer function : 000 ~s no timer 001 hundredths of a second 010 seconds 011 minutes 100 hours 101 days 110 not used 111 test mode, all counters in parallel (factory use only) timer interrupt enable : 0 timer flag, no interrupt 1 timer flag, interrupt clock alarm function : 00 no clock alarm 01 daily alarm 10 weekday alarm 11 dated alarm timer alarm enable : 0 no timer alarm 1 timer alarm alarm interrupt enable : (valid only when alarm enable in control / status register is set 0 alarm flag, no interrupt 1 alarm flag, interrupt Fig.8 Alarm control register; clock mode. 1997 Jul 15 10Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 MSB L7te]s}*{s]2} LSB lo | memory location OE (alarm weekday / month) weekday 0 enabled when set weekday 1 enabled when set weekday 2 enabled when set weekday 3 enabled when set weekday 4 enabled when set weekday 5 enabled when set weekday 6 enabled when set not used MRB0O06 Fig.9 Selection of alarm weekdays. 7.7 Timer The timer (location 07) is enabled by setting the control/status register = XXOX X1XX. The timer counts up from 0 (or a programmed value) to 99. On overflow, the timer resets to 0. The timer flag (LSB of control/status register) is set on overflow of the timer. This flag must be reset by software. The inverted value of this flag can be transferred to the external interrupt by setting bit 3 of the alarm control register. Additionally, a timer alarm can be programmed by setting the timer alarm enable (bit 6 of the alarm control register). When the value of the timer equals a pre-programmed value in the alarm timer register (location OF), the alarm flag is set (bit 1 of the control/status register). The inverted value of the alarm flag can be transferred to the external interrupt by enabling the alarm interrupt (bit 6 of the alarm control register). Resolution of the timer is programmed via the 3 LSBs of the alarm control register (see Fig.11, Alarm and timer Interrupt logic diagram). 7.8 Event counter mode Event counter mode is selected by bits 4 and 5 which are logic 1, 0 in the control/status register. The event counter mode is used to count pulses externally applied to the oscillator input (OSCO left open-circuit). 1997 Jul 15 11 The event counter stores up to 6 digits of data, which are stored as 6 hexadecimal values located in locations 1, 2, and 3. Thus, up to 1 million events may be recorded. An event counter alarm occurs when the event counter registers match the value programmed in locations 9, A, and B, and the event alarm is enabled (bits 4 and 5 which are logic 0, 1 in the alarm control register). In this event, the alarm flag (bit 1 of the control/status register) is set. The inverted value of this flag can be transferred to the interrupt pin (pin 7) by setting the alarm interrupt enable in the alarm control register. In this mode, the timer (location 07) increments once for every one, one-hundred, ten thousand, or 1 million events, depending on the value programmed in bits 0, 1 and 2 of the alarm control register. In all other events, the timer functions are as in the clock mode. 7.9 Interrupt output The conditions for activating the open-drain n-channel interrupt output INT (active LOW) are determined by appropriate programming of the alarm control register. These conditions are clock alarm, timer alarm, timer overflow, and event counter alarm. An interrupt occurs when the alarm flag or the timer flag is set, and the corresponding interrupt is enabled. In all events, the interrupt is cleared only by software resetting of the flag which initiated the interrupt.Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 MSB LSB L7tets}+{s}e{+]o] memory location 08 reset state: 0000 0000 | timer function : 000 001 010 011 100 101 110 111 no timer units 100 10 000 1 000 000 not allowed not allowed test mode, all counters in parallel timer interrupt enable : 0 timer flag, no interrupt 1 timer flag, interrupt clock alarm function : 00 no event alarm 01 event alarm 10 not allowed 11 not allowed timer alarm enable : 0 no timer alarm 1 timer alarm MRBOO7 Fig.10 Alarm control register, event-counter mode. alarm interrupt enable : 0 alarm flag, no interrupt 1 alarm flag, interrupt In the clock mode, if the alarm enable is not activated (alarm enable bit of control/status register is logic 0), the interrupt output toggles at 1 Hz with a 50% duty cycle (may be used for calibration). This is the default power-on state of the device. The OFF voltage of the interrupt output may exceed the supply voltage, up to a maximum of 6.0 V. A logic diagram of the interrupt output is shown in Fig.11. 7.10 Oscillator and divider A 32.768 kHz quartz crystal has to be connected to OSCI (pin 1) and OSCO (pin 2). A trimmer capacitor between OSCI and Vpp is used for tuning the oscillator (see quartz frequency adjustment). A 100 Hz clock signal is derived from the quartz oscillator for the clock counters. In the 50 Hz clock mode or event-counter mode the oscillator is disabled and the oscillator input is switched to a high impedance state. 1997 Jul 15 12 This allows the user to feed the 50 Hz reference frequency or an external high speed event signal into the input OSCI. 7.11 Initialization When power-up occurs the |2C-bus interface, the control/status register and all clock counters are reset. The device starts time-keeping in the 32.768 KHz clock mode with the 24 h format on the first of January at 0.00.00: 00. A 1 Hz square wave with 50% duty cycle appears at the interrupt output pin (starts HIGH). It is recommended to set the stop counting flag of the control/status register before loading the actual time into the counters. Loading of illegal states may lead to a temporary clock malfunction.Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 MUX ~ oscillator | mode x} select y t V - , CLOCK/CALENDAR YY contro! ALARM TIMER clock alarm timer timer alarm control alarm overflow control NAN \Q Y) aanaae L7tels}}ate} | 0 | elet]s}e]+[o| Lo CONTROL/STATUS ALARM REGISTER ") CONTROL REGISTER timer overflow interrupt alarm interrupt MBD878 (1) If the alarm enable bit of the control/status register is reset (logic 0), a 1 Hz signal can be observed on the interrupt pin INT. Fig.11 Alarm and timer interrupt logic diagram. 1997 Jul 15 13Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 8 CHARACTERISTICS OF THE I?C-BUS The |I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer (see Fig. 12) One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. SDA / I | data line | change | | stable; | of data | | data valid | allowed | MBCE21 Fig.12 Bit transfer. 8.2. Start and stop conditions (see Fig. 13) Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). I _ | - SCL | \ / \ / | SCL | $s P a a START condition STOP condition MBC622 Fig.13 Definition of start and stop conditions. 1997 Jul 15 14Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 8.3. System configuration (see Fig. 14) A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. SDA SCL MASTER SLAVE MASTER SLAVE MASTER TRANSMITTER / TRANSMITTER / TRANSMITTER / RECEIVER RECEIVER RECEIVER TRANSMITTER RECEIVER MBA605 Fig.14 System configuration. 8.4 Acknowledge (see Fig.15) The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA The number of data bytes transferred between the start line is stable LOW during the HIGH period of the and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. 4 DATA OUTPUT | \ BY TRANSMITTER | | | | | {xX XX / | | not acknowledge \ | | DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER | Sf \_f \_ LS t START CONDITION clock pulse for MBC602 acknowledgement Fig.15 Acknowledgment on the I?C-bus. 1997 Jul 15 15Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 9 |?C-BUS PROTOCOL 9.1 Addressing Before any data is transmitted on the I@C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. The clock/calendar slave address is shown in Fig.16. Bit AO corresponds to hardware address pin AO. Connecting this pin to Vpp or Vgg allows the device to have one of two different addresses. [ifo]i 0] o | 0 [ao [Ray] _ group 1 i group > MRBO16 Fig.16 Slave address. 9.2. Clock/calendar READ/WRITE cycles The I?C-bus configuration for the different PCF8583 READ and WRITE cycles is shown in Figs 17, 18 and 19. acknowledgement acknowledgement acknowledgement from slave from slave from slave T T T T T T ! T T T T T T T t T T T T T T ! SLAVE ADDRESS |0|A}) WORD ADDRESS A DATA A} P 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RW | nbytes I auto increment memory word address MBD822 Fig.17 Master transmits to slave receiver (WRITE) mode. 1997 Jul 15 16Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 acknowledgement acknowledgement acknowledgement acknowledgement from slave from slave from slave from master T T T T T T T ! T T T T T T T ! T T T T T T T t T T T T T T T ! S | SLAVE ADDRESS 0]A] WORD ADDRESS A| Ss SLAVE ADDRESS 1]/A DATA AF---- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x r+ 4 RAW at this moment master - RW n bytes transmitter becomes auto increment master - receiver and memory word address PCF8593 slave - receiver becomes slave - transmitter no acknowledgement from master 1 T T T T T T T ! --4 DATA 1| P u last byte t auto increment MBD8&23 memory word address Fig.18 Master reads after setting word address (write word address; READ data). acknowledgement acknowledgement acknowledgement from slave from slave from slave T T T T T T T ! T T T T T T T t T T T T T T T t Ss SLAVE ADDRESS 1]/A DATA A DATA 1] P 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RW n bytes last bytes auto increment auto increment word address word address MBD824 Fig.19 Master reads slave immediately after first byte (READ mode). 1997 Jul 15 17Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT Vpp supply voltage (pin 8) 0.8 +7.0 Vv Ipp supply current (pin 8) - 50 mA Iss supply current (pin 4) - 50 mA Vi input voltage 0.8 Vpp + 0.8 V I DC input current - 10 mA lo DC output current - 10 mA Prot total power dissipation per package - 300 mW Po power dissipation per output - 50 mW Tamb operating ambient temperature 40 +85 C Tstg storage temperature 65 +150 C 11. HANDLING Inputs and outputs are protected against electrostatic charge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC 12 under Handling MOS Devices. 12 DC CHARACTERISTICS Vpp = 2.5 to 6.0 V; Vgsg = 0 V; Tamb = 40 to +85 C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. | TYP.() MAX. UNIT Vpp supply voltage l2C-bus active 2.5 - 6.0 Vv (operating mode) I2C-bus inactive 1.0 - 6.0 V Vpposc supply voltage Tamb = 0 to 70 C; note 2 1.0 - 6.0 Vv (quartz oscillator) Ipp supply current fgc_ = 100 kHz; clock mode; - - 200 HA (operating mode) note 3 Ippo supply current see Fig.20 (clock mode) fgc. = 0 Hz; Vpp = 5 V - 10 50 uA fscL = O HZ; Vpp = 1 V 2 10 HA IbprR data retention fosci = 0 HZ; Vpp = 1 V Tamb = 40 to + 85C 5 HA Tamb = 25 to + 70C 2 HA VEN l2C-bus enable level note 4 1.5 1.9 2.3 Vv SDA VIL LOW level input voltage note 5 0.8 - 0.3Vpp |V Vin HIGH level input voltage note 5 0.7Vpp |- Vpp +0.8 | V lot LOW level output current VoL = 0.4 V 3 - - mA lu input leakage current Vi = Vpp or Vss -1 - +1 HA Ci input capacitance note 6 - - 7 pF 1997 Jul 15 18Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 SYMBOL PARAMETER CONDITIONS MIN. | TYP.) | MAX. UNIT AO; OSCI Iu input leakage current V, = Vpp or Vss | 250 | - | +250 nA INT lot LOW level output current VoL = 0.4 V 3 - - mA lu input leakage current Vi = Vpp or Vss -1 - +1 HA SCL Ci input capacitance note 6 - - 7 pF Iu input leakage current Vi = Vpp or Vss -1 - +1 HA Notes 1. Typical values measured at Tamb = 25 C. ak ODN must not exceed +0.5 mA. 6. Tested on sample basis. When powering-up the device, Vpp must exceed 1.5 V until stable operation of the oscillator is established. Event counter mode: supply current dependant upon input frequency. The I2C-bus logic is disabled if Vpp < Ven. When the voltages are above or below the supply voltages Vpp or Vss, an input current may flow; this current Ippo (uA) fseL = 32 kHz; Tamb =25C. MRBO12 / Vpp (Y) Fig.20 Typical supply current in clock mode as a function of supply voltage. 1997 Jul 15 19Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 13 AC CHARACTERISTICS Vpp = 2.5 to 6.0 V; Vsg = 0 V; Tamb = 40 to +85 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Oscillator Cose integrated oscillator - 40 - pF capacitance Afose oscillator stability for AVpp = 100 mV; - 2x107 | - Tamb = 25 C; Vpp = 1.5 V fi input frequency note 1 - - 1 MHz Quartz crystal parameters (f = 32.768 kHz) Rg series resistance - - 40 kQ CL parallel load capacitance - 10 - pF Cr trimmer capacitance 5 - 25 pF I2C-bus timing (see Fig.21; notes 2 and 3) fse SCL clock frequency - - 100 kHz tsp tolerable spike width on bus - - 100 ns tBuE bus free time 4.7 - - us tsu-sTA START condition set-up time 4.7 - - us tHD-STA START condition hold time 4.0 - - us tLow SCL LOW time 4.7 - - us tHIGH SCL HIGH time 4.0 - - us t SCL and SDA rise time - - 1.0 us tr SCL and SDA fall time - - 0.3 us tsu-DAT data set-up time 250 - - ns tuD-DAT data hold time 0 - - ns tvD:DAT SCL LOW to data out valid - - 3.4 us tsu-sto STOP condition set-up time 4.0 - - us Notes 1. Event counter mode only. 2. All timing values are valid within the operating supply voltage and ambient temperature range and reference to Vi. and Vjy with an input voltage swing of Vgg to Vpp. 3. Adetailed description of the I?C-bus specification, with applications, is given in brochure The C-bus and how to use it. This brochure may be ordered using the code 9398 393 40011. 1997 Jul 15 20Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 START BIT 7 BIT6 BIT O ACKNOWLEDGE STOP PROTOCOL CONDITION MSB (A6) LSB (A) CONDITION (S) (A7) (RW) (P) tsu:sTA tLlow THIGH 1/F scl m [ \ | Fig.21 |?C-bus timing diagram; rise and fall times refer to Vi_ and Vip. MBD820 SCL L__ tf y SDA K tHD:STA tsupat s ' HD-DAT t Vb:DAT tsu:sto 14 APPLICATION INFORMATION 14.1. Quartz frequency adjustment 14.1.1. METHOD 1: FIXED OSCI CAPACITOR By evaluating the average capacitance necessary for the application layout a fixed capacitor can be used. The frequency is best measured via the 1 Hz signal available after power-on at the interrupt output (pin 7). The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average +5 x 10-). Average deviations of +5 minutes per year can be achieved. 14.1.2 METHOD 2: OSCI TRIMMER Using the alarm function (via the I@C-bus) a signal faster than 1 Hz can be generated at the interrupt output for fast setting of a trimmer. 1997 Jul 15 Procedure: Power-on Initialization (alarm functions). Routine: * Set clock to time T and set alarm to time T + dT At time T + dT (interrupt) repeat routine. 14.1.3. METHOD 3: Direct measurement of OSC out (accounting for test probe capacitance). The PCF8583 slave address has a fixed combination 1010 as group 1.Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 Vop +> SDA MASTER V TRANSMITTER DD SCL in i AO CLOCK a CALENDAR OSCl PCF8583 c_ '1010' sDAL4 T_ osco Vss Vpp Van +44 Ao DD EVENT = gg. COUNTER JL 0sc! persse3 "1010 SDA4 osco Vg Vpp as R RR: pull-up resistor R = trige / C-bus SDA SCL (I?C-bus) MRBO18 Fig.22 Application diagram. 1997 Jul 15 22Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 15 PACKAGE OUTLINES DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1 | seating plane 8 5 [ 2 alata py--+---+ | TIT 4 o 5 10 mm be dd scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A Ay Ag 4 1 7) UNIT | way. | min. | mex. b by bo c pM | EM | e e, L Me | My wo} ee 1.73 0.53 1.07 0.36 9.8 6.48 3.60 8.25 10.0 mm | 42 | 051 | 32 | 444 | 038 | o89 | 023 | 92 | 620 | 254 | 76 | 305 | 780 | aa | OP54) 1:15 inch 0.068 | 0.021 | 0.042 | 0.014 0.39 0.26 0.14 0.32 0.39 nenes | 0.17 0.020 0.13 0.045 | 0.015 | 0.035 | 0.009 0.36 0.24 0.10 0.30 0.12 0.31 0.33 0.01 0.045 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES VERSION PROJECTION | 'SSUEDATE IEC JEDEC EIAJ 92-447 SOT97-1 050G01 MO-001AN f-} 35 0D 04 1997 Jul 15 23Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 $08: plastic small outline package; 8 leads; body width 7.5 mm SOT176-1 aloN f= \ Ce 7 \ L L CI) 84S TU! - CI CI CI c 7 a S=-J ly He = e-Z 8 | 5 | | | Y | i 0 | Ao i 4 )---- 4 Ay | \ (As) | in 1 inde ! pin 1 in m i ara L 1 > Lp T H H [at | | ik | J 4 [ele 0 5 10 mm Ll l l l l l l l J scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT | pax | At A2 | A3 | bp c Dp | EO) | e He L Lp Q v w y 201) | 6 03 | 2.45 0.49 | 0.32 | 765 | 7.6 10.65 14 14 20 mm | 265 | 91 | 225 | 975 | o36 | 023 | 745] 74 | 127 | 1000] 145 | o45 | 10 | 979 | 978] Ol | 4g | go . 0.012 | 0.096 0.019] 0.013] 0.30 | 0.30 0.419 0.043 | 0.043 0.079| 0 inches | 0.10 | 9094 | 0.089] ! |0.014] 0.009] 0.29 | 0.29 | 95} 0.304 | 9-97 | o.o18| 0.039] 901 | 991 | 9-04 | O74 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC EIAJ PROJECTION SOT176-1 Ee} 97-05-22 1997 Jul 15 24Philips Semiconductors Product specification Clock/calendar with 240 x 8-bit RAM PCF8583 16 SOLDERING 16.1. Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our IC Package Databook (order code 9398 652 90011). 16.2 DIP 16.2.1 SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T stg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 16.2.2 REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 16.3 SO 16.3.1. REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1997 Jul 15 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 16.3.2 WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow. The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.3.3. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.