A6812ELWTR - Allegro Microsystems

Description

The A6812 device combines a 20-bit CMOS shift register,

ac com pa ny ing data latches and control cir cuit ry with bipolar

sourcing out puts ,and PNP active pull-downs. De signed

pri mar ily to drive vacuum-flu o res cent displays, the 60 V and

-40 mA output ratings also allow these devices to be used in

many other peripheral power driver applications. The A6812

features an increased data-input rate (com pared with the older

UCN/UCQ5812-F) and a controlled output slew rate.

The CMOS shift register and latches allow direct interfacing

with mi cro pro ces sor-based systems. With a 3.3 or 5 V logic

supply, they operate to at least 10 MHz.

A CMOS serial data output permits cascaded con nec tions in

ap pli ca tions re quir ing additional drive lines. Similar devices

are avail able as the A6810 (10-bit) and A6818 (32-bit).

The A6812 output source drivers are NPN Dar ling tons,

capable of sourcing up to 40 mA. The controlled output slew

rate reduces elec tro mag net ic noise, which is an important

consideration in systems that include telecommunications

and/or microprocessors and to meet government emis sions

26182.126F

Features and Benefits

▪ Controlled output slew rate

▪ High-speed data storage

▪ 60 V minimum output break down

▪ High data-input rate

▪ PNP active pull-downs

▪ Low output-saturation voltages

▪ Low-power CMOS logic and latches

▪ Improved replacements for TL5812x, UCN5812x, and

UCQ5812x

DABiC-IV 20-Bit Serial-Input

Latched Source Driver

Continued on the next page…

Package:

Functional Block Diagram

Not to scale

A6812

28-pin PLCC

(EP package)

28-pin SOICW

(Package LW)

DABiC-IV 20-Bit Serial-Input

Latched Source Driver

A6812

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Selection Guide

Part Number Pb-free Packing Package Ambient Temperature, TA

(°C)

A6812EEPTR* – 800 pieces/13-in. reel PLCC –40 to 85A6812EEPTR-T* Yes

A6812ELWTR-T Yes 1000 pieces/13-in. reel SOIC-W

A6812KLWTR-T* Yes 1000 pieces/13-in. reel SOIC-W –40 to 125

A6812SEPTR* – 800 pieces/13-in. reel PLCC –20 to 85A6812SEPTR-T Yes

A6812SLWTR-T* Yes 1000 pieces/13-in. reel SOIC-W

*Variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of the variant is

currently restricted to existing customer applications. The variant should not be purchased for new design applications because obsolescence

in the near future is probable. Samples are no longer available. Status change: May 4, 2009.

regulations. For inter-digit blanking, all output drivers can be

dis abled and all sink drivers turned on with a BLANK ING input

high. The PNP active pull-downs sink at least 2.5 mA.

Three temperature ranges are available for optimum performance in

commercial (suffix S-), industrial (suffix E-), or automotive (suffix

K-) ap pli ca tions. Pack age styles are provided for surface-mount

SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix

-EP). Copper lead frames, low logic-power dis si pa tion, and low

output-saturation voltages allow these drivers to source 25 mA

from all outputs continuously to more than 43°C (suffix -LW) or

61°C (suffix -EP).

Each package is available in a lead (Pb) free version, with 100%

matte tin leadframe plating.

Description (continued)

DABiC-IV 20-Bit Serial-Input

Latched Source Driver

A6812

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Absolute Maximum Ratings*

Characteristic Symbol Notes Rating Units

Logic Supply Voltage VDD 7V

Driver Supply Voltage VBB 60 V

Input Voltage Range VIN –0.3 to VDD + 0.3 V

Continuous Output Current Range IOUT –40 to 15 mA

Operating Ambient Temperature TA

Range E –40 to 85 ºC

Range K –40 to 125 ºC

Range S –20 to 85 ºC

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature Tstg –65 to 125 ºC

*Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high

static electrical charges.

Thermal Characteristics

Characteristic Symbol Test Conditions* Value Units

Package Thermal Resistance RθJA

Package EP, 1-layer PCB with solder limited to mounting pads 68 ºC/W

Package LW, 1-layer PCB with solder limited to mounting pads 80 ºC/W

*Additional thermal information available on the Allegro website

50 75 100 125 150

2.5

0.5

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

AMBIENT TEMPERATURE IN oo

ooC

2.0

1.5

1.0

Dwg. GP-024-2

SUFFIX 'EP', R = 68oC/W

QJA

SUFFIX 'LW', R = 80 C/W

QJA

DABiC-IV 20-Bit Serial-Input

Latched Source Driver

A6812

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

TYPICAL INPUT CIRCUIT TYPICAL OUTPUT DRIVER

Dwg. EP-010-5

Dwg. EP-021-19

OUTN

10 19

LOAD

SUPPLY BB

OUT2

OUT7

OUT8

Dwg. PP-029-7

OUT19

OUT18

OUT13

14 27

SERIAL

DATA OUT

BLANKING

LOGIC

SUPPLY

STROBE

GROUND CLOCK

CLK

BLNK

OUT9

OUT10

OUT12

OUT11

LATCHES

326

SERIAL

DATA IN

OUT6

OUT1

OUT4

OUT3

OUT20

OUT5

OUT17

OUT16

OUT15

OUT14

EP Package LW Package

16 28

Dwg. PP-059-1

OUT

LATCHES

CLOCK

CLK

SERIAL

DATA OUT

LOAD

SUPPLY

SERIAL

DATA IN

STROBE

GROUND

LOGIC

SUPPLY

BLANKING

OUT

LATCHES

DABiC-IV 20-Bit Serial-Input

Latched Source Driver

A6812

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

TRUTH TABLE

Serial Shift Register Contents Serial Latch Contents Output Con tents

Data Clock Data Strobe

Input Input I1 I

2 I

3 ... IN-1 I

N Output Input I1 I

2 I

3 ... IN-1 I

N Blanklng I1 I

2 I

3 ... IN-1

H H R1 R2 ... RN-2 R

N-1 R

N-1

L L R1 R2 ... RN-2 R

N-1 RN-1

X R1 R2 R3 ... RN-1 RN RN

X X X ... X X X L R1 R2 R3 ... RN-1 RN

1 P2 P3 ... PN-1 PN P

N H P1 P2 P3 ... PN-1 PN L P1 P

2 P

3 ... PN-1 PN

X X X ... X X H L L L ... L L

L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

DABiC-IV 20-Bit Serial-Input

Latched Source Driver

A6812

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Limits @ VDD = 3.3 V Limits @ VDD = 5 V

Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units

Output Leakage Current ICEX V

OUT = 0 V — <-0.1 -15 — <-0.1 -15 μA

Output Voltage VOUT(1) I

OUT = -25 mA 57.5 58.3 — 57.5 58.3 — V

OUT(0) I

OUT = 1 mA — 1.0 1.5 — 1.0 1.5 V

Output Pull-Down Current IOUT(0) V

OUT = 5 V to VBB 2.5 5.0 — 2.5 5.0 — mA

Input Voltage VIN(1) 2.2 — — 3.3 — — V

IN(0) — — 1.1 — — 1.7 V

Input Current IIN(1) V

IN = VDD — <0.01 1.0 — <0.01 1.0 μA

IN(0) V

IN = 0 V — <-0.01 -1.0 — <-0.01 -1.0 μA

Input Clamp Voltage VIK I

IN = -200 μA — -0.8 -1.5 — -0.8 -1.5 V

Serial Data Output Volt age VOUT(1) I

OUT = -200 μA 2.8 3.05 — 4.5 4.75 — V

OUT(0) I

OUT = 200 μA — 0.15 0.3 — 0.15 0.3 V

Maximum Clock Frequency fc 10* — — 10* — — MHz

Logic Supply Current IDD(1) All Outputs High — 0.25 0.75 — 0.3 1.0 mA

DD(0) All Outputs Low — 0.25 0.75 — 0.3 1.0 mA

Load Supply Current IBB(1) All Outputs High, No Load — 3.0 6.0 — 3.0 6.0 mA

BB(0) All Outputs Low — 0.2 20 — 0.2 20 μA

Blanking

-to-

Output Delay tdis(BQ) C

L = 30 pF, 50% to 50% — 0.7 2.0 — 0.7 2.0 μs

en(BQ) CL = 30 pF, 50% to 50% — 1.8 3.0 — 1.8 3.0 μs

Strobe

-to-

Output Delay tp(STH-QL) R

L = 2.3 kΩ, CL 30 pF — 0.7 2.0 — 0.7 2.0 μs

p(STH-QH) R

L = 2.3 kΩ, CL 30 pF — 1.8 3.0 — 1.8 3.0 μs

Output Fall Time tf R

L = 2.3 kΩ, CL 30 pF 2.4 — 12 2.4 — 12 μs

Output Rise Time tr R

L = 2.3 kΩ, CL 30 pF 2.4 — 12 2.4 — 12 μs

Output Slew Rate dV/dt RL = 2.3 kΩ, CL 30 pF 4.0 — 20 4.0 — 20 V/μs

Clock

-to-

Serial Data Out Delay tp(CH-SQX) I

OUT = ±200 μA — 50 — — 50 — ns

Negative current is deﬁ ned as coming out of (sourcing) the speciﬁ ed device terminal.

Typical data is is for design information only and is at TA = +25°C.

* Operation at a clock frequency greater than the speciﬁ ed minimum is possible but not warranteed.

ELECTRICAL CHARACTERISTICS at TA = +25°C (A6812S-) or over operating tem per a ture range (A6812E- or

A6812K-), VBB = 60 V; un less otherwise noted

DABiC-IV 20-Bit Serial-Input

Latched Source Driver

A6812

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

TIMING REQUIREMENTS and SPECIFICATIONS

(Logic Levels are VDD and Ground)

Serial Data present at the input is trans ferred to the shift

input pulse. On suc ceed ing CLOCK pulses, the registers shift

data information towards the SERIAL DATA OUTPUT. The

SERIAL DATA must appear at the input prior to the rising edge

of the CLOCK input waveform.

Information present at any register is transferred to the re-

spective latch when the STROBE is high (serial-to-par al lel con-

ver sion). The latches will continue to accept new data as long

as the STROBE is held high. Ap pli ca tions where the latches are

bypassed (STROBE tied high) will require that the BLANKING

input be high during serial data entry.

When the BLANKING input is high, the output source driv-

ers are disabled (OFF); the pnp active pull-down sink drivers are

ON. The in for ma tion stored in the latches is not affected by the

BLANKING input. With the BLANK ING input low, the outputs

are con trolled by the state of their re spec tive latches.

A. Data Active Time Before Clock Pulse

(Data Set-Up Time), tsu(D) ........................................ 25 ns

B. Data Active Time After Clock Pulse

(Data Hold Time), th(D) ............................................. 25 ns

C. Clock Pulse Width, tw(CH) .............................................. 50 ns

D. Time Between Clock Ac ti va tion and Strobe, tsu(C) ...... 100 ns

E. Strobe Pulse Width, tw(STH) ........................................... 50 ns

NOTE – Timing is representative of a 10 MHz clock. Higher

speeds may be attainable with increased supply voltage; op-

er a tion at high temperatures will reduce the speciﬁ ed max i mum

clock frequency.

CLOCK

SERIAL

DATA IN

STROBE

BLANKING

OUTN

Dwg. WP-029

50%

SERIAL

DATA OUT

DATA

10%

90%

50%

A B

D E

LOW = ALL OUTPUTS ENABLED

p(STH-QL)

p(CH-SQX)

DATA

p(STH-QH)

BLANKING

OUT

Dwg. WP-030A

DATA

10%

50%

en(BQ)

dis(BQ)

HIGH = ALL OUTPUTS BLANKED (DISABLED)

50%

90%

DABiC-IV 20-Bit Serial-Input

Latched Source Driver

A6812

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

EP Package, 28-Pin PLCC

2128

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

ATerminal #1 mark area

For Reference Only

(reference JEDEC MS-018 AB)

Dimensions in millimeters

12.45±0.13

0.51 MIN

SEATING

PLANE

C0.10

28X

11.51±0.08

5.21±0.36

0.74±0.08

5.21±0.36

0.43±0.10

5.21±0.36

11.51±0.08

0.51

1.27

4.37 +0.20

–0.18

DABiC-IV 20-Bit Serial-Input

Latched Source Driver

A6812

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

LW Package, 28-Pin SOICW

17.90±0.20

10.30±0.33

7.50±0.10

SEATING

PLANE

C0.1

28X

1.27

0.20 ±0.10

2.65 MAX

0.25

4° ±4

0.27 +0.07

–0.06

0.84 +0.44

–0.43

GAUGE PLANE

SEATING PLANE

BReference pad layout (reference IPC SOIC127P1030X265-28M)

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances

For Reference Only

(Reference JEDEC MS-013 AE)

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

ATerminal #1 mark area

0.41 ±0.10

2.20

0.65

9.60

1.27

PCB Layout Reference View