APU3146
200407061-1/28
Data and specifications subject to change without notice.
Technology Licensed from International Rectifier
DESCRIPTION
The APU3146 IC combines a Dual synchronous Buck
controller, providing a cost-effective, high performance
and flexible solution. The APU3146 can configured as 2-
independent or as 2-phase controller. The 2-phase con-
figuration is ideal for high current applications. The
APU3146 features 180 out of phase operation which re-
duces the required input/output capacitance and results
to few number of capacitor quantity. Other key features
offered by this device include two independent program-
mable soft starts, programmable switching frequency up
to 500KHz per phase, under voltage lockout function.
The current limit is provided by sensing the lower
MOSFET's on-resistance for optimum cost and perfor-
mance.
Dual Synchronous Controller with 180 out-of-phase
Configurable to 2-Independent Outputs or 2-Phase
Single Output
Current Sharing Using Inductor's DCR
Current Limit using MOSFET's RDS(ON)
Hiccup/Latched Current Limit
Latched Over-Voltage Protection
Vcc from 4.5V to 16V Input
Programmable Switching Frequency up to 500KHz
Two Independent Soft-Starts/ Shutdowns
0.8V Precision Reference Voltage Available
Power Good Output
External Frequency Synchronization
FEATURES
DUAL SYNCHRONOUS PWM CONTROLLER WITH
CURRENT SHARING CIRCUITRY AND AUTO-RESTART
Figure 1 - Typical application of APU3146 in 2-phase configuration with inductor current sensing
PACKAGE ORDER INFORMATION
DEVICE PACKAGE
APU3146O(/M) 28-Pin TSSOP(/SOIC WB)
APPLICATIONS
Embedded Computer Systems
Telecom Systems
2-Phase Power Supply
Point of Load Power Architectures DDR Memory Applications
Graphic Card
12V
PGood Q5
L4
Q4
C5
U1
1.8V @ 30A
R8
C16
L3
C17
R9
R7
C10
R4
C9
R3
C8
C3
C4 C13
C11
PGnd1
V
CL
V
OUT3
LDrv1
HDrv1
Fb1
V
P2
Fb2
LDrv2
HDrv2
VcH1 VcH2
Vcc
Gnd
Comp2
Comp1
SS1 / SD
PGood
V
REF
APU3146
Q3
Q2
C14
Sync
Rt
Hiccup
SS2 / SD
PGnd2
OCSet2
OCSet1
V
SEN1
V
SEN2
R2
R1
R6
D1
C12
D2
BAT54A
C18
R5
C15
R11
R10
2/28
APU3146
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=12V, VcH1=VcH2=VCL=12V and TA=0 to 70°C.
Typical values refer to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures
equal to the ambient temperature.
ABSOLUTE MAXIMUM RATINGS
Vcc, VCL Supply Voltage .............................................. -0.5V To 16V
VcH1 and VcH2 Supply Voltage ................................ -0.5V To 25V
PGOOD................. ................................................... -0.5V To 16V
Storage Temperature Range ...................................... -40°C To 125°C
Operating Junction Temperature Range ..................... -40°C To 125°C
Caution: Stresses above those listed in Absolute Maximum Ratings" may cause permanent damage to the device.
PACKAGE INFORMATION
28-PIN TSSOP (O) 28-PIN SOIC WIDE BODY(M)
PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS
Reference Voltage Section
Reference Voltage
Voltage Line Regulation
UVLO Section
UVLO Threshold - Vcc
UVLO Hysteresis - Vcc
UVLO Threshold - VcH1
UVLO Hysteresis - VcH1
UVLO Threshold - VcH2
UVLO Hysteresis - VcH2
Supply Current Section
Vcc Dynamic Supply Current
VcH1 & VcH2 Dynamic Current
VCL Dynamic Supply Current
Vcc Static Supply Current
VcH1/VcH2 Static Current
VCL Static Supply Current
5<Vcc<12
Supply Ramping Up
Ramp Up and Ramp Down
Supply Ramping Up
Ramp Up and Ramp Down
Supply Ramping Up
Ramp Up and Ramp Down
Freq=300KHz, CL=1500pF
Freq=300KHz, CL=1500pF
Freq=300KHz, CL=1500pF
SS=0V
SS=0V
SS=0V
0.805
0.02
4.2
0.25
3.5
0.1
3.5
0.1
10
15
15
10
6
6
V
%/V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
RthJA = 84°C/W RthJA=80oC/W
VREF
LREG
UVLOVCC
UVLOVCH1
UVLOVCH2
Dyn ICC
Dyn ICH
Dyn ICL
ICCQ
ICHQ
ICLQ
V
CC
Comp2
Rt
Sync
VcH2
HDrv2
Fb2
PGnd2 HDrv1
VcH1
OCSet1
Comp1
V
SEN1
SS1 / SD
Fb1
PGood
V
REF
Gnd
4
3
2
1
25
26
27
28
7
6
5
22
23
24
12 17
11 18
10 19
920
821
LDrv2
V
CL
14
13
LDrv1
PGnd1
15
16
V
P2
Hiccup
OCSet2
SS2 / SD
V
SEN2
V
OUT3
0.789
3.9
3.2
3.2
0.821
0.04
4.5
3.8
3.8
15
25
25
15
10
10
V
CC
Comp2
Rt
Sync
VcH2
HDrv2
Fb2
PGnd2 HDrv1
VcH1
OCSet1
Comp1
V
SEN1
SS1 / SD
Fb1
PGood
V
REF
Gnd
4
3
2
1
25
26
27
28
7
6
5
22
23
24
12 17
11 18
10 19
920
821
LDrv2
V
CL
14
13
LDrv1
PGnd1
15
16
V
P2
Hiccup
OCSet2
SS2 / SD
V
SEN2
V
OUT3
APU3146
3/28
PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS
Soft-Start Section
Charge Current
Power Good Section
VSENS1 Lower Trip Point
VSENS2 Lower Trip Point
PGood Output Low Voltage
Error Amp Section
Fb Voltage Input Bias Current
Transconductance 1
Transconductance 2
Error Amp Source/Sink Current
Input Offset Voltage for PWM1/2
VP2 Voltage Range
Oscillator Section
Frequency
Ramp Amplitude
Synch Frequency Range
Synch Pulse Duration
Synch High Level Threshold
Synch Low Level Threshold
VOUT3 Internal Regulator
Output Voltage
Output Current
Protection Section
OVP Trip Threshold
OVP Fault Prop Delay
Current Limit Threshold
Current Source
Hiccup Duty Cycle
Hiccup High Level Threshold
Hiccup Low Level Threshold
Output Drivers Section
Rise Time
Fall Time
Dead Band Time
Max Duty Cycle
Min Duty Cycle
Min Pulse Width
Thermal Shutdown Trip Point
Thermal Shutdown Hysteresis
SS=0V
VSENS1 Ramping Down
VSENS2 Ramping Down
ISINK=2mA
SS=3V
Fb to VREF
Note1
Rt(SET) to 30K
Note1
20% above free running freq
Note1
Note1
Output forced to 1.125VREF,Note1
Hiccup pin pulled high, Note1
Note1
CL=1500pF, Figure 2
CL=1500pF, Figure 2
Figure 2
Fb=0.6V, FSW=300KHz
Fb=1V
FSW=300KHz, Note1
Note 1
25
0.9VREF
0.9VREF
0.1
-0.1
100
0
1.25
300
6.2
1.15VREF
20
5
18
25
50
85
0
140
20
µA
V
V
V
µA
µmho
µmho
µA
mV
V
KHz
V
KHz
ns
V
V
V
mA
V
µs
µA
%
V
V
ns
ns
ns
%
%
ns
C
C
SSIB
PGFB1L
PGFB2H
IFB1
gm1
gm2
VOS(ERR)2
VP2
Freq
VRAMP
OVP
OCSet
Tr
Tf
TDB
DMAX
DMIN
Puls(min)
20
0.8VREF
0.8VREF
1400
1400
60
-5
0.8
255
200
2
5.9
50
1.1VREF
16
2
32
0.95VREF
0.95VREF
0.5
-0.5
2300
2300
140
+5
1.5
345
800
0.8
6.7
1.2VREF
5
24
0.8
50
50
100
Note 1: Guaranteed by design but not tested for production.
150
4/28
APU3146
PIN DESCRIPTIONS
PIN# PIN SYMBOL PIN DESCRIPTION
1
2
3
4
5,23
6,22
7,21
8
20
9,19
10,18
11,17
12,16
13,15
14
24
25
PGood
Vcc
VOUT3
Rt
VSEN2, VSEN1
Fb2,Fb1
Comp2, Comp1
SS2 / SD
SS1 / SD
OCSet2,OCSet1
VcH2, VcH1
HDrv2, HDrv1
PGnd2, PGnd1
LDrv2, LDrv1
VCL
Sync
Hiccup
Power Good pin. Low when any of the outputs fall 10% below the set voltages.
Supply voltage for the internal blocks of the IC.
Output of the internal LDO.
Switching frequency setting resistor. (see Figure 10 for selecting resistor values).
Sense pins for OVP and PGood. For 2-Phase operation tie these pins together.
Inverting inputs to the error amplifiers. In current sharing mode, Fb1 is connected to a
resistor divider to set the output voltage and Fb2 is connected to programming resistor to
achieve current sharing. In independent 2-channel mode, these pins work as feedback
inputs for each channel.
Compensation pins for the error amplifiers.
These pins provide soft-start for the switching regulator. An internal current source charges
external capacitors that are connected from these pins to ground which ramp up the
output of the switching regulators, preventing them from overshooting as well as limiting
the input current. The converter can be shutdown by pulling these pins below 0.3V.
Current limit resistor (RLIM) connection pins for output 1 and 2. The other ends of RLIMs are
connected to the corresponding switching nodes.
Supply voltage for the high side output drivers. These are connected to voltages that must
be typically 6V higher than their bus voltages. A 1µF high frequency capacitor must be
connected from these pins to GND to provide peak drive current capability.
Output drivers for the high side power MOSFETs. 1)
These pins serve as the separate grounds for MOSFET drivers and should be connected
to the system’s ground plane.
Output drivers for the synchronous power MOSFETs.
Supply voltage for the low side output drivers. This pin should be high for normal operation
The internal oscillator may be synchronized to an external clock via this pin.
When pulled High, it puts the device current limit into a hiccup mode. When pulled Low,
the output latches off, after an overcurrent event.
Figure 2 - Deadband time definition.
TDB(TYP)=(Deadband H_toL+Deadband L_to -H)/2
DEADBAND TIME
90%
10%
90%
10%
High Side
Driver HD
Low Side
Driver LD
Tr Tf
Deadband
H_to_L
Deadband
L_to_H
Tr Tf
2V
2V
APU3146
5/28
Figure 3 - Block diagram of APU3146.
PIN DESCRIPTIONS
PIN# PIN SYMBOL PIN DESCRIPTION
26
27
28
VP2
VREF
Gnd
Non-inverting input to the second error amplifier. In the current sharing mode, it is con-
nected to the programming resistor. In independent 2-channel mode it is connected to
VREF pin when Fb2 is connected to the resistor divider to set the output voltage.
Reference Voltage. The drive capability of this pin is about 2uA.
Analog ground for internal reference and control circuitry. Connect to PGnd plane with a
short trace.
BLOCK DIAGRAM
Bias
Generator
LDrv2
Two Phase
Oscillator
0.8V
3V
Ramp1
Sync
Gnd
HDrv2
VcH2
SS1 / SD
Comp2
Error Amp2
PWM Comp2
POR
V
OUT3
25uA
Reset Dom
LDrv1
V
CL
HDrv1
VcH1
Fb1
Comp1
Error Amp1
PWM Comp1
Reset Dom
Set1
Set2
Ramp2
64uA
Max
UVLO
VcH2
3.5V / 3.3V
VcH1
3.5V / 3.3V
4.2V / 4.0V
Fb2 PGnd2
Vcc
Rt
0.8V
SS2 / SD
20
22
21
6
28
3
12
13
11
15
17
18
V
P2
V
REF
PGood / OVP
PGood
R
S
Q
4
24
27
26
14
10
1
Q
S
R
0.3V
SS2
V
SEN1
V
SEN2
OCSet2
9
OVP
HDrv OFF / LDrv ON
2
8
7
23
5
Thermal
Shutdown
PGnd1
16
OCSet1
19
25uA
64uA
0.3V
SS1
Hiccup
25
Hiccup
Control
SS1
SS2
Mode
Regulator
Mode
Control
POR
Mode
0.8V
V
P2
Mode
20uA
20uA
POR
0.8V
3uA
SS2
3uA
SS1
1) These pins should not go negative (-0.5V), this may cause instability for the gate drive circuits. To prevent this,
a low forward voltage drop diode is required between these pins and ground as shown in Figure 1.
6/28
APU3146
FUNCTIONAL DESCRIPTION
information for current sharing. The voltage drops across
the current sense resistors (or DCR of inductors) are
measured and their difference is amplified by the slave
error amplifier and compared with the ramp signal to
generate the PWM pulses to match the output current.
In this mode the SS2 pin should be floating.
Introduction
The APU3146 is versatile device for high performance Buck
Figure 4 - Loss-less inductive current sensing
and current sharing.
In the diagram, L1 and L2 are the output inductors. RL1
and RL2 are inherent inductor resistances. The resistor
R1 and capacitor C1 are used to sense the average in-
ductor current. The voltage across the capacitors C1
and C2 represent the average current flowing into resis-
tance RL1 and RL2. The time constant of the RC network
should be equal or at most three times larger than the
time constant L1/RL1.
L1 R
L1
R1
L2 R
L2
R2 C2
APU3146
Comp
0.8V
Fb1
VP2
FB2
Master E/A
Slave E/A
PWM Comp2
PWM Comp1
C1
V
OUT
L1
R
L1
R1×C1=(1~3)× ---(1)
Figure 5 - 30A Current Sharing using Inductor sensing
(5A/Div)
converters. It is included of two synchronous Buck con-
trollers which can be operated both in two independent
mode or in 2-phase mode.
The timing of the IC is provided through an internal oscil-
lator circuit. These are two out-of-phase oscillators that
can be programmed up to 400KHz per phase.
Supply Voltage
Vcc is the supply voltage for internal controller. The op-
erating range is from 4.5V to 16V. It also is fed to the
internal LDO. When Vcc is below under-voltage thresh-
old, all MOSFET drivers will be turned off.
Internal Regulator
The regulator powers directly from VCC and generates a
regulated voltage (Typ. 6.2V@50mA). The output is pro-
tected for short circuit. This voltage can be used for charge
pump circuitry as describe in Figure12.
Input Supplies UnderVoltage LockOut
The APU3146 UVLO block monitors three input voltages
(VCC, VCH1 and VCH2) to ensure reliable start up. The
MOSFET driver output turn off when any of the supply
voltages drops below set thresholds. Normal operation
resumes once the supply voltages rise above the set
values.
Independent Mode
In this mode the APU3146 provides control to two inde-
pendent output power supplies with either common or
different input voltages. The output voltage of each indi-
vidual channel is set and controlled by the output of the
error amplifier, which is the amplified error signal from
the sensed output voltage and the reference voltage. The
error amplifier output voltage is compared to the ramp
signal thus generating fixed frequency pulses of variable
duty-cycle, which are applied to the FET drivers, Fig-
ure18 shows a typical schematic for such application.
2-Phase Mode
This feature allows to connect both outputs together to
increase current handling capability of the converter to
support a common load. The current sharing can be done
either using external resistors or sensing the DCR of
inductors (see Figure 4). In this mode, one control loop
acts as a master and sets the output voltage as a regu-
lar Voltage Mode Buck controller and the other control
loop acts as a slave and monitors the current
APU3146
7/28
Dual Soft-Start
The APU3146 has programmable soft-start to control the
output voltage rise and limit the inrush current during
start-up. It provides a separate Soft-Start function for each
outputs. This will enable to sequence the outputs by
controlling the rise time of each output through selection
of different value soft-start capacitors. The soft-start pins
will be connected together for applications where, both
outputs are required to ramp-up at the same time.
To ensure correct start-up, the soft-start sequence ini-
tiates when the VCC, VCH1 and VCH2 rise above their
threshold (4.2V and 3.5V respectively) and generate the
Power On Reset (POR) signal. Soft-start function oper-
ates by sourcing an internal current to charge an exter-
nal capacitor to about 3V. Initially, the soft-start function
clamps the E/A’s output of the PWM converter. During
power up, the converter output starts at zero and thus
the voltage at Fb is about 0V. A current (64µA) injects
into the Fb pin and generates a voltage about 1.6V
(64µA×25K) across the negative input of E/A and (see
Figure6).
The magnitude of this current is inversely proportional to
the voltage at soft-start pin. The 25µA current source
starts to charge up the external capacitor. In the mean
time, the soft-start voltage ramps up, the current flowing
into Fb pin starts to decrease linearly and so does the
voltage at negative input of E/A.
SS1 / SD
Comp2
Error Amp2
POR
25uA
Fb1
Comp1
Error Amp1
64uA
Max
Fb2
0.8V
SS2 / SD
20
22
21
6
V
P2
26
8
7
25uA
64uA
Figure 6 -Soft-start circuit for APU3146
When the soft-start capacitor is around 1V, the current
flowing into the Fb pin is approximately 32µA. The volt-
age at the positive input of the E/A is approximately:
The E/A will start to operate and the output voltage starts
to increase. As the soft-start capacitor voltage contin-
ues to go up, the current flowing into the Fb pin will keep
decreasing. Because the voltage at pin of E/A is regu-
lated to reference voltage 0.8V, the voltage at the Fb is:
V
FB
= 0.8-(25K×Injected Current)
The feedback voltage increases linearly as the injecting
current goes down. The injecting current drops to zero
when soft-start voltage is around 2V and the output volt-
age goes into steady state. Figure 7 shows the theoreti-
cal operational waveforms during soft-start.
32µA×25K = 0.8V
Soft-Start
Voltage
Voltage at negative input
of Error Amp
Voltage at Fb pin
Current flowing
into Fb pin
64uA
0uA
0V
0.8V
≅
1.6V
0.8V
0V
3V
≅
2V
≅
1V
Output of POR
Figure 7 - Theoretical operational waveforms
during soft-start.
The output start-up time is the time period when soft-
start capacitor voltage increases from 1V to 2V. The
start-up time will be dependent on the size of the exter-
nal soft-start capacitor. The start-up time can be esti-
mated by: 25µA×T
START
/C
SS
= 2V-1V
8/28
APU3146
L1
R
SET
APU3146
OCSet
I
OCSET
V
OUT
Hiccup
Control
Q1
Q2
Figure 9 - Diagram of the over current sensing.
VOCSET = IOCSET×RSET-RDS(ON)×iL ---(2)
VOCSET = IOCSET×RSET - RDS(ON)×IL = 0
The critical inductor current can be calculated by set-
ting:
ISET = IL(CRITICAL)= ---(3)
RSET×IOCSET
RDS(ON)
The internal current source develops a voltage across
RSET. When the low side switch is turned on, the induc-
tor current flows through the Q2 and results a voltage
which is given by:
The value of RSET should be checked in an actual
circuit to ensure that the Over Current Protection
circuit activates as expected. The APU3146 current
limit is designed primarily as disaster preventing, "no
blow up" circuit, and is not useful as a precision
current regulator.
In two independent mode, the output of each channel
is protected independently which means if one output
is under overload or short circuit condition, the other
output will remain functional. The OCP set limit can be
programmed to different levels by using the external
resistors. This is valid for both hiccup mode and latch
up mode.
In 2-phase configuration, the OCP's output depends on
any one channel, which means as soon as one
channel goes to overload or short circuit condition the
output will enter either hiccup or latch-up, dependes on
status of Hiccup pin.
For a given start up time, the soft-start capacitor can be
calculated by: CSS ≅ 25µA×TSTART/1V
Over-Current Protection
The APU3146 can provide two different schemes for Over-
Current Protection (OCP). When the pin Hiccup is pulled
high, the OCP will operate in hiccup mode. In this mode,
during overload or short circuit, the outputs enter hiccup
mode and stay in that mode until the overload or short
circuit is removed. The converter will automatically re-
cover.
When the Hiccup pin is pulled low, the OCP scheme
will be changed to the latch up type, in this mode the
converter will be turned off during Overcurrent or short
circuit. The power needs to be recycled for normal
operation.
Each phase has its own independent OCP circuitry.
The OCP is performed by sensing current through the
RDS(ON) of low side MOSFET. As shown in Figure 9, an
external resistor (RSET) is connected between OCSet pin
and the drain of low side MOSFET (Q2) which sets the
current limit set point.
The soft-start is part of Over Current Protection scheme,
during the overload or short circuit condition the external
soft start capacitors will be charged and discharged in
certain slope rate to achieve the hiccup mode function.
Out-of-Phase Operation
The APU3146 drives its two output stages 180 out-of-
phase. In 2-phase configuration, the two inductor ripple
currents cancel each other and result in a reduction of
the output current ripple and yield a smaller output ca-
pacitor for the same ripple voltage requirement.
In single input voltage applications, the input ripple cur-
rent reduces. This result in much smaller input capacitor's
RMS current and reduces the input capacitor quantity.
SS1 / SD
20
25uA
3uA
Hiccup
If using one soft start capacitor in dual configuration for a
precise power up the OCP needs to be set to latch mode.
Figure 8 - 3uA current source for discharging soft
start-capacitor during Hiccup mode
APU3146
9/28
Frequency Synchronization
The APU3146 is capable of accepting an external digital
synchronization signal. Synchronization will be enabled
by the rising edge at an external clock. Per-channel switch-
ing frequency is set by external resistor (Rt). The free
running oscillator frequency is twice the per-channel fre-
quency. During synchronization, Rt is selected such that
the free running frequency is 20% below the sync fre-
quency. Synchronization capability is provided for both 2-
output and 2-phase configurations. When unused, the
Sync pin will remain floating and is noise immune.
Thermal Shutdown
Temperature sensing is provided inside APU3146. The trip
threshold is typically set to 140C. When trip threshold is
exceeded, thermal shutdown turns off both FETs. Ther-
mal shutdown is not latched and automatic restart is ini-
tiated when the sensed temperature drops to normal
range. There is a 20C hysteresis in the shutdown thresh-
old.
Shutdown
The outputs can be shutdown independently by pulling
the respective soft-start pins below 0.3V. This can be
easily done by using an external small signal transis-
tor. During shutdown both MOSFETs will be turned off.
During this mode the LDO will stay on. Cycling soft-
start pins will clear all fault latches and normal opera-
tion will resume.
Low Temperature Start-Up
The controller is capable of starting at -40C ambient
temperature.
Operation Frequency Selection
Power Good
The APU3146 provides a power good signal. The power
good signal should be available after both outputs have
reached regulation. This pin needs to be externally pulled
high. High state indicates that outputs are in regulation.
Power good will be low if either one of the output voltages
is 10% below the set value. There is only one power good
for both outputs.
Over-Voltage Protection OVP
Over-voltage is sensed through separate VOUT sense pins
Vsen1 and Vsen2. A separate OVP circuit is provided for
each output. Upon over-voltage condition of either one of
the outputs, the OVP forces a latched shutdown on both
outputs. In this mode, the upper FET drivers turn-off and
the lower FET drivers turn-on, thus crowbaring the out-
puts. Reset is performed by recycling either Vcc.
Error Amplifier
The APU3146 is a voltage mode controller. The error am-
plifiers are of transconductance type. In independent mode,
each amplifier closes the loop around its own output volt-
age. In current sharing mode, amplifier 1 becomes the
master which regulates the common output voltage. Am-
plifier 2 performs the current sharing function. Both am-
plifiers are capable of operating with Type III compensa-
tion control scheme.
Figure 10- Switching Frequency versus External Resistor.
The optimum operating frequency range for APU3146 is
300KHz per phase, theoretically the APU3146 can be
operated at higher switching frequency (e.g. 500KHz).
However the power dissipation for IC, which is function
of applied voltage, gate drivers load and switching fre-
quency, will result in higher junction temperature of de-
vice. It may exceed absolute maximum rating of junc-
tion temperature, figure 18 (page 16) shows case tem-
perature versus switching frequency with different ca-
pacitive loads.
This should be considered when using APU3146 for such
application. The below equation shows the relationship
between IC's maximum power dissipation and Junction
temperature:
Where:
Tj: Maximum Operating Junction Temperature (125°C)
TA: Ambient Temperature (70°C)
θJA = Thermal Impedance of package (84°C/W)
For Tj=125°C TA=70°C and θJA=84°C/W
This will result to power dissipation of 650mW, this in-
cludes biasing current for all four external MOSFETs
and IC's biasing current.
The switching frequency is determined by an external
resistor (Rt). The switching frequency is approximately
inversely proportioned to resistance (see Fig 10).
Per channel Switching Frequency vs. RT
200
250
300
350
400
450
500
550
600
650
700
10 20 30 40 50
RT(Kohm)
Switching Frequency in KHz
Pd = ΤJ-ΤA
θJA
10/28
APU3146
APPLICATION INFORMATION
Design Example:
The following example is a typical application for APU3146,
the schematic is Figure18 on page17.
Output Voltage Programming
Output voltage is programmed by reference voltage and
external voltage divider. The Fb1 pin is the inverting input
of the error amplifier, which is referenced to the voltage
on non-inverting pin of error amplifier. For this applica-
tion, this pin (VP) is connected to reference voltage (VREF).
The output voltage is defined by using the following equa-
tion:
When an external resistor divider is connected to the
output as shown in Figure 11.
Figure 11 - Typical application of the APU3146 for
programming the output voltage.
Equation (4) can be rewritten as:
Will result to:
VOUT(2.5V) = 2.5V
VREF = 0.8V
R9= 2.14K, R5= 1K
If the high value feedback resistors are used, the input
bias current of the Fb pin could cause a slight increase
in output voltage. The output voltage can be set more
accurately by using low value, precision resistors.
For a start-up time of 4ms for both output, the soft-start
capacitor will be 0.1µF. Connect ceramic capacitors at
0.1µF from SS1 pin and SS2 pin to GND.
Supply VCH1 and VCH2
To drive the high side switch, it is necessary to supply
a gate voltage at least 4V grater than the bus voltage.
This is achieved by using a charge pump configuration
as shown in Figure 12. This method is simple and inex-
pensive. The operation of the circuit is as follows: when
the lower MOSFET is turned on, the capacitor (C1)
charges up to VOUT3, through the diode (D1). The bus
voltage will be added to this voltage when upper
MOSFET turns on in next cycle, and providing supply
voltage (VCH1) through diode (D2). Vc is approximately:
Capacitors in the range of 0.1µF and 1µF are generally
adequate for most applications. The diode must be a
fast recovery device to minimize the amount of charge
fed back from the charge pump capacitor into VOUT3.
The diodes need to be able to block the full power rail
voltage, which is seen when the high side MOSFET is
switched on. For low voltage application, schottky di-
odes can be used to minimize forward drop across the
diodes at start up.
Figure 12 - Charge pump circuit.
R6 = R5 ×
- 1
VOUT
VP
( )
Fb
APU3146
V
OUT
R
5
R
6
V
REF
V
P
VCH1 ≅ VOUT3 + VBUS - (VD1 + VD2)
VIN = 12V
VOUT(2.5V) = 2.5V @ 10A
VOUT(1.8V) = 1.8V @ 10A
∆VOUT = Output voltage ripple ≅ 3% of VOUT
FS = 300KHz
L2
APU3146
D1
C1
VCH1
HDrv
Regulator Q1
Q2
V
OUT3
C2
V
BUS
D2
C3
Css ≅ 25×tSTART (µF) ---(5)
Where tSTART is the desired start-up time (ms)
VOUT = VP × 1 +
---(4)
R6
R5
VP2 = VREF = 0.8V
( )
VOUT(1.8V) = 1.8V
VREF = 0.8
R7= 1.24K, R8 = 1K
Soft-Start Programming
The soft-start timing can be programmed by selecting
the soft-start capacitance value. The start-up time of
the converter can be calculated by using:
APU3146
11/28
For higher efficiency, low ESR capacitors is recom-
mended.
Choose two Poscap from Sanyo 16TPB47M (16V, 47µF,
70mΩ ) with a maximum allowable ripple current of 1.4A
for inputs of each channel.
Inductor Selection
The inductor is selected based on operating frequency,
transient performance and allowable output voltage ripple.
Low inductor value results to faster response to step
load (high ∆i/∆t) and smaller size but will cause larger
output ripple due to increase of inductor ripple current.
As a rule of thumb, select an inductor that produces a
ripple current of 10-40% of full load DC.
For the buck converter, the inductor value for desired
operating ripple current can be determined using the fol-
lowing relation:
VIN - VOUT = L× ; ∆t = D× ; D =
1
fS
VOUT
VIN
∆i
∆t
L = (VIN - VOUT)× ---(7)
VOUT
VIN×∆i×fS
Where:
VIN = Maximum Input Voltage
VOUT = Output Voltage
∆i = Inductor Ripple Current
fS = Switching Frequency
∆t = Turn On Time
D = Duty Cycle
Where:
∆VO = Output Voltage Ripple
∆i = Inductor Ripple Current
∆VO = 3% of VO will result to ESR(2.5V) =19.7mΩ and
ESR(1.8V) =16mΩ
ESR ≤ ---(8)
∆VO
∆IO
The Sanyo TPC series, Poscap capacitor is a good choice.
The 6TPC330M, 330µF, 6.3V has an ESR 40mΩ. Se-
lecting two of these capacitors in parallel for 2.5V out-
put, results to an ESR of ≅ 20mΩ which achieves our
low ESR goal. And selecting four of these capacitors in
parallel for 1.8V output, results to an ESR of ≅ 10mΩ
which achieves our low ESR goal.
The capacitors value must be high enough to absorb the
inductor's ripple current.
Power MOSFET Selection
The APU3146 uses four N-Channel MOSFETs. The se-
lections criteria to meet power transfer requirements is
based on maximum drain-source voltage (VDSS), gate-
source drive voltage (VGS), maximum output current, On-
resistance RDS(ON) and thermal management.
The both control and synchronous MOSFETs must have
a maximum operating voltage (VDSS) that exceeds the
maximum input voltage (VIN).
Input Capacitor Selection
The 1800 out of phase will reduce the RMS value of the
ripple current seen by input capacitors. This reduces
numbers of input capacitors. The input capacitors must
be selected that can handle both the maximum ripple
RMS at highest ambient temperature as well as the
maximum input voltage. The RMS value of current ripple
for duty cycles under 50% is expressed by:
For ∆i(2.5V) = 38%(IO(2.5V) ), then the output inductor will
be:
L4 = 1.71µH
For ∆i(1.8V) = 30%(IO(1.8V) ), then the output inductor will
be:
L3 = 1.7µH
Panasonic provides a range of inductors in different val-
ues and low profile for large currents.
Output Capacitor Selection
The criteria to select the output capacitor is normally
based on the value of the Effective Series Resistance
(ESR). In general, the output capacitor must have low
enough ESR to meet output ripple and load transient
requirements, yet have high enough ESR to satisfy sta-
bility requirements. The ESR of the output capacitor is
calculated by the following relationship:
IRMS= (I1
2D1(1-D1)+I2
2D2(1-D2)-2I1I2D1D2) --- (6)
Where:
IRMS is the RMS value of the input capacitor current
D1 and D2 are the duty cycle for each output
I1 and I2 are the current for each output
For this application the IRMS =4.8A
(ESL, Equivalent Series Inductance is neglected)
Choose ETQP6F1R8BFA (1.71µH, 14A, 3.3mΩ) both
for L3 and L4.
For 2-phase application, equation (7) can be used for
calculating the inductors value. In such case the induc-
tor ripple current is usually chosen to be between 10-
40% of maximum phase current.
12/28
APU3146
Choose IRF7457 both for control and synchronous
MOSFET. This device provide low on-resistance in a com-
pact SOIC 8-Pin package.
The MOSFET have the following data:
The total conduction losses for each output will be:
The switching loss is more difficult to calculate, even
though the switching transition is well understood. The
reason is the effect of the parasitic components and
switching times during the switching procedures such
as turn-on / turnoff delays and rise and fall times. The
control MOSFET contributes to the majority of the switch-
ing losses in a synchronous Buck converter. The syn-
chronous MOSFET turns on under zero voltage condi-
tions, therefore, the switching losses for synchronous
MOSFET can be neglected. With a linear approxima-
tion, the total switching loss can be expressed as:
These values are taken under a certain condition test.
For more details please refer to the IRF7457 data sheet.
By using equation (9), we can calculate the total switch-
ing losses.
Programming the Over-Current Limit
The over-current threshold can be set by connecting a
resistor (RSET) from drain of low side MOSFET to the
OCSet pin. The resistor can be calculated by using equa-
tion (3).
The RDS(ON) has a positive temperature coefficient and it
should be considered for the worse case operation.
PCON(TOTAL, 2.5V) = PCON(UPPER) + PCON(LOWER)
PCON(TOTAL, 2.5V) = 1.0W
PSW(TOTAL,2.5V) = 0.414W
PSW(TOTAL,1.8V) = 0.414W
IRF7457
VDSS = 20V
ID = 15A
RDS(ON) = 7mΩ
Where:
VDS(OFF) = Drain to Source Voltage at off time
tr = Rise Time
tf = Fall Time
T = Switching Period
ILOAD = Load Current
PSW = ILOAD ---(9)
×
VDS(OFF)
2
tr + tf
T×
IRF7457
tr = 16ns
tf = 7ns
RDS(ON) = 7mΩ×1.5 = 10.5mΩ
ISET ≅ IO(LIM) = 10A×1.5 = 15A
(50% over nominal output current)
This results to:
RSET = R1=R6=7.8KΩ
V
DS
V
GS
10%
90%
t
d
(ON)
t
d
(OFF)
t
r
t
f
Figure 13 - Switching time waveforms.
From IRF7457 data sheet we obtain:
2
2
PCOND(Upper Switch) = ILOAD×RDS(ON)×D×ϑ
PCOND(Lower Switch) = ILOAD×RDS(ON)×(1 - D)×ϑ
ϑ = RDS(ON) Temperature Dependency
The gate drive requirement is almost the same for both
MOSFETs. Logic-level transistor can be used and cau-
tion should be taken with devices at very low VGS to pre-
vent undesired turn-on of the complementary MOSFET,
which results a in shoot-through.
The total power dissipation for MOSFETs includes con-
duction and switching losses. For the Buck converter,
the average inductor current is equal to the DC
load current. The conduction loss is defined as:
The RDS(ON) temperature dependency should be consid-
ered for the worst case operation. This is typically given
in the MOSFET data sheet. Ensure that the conduction
losses and switching losses do not exceed the package
ratings or violate the overall thermal budget.
PCON(TOTAL, 1.8V) = PCON(UPPER) + PCON(LOWER)
PCON(TOTAL, 1.8V) = 1.0W
APU3146
13/28
The ESR zero of the output capacitor is expressed as
follows:
Figure 15 - Compensation network without local
feedback and its asymptotic gain plot.
The transfer function (Ve / VOUT) is given by:
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a gain
and zero, expressed by:
|H(s)| is the gain at zero cross frequency.
First select the desired zero-crossover frequency (FO1):
V
OUT
Vp=V
REF
R
5
R
6
R
4
C
9
Ve
E/A
F
Z
H(s) dB
Frequency
Gain(dB)
Fb
Comp
FESR = ---(10A)
1
2π×ESR×Co
H(s) = gm× × ---(11)
( )
R5
R6 + R5
1 + sR4C9
sC9
FZ = ---(13)
1
2π×R4×C9
|H(s=j×2π×FO)| = gm× ×R4 ---(12)
R5
R6+R5
Feedback Compensation
The APU3146 is a voltage mode controller; the control
loop is a single voltage feedback path including error
amplifier and error comparator. To achieve fast transient
response and accurate output regulation, a compensa-
tion circuit is necessary. The goal of the compensation
network is to provide a closed loop transfer function with
the highest 0dB crossing frequency and adequate phase
margin (greater than 45).
The output LC filter introduces a double pole, –40dB/
decade gain slope above its corner resonant frequency,
and a total phase lag of 180 (see Figure 14). The Reso-
nant frequency of the LC filter is expressed as follows:
Where: Lo is the output inductor
For 2-phase application, the effective output
inductance should be used
Co is the total output capacitor
Figure 14 shows gain and phase of the LC filter. Since
we already have 180 phase shift just from the output
FLC = ---(10)
1
2π× LO×CO
Gain
F
LC
0dB
Phase
0
F
LC
-180
Frequency Frequency
-40dB/decade
Figure14 - gain and phase of LC filter
The APU3146’s error amplifier is a differential-input
transconductance amplifier. The output is available for
DC gain control or AC phase compensation.
The E/A can be compensated with or without the use of
local feedback. When operated without local feedback,
the transconductance properties of the E/A become evi-
dent and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC circuit
from Comp pin to ground as shown in Figure 15.
Note that this method requires the output capacitor to
have enough ESR to satisfy stability requirements. In
general, the output capacitor’s ESR generates a zero
typically at 5KHz to 50KHz which is essential for an
acceptable phase margin.
FO1 > FESR and FO1 ≤ (1/5 ~ 1/10)×fS
14/28
APU3146
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
FO1 = Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R5 and R6 = Resistor Dividers for Output Voltage
Programming
gm = Error Amplifier Transconductance
This results to R4=2.61K
Choose R4=2.61K
To cancel one of the LC filter poles, place the zero be-
fore the LC filter resonant frequency pole:
Using equations (13) and (15) to calculate C9, we get:
Same calcuation For V1.8V will result to: R3 = 2.8K and
C8 = 22nF
One more capacitor is sometimes added in parallel with
C9 and R4. This introduces one more pole which is mainly
used to suppress the switching noise. The additional
pole is given by:
The pole sets to one half of switching frequency which
results in the capacitor CPOLE:
C9 ≅ 17.18nF; Choose C9 =18nF
FLC = 4.75KHz
R5 = 1K
R6 = 2.14K
gm = 2000µmho
For V2.5V:
VIN = 12V
VOSC = 1.25V
FO1 = 30KHz
FESR = 12KHz
R4 = × × × ---(14)
FO1×FESR
FLC2
VOSC
VIN
R5 + R6
R5
1
gm
For:
Lo = 1.71µH
Co = 660µF
FZ ≅ 75%FLC
FZ ≅ 0.75×1
2π LO × CO
---(15)
FZ = 3.56KHz
R4 = 2.61K
FP =
2π×R4×
1
C9×CPOLE
C9 + CPOLE
CPOLE = ≅
for FP << fS
2
1
π×R4×fS
π×R4×fS -
1
1
C9
For a general solution for unconditional stability for ce-
ramic output capacitor with very low ESR or any type of
output capacitors, in a wide range of ESR values we
should implement local feedback with a compensation
network. The typically used compensation network for a
voltage-mode controller is shown in Figure 16.
Figure 16- Compensation network with local
feedback and its asymptotic gain plot.
In such configuration, the transfer function is given by:
The error amplifier gain is independent of the transcon-
ductance under the following condition:
By replacing ZIN and Zf according to Figure 16, the trans-
former function can be expressed as:
As known, transconductance amplifier has high imped-
ance (current source) output, therefore, consider should
be taken when loading the E/A output. It may exceed its
source/sink output current capability, so that the ampli-
fier will not be able to swing its output voltage over the
necessary range.
The compensation network has three poles and two ze-
ros and they are expressed as follows:
1 - gmZf
1 + gmZIN
Ve
VOUT =
gmZf >> 1 and gmZIN >>1 ---(16)
H(s) =
1+sR7
×(1+sR8C10)
(1+sR7C11)×[1+sC10(R6+R8)]
×[ ( )]
1
sR6(C12+C11)C12C11
C12+C11
V
OUT
Vp=V
REF
R
5
R
6
R
8
C
10
C
12
C
11
R
7
Ve
F
Z
1
F
Z
2
F
P
2
F
P
3
E/A
Z
f
Z
IN
Frequency
Gain(dB)
H(s) dB
Fb
Comp
APU3146
15/28
Cross Over Frequency:
The stability requirement will be satisfied by placing the
poles and zeros of the compensation network according
to following design rules. The consideration has been
taken to satisfy condition (16) regarding transconduc-
tance error amplifier.
These design rules will give a crossover frequency ap-
proximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load tran-
sient response. The DC gain will be large enough to pro-
vide high DC-regulation accuracy (typically -5dB to -12dB).
The phase margin should be greater than 45 for overall
stability.
Based on the frequency of the zero generated by ESR
versus crossover frequency, the compensation type can
be different. The table below shows the compensation
type and location of crossover frequency.
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Lo = Output Inductor
Co = Total Output Capacitors
FO = R7×C10× ×
VIN
VOSC
1
2π×Lo×Co ---(17)
FP1 = 0
1
2π×C10×(R6 + R8)
FZ2 = ≅1
2π×C10×R6
FZ1 = 1
2π×R7×C11
FP3 = ≅
1
2π×R7×
1
2π×R7×C12
FP2 = 1
2π×R8×C10
( )
C12×C11
C12+C11
Details are dicussed in application Note AN-1043 which
can be downloaded from the IR Web-Site.
Compensator
Type
Type II (PI)
Type III (PID)
Method A
Type III (PID)
Method B
Location of Zero
Crossover Frequency
(FO)
FPO < FZO < FO < fS/2
FPO < FO < FZO < fS/2
FPO < FO < fS/2 < FZO
Typical
Output
Capacitor
Electrolytic,
Tantalum
Tantalum,
Ceramic
Ceramic
Table - The compensation type and location of zero
crossover frequency.
The slave error amplifier is a differential-input transcon-
ductance amplifier, in 2-phase configuration the main goal
for the slave feed back loop is to control the inductor
current to match the masters inductor current as well
provides highest bandwidth and adequate phase margin
for overall stability. The following analysis is valid for both
using external current sense resistor and using DCR of
inductors.
Where:
VIN = Input Voltage
VOUT = Output Voltage
L2 = Output Inductor
VOSC = Oscillator Peak Voltage
G(s) = = ---(18)
IL2(s)
Ve(s)
VIN - VOUT
sL2 × VOSC
D(s) = =
Ve(s)
RS2 × IL2(s)
1 + sC2R2
sC2
( )
RS1
RS2
( )
gm××---(19)
L
2
L
1
C
2
R
2
R
S2
R
S1
Ve
I
L2
I
L1
Fb2
E/A2 Comp2
Vp2
H(s)=[G(s) × D(s) × RS2]
1+sR2C2
sC2
( )( )
gm×RS1
RS2 ( )
VIN-VOUT
sL2×VOSC
H(s)=RS2×××
Compensation for Slave Error Amplfier for 2-Phase
Configuration
The transfer function of power stage is expressed by:
As shown the transfer function is a function of inductor
current.
The transfer function for the compensation network is
given by equation (19), when using a series RC circuit
as shown in Figure 17:
Figure 17 - The PI compensation network
for slave channel.
The loop gain function is:
16/28
APU3146
From (20), R2 can be express as:
Set the zero of compensator to be half of FLC(SLAVE), the
compensator capacitor, C2, can be calculated as:
When using the DCR of inductors as current sense ele-
ment, replace RS1 in equation (21) with DCR value of in-
ductor.
H(Fo) = gm×RS1×R2× =1 ---(20)
VIN - VOUT
2π×Fo×L2×VOSC
R2 = ×2π × FO2 × L2 × VOSC
VIN - VOUT
FLC(SLAVE) =1
2π L2×COUT
Fz = FLC(SLAVE)
2
C2 = ---(22)
1
2π × R2 × Fz
Layout Consideration
The layout is very important when designing high fre-
quency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
Start by placing the power components. Make all the
connections in the top layer with wide, copper filled ar-
eas. The inductor, output capacitor and the MOSFET
should be as close to each other as possible. This helps
to reduce the EMI radiated by the power traces due to
the high switching. Place input capacitor near to the
drain of the high-side MOSFET.
The layout of driver section should be designed for a low
resistance (a wide, short trace) and low inductance (a
wide trace with ground return path directly beneath it),
this directly affects the driver's performance.
To reduce the ESR, replace the one input capacitor with
two parallel ones. The feedback part of the system should
be kept away from the inductor and other noise sources
and must be placed close to the IC. In multilayer PCB's,
use one layer as power ground plane and have a sepa-
rate control circuit ground (analog ground), to which all
signals are referenced. The goal is to localize the high
current paths to a separate loops that does not interfere
with the more sensitive analog control function. These
two grounds must be connected together on the PC board
layout at a single point.
Select a zero crossover frequency for control loop (FO2)
1.25 times larger than zero crossover frequency for volt-
age loop (FO1):
1
gm × RS1
---(21)
Fo2 ≅ 1.25%xF01
Figure18- Case Temperature versus Switching Frequency at Room Temperature
Test Condition: Vin=Vcl=Vch1=Vch2=12V, Capacitors used as loads for output
drivers.
Switching Frequency vs. Case Temp
30
40
50
60
70
80
90
200 300 400 500 600 700
Freq (KHz)
Case temp (oC)
100pF
1000pF
1800pF
3300pF
APU3146
17/28
12V
PGood
C1
47uF
C2
47uF
L1
Q5
IRF7457
L4
Q4
IRF7457
C5
1uF
U1
1.8V @ 10A
C16
4x 330uF, 40m
Ω
6TPB330M
L3
R7
1.24K
C10
0.1uF
R4
C9
R3
C8
C3
1uF
C4
1uF
C13
1uF
C11
0.1uF
PGnd1
V
CL
V
OUT3
LDrv1
HDrv1
Fb1
V
P2
Fb2
LDrv2
HDrv2
VcH1 VcH2
Vcc
Gnd
Comp2
Comp1
SS1 / SD
PGood
V
REF
APU3146
Q3
IRF7457
Q2
IRF7457
C14
2x 47uF
16TPB47M
Sync
Rt
Hiccup
SS2 / SD
PGnd2
OCSet2
OCSet1
V
SEN1
R2
R1
R6
D1
BAT54S
1uH
33K
20nF 2.8K
2.61K
18nF
C12
1uF
7.8K
7.8K
D2
BAT54A
1.7uH
1.7uH
C15
0.1uF
2.5V @ 10A
R9
2.14K
R5
1K
R8
1K
C18
2x 330uF, 40m
Ω
6TPB330M
C17
2x 47uF
16TPB47M
R20
1.24K
R21
1K
V
SEN1
V
SEN1
R22
2.24K
R23
1K
V
SEN2
V
SEN2
V
SEN2
Figure 19 - Typical application of APU3146.
12V input and two independent outputs.
18/28
APU3146
TYPICAL OPERATING CHARACTERISTICS
Test Conditions:
VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=300KHz
Figure 20 - Input Supply Ramps up.
Ch1: 1.8V, Ch2: 2.5V, Ch3: Input Supply
Figure 21 - Input Supply Ramps up/down.
Ch1: 1.8V, Ch2: 2.5V, Ch3: Input Supply
Figure 22 - Normal condition at No Load.
Ch1: HDrv2, Ch2: HDrv1, Ch3 and Ch4: Inductor
Currents
Figure 23 - Normal condition at 10A Load.
Ch1: HDrv2, Ch2: HDrv1, Ch3 and Ch4: Inductor
Currents
Ch3:ch4: 5A/div Ch3:ch4: 5A/div
APU3146
19/28
Figure 24 - Soft_Start.
Ch1: SS2, Ch2: 1.8V, Ch3: SS1, Ch4: 2.5V
Figure 25 - Soft_Start.
Ch1: Vin, Ch2: Vout3(LDO), Ch3: SS2, Ch4: SS2
Figure 26 - Deadband Time (1.8V Output).
Ch1: LDrv2, Ch2: HDrv2, Ch3: Switching Node Figure 27 - Deadband Time (2.5V Output).
Ch1: LDrv1, Ch2: HDrv1, Ch3: Switching Node
TYPICAL OPERATING CHARACTERISTICS
Test Conditions:
VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=300KHz
20/28
APU3146
Figure 28 - Shut Down (Pulling down the SS1 pin).
Ch1: HDrv1, Ch2: LDrv1, Ch3: SS1
Figure 29 - Shut Down (pulling down the SS2 pin).
Ch1: HDrv2, Ch2: LDrv2, Ch3: SS2
Figure 30 - High side and Low side Drivers peak
Current for 1.8V Output
Ch1: HDrv2, Ch2: LDrv2, Ch3: High Side Peak
Current, Ch4: Low Side Peak Current
Figure 31 - High side and Low side Drivers peak
Current for 2.5V Output
Ch1: HDrv1, Ch2: LDrv1, Ch3: High Side Peak
Current, Ch4: Low Side Peak Current
Ch3:ch4: 1A/div Ch3:ch4: 1A/div
TYPICAL OPERATING CHARACTERISTICS
Test Conditions:
VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=300KHz
APU3146
21/28
Figure 32 - Load Transient Response.
Ch2: 2.5V, Ch4: Step Load (0-10A)
Figure 33 - Load Transient Response.
Ch1: 1.8V, Ch3: Step Load (0-10A)
Figure 35 - Short Circuit Condition (Hiccup Mode).
Ch1: SS1 pin, Ch2: SS2 pin, Ch3 and Ch4 : Inductor
Currents
Ch3:ch4: 5A/div Ch3:ch4: 5A/div
Ch3:ch4: 10A/div
TYPICAL OPERATING CHARACTERISTICS
Test Conditions:
VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=300KHz
Figure 34 - Power Good Signal
Ch1: Input Supply, Ch2: 2.5V Output, Ch3: 1.8V
Output, Ch4 : Power Good Signal
22/28
APU3146
Figure 36 - 2-phase operation with inductor current sensing.
12V to 1.8V @ 30A output
TYPICAL APPLICATION
12V
PGood
C1
47uF
C2
47uF
L1
Q5
IRFR3711
L4
Q4
IRFR3706
C5
1uF
U1
1.8V @ 30A
R8
1K
C16
8x 330uF, 40m
Ω
6TPB330M
L3
C17
3x 47uF
R9
R7
1.24K
C10
0.1uF
R4
C9
R3
C8
C3
1uF
C4
1uF
C13
1uF
C11
0.1uF
PGnd1
V
CL
V
OUT3
LDrv1
HDrv1
Fb1
V
P2
Fb2
LDrv2
HDrv2
VcH1 VcH2
Vcc
Gnd
Comp2
Comp1
SS1 / SD
PGood
V
REF
APU3146
Q3
IRFR3711
Q2
IRFR3706
C14
3x 47uF
Sync
Rt
Hiccup
SS2 / SD
PGnd2
OCSet2
OCSet1
V
SEN1
V
SEN2
R2
R1
R6
D1
BAT54S
1uH
33K
22nF
C6 120pF
2.2K
8K
C7 82pF
12nF
C12
1uF
12K
12K
D2
BAT54A
1uH, 2m
Ω
DCR
C18
1uF
R5
1K C15
1uF
1uH, 2m
Ω
DCR
1K
R21
1K
V
SEN
R20
1.24K
V
SEN
APU3146
23/28
TYPICAL APPLICATION
12V
PGood
C1
47uF
C2
47uF
L1
Q5
IRFR3711
L4
Q4
IRFR3706
C5
1uF
U1
1.8V @ 30A
R8
1K
C16
8x 330uF, 40m
Ω
6TPB330M
L3
C17
3x 47uF
R5
R9
R7
1.24K
C10
0.1uF
R4
C9
R3
C8
C3
1uF
C4
1uF
C13
1uF
C11
0.1uF
PGnd1
V
CL
V
OUT3
LDrv1
HDrv1
Fb1
V
P2
Fb2
LDrv2
HDrv2
VcH1 VcH2
Vcc
Gnd
Comp2
Comp1
SS1 / SD
PGood
V
REF
APU3146
Q3
IRFR3711
Q2
IRFR3706
C14
3x 47uF
Sync
Rt
Hiccup
SS2 / SD
PGnd2
OCSet2
OCSet1
V
SEN1
V
SEN2
R2
R1
R6
D1
BAT54S
1uH
33K
22nF
C6 120pF
2.2K
8K
C7 82pF
12nF
C12
1uF
12K
1uH 2m
Ω
12K
2m
Ω
D2
BAT54A
1uH
R21
1K
R20
1.24K
V
SEN
V
SEN
Figure 37 - 2-phase operation with resistor current sensing.
12V to 1.8V @ 30A output
24/28
APU3146
Figure 38 - Typical application of APU3146 using 5V and 12V supplies to generate single output voltage.
1.8V @ 30A using inductor sensing.
TYPICAL APPLICATION
12V
PGood
C1
47uF
C2
47uF
L1
IRFR3711
L4
IRFR3706
C5
1uF
U1
1.8V @ 30A
R8
1K
C16
8x 330uF, 40m
Ω
6TPB330M
L3
C17
3x 150uF
R7
1.24K
C10
0.1uF
R4
C9
R3
C8
C3
1uF
C4
1uF
C13
1uF
C11
0.1uF
PGnd1
V
CL
V
OUT3
LDrv1
HDrv1
Fb1
V
P2
Fb2
LDrv2
HDrv2
VcH1 VcH2
Vcc
Gnd
Comp2
Comp1
SS1 / SD
PGood
V
REF
APU3146
Q3
IRFR3711
Q2
IRFR3706
C14
3x 47uF
Sync
Rt
Hiccup
SS2 / SD
PGnd2
OCSet2
OCSet1
V
SEN1
V
SEN2
R2
R1
R6
D1
BAT54S
1uH
33K
22nF
C6 120pF
2.2K
23K
C7 27pF
4.7nF
C12
1uF
12K
R9
1K
12K
R5
1K
1uH,
2m
Ω
DCR
L2
1uH
C18
150uF
5V
C20
1uF
C19
0.1uF
D2
BAT54A
D3
BAT54S
C21
1uF
C22
1uF
Q4
Q5 1uH,
2m
Ω
DCR
R21
1K
R20
1.24K
APU3146
25/28
Figure 39 - Typical application of APU3146.
1.8V @ 30A output with 5V and 12V input and different input current setting.
(5V @ 5A and 12V @ 3A)
TYPICAL APPLICATION
12V
PGood
C1
47uF
C2
47uF
L1
Q5
IRFR3711
L4
Q4
IRFR3706
C5
1uF
U1
1.8V @ 30A
R8
1K
C16
8x 330uF, 40m
Ω
6TPB330M
L3
C17
3x 150uF
R5
R9
R7
1.24K
C10
0.1uF
R4
C9
R3
C8
C3
1uF
C4
1uF
C13
1uF
C11
0.1uF
PGnd1
V
CL
V
OUT3
LDrv1
HDrv1
Fb1
V
P2
Fb2
LDrv2
HDrv2
VcH1 VcH2
Vcc
Gnd
Comp2
Comp1
SS1 / SD
PGood
V
REF
APU3146
Q3
IRFR3711
Q2
IRFR3706
C14
3x 47uF
Sync
Rt
Hiccup
SS2 / SD
PGnd2
OCSet2
OCSet1
V
SEN1
V
SEN2
R2
R1
R6
D1
BAT54S
1uH
33K
22nF
C6 120pF
2.2K
23K
C7 27pF
4.7nF
C12
1uF
15K
1uH 3m
Ω
10K
2m
Ω
1uH
L2
1uH
C18
150uF
5V
C20
1uF
C19
0.1uF
D2
BAT54A
D3
BAT54S
R21
1K
R20
1.24K
26/28
APU3146
TYPICAL APPLICATION
Figure 40 - Single 5V input and two independent outputs.
5V
PGood
C1
47uF
C2
47uF
L1
Q5
1/2 IRF7910
L4
Q4
1/2 IRF7910
C5
1uF
U1
1.8V @ 10A
C16
4x 330uF, 40m
Ω
6TPB330M
L3
R7
1.24K
C10
0.1uF
R4
C9
R3
C8
C3
1uF
C4
1uF
C13
1uF
C11
0.1uF
PGnd1
V
CL
V
OUT3
LDrv1
HDrv1
Fb1
V
P2
Fb2
LDrv2
HDrv2
VcH1 VcH2
Vcc
Gnd
Comp2
Comp1
SS1 / SD
PGood
V
REF
APU3146
Q3
IRF7460
Q2
IRF7457
C14
3x 330uF
6TPB330M
Sync
Rt
Hiccup
SS2 / SD
PGnd2
OCSet2
OCSet1
V
SEN1
V
SEN2
R2
R1
R6
D1
BAT54S
1uH
33K
8.2nF
C6 47pF
6K
15K
C7 27pF
4.7nF
C12
1uF
10K
8.5K
D2
BAT54A
1uH
3.3uH
C15
0.1uF
2.5V @ 5A
R9
2.14K
R5
1K
R8
1K
C18
2x 330uF, 40m
Ω
6TPB330M
C17
3x 330uF
6TPB330M
R22
2.14K
R23
1K
V
SEN2
R20
1.24K
R21
1K
V
SEN1
APU3146
27/28
TYPICAL APPLICATION
Figure 41 - Typical application of APU3146.
5V input, 12V drive and two independent outputs.
5V
PGood
C1
47uF
C2
47uF
L1
Q5
IRF7460
L4
Q4
IRF7457
C5
1uF
U1
1.8V @ 10A
C16
4x 330uF, 40m
Ω
6TPB330M
L3
C17
3x 330uF
6TPB330M
R7
1.24K
C10
0.1uF
R4
C9
R3
C8
C3
1uF
C4
1uF
C13
1uF
PGnd1
V
CL
V
OUT3
LDrv1
HDrv1
Fb1
V
P2
Fb2
LDrv2
HDrv2
VcH1 VcH2
Vcc
Gnd
Comp2
Comp1
SS1 / SD
PGood
V
REF
APU3146
Q3
IRF7460
Q2
IRF7457
C14
3x 330uF
6TPB330M
Sync
Rt
Hiccup
SS2 / SD
PGnd2
OCSet2
OCSet1
V
SEN1
V
SEN2
R2
R1
R6
1uH
33K
8.2nF
C6 47pF
6K
15K
C7 27pF
4.7nF
10K
5.1K
D2
BAT54A
1uH
3.3uH
C15
0.1uF
2.5V @ 5A
R9
2.14K
R5
1K
R8
1K
C18
2x 330uF, 40m
Ω
6TPB330M
12V
R20
1.24K
R21
1K
V
SEN1
R22
2.14K
R23
1K
V
SEN2
28/28
APU3146
TYPICAL APPLICATION
Figure 42 - Typical application of APU3146.
5V to 2.5V and 3.3V to 1.8V inputs and two independent outputs.
5V
PGood
C1
47uF
C2
47uF
L1
Q5
1/2 IRF7910
L4
Q4
1/2 IRF7910
C5
1uF
U1
2.5V @ 5A
C16
2x 330uF, 40m
Ω
6TPB330M
L3
C17
2x 330uF
6TPB330M
R7
2.14K
C10
0.1uF
R4
C9
R3
C8
C3
1uF
C4
1uF
C13
1uF
C11
0.1uF
PGnd1
V
CL
V
OUT3
LDrv1
HDrv1
Fb1
V
P2
Fb2
LDrv2
HDrv2
VcH1 VcH2
Vcc
Gnd
Comp2
Comp1
SS1 / SD
PGood
V
REF
APU3146
Q3
1/2 IRF7910
Q2
1/2 IRF7910
C14
2x 330uF
6TPB330M
Sync
Rt
Hiccup
SS2 / SD
PGnd2
OCSet2
OCSet1
V
SEN1
V
SEN2
R2
R1
R6
D1
BAT54S
1uH
33K
4.7nF
C6 27pF
15K
8.2K
C7 27pF
5.6nF
C12
1uF
8.5K
8.5K
D2
BAT54A
3.3uH
2.2uH
C15
0.1uF
1.8V @ 5A
R9
1.24K
R5
1K
R8
1K
C18
2x 330uF, 40m
Ω
6TPB330M
3.3V
R22
1.24K
R23
1K
V
SEN2
R20
2.14K
R21
1K
V
SEN1
