EPROM - Application Notes - Atmel Corporation

The Benefits of Atmel’s RAPID™

Programming Algorithm

Introduction

In designing and manufacturing certain

modern-day p r oducts , t he m ethods u se d

to build these products are often as

import ant to the desig n engineer as th e

components themselves. This is true

about programmable memory devices as

well, especially EPROMs. Most EPROM

vendor s use their own un ique progr am-

ming algorithm, which is based on the

process used to make EPROMs, the

design engineer needs to know about

the algorithm during the system design

cycle to insure that the EPROMs can

ultimately be programmed.

This application note details the Atmel

RAPID programming algorithm and

briefly explains why this algorithm is

superi or to others. In addi tion, it wil l give

an introduction to EPROM technology

and the mechanics of programming.

These should provide a basic under-

standing in the growing field of

EPROMs.

Pr ogramming EPROMs the

RAPID™ Way

Several years ago, when Atmel reduced

the geometry of its EPROM products

from 1.5µ to 1.2µ linewidth, the Com-

pany ado pted an entir ely new progr am-

ming algorithm for these devices. A

reason for this algorithm change was to

improve programming yields and

lengthen long-term data retention. This

was accomplished by using a shorter

programming -pulse length d uring pro-

gramming. The new RAPID algorithm

reduces the 1 ms programming pulse

width of the original FAST algorith m to

only 100 µs, and it completely eliminates

extra overprogramming pulses. The

advantages of the RAPID programming

algorithm are production proven even

with today’s advanced 0.5 micron

EPROM technology.

UV Erasable

EPROM

Application

Note

CMOS EPROM

Rev. 0578A–10/98

The Benefits of

Atmel’s

RAPID™

Programming

Algorithm

Figure 1. Cross Section of a Typical EPROM Cell

EPROM

But higher yields and i ncreased reliability aren’ t the only

benefits the RAPID algorithm provides, it also takes less

time to pr ogram thes e device s. The RAPID algori thm can

redu ce the p rogra mming overhe ad cost s by a fa ctor of 40!

Here’s how it works:

If you program an AT27C512R, 512K EPROM in a single-

devic e programm er, using the FA ST or any other type of 1

ms algorithm (1 ms initial pulse, plus 3 ms overprogram-

ming pulse) the time spent programming will be:

524288 bits ÷ 8 bits/byte = 65536 bytes

65536 bytes × 0.004 seconds/byte = 262 seconds

That’s 262 seconds, or 4 minutes and 22 seconds. This

works out to about a 75 cents programming cost, assuming

an operat or’s rate of $10 per hou r. Here’s wher e the cos t

savings start: since we cannot reduce the number of bits to

program, we r educe the total prog ramming time by shor t-

ening the programming pulse width. Using 100 µs per byte,

this is what happens:

65536 bytes × 0.0001 seconds/byte = 6.5 seconds

This amo unt of programming-ti me savings i s what can be

expected when using the RAPID algorithm. The big

improvemen t is from reducing the total byte-pr ogramming

time from 4 ms to 100 µs. With this example, total program-

ming c ost is a bout thr ee cen ts. The RAPID al gorithm can

actually save up to 72 cents per device. Imagine how much

can be saved with 10,000 EPROMs!

There’s more to the RAPID algorithm tha n shorter pro-

gramming tim es and cost savings. It has a spec ial way of

checkin g that each cell is correctly pr ogrammed, a nd that

cells are programmed with the required amount of charge.

In fact, the RAPID algorithm even guarantees that the

EPROM is correctly programmed. Programming algorithms

of the FAST type, or their relatives, the QUICK-PULSE

types, check each memory location f or the pr ogrammed

data immedia tely after programming that locatio n. This

check, which takes pl ace before the final verify at the end

of the programming cycle, is basically an “insurance”

check, because it is performed at an elevated voltage,

which is a worst-case condition. There is a flaw, however,

in this type of programming algorithm: memory locations

that have been previously programmed can be partially

erased by programm ing subs equent l ocations (du e to the

elevated voltage on the same row or column in the memory

array) and marginally programmed cells will go virtually

undetected. The question is, doesn’t the programmer

check each device during verify after programming?

Wouldn’t those failures be caught then? Not necessarily,

because when pa rt s ar e chec ke d dur i ng the progr am ver ify

mode, the voltage is not elevated as high as it was during

programmi ng.

Figure 2. Process of Hot Electron Injection

Select Gate

Oxide Insulator

Floating Gate

Oxide Insulator

N-Type N-Type

Source Drain

= 0.0V V

≤

10V

≥

+12.0V

P-Type Substrate

When enough electrons

accumulate on to the

floating gate, it becomes

programmed

Electrons have enough

energy caused by the

high field in the

channel near the

drain to jump the

oxide barrier

N-type channel is

formed when electrons

are attracted to

select gate’s positive

potential

e-e-e-e-e-

e-e-

Figure 3. Unprogrammed Cell

EPROM

The RAPID programming algorithm was designed to fix this

oversight. First, i t goes through the entire devic e and pro-

grams every cell without checking. Then it goes back to the

beginning of the memory array and verifies the data in each

cell at the elevated voltage. Once the device passes,

another final verification is done at 5V. The RAPID algo-

rithm will do a better job at preventing any marginally pro-

grammed parts from passing the programmer than other

algorithms.

An important fringe benefit of the RAPID algorithm,

because of the way it g uarantees successful programma-

bility, is long-term data retention. Basically, long-term data

retention is how long the EPROM stays programmed,

which is typically greater than ten years. Although long-

term data retention is not the same as device programma-

bility, they are related in this way: programmability tells how

well the electrons have accumulated on the EPROM’s

floating gate, l ong-term data retention tells how long the

electrons will stay there. The programming algorithm has

an overwhelming influence on programmability, making it

an overwhelming influence on long-term data retention as

well. Therefore, a poor programming algor ithm, one that

doesn’t guarantee programmability, can be responsible for

poor long-term data retention. The RAPID algorithm can

add years of data retention to your parts, because of the

way it checks for programmability. Marginally programmed

parts just don’t stand a chance of getting past the program-

mer.

EPROM Programming, How it Works

Contemporary EPROM programming algorithms can be

divided into two main sections, programming and verifying

(or reading). Programming begins by selecting the desired

voltage levels and byte address. It co ntinues with a pr o-

grammi ng pu lse applied to th at by te , fol lo wed b y a ve rify at

the elev ated VCC used for p rogramming. Verifying checks

the data in two passes with the original data, with VCC set to

5.5V on the first pass, and 4.5V on the second.

Basically, EPROMs are programmed through the accumu-

lation of electrons on the floating gate of an N-Channel

EPROM cell (see F igure 1) by the process of hot-electr on

injection. Hot-electron injection is where electrons, flowing

as a current between the drain and source of a saturated

EPROM cell, gain enough energy from the high electric

field to j ump the o xi de b arr ier be twee n the ch ann el and the

floating gate (see Figure 2). Before programming, the MOS

threshold voltage, VTH (otherwise known as the gate

threshold voltage) of the erased floating-gate EPROM cell

is about 1.0V to 2.0V (see Figure 3). After programming, its

threshold voltage is about 6.5V to 9.0V, due to the accumu-

lated electrons on the floating gate. In read mode, the

address decoding circuitry in the chip selects the desired

cell by pull in g the g ate v oltage of the c ell to VCC. Since VCC

is typ ically 4 .5V to 5.5 V, an eras ed cell with a V TH = 1.5V

would be turned on (Figure 3), while a programmed cell

with a VTH = 7.5V would remain off (see Figure 4). This

floating-ga te pro cess i s how a single M OSFET- like trans is-

tor can provide for the two logic levels used in digital cir-

cuitry.

If VCC is gradually raised in voltage to a point near the

threshold voltage of a programmed EPROM cell, the cell

would just begin to conduct, and would no longer appear to

be programmed. This point, where the programmed

EPROM cell begins to look unprogrammed, is defined as

the programming margin (see Figure 5). The value of the

programming margin can, in some cases, be simply equal

to the value of the VCC voltage present during program-

ming. T his is w hy the RA PID algori thm hold s the v alue of

VCC constant at 6.5V dur ing programming; to insure that

each EPROM c ell has a programming margin of at leas t

that voltage. This margin is verified by reading each byte

twice, once during the initial programming operation and

again during the final read (or verify) operation, where the

data from the EPROM is compared to the desired data.

The differe nce between the value of V CC during program-

ming (the gu aranteed programmi ng margin) and the 5.5V

VCC maximum supply rating (from the data sheet) serves as

a reliability guardband for long-term data retention and,

more importantly, for system noise immunity. Poor pro-

gramming margin can redu ce system noise im munity an d

lead to EPROM ch ip instability due to power-supply noise

on the VCC pin. T his instab ility can ca use oscillati ons and

read-mode data glitching that can be a problem in even in

Figure 4. Programmed Cell. Note how VTH raises after

electrons are accumulated on the EPROM floating gate

from programming.

EPROM

the slowest and most nois eless of systems. Since powe r-

supply noise is a somewhat random occurrence, data

error s can ha ppen int ermitt ently, wh ich ca n underm ine th e

reliability and integrity of the host system. These problems

can be avoided by using the programming algorithm rec-

ommended by the EPROM chip vendor. The higher the

guaranteed programming margin, the less likely any prob-

lems will occur.

Another important benefit of high-programming margin is

that it ex tends the l ong-ter m data retentio n o f the d evice. If

the 6.0V programming margin (FAST algorithm) on the

EPROM gr adually dimini shes to 5.5V ov er a 10-year tim e

span, the randomly occurring noise spikes on the VCC line

can caus e the EPROM to y ield faulty data. O n the other

hand, given the same d ischarge ra te (as a func tion of the

silicon processing), an EPROM with a programming margin

of 6.5V (RAPID algorithm) would take over 20 years to

reach the 5.5V thresh old that would lead to faulty data

yield. All th ings being equal, better programming margin

leads to longer data retention.

Guaranteeing Programmability

Most people might ask, “What’s in a programming algo-

rithm? Aren ’t th ey al l the sam e?” Th at que st ion woul d hav e

been answered with a resounding “YES” 10 years ago

when, quite frankly, they were the same. But it’s not true

today. Ther e are ove r 2 0 ma nufact urer s mak ing EPR OMs,

and few of them use the same programming algorithm.

Today, the programming algorithm is as important to

EPROM testing as the actual device testing procedure. In

fact, the dev ice test proced ures are often ( if not always)

based upon the progr amming a lgorit hm. Th e prog ramm ing

algorithm has a direct effect on EPROM test yield, and

manufa ctur er s sel ect their p ro gr amm in g al gorithms so they

can obtain the highest yield possible. Additionally, the pro-

gramming algorithm is d irectly responsible for the number

of device s that pass the cus tomers progra mmer, which is

called programming yield. This is of vital importance to an

EPRO M manufa cturer l ike Atmel , since the worst pla ce for

Figure 5. Programming Margin. To find programming mar-

gin, increase gate voltage (VCC) until the first “0” turns into a

“1”.

Figure 6. QUICK-PULSE Type

EPROM

an EPROM to fail pr ogramming is in the customer’s pro-

grammer. W ith this in m ind, let’s look at how the RAPID

algorithm can guarantee better programmability than a

common type of quick-pulsing algorithm.

We’ll begin by comparing a common type of quick-pulsing

algorit hm with the Atm el RAP ID algori thm. Ex amine Figure

6, which is the flowchart for the QUICK-PULSE type of

algorithm. If you look very closely you will see that the algo-

rit hm is brok en up in t o two majo r sec tio ns. T he main p art i s

the program/verify section, the other part is the final verify

section. Basically, the first section starts at byte address

0000H, pro grams the eight EPR OM cells at that addres s,

and verifies that those cells contain the correct data with a

verify at 6.25 V on V CC. If the byt e passes , it go es on to the

next byte. If it fails, it repeats everything up to 25 times

before it fails the device. The second se ction lowers th e

VCC voltage to 5.0V and checks if all address locations read

with the correct data . Although the flowchart specifies a

one-pass final ver ify at 5.0V, m any progr ammers ver ify in

two passes, one with VCC at 4.75V and the other with VCC

at 5.25V.

Now ex am in e Fi g ur e 7, t he Atmel RA PI D al go r i t hm . It lo oks

similar to the qu ick-pulsing t ype of algorithm, but with a

slight difference. If you look closely you’ll see that it con-

sists of three sections instead of just two. The first section

is the programming section, where the programmer pro-

grams ev ery locati on in the EPRO M without ve rifying . Next

there is the ve rify/repair sectio n, where the programmer

starts at the beginning of the EPROM and verifies every

location for the correct data at 6.5V. Any cells that don’t

pass are reprogrammed up to ten times before the device

is failed. The last section lowers VCC to 5.0V and does a

final ve rify of the data (he re again , most pr ogramm ers ver-

ify in two pas ses, one wi th V CC at 4.75V and the other wit h

VCC at 5.25V). This type of programming algorithm is called

a two-pas s al gorithm, bec au se it goe s t h roug h th e m emo ry

array twice during programming.

Well, this all sounds fine, but what difference can the pr o-

gramming algorithm possibly make? We can find the

answer to that question in a particularly sneaky deprogram-

ming mode that EPROMs can exhibit. We all know that

EPRO M s ar e erased by exp o sin g th em to sh or t- w av e u lt r a -

violet light, right? Nothing more than applying Einstein’s

discovery of the photoelectric effect. But there is another

erasure mode that can occur, one that people in the

E2PROM business know abou t. If you were to examine

some E PROM cells in an electr on micro scope, you mi ght

find a few that have small, tooth-like projections (called

asperities) on the top of the floating gate polysilicon. These

projections won’t affect the normal operation of the

EPROM, but they could give you problems during program-

ming. When you program a row of cells on an EPROM,

cells that have been previously programmed still feel the

full brunt of the high VPP voltage on their gates when sub-

sequent cells on the same row are programmed, because

all of the cells on a row have their gates connected

together. The combination of high voltage on the gate and

ground on the drain and source causes an intense electric

field in each previously programmed cell. If any one of the

cells on that row have these tooth-like projections on their

floating gate polysilic on, the resulting electric field i n the

oxide above the projections will be much more intense than

normal. This i ntensified electric field c an give some of the

electrons on the floating gate enough energy to jump the

oxide barrier, thereby partially erasing the EPROM cell.

This unwanted effect, called programming erase, can be

responsible for poor programming margins unless the pro-

gramming algorithm takes this problem into account.

Figure 7. RAPID Programming Algorithm

EPROM

Before we continue, it’s important to realize that this type of

cell doesn’t have a reliability problem, it has a program-

mability problem. This cell will have the same long-term

data retention as any other cell in th e device, even if it

loses part of its prog ramming charge. Although it is an

EPR OM, it has th e same charg e retentio n charact eristics

as many manufacturers’ E2PROM cells that use this type of

erasure mo de, and the y all exh ibit exce llent l ong-t erm data

retentio n. The chal lenge is to find thes e low- margin c ells in

the device with our programming algorithm, and to repair

them so that the device functions normally.

Let’s see what kind of impact a cell like this can have on

programming margin by programming a row of EPROM

cells from our AT27C010 one-megabit EPROM with both

algor ithms. The arr ay geo metry on the one -mega bit is 12 8

columns by 1024 rows, by 8 outputs. This means that a sin-

gle r ow from a si ngle out put has 12 8 EPROM c ells. Let ’s

say that the second cell on this row, bit 1 (we’ll call them

bits and s tart with bit 0 ), has an asp erity, just l ike the on e

mentioned above. When we go to program bits 2, 3, 4, etc.,

the voltage present on the gate of bit 1 causes the

E2PROM-like erasure mode. Given enough subsequent

bits to program, bit 1 may lose enough charge to appear

unprogrammed. Let’s take a look at how the QUICK-

PULSE type of algorithm will fail the device, or even worse,

pass it with poo r progra mming ma rgin. The n we’ll se e how

the RAPID algorithm will program it such that it works per-

fectly!

If we examine Figure 8, we see the row of EPROM cells

taken from our AT 27C0 10 one -me gabit dev ice. Rec all t hat

bit 1 is the cell that’s having the programmability problem,

while the rest of the bits function normally. For the sake of

example, let’s say that for each subsequent bit after bit 1

that’s program med, bit 1 will lose eight mi llivolts (mV) of

programming margin. Let’s also assume that the nominal

programming margin for each cell is at least the value of

VCC present during programming, which is 6.25V for

QUICK-PULSE type algorithms and 6.5V for the RAPID

algorithm. Starting with the QUICK-PULSE type of algo-

rithm at bit 0, we program it, verify it, and find that it passes

(remember our flowchart from Figure 6?) with th e correct

margin (see Figure 9). We move to cell 1, program it, verify

it, and it passes (see Figure 10). Remember, bit 1 only

loses voltage margin when subsequent cells are pro-

grammed. Now we move on to bit 2, program it, verify it,

and in the process reduce bit 1’s programming margin

down to 6.242 V (see Fi gure 11). Nex t we go to bi t 3, pro-

gram i t, verify it, a nd in tur n reduce bit 1’s programm ing

margi n down to 6.23 4V (see Figu re 12). This pr ocess co n-

tinues until we get to bit 127. By this time bit 1 has experi-

enced 126 subs equent cell programmi ng cycles, and its

programmi ng ma r gin will be r edu ced to 5.24 2V (see Figure

13). Since th e QUICK-PULSE type of algorithm does its

high-voltage verify immediately after programming, the

algorithm has no way o f k now ing wh at h as h appe ned to bi t

1, once i t fi nishes progr am min g i t. O nly w hen the algor ith m

does its final verify with VCC set at 5.25V could it detect that

bit 1 is not fully programmed.

In this example we were able to detect bit 1 as being bad,

and we would fail the device. But what if bit 1’s erasure rate

was slightly less than 8 mV per subsequent cell, say 7.7

mV? Bit 1’s margin might be somewhere around 5.3V,

which wou ld probably pass the 5.2 5V verify check on our

programmer. But remember the problem that we discussed

earlier, about the power supply nois e glitches messing up

the operation of devices with low programming margin? A

device with only 5.3V of margin is a prime candidate for this

type of problem. A small noise glitch occurring during data

access on t he VCC line of this EP ROM c ould ea sily ch ang e

the output from a “0” to a “1”. And, to make matters wor se,

this problem would probably occur randomly; the eventual

diagnosis being that the device was intermittent. The unfor-

tunate truth is that there is nothing wrong with the EPROM,

it’s the programming algorithm that’s at fault.

So let’s go back to our row of 128 EPROM cells, erase

them, and reprogram them with the RAPID algorithm.

Remember that with th e RAPID alg orithm the in itial pro-

Figure 8. Row of E PROM cells from AT2 7C010. No te tha t

the programming margin of each cell is 0, which allows

each bit to read a “1”.

Figure 9. Bit 0 has been programmed, (QUICK-PULSE

algorithm).

Figure 10. Bit 0 and bit 1 have been programmed.

Programming Margin (Volts):

0000000 00

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6• • • Bit

126 Bit

127

Programming Margin (Volts):

6.25000000 00

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6• • • Bit

126 Bit

127

Programming Margin (Volts):

6.256.2500000 00

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6• • • Bit

126 Bit

127

EPROM

gram an d ve rify r ou tin es a re l oc ated i n di fferen t s ec ti ons of

the algor ithm, t hey are not con tained within the sa me loop .

Starting at bit 0, we program it (to 6.5V this time, see Figure

14). Then move to b it 1, and program it (see F igure 15).

Next to bit 2, program it, and in turn reduce bit 1’s program-

ming margin to 6.492V (see Figure 16). Then on to bit 3,

program it, and further reduce bit 1’s programming margin

to 6.484V. We continue programming until we get to bit

127, and you’l l fin d that the pr ogrammi ng ma rgin for all the

cells looks similar to figure 8 (see Figure 17). But wait,

we’re not finished yet. We move back to the beginning of

the EPRO M arr ay , whic h is b it 0, and v erif y th at it has 6.5V

of prog rammi ng m ar gin . S i nce w e ar e ver ifyi ng a t 6.5V, w e

pass it. We now move to bit 1 and notice that its program-

ming margin is 5.492V. This fails our 6.5V verify, so we pro-

gram it one more time and raise its margin back to 6.5V,

then pass it (see Figure 18). Then we move to bit 2, and

pass it, since its programming margin is also 6.5V. Notice

that we didn’t deprogram bit 1 in the process of verifying bit

2. We o nly depr ogram bit 1 when we pro gram s ubsequ ent

cells ; readin g or verifyin g (which i s readin g) doesn’t ge ner-

ate the intense electric fields needed to deprogram

EPROM cells. After verifying (and repairing) this row of

cells, w e return V CC to 5.25V, do a final data verify, then

pass the row ( see Fig ure 18 ). Now comp ar e Fi gure 1 8 wi th

Figure 13. That’s how the RAPID algorithm can guarantee

progra mmabi lity!

Well, you may ask, what if we had five problem cells on the

same row? Wouldn’t the additional programming pulses

during the verify function deprogram previously pro-

grammed and verified cells? They probably would, but the

maximum amount of deprogramming on the first bit (using

this mode l) would be only 32 mV (4 x 8 mV). This gives us

a programming margin of 6.468V, which is still an excellent

programming margin.

When you compare the QUICK-PULSE type algorithms to

the RAPID algorithm, ther e really is no comparis on. The

RAPID algorith m simply guarantees p rogrammability, a nd

we demonstrated this with the deprogramming bit example,

Figure 11. Bits 0, 1, and 2 are programmed. Notice that bit

1 has been slightly erased.

Figure 12. Bit 3 has just been programmed. Notice that bit

1 has been further erased.

Figure 13. The entire row has been programmed. Notice

how much bit 1 has been erased.

Programming Margin (Volts):

6.25 6.242 6.25 0 0 0 0 0 0

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6• • • Bit

126 Bit

127

Programming Margin (Volts):

6.25 6.234 6.25 6.25 0 0 0 0 0

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6• • • Bit

126 Bit

127

Programming Margin (Volts):

6.25 5.242 6.25 6.25 6.25 6.25 6.25 6.25 6.25

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6• • • Bit

126 Bit

127

Figure 14. Bit 0 has just been reprogramm ed (RAPID

algorithm).

Figure 15. Bit 1 has just been programmed.

Figure 16. Bit 2 has just been programmed. Notice how bit

1 has been slightly erased again.

Programming Margin (Volts):

6.50000000 00

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6• • • Bit

126 Bit

127

Programming Margin (Volts):

6.506.5000000 00

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6• • • Bit

126 Bit

127

Programming Margin (Volts):

6.506.4926.500000 00

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6• • • Bit

126 Bit

127

EPROM

which is one of the trickiest programming problems you can

have. But the RAPID alg orithm caught the problem, an d

repaired the bit so that the EPROM will function normally.

Figure 17. The entire row has just been programmed.

Notice how much bit 1 has been erased.

Figure 18. The entire row has just be verified at 6.50 volts.

Notice how bit 1 has been repaired, its margin being

ret urned to 6.50 volts using the RAPID algorithm.

Programming Margin (Volts):

6.50 5.492 6.50 6.50 6.50 6.50 6.50 6.50 6.50

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6• • • Bit

126 Bit

127

Programming Margin (Volts):

6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6• • • Bit

126 Bit

127

EPROM

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TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Atmel Rousset

Zone Indu strie lle

13106 Rousset Cedex, France

TEL (33) 4 42 53 60 00

FAX (33) 4 42 53 60 01

Fax-on-Demand

North America:

1-(800) 292-8635

International:

1-(408) 441-0732

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Printed on recycled paper.

0578A–10/98/xM