ds029_1_2.fm Page 1 Monday, February 14, 2000 9:08 AM 0 QPROTM XQ4000XL Series QML High-Reliability FPGAs R DS029 (v1.2) February 9, 2000 0 XQ4000X Series Features * * * * Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing) Ceramic and plastic packages Also available under the following standard microcircuit drawings (SMD) - XQ4013XL 5962-98513 - XQ4036XL 5962-98510 - XQ4062XL 5962-98511 - XQ4085XL 5962-99575 For more information contact the Defense Supply Center Columbus (DSCC) http://www.dscc.dla.mis/v/va/smd/smdsrch.html * * Available in -3 speed System featured Field-Programmable Gate Arrays - SelectRAMTM memory: on-chip ultra-fast RAM with - synchronous write option - dual-port RAM option - Abundant flip-flops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - Eight global low-skew clock or signal distribution networks * * * * System Performance beyond 50 MHz Flexible Array Architecture Low Power Segmented Routing Architecture Systems-Oriented Features - IEEE 1149.1-compatible boundary scan logic support * * * - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12 mA Sink Current Per XQ4000XL Output Configured by Loading Binary File - Unlimited reprogrammability Readback Capability - Program verification - Internal node observability Development System runs on most common computer platforms - - Interfaces to popular design environments - - Fully automatic mapping, placement and routing - - Interactive design editor for design optimization DS029 (v1.2) February 9, 2000 0* * * * * * * * * Highest Capacity -- Over 130,000 Usable Gates Additional Routing Over XQ4000E - almost twice the routing capacity for high-density designs Buffered Interconnect for Maximum Speed New Latch Capability in Configurable Logic Blocks Improved VersaRingTM I/O Interconnect for Better Fixed Pinout Flexibility - Virtually unlimited number of clock signals Optional Multiplexer or 2-input Function Generator on Device Outputs 5V tolerant I/Os 0.35 m SRAM process Introduction XQ4000X Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of thirteen years of FPGA design experience and feedback from thousands of customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated soft-ware to achieve fully automated implementation of complex, high-density, high-performance designs. Refer to the complete Commercial XC4000X Series Field Programmable Gate Arrays Data Sheet for more information on device architecture and timing, and the latest Xilinx databook for package pinouts other than the CB228 (included in this data sheet). (Pinouts for XQ4000XL device are identical to XC4000XL.) 1 ds029_1_2.fm Page 2 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs Table 1: XQ4000X Series High Reliability Field Progammable Gate Arrays Max Logic Max. RAM Typical Gate Gates Bits Range (No RAM) (No Logic) (Logic and RAM)* Device Logic Cells CLB Matrix Total CLBs Number of Flip-Flops Max. User I/O XQ4013XL 2432 13,000 18,432 10,000-30,000 24x24 576 1,536 192 PG223, CB228, PQ240, BG256 XQ4036XL 3078 36,000 41,472 22,000-65,000 36x36 1,296 3,168 288 PG411, CB228, HQ240, BG352 XQ4062XL 5472 62,000 73,728 40,000-130,000 48x48 2,304 5,376 384 PG475, CB228, HQ240, BG432 XQ4085XL 7448 85,000 100,352 55,000-180,000 56x56 3,136 7,168 448 PG475, CB228, HQ240, BG432 Packages * Maximum values of typical gate range includes 20% to 30% of CLBs used as RAM. XQ4000XL Switching Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered final. All specifications subject to change without notice. Additional Specifications Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. For design considerations requiring more detailed timing information, see the appropriate family a.c. supplements available on the Xilinx WEBLINX at http://www.xilinx.com. Absolute Maximum Ratings Symbol Description VCC Supply voltage relative to GND Units -0.5 to 4.0 V VIN Input voltage relative to GND (Note 1) -0.5 to 5.5 V VTS Voltage applied to 3-state output (Note 1) -0.5 to 5.5 V VCCt Longest Supply Voltage Rise Time from 1 V to 3V TSTG Storage temperature (ambient) TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) TJ Junction temperature 50 ms -65 to +150 C +260 C Ceramic Package +150 C Plastic Package +125 C Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2 DS029 (v1.2) February 9, 2000 ds029_1_2.fm Page 3 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs Recommended Operating Conditions Symbol VCC Min Max Units Supply voltage relative to GND, TJ = -55C to +125C Description Plastic 3.0 3.6 V Supply voltage relative to GND, TC = -55C to +125C Ceramic 3.0 3.6 V V VIH High-level input voltage 50% of VCC 5.5 VIL Low-level input voltage 0 30% of VCC V TIN Input signal transition time 250 ns Note 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per xC. Note 2: Input and output measurement threshold is ~50% of VCC. XQ4000XL DC Characteristics Over Recommended Operating Conditions Symbol VOH Description Min High-level output voltage @ IOH = -4.0 mA, VCC min (LVTTL) High-level output voltage @ IOH = -500 A, (LVCMOS) VOL Low-level output voltage @ IOL = 12.0 mA, VCC min (LVTTL) (Note 1) VDR Data Retention Supply Voltage (below which configuration data may be lost) ICCO Quiescent FPGA supply current (Note 2) Input or output leakage current CIN Input capacitance (sample tested) V 0.4 10% VCC 2.5 -10 Units V 90% VCC Low-level output voltage @ IOL = 1500 A, (LVCMOS) IL Max 2.4 V V V 5 mA +10 A BGA, PQ, HQ, packages 10 pF PGA packages 16 pF IRPU Pad pull-up (when selected) @ Vin = 0 V (sample tested) 0.02 0.25 mA IRPD Pad pull-down (when selected) @ Vin = 3.6 V (sample tested) 0.02 0.15 mA IRLL Horizontal Longline pull-up (when selected) @ logic Low 0.3 2.0 mA Note 1: With up to 64 pins simultaneously sinking 12 mA. Note 2: With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating. DS029 (v1.2) February 9, 2000 3 ds029_1_2.fm Page 4 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs XQ4000XL Global Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade -3 -1 Symbol Device Max Max From pad through Global Low Skew buffer, to any clock K TGLS XQ4013XL XQ4036XL XQ4062XL XQ4085XL 3.6 4.8 6.3 - 5.7 ns ns ns ns From pad through Global Early buffer, to any IOB clock. Values are for BUFGE #s 1, 2, 5 and 6. Add 1 - 2 ns for BUFGE #s 3, 4, 7 and 8 and for all CLB clock Ks driven from any of the 8 BUFGEs, or consult TRCE. TGE XQ4013XL XQ4036XL XQ4062XL XQ4085XL 2.4 3.1 4.9 - 4.7 ns ns ns ns Description 4 Units DS029 (v1.2) February 9, 2000 ds029_1_2.fm Page 5 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs XQ4000XL CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000XL devices and expressed in nanoseconds unless otherwise noted. Speed Grade Description Symbol -3 Min -1 Max Min Max Units Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H' to X/Y outputs F/G inputs via transparent latch to Q outputs C inputs via SR/H0 via H to X/Y outputs C inputs via H1 via H to X/Y outputs C inputs via DIN/H2 via H to X/Y outputs C inputs via EC, DIN/H2 to YQ, XQ output (bypass) TILO TIHO TITO THH0O THH1O THH2O TCBYP 1.6 2.7 2.9 2.5 2.4 2.5 1.5 1.3 2.2 2.2 2.8 1.9 2.0 1.1 ns ns ns ns ns ns ns Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Carry Net Delay, COUT to CIN TOPCY TASCY TINCY TSUM TBYP TNET 2.7 3.3 2.0 2.8 0.26 0.32 2.0 2.5 1.5 2.4 0.20 0.25 ns ns ns ns ns ns Sequential Delays Clock K to Flip-Flop outputs Q Clock K to Latch outputs Q TCKO TCKLO 2.1 2.1 1.6 1.6 ns ns CLB Fast Carry Logic Setup Time before Clock K F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK 1.1 2.2 2.0 1.9 2.0 0.9 1.0 0.6 2.3 3.4 0.9 1.7 1.6 1.4 1.6 0.7 0.8 0.5 1.9 2.7 ns ns ns ns ns ns ns ns ns ns TCKI TCKIH TCKHH0 TCKHH1 TCKHH2 TCKDI TCKEC TCKR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ns ns ns ns ns ns ns ns TCH TCL 3.0 3.0 2.5 2.5 ns ns TRPW TRIO 3.0 Hold Time after Clock K F/G inputs F/G inputs via H C inputs via SR/H0 through H C inputs via H1 through H C inputs via DIN/H2 through H C inputs via DIN/H2 C inputs via EC C inputs via SR, going Low (inactive) Clock Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q 3.7 2.5 2.8 ns ns 19.8 15.0 ns Global Set/Reset Minimum GSR Pulse Width Delay from GSR input to any Q TMRW Toggle Frequency (MHz) (for export control) FTOG DS029 (v1.2) February 9, 2000 TMRQ See page 14 for TRRI values per device. 166 200 MHz 5 ds029_1_2.fm Page 6 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs XQ4000XL RAM Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000XL devices and are expressed in nanoseconds unless otherwise noted. Single Port RAM Speed Grade -3 -1 Units Size Symbol Min Max Min Max Write Operation Address write cycle time (clock K period) 16x2 32x1 TWCS TWCTS 9.0 9.0 7.7 7.7 ns ns Clock K pulse width (active edge) 16x2 32x1 TWPS TWPTS 4.5 4.5 3.9 3.9 ns ns Address setup time before clock K 16x2 32x1 TASS TASTS 2.2 2.2 1.7 1.7 ns ns Address hold time after clock K 16x2 32x1 TAHS TAHTS 0 0 0 0 ns ns DIN setup time before clock K 16x2 32x1 TDSS TDSTS 2.0 2.5 1.7 2.1 ns ns DIN hold time after clock K 16x2 32x1 TDHS TDHTS 0 0 0 0 ns ns WE setup time before clock K 16x2 32x1 TWSS TWSTS 2.0 1.8 1.6 1.5 ns ns WE hold time after clock K 16x2 32x1 TWHS TWHTS 0 0 0 0 ns ns Data valid after clock K 16x2 32x1 TWOS TWOTS Address read cycle time 16x2 32x1 TRC TRCT Data Valid after address change (no Write Enable) 16x2 32x1 TILO TIHO Address setup time before clock K 16x2 32x1 TICK TIHCK 6.8 8.1 5.8 6.9 ns ns Read Operation 6 4.5 6.5 2.6 3.8 1.6 2.7 1.3 2.3 ns ns 1.3 2.2 0.9 1.7 ns ns ns ns DS029 (v1.2) February 9, 2000 ds029_1_2.fm Page 7 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs Dual Port RAM Speed Grade Size Symbol -3 Min -1 Max Min Max Unit s 6.7 ns ns ns ns ns ns ns ns ns Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS 9.0 4.5 2.5 0 2.5 0 1.8 0 7.7 3.9 1.7 0 2.0 0 1.6 0 7.8 Note 1: Timing for16 x1 RAM option is identical to16 x 2 RAM. DS029 (v1.2) February 9, 2000 7 ds029_1_2.fm Page 8 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs XQ4000XL CLB RAM Synchronous (Edge-Triggered) Write Timing TWPS WCLK (K) TWSS TWHS TDSS TDHS TASS TAHS WE DATA IN ADDRESS TILO TILO TWOS DATA OUT OLD NEW DS029_01_011300 XQ4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing TWPDS WCLK (K) TWHS TWSS WE TDSDS TDHDS TASDS TAHDS DATA IN ADDRESS TILO DATA OUT TILO TWODS OLD NEW DS029_02_011300 8 DS029 (v1.2) February 9, 2000 ds029_1_2.fm Page 9 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs XQ4000XL Pin-to-Pin Output Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. XQ4000XL Output Flip-Flop, Clock to Out Speed Grade -3 -1 Device Max Max Global Low Skew Clock to Output using OFF TICKOF XQ4013XL XQ4036XL XQ4062XL XQ4085XL 8.6 9.8 11.3 - 9.5 ns ns ns ns Global Early Clock to Output using OFF Values are for BUFGE #s 3, 4, 7, and 8. Add 1.4 ns for BUFGE #s 1, 2, 5, and 6. TICKEOF XQ4013XL XQ4036XL XQ4062XL XQ4085XL 7.4 8.1 9.9 - 8.5 ns ns ns ns TSLOW All Devices 3.0 3.0 ns Description For output SLOW option add Symbol Units OFF = Output Flip Flop Note 1: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. Note 2: Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see graph below. XQ4000XL Output Mux, Clock to Out Speed Grade -3 -1 Device Max Max Global Low Skew Clock to Output using OFF TICKOF XQ4013XL XQ4036XL XQ4062XL XQ4085XL 8.8 10.0 11.4 - - ns ns ns ns Global Early Clock to Output using OFF. Val- TICKEOF ues are for BUFGE #s 3, 4, 7, and 8. Add 1.4 ns for BUFGE #s 1, 2, 5, and 6. XQ4013XL XQ4036XL XQ4062XL XQ4085XL 7.6 8.2 10.0 - - ns ns ns ns For output SLOW option add All Devices 3.0 3.0 ns Description Symbol TSLOW Units OFF = Output Flip Flop Note 1: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. Note 2: Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see graph below. DS029 (v1.2) February 9, 2000 9 ds029_1_2.fm Page 10 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs Capacitive Load Factor Figure 1 is usable over the specified operating conditions of voltage and temperature and is independent of the output slew rate control. 3 2 Delta Delay (ns) Figure 1 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the specified output delay if the load capacitance is different than 50 pF. For example, if the actual load capacitance is 120 pF, add 2.5 ns to the specified delay. If the load capacitance is 20 pF, subtract 0.8 ns from the specified output delay. 1 0 -1 -2 0 20 40 60 80 100 120 140 Capacitance (pF) DS029_03_011300 Figure 1: Delay Factor at Various Capacitive Loads 10 DS029 (v1.2) February 9, 2000 ds029_1_2.fm Page 11 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs XQ4000XL Pin-to-Pin Input Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. XQ4000XL Global Low Skew Clock, Set-Up and Hold Description Input Setup and Hold Times Using Global Low Skew Clock and IFF No Delay Symbol TPSN/TPHN Partial Delay TPSP/TPHP Full Delay TPSD/TPHD Speed Grade Device -3 Min -1 Min Units XQ4013XL XQ4036XL XQ4062XL XQ4085XL XQ4013XL XQ4036XL XQ4062XL XQ4085XL XQ4013XL XQ4036XL XQ4062XL XQ4085XL 1.2 / 3.2 1.2 / 5.5 1.2 / 7.0 6.1 / 0.0 6.4 / 1.0 6.7 / 1.2 6.4 / 0.0 6.6 / 0.0 6.8 / 0.0 - 0.9 / 7.1 9.8 / 1.2 9.6 / 0.0 ns ns ns ns ns ns ns ns ns ns ns ns IFF = Input Flip-Flop or Latch Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions. DS029 (v1.2) February 9, 2000 11 ds029_1_2.fm Page 12 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs XQ4000XL BUFGE #s 3, 4, 7, & 8 Global Early Clock, Set-up and Hold for IFF and FCL Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. Description Input Setup and Hold Times No Delay Global Early Clock and IFF Global Early Clock and FCL Symbol TPSEN/TPHEN TPFSEN/TPFHEN Partial Delay Global Early Clock and IFF Global Early Clock and FCL TPSEP/TPHEP TPFSEP/TPFHEP Full Delay Global Early Clock and IFF TPSED/TPHED Speed Grade Device -3 Min -1 Min XQ4013XL XQ4036XL XQ4062XL XQ4085XL XQ4013XL XQ4036XL XQ4062XL XQ4085XL XQ4013XL XQ4036XL XQ4062XL XQ4085XL 1.2 / 4.7 1.2 / 6.7 1.2 / 8.4 5.4 / 0.0 6.4 / 0.8 8.4 / 1.5 12.0 / 0.0 13.8 / 0.0 13.1 / 0.0 - 0.9 / 6.6 11.0 / 0.0 13.6 / 0.0 IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions. 12 DS029 (v1.2) February 9, 2000 ds029_1_2.fm Page 13 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs XQ4000XL BUFGE #s 1, 2, 5, & 6 Global Early Clock, Set-up and Hold for IFF and FCL Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. Description Input Setup and Hold Times No Delay Global Early Clock and IFF Global Early Clock and FCL Symbol TPSEN/TPHEN TPFSEN/TPFHEN Partial Delay Global Early Clock and IFF Global Early Clock and FCL TPSEP/TPHEP TPFSEP/TPFHEP Full Delay Global Early Clock and IFF TPSED/TPHED Speed Grade Device XQ4013XL XQ4036XL XQ4062XL XQ4085XL XQ4013XL XQ4036XL XQ4062XL XQ4085XL XQ4013XL XQ4036XL XQ4062XL XQ4085XL -3 Min -1 Min 1.2 / 4.7 1.2 / 6.7 1.2 / 8.4 0.9 / 6.6 6.4 / 0.0 7.0 / 0.0 9.0 / 0.8 12.6 / 0.0 10.0 / 0.0 12.2 / 0.0 13.1 / 0.0 13.6 / 0.0 IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions. DS029 (v1.2) February 9, 2000 13 ds029_1_2.fm Page 14 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs XQ4000XL IOB Input Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Description Clocks Clock Enable (EC) to Clock (IK) Delay from FCL enable (OK) active edge to IFF clock (IK) active edge Setup Times Pad to Clock (IK), no delay Pad to Clock (IK), via transparent Fast Capture Latch, no delay Pad to Fast Capture Latch Enable (OK), no delay Hold Times All Hold Times Global Set/Reset Minimum GSR Pulse Width Delay from GSR input to any Q Propagation Delays Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Pad to I1, I2 via transparent FCL and input latch, no delay Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) FCL Enable (OK) active edge to I1, I2 (via transparent standard input latch) Speed Grade Device -3 Min -1 Min Units TECIK TOKIK All devices All devices 0.3 1.7 0.3 1.7 ns ns TPICK TPICKF All devices All devices 1.7 2.3 1.7 2.3 ns ns TPOCK All devices 0.7 0.7 ns All devices 0 0 ns TMRW TRRI All devices XQ4013XL XQ4036XL XQ4062XL XQ4085XL All devices All devices All devices All devices All devices All devices 19.8 26.0 Max 1.6 2.6 3.1 1.8 1.9 3.6 ns ns ns ns ns TPID TPLI TPFLI TIKRI TIKLI TOKLI 19.8 15.9 22.5 29.1 Max 1.6 2.6 3.1 1.8 1.9 3.6 Symbol ns ns ns ns ns ns IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch 14 DS029 (v1.2) February 9, 2000 ds029_1_2.fm Page 15 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs XQ4000XL IOB Output Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values are expressed in nanoseconds unless otherwise noted. Speed Grade Description -3 Symbol Min TCH TCL 3.0 3.0 -1 Max Min Max Units Clocks Clock High Clock Low 2.5 2.5 ns ns Propagation Delays Clock (OK) to Pad Output (O) to Pad 3-state to Pad hi-Z (slew-rate independent) 3-state to Pad active and valid Output (O) to Pad via Fast Output MUX Select (OK) to Pad via Fast MUX TOKPOF TOPF TTSHZ TTSONF TOFPF TOKFPF 5.0 4.1 4.4 4.1 5.5 5.1 3.8 3.1 3.0 3.3 4.2 3.9 ns ns ns ns ns ns Setup and Hold Times Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock Enable (EC) to clock (OK) setup time Clock Enable (EC) to clock (OK) hold time TOOK TOKO TECOK TOKEC 0.5 0.0 0.0 0.3 0.3 0.0 0.0 0.1 ns ns ns ns TMRW TRPO 19.8 15.0 ns 20.5 27.1 33.7 - 29.5 ns ns ns ns Global Set/Reset Minimum GSR pulse width Delay from GSR input to any Pad XQ4013XL XQ4036XL XQ4062XL XQ4085XL Slew Rate Adjustment For output SLOW option add TSLOW 3.0 2.0 ns Note 1: Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads. DS029 (v1.2) February 9, 2000 15 ds029_1_2.fm Page 16 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs Pinouts CB228 Package for XQ4013XL/4036XL/4062XL/4085XL PIN_NAME VTT VSS BUFGP_TL_A16_GCK1_IO A17_IO IO IO TDI_IO TCK_IO IO IO IO IO IO IO VSS IO_FCLK1 IO TMS_IO IO IO IO IO IO IO IO IO IO VSS VCC IO IO IO IO IO IO IO IO VCC IO IO IO IO_FCLK2 VSS 16 CB228 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 PIN_NAME IO IO IO IO IO IO IO IO IO IO IO BUFGS_BL_GCK2_IO M1 VSS M0 VCC M2 BUFGP_BL_GCK3_IO HDC_IO IO IO IO LDC_IO IO IO IO IO IO IO VSS IO IO IO IO IO IO IO IO IO IO IO /ERR_INIT_IO VCC VSS IO IO CB228 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 DS029 (v1.2) February 9, 2000 ds029_1_2.fm Page 17 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs PIN_NAME IO IO IO IO IO IO VCC IO IO IO IO VSS IO IO IO IO IO IO IO IO IO IO IO BUFGS_BR_GCK4_IO VSS DONE VCC /PROG D7_IO BUFGP_BR_GCK5_IO IO IO IO IO D6_IO IO IO IO IO IO VSS IO IO IO_FCLK3 IO D5_IO /CS0_IO IO DS029 (v1.2) February 9, 2000 CB228 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 PIN_NAME IO IO IO D4_IO IO VCC VSS D3_IO /RS_IO IO IO IO IO D2_IO IO VCC IO IO_FCLK4 IO IO VSS IO IO IO IO IO IO D1_IO BUSY_/RDY_RCLK_IO IO IO D0_DIN_IO BUFGS_TR_GCK6_DOUT_IO CCLK VCC TDO VSS A0_/WS_IO BUFGP_TR_GCK7_A1_IO IO IO CSI_A2_IO A3_IO IO IO IO IO IO CB228 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 17 ds029_1_2.fm Page 18 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs PIN_NAME IO VSS IO IO IO IO VCC A4_IO A5_IO IO IO A21_IO A20_IO A6_IO A7_IO VSS VCC A8_IO A9_IO A19_IO A18_IO IO IO A10_IO A11_IO VCC IO IO IO IO VSS IO IO IO IO A12_IO A13_IO IO IO IO IO A14_IO BUFGS_TL_GCK8_A15_IO VCC 18 CB228 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P206 P207 P208 P209 P210 P211 P212 P213 P214 P215 P216 P217 P218 P219 P220 P221 P222 P223 P224 P225 P226 P227 P228 DS029 (v1.2) February 9, 2000 ds029_1_2.fm Page 19 Monday, February 14, 2000 9:08 AM R QPROTM XQ4000XL Series QML High-Reliability FPGAs Ordering Information Example for QPROTM military temperature part: XQ 4062XL -3 PG 475 M Mil-PRF-38535 (QML) Processed Temperature Range M = Military Ceramic (TC = -55oC to +125 oC) N = Military Plastic (TJ = -55C to +125C) Device Type XQ4085XL XQ4062XL XQ4036XL XQ4013XL Number of Pins Speed Grade -3 -1 (XQ4085XL only) Package Type CB = Top Brazed Ceramic Quad Flat Pack PG = Ceramic Pin Grid Array PQ/HQ = Plastic Quad Flat Back BG = Plastic Ball Grid Array Example for SMD part: 5962 98511 01 Q X C Generic Standard Microcircuit Drawing (SMD) Prefix Lead Finish C = Gold B = Solder Device Type XQ4028EX = 98509 XQ4013XL = 98513 XQ4036XL = 98510 XQ4062XL = 98511 XQ4085XL = 99575 Speed Grade 01 = -4 for XQ4028EX 01 = -3 for XQ4103XL/4036XL/4062XL 01 = -1 for XQ4085XL Package Type X = Pin Grid Y = Ceramic Quad Flat Pack (Base Mark) Z = Ceramic Quad Flat Pack (Lid Mark) T = Plastic Quad Flat Pack U = Plastic Ball Grid Q = QML Certified N = QML Plastic (N - Grade) Revision Control Date 5/98 1/99 2/9/00 Version 1.0 1.1 1.2 DS029 (v1.2) February 9, 2000 Description Original document release. Addition of new packages, clarification of parameters. Addition of XQ4085XL -1 speed grade part 19