DS029 (v1.2) February 9, 2000 1
XQ4000X Series Features
• Certified to MIL-PRF-38535 Appendix A QML (Qualified
Manufacturer Listing)
• Ceramic and plastic packages
• Also available under the following standard microcircuit
drawings (SMD)
- XQ4013XL 5962-98513
- XQ4036XL 5962-98510
- XQ4062XL 5962-98511
- XQ4085XL 5962-99575
• For more information contact the Defense Supply
Center Columbus (DSCC)
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
• A vailable in -3 speed
• System featured Field-Programmable Gate Arrays
- SelectRAM ™ memory: on-chip ultra-fast RAM with
- synchronous write option
- dual-port RAM option
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
• System Performance beyond 50 MHz
• Flexible Array Architecture
• Low Pow er Segmented Routing Architecture
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA Sink Current Per XQ4000XL Output
• Configured by Loading Binary File
- Unlimited reprogrammability
• Readback Capability
- Program verification
- Internal node observ ability
• Development System runs on most comm on computer
platforms
- - Interfaces to popular design environments
- - Fully automatic mapping, placement and routing
- - Interactive design editor for design optimization
• Highest Capacity — Over 130,000 Usable Gates
• Additional Routing Over XQ4000E
- almost twice the routing capacity for high-density
designs
• Buff ered Interconnect for Maximum Speed
• New Latch Capability in Configurable Logic Blocks
• Improved VersaRing™ I/O Interconnect f or Better Fix ed
Pinout Flexibility
- Virtually unlimited number of clock signals
• Optional Multiple xer or 2-input Function Generator on
Device Outputs
• 5V tolerant I/Os
• 0.35 µm SRAM process
Introduction
XQ4000X Series high-performance, high-capacity Field
Programmable Gate Arrays (FPGAs) provide the benefits
of custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of thirteen years of FPGA design experience and
f eedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated
soft-ware to achieve fully automated implementation of
complex, high-density, high-performance designs.
Refer to the complete Commercial XC4000X Series Field
Programmable Gate Arrays Data Sheet for more informa-
tion on device architecture and timing, and the latest Xilinx
databook for package pinouts other than the CB228
(included in this data sheet). (Pinouts f or XQ4000XL device
are identical to XC4000XL.)
0
QPRO™ XQ4000XL Series QML
High-Reliability FPGAs
DS029 (v1.2) February 9, 2000 00*
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ds029_1_2.fm Page 1 Monday, February 14, 2000 9:08 AM
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
2DS029 (v1.2) Februar y 9, 2000
XQ4000XL Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families.
Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterizat ion. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminar y are to be considered final.
All specifications subject to change without notice.
Additional Specifications
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply v oltage and junction
temperature conditions. The parameters included are common to popular designs and typical applications. For design
considerations requiring more detailed timing information, see the appropriate family a.c. supplements available on the
Xilinx WEBLINX at http://www.xilinx.com.
Absolute Maximum Ratings
Note 1: Maximum DC overshoot or und ershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to
achieve . During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts
less than 10 ns and with the forcing current being limited to 200 mA.
Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress rat-
ings only, and functional ope ration of the device at thes e or any oth er co nditio ns beyond those liste d un der Opera t ing Co ndi tions i s
not implied. Exposure to Absolute Maximum Ratings conditions for e xtended periods of time may affect device reliability.
Table 1: XQ4000X Series High Reliability Field Progammable Gate Arrays
Device Logic
Cells
Max Logic
Gates
(No RAM)
Max. RAM
Bits
(No Logic)
Typical Gate
Range
(Logic and RAM)*
CLB
Matrix Total
CLBs Number of
Flip-Flops Max.
User I/O Packages
XQ4013 X L 2432 13,000 18,432 10,000-3 0,000 24x2 4 576 1,536 192 PG223, CB2 28 ,
PQ240, BG256
XQ4036 X L 3078 36,000 41,472 22,000-6 5,000 36x3 6 1,296 3,168 288 PG411, CB2 28 ,
HQ240, BG352
XQ4062 X L 5472 62,000 73,728 40,000-130,000 4 8x4 8 2,304 5,376 384 PG475, CB2 28 ,
HQ240, BG432
XQ4085 X L 7448 85,000 100,352 55,000-180,000 5 6x5 6 3,136 7,168 448 PG475, CB2 28 ,
HQ240, BG432
* Maximum values of typical gate range includes 20% to 30% of CLBs used as RAM .
Symbol Description Units
VCC Supply voltage relative to GND -0.5 to 4.0 V
VIN Input voltage relative to GND (Note 1) -0.5 to 5.5 V
VTS Voltage applied to 3-state output (Note 1) -0.5 to 5.5 V
VCCt Longest Supply Voltage Rise Time from 1 V to 3V 50 ms
TSTG Storage temperature (ambient) -65 to +150 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 °C
TJJunction temperature Ceramic Package +150 °C
Plastic Package +125 °C
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DS029 (v1.2) February 9, 2000 3
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
Recommended Operating Conditions
Note 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per ×C.
Note 2: Input and output measurement threshold is ~50% of VCC.
XQ4000XL DC Characteristics Over Recommended Operating Conditions
Note 1: With up to 64 pins simultaneously sinking 12 mA.
Note 2: With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating.
Symbol Description Min Max Units
VCC
Supply voltage relative to GND, TJ = -55°C to
+125°CPlastic 3.0 3.6 V
Supply voltage relative to GND, TC = -55°C to
+125°CCeramic 3.0 3.6 V
VIH High-level input voltage 50% of VCC 5.5 V
VIL Low-level input voltage 0 30% of VCC V
TIN Input signal transition time 250 ns
Symbol Description Min Max Units
VOH High-level output voltage @ IOH = -4.0 mA, VCC min (LVTTL) 2.4 V
High-level output voltage @ IOH = -500 µA, (LVCMOS) 90% VCC V
VOL Low-level output voltage @ IOL = 12.0 mA, VCC min (LVTTL) (Note 1) 0.4 V
Low-level output voltage @ IOL = 1500 µA, (LVCM O S) 10% VCC V
VDR Data Retention Supply Voltage (below which configuration data may be lost) 2.5 V
ICCO Quiesce nt FPG A supply curren t (Note 2) 5 mA
ILInput or output leakage current -10 +10 µA
CIN Input capacitance (sample tested) BGA, PQ, HQ, packages 10 pF
PGA packages 16 pF
IRPU Pad pull-up (when selected) @ Vin = 0 V (sample tested) 0.02 0.25 mA
IRPD Pad pull-down (when selected) @ Vin = 3.6 V (sample tested) 0.02 0.15 mA
IRLL Horizontal Longline pull-up (when selected) @ logic Low 0.3 2.0 mA
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
4DS029 (v1.2) Februar y 9, 2000
XQ4000XL Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods s pecified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When f ewer vertical clock lines are connected, the clock distribution is f aster; when multiple clock lines per column are driven
from the same global clock, the dela y is longer. F or more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated t o the simulation netlist. These path dela ys, provided as a guideline, ha v e been ex tracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature).
Speed Grade -3 -1 Units
Description Symbol Device Max Max
From pad through Global Low Skew buffer, to any clock K TGLS XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
3.6
4.8
6.3
-
-
-
-
5.7
ns
ns
ns
ns
From pad through Global Early buffer, to any IOB clock. Values are for
BUFGE #s 1, 2, 5 and 6. Add 1 - 2 ns for BUFGE #s 3, 4, 7 and 8 and
for all CLB clock Ks driven from any of the 8 BUFGEs, or consult TRCE.
TGE XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
2.4
3.1
4.9
-
-
-
-
4.7
ns
ns
ns
ns
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DS029 (v1.2) February 9, 2000 5
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XQ4000XL devices and expressed in nanoseconds unless otherwise noted.
Speed Grade -3 -1 Units
Description Symbol Min Max Min Max
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
C inputs via DIN/H2 via H to X/Y outputs
C inputs via EC, DIN/H2 to YQ, XQ output (bypass)
TILO
TIHO
TITO
THH0O
THH1O
THH2O
TCBYP
1.6
2.7
2.9
2.5
2.4
2.5
1.5
1.3
2.2
2.2
2.8
1.9
2.0
1.1
ns
ns
ns
ns
ns
ns
ns
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1, F3) to COUT
CIN through function generators to X/Y outputs
CIN to COUT, bypass function generators
Carry Net Delay, COUT to CIN
TOPCY
TASCY
TINCY
TSUM
TBYP
TNET
2.7
3.3
2.0
2.8
0.26
0.32
2.0
2.5
1.5
2.4
0.20
0.25
ns
ns
ns
ns
ns
ns
Sequential Delays
Clock K to Flip-Flop outputs Q
Clock K to Latch outputs Q TCKO
TCKLO 2.1
2.1 1.6
1.6 ns
ns
Setup Time bef ore Clo ck K
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F/G
CIN input via F/G and H
TICK
TIHCK
THH0CK
THH1CK
THH2CK
TDICK
TECCK
TRCK
TCCK
TCHCK
1.1
2.2
2.0
1.9
2.0
0.9
1.0
0.6
2.3
3.4
0.9
1.7
1.6
1.4
1.6
0.7
0.8
0.5
1.9
2.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time after Clock K
F/G inputs
F/G inputs via H
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via DIN/H2 through H
C inputs via DIN/H2
C inputs via EC
C inputs via SR, going Low (inactive)
TCKI
TCKIH
TCKHH0
TCKHH1
TCKHH2
TCKDI
TCKEC
TCKR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
Clock
Clock High time
Clock Low time TCH
TCL 3.0
3.0 2.5
2.5 ns
ns
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q TRPW
TRIO 3.0 3.7 2.5 2.8 ns
ns
Global Set/Reset
Minimum GSR Pulse Width TMRW 19.8 15.0 ns
Delay from GSR input to any Q TMRQ See page 14 for TRRI values per device.
Toggle Frequency (MHz) (for export control) FTOG 166 200 MHz
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
6DS029 (v1.2) Februar y 9, 2000
XQ4000XL RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XQ4000XL devices and are expressed in nanoseconds unless otherwise noted.
Single Port RAM Speed Grade -3 -1 Units
Size Symbol Min Max Min Max
Write Operation
Address write cycle time (clock K period) 16x2
32x1 TWCS
TWCTS
9.0
9.0 7.7
7.7 ns
ns
Clock K pulse width (active edge) 16x2
32x1 TWPS
TWPTS
4.5
4.5 3.9
3.9 ns
ns
Address setup time before clock K 16x2
32x1 TASS
TASTS
2.2
2.2 1.7
1.7 ns
ns
Address hold time after clock K 16x2
32x1 TAHS
TAHTS
0
00
0ns
ns
DIN setup time before clock K 16x2
32x1 TDSS
TDSTS
2.0
2.5 1.7
2.1 ns
ns
DIN hold time after clock K 16x2
32x1 TDHS
TDHTS
0
00
0ns
ns
WE setup time before clock K 16x2
32x1 TWSS
TWSTS
2.0
1.8 1.6
1.5 ns
ns
WE hold time after clock K 16x2
32x1 TWHS
TWHTS
0
00
0ns
ns
Data valid after clock K 16x2
32x1 TWOS
TWOTS
6.8
8.1 5.8
6.9 ns
ns
Read Operation
Address read cycle time 16x2
32x1 TRC
TRCT
4.5
6.5 2.6
3.8 ns
ns
Data Valid after address change (no Write Enable) 16x2
32x1 TILO
TIHO
1.6
2.7 1.3
2.2 ns
ns
Address setup time before clock K 16x2
32x1 TICK
TIHCK
1.3
2.3 0.9
1.7 ns
ns
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DS029 (v1.2) February 9, 2000 7
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
Dual Port RAM Speed Grade -3 -1 Unit
s
Size Symbol Min Max Min Max
Write Operation
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
TWCDS
TWPDS
TASDS
TAHDS
TDSDS
TDHDS
TWSDS
TWHDS
TWODS
9.0
4.5
2.5
0
2.5
0
1.8
07.8
7.7
3.9
1.7
0
2.0
0
1.6
06.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Timing for16 x1 RAM option is identical to16 x 2 RAM.
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
8DS029 (v1.2) Februar y 9, 2000
XQ4000XL CLB RAM Synchronous (Edge-Triggered) Wr ite Timing
XQ4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing
DS029_01_011300
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT OLD NEW
TDSS TDHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
TWOS TILO
TILO
DS029_02_011300
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD NEW
TDSDS TDHDS
TASDS TAHDS
TWSS
TWPDS
TWHS
TWODS TILO
TILO
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DS029 (v1.2) February 9, 2000 9
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed ov er worst-case operati ng conditions (supply voltage and junction temperature). Listed below are representative
v alues for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values pro vided by the static timing analyzer (TRCE in the Xilinx De velopment
System) and back-annotated to the simulation netlist. These pat h dela ys, pro vided as a guideli ne , ha v e been e xt racted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
XQ4000XL Output Flip-Flop, Clock to Out
XQ4000XL Output Mux, Clock to Out
Speed Grade -3 -1 Units
Description Symbol Device Max Max
Global Low Skew Clock to Output using OFF TICKOF XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
8.6
9.8
11.3
-
-
-
-
9.5
ns
ns
ns
ns
Global Early Clock to Output using OFF
Values are for BUFGE #s 3, 4, 7, and 8. Add
1.4 ns for BUFGE #s 1, 2, 5, and 6.
TICKEOF XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
7.4
8.1
9.9
-
-
-
-
8.5
ns
ns
ns
ns
For output SLOW option add TSLOW A ll Devices 3.0 3.0 ns
OFF = Output Flip Flop
Note 1: Listed ab ove are repre sent ative values wher e one gl ob al cl ock input dr ives on e vertical clock line in each
accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Note 2: Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads,
see gr aph below.
Speed Grade -3 -1 Units
Description Symbol Device Max Max
Global Low Skew Clock to Output using OFF TICKOF XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
8.8
10.0
11.4
-
-
-
-
ns
ns
ns
ns
Global Early Clock to Output using OFF. Val-
ues are for BUFGE #s 3, 4, 7, and 8. Add 1. 4
ns for BUFGE #s 1, 2, 5, and 6.
TICKEOF XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
7.6
8.2
10.0
-
-
-
-
ns
ns
ns
ns
For output SLOW option add TSLOW A ll Devices 3.0 3.0 ns
OFF = Output Flip Flop
Note 1: Listed ab ove are repre sent ative values wher e one gl ob al cl ock input dr ives on e vertical clock line in each
accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Note 2: Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads,
see gr aph below.
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
10 DS029 (v1.2) Februar y 9, 2000
Capacitive Load Factor
Figure 1 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the speci-
fied output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
120 pF, add 2.5 ns to the specified delay. If the load capac-
itance is 20 pF, subtract 0.8 ns from the specified output
delay.
Figure 1 is usable ov er the specified operating conditions of
voltage and temperature and is independent of the output
slew rate control.
Figure 1: Delay Factor at Various Capacitive Loads
DS029_03_011300
-2 020406080
Capacitance (pF)
Delta Delay (ns)
100 120 140
-1
0
1
2
3
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DS029 (v1.2) February 9, 2000 11
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed ov er worst-case operati ng conditions (supply voltage and junction temperature). Listed below are representative
v alues for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values pro vided by the static timing analyzer (TRCE in the Xilinx De velopment
System) and back-annotated to the simulation netlist. These pat h dela ys, pro vided as a guideli ne , ha v e been e xt racted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
XQ4000XL Global Low Skew Clock, Set-Up and Hold
Speed Grade -3 -1 Units
Description Symbol Device Min Min
Input Setup and Hold Times Using
Global Low Skew Clock and IFF
No Delay TPSN/TPHN XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.2 / 3.2
1.2 / 5.5
1.2 / 7.0
-
-
-
-
0.9 / 7.1
ns
ns
ns
ns
Partial Delay TPSP/TPHP XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
6.1 / 0.0
6.4 / 1.0
6.7 / 1.2
-
-
-
-
9.8 / 1.2
ns
ns
ns
ns
Full Delay TPSD/TPHD XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
6.4 / 0.0
6.6 / 0.0
6.8 / 0.0
-
-
-
-
9.6 / 0.0
ns
ns
ns
ns
IFF = Input Flip-Flop or Latch
Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest
distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer (TRCE) to deter-
mine the setup and hold times under given design conditions.
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
12 DS029 (v1.2) Februar y 9, 2000
XQ4000XL BUFGE #s 3, 4, 7, & 8 Global Early Clock, Set-up and Hold for IFF and FCL
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed ov er worst-case operati ng conditions (supply voltage and junction temperature). Listed below are representative
v alues for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values pro vided by the static timing analyzer (TRCE in the Xilinx De velopment
System) and back-annotated to the simulation netlist. These pat h dela ys, pro vided as a guideli ne , ha v e been e xt racted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Speed Grade -3 -1
Description Symbol Device Min Min
Input Setup and Hold Times
No Delay
Global Early Clock and IFF
Global Early Clock and FCL TPSEN/TPHEN
TPFSEN/TPFHEN
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.2 / 4.7
1.2 / 6.7
1.2 / 8.4
-
-
-
-
0.9 / 6.6
Partial Delay
Global Early Clock and IFF
Global Early Clock and FCL TPSEP/TPHEP
TPFSEP/TPFHEP
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
5.4 / 0.0
6.4 / 0.8
8.4 / 1.5
-
-
-
-
11.0 / 0.0
Full Delay
Global Early Clock and IFF TPSED/TPHED
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
12.0 / 0.0
13.8 / 0.0
13.1 / 0.0
-
-
-
-
13.6 / 0.0
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
Note 1: Setup ti me is meas ured with the fastest route a nd the lig htest load. Ho ld time is m easured u sing the f ur thest dis-
tance a nd a reference load of one clock pin p er two IOBs. Use the static timi ng analyzer(T RCE) to det ermi ne the
setup and hold times under given design conditi ons .
ds029_1_2.fm Page 12 Monday, February 14, 2000 9:08 AM
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DS029 (v1.2) February 9, 2000 13
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL BUFGE #s 1, 2, 5, & 6 Global Early Clock, Set-up and Hold for IFF and FCL
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed ov er worst-case operati ng conditions (supply voltage and junction temperature). Listed below are representative
v alues for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values pro vided by the static timing analyzer (TRCE in the Xilinx De velopment
System) and back-annotated to the simulation netlist. These pat h dela ys, pro vided as a guideli ne , ha v e been e xt racted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Speed Grade -3 -1
Description Symbol Device Min Min
Input Setup and Hold Times
No Delay
Global Early Clock and IFF
Global Early Clock and FCL TPSEN/TPHEN
TPFSEN/TPFHEN
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.2 / 4.7
1.2 / 6.7
1.2 / 8.4
-
-
-
-
0.9 / 6.6
Partial Delay
Global Early Cloc k and IFF
Global Early Clock and FCL TPSEP/TPHEP
TPFSEP/TPFHEP
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
6.4 / 0.0
7.0 / 0.0
9.0 / 0.8
-
-
-
-
12.6 / 0.0
Full Delay
Global Early Cloc k and IFF TPSED/TPHED
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
10.0 / 0.0
12.2 / 0.0
13.1 / 0.0
-
-
-
-
13.6 / 0.0
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the fur-
thest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE)
to determine the setup and hold times under given design conditions.
ds029_1_2.fm Page 13 Monday, February 14, 2000 9:08 AM
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
14 DS029 (v1.2) Februar y 9, 2000
XQ4000XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer repor t. All timing parameters assum e
worst-case operating conditions (supply voltage and junction temperature).
Speed Grade -3 -1 Units
Description Symbol Device Min Min
Clocks
Clock Enable (EC) to Clock (IK) TECIK All devices 0.3 0.3 ns
Delay from FCL enable (OK) active edge to IFF clock (IK)
active edge TOKIK All devices 1.7 1.7 ns
Setup Time s
Pad to Clock (IK), no delay TPICK All devices 1.7 1.7 ns
Pad to Clock (IK), via transparent Fast Capture Latch, no
delay TPICKF All devices 2.3 2.3 ns
Pad to Fast Capture Latch Enable (OK), no delay TPOCK All devices 0.7 0.7 ns
Hold Times
All Hold Times All devices 0 0 ns
Global Set/Reset
Minimum GSR Pulse Width
Delay from GSR input to any Q TMRW
TRRI
All devices
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
19.8
15.9
22.5
29.1
-
19.8
-
-
-
26.0
ns
ns
ns
ns
ns
Propagation Delays Max Max
Pad to I1 , I2 TPID All devices 1.6 1.6 ns
Pad to I1, I2 via transparent input latch, no delay TPLI All devices 2.6 2.6 ns
Pad to I1, I2 via transparent FCL and input latch, no delay TPFLI All devices 3.1 3.1 ns
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
FCL Enable (OK) active edge to I1, I2
(via transparent standard input latch)
TIKRI
TIKLI
TOKLI
All devices
All devices
All devices
1.8
1.9
3.6
1.8
1.9
3.6
ns
ns
ns
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
ds029_1_2.fm Page 14 Monday, February 14, 2000 9:08 AM
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DS029 (v1.2) February 9, 2000 15
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer repor t. All timing parameters assum e
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values are expressed in nanoseconds unless otherwise noted.
Speed Grade -3 -1 Units
Description Symbol Min Max Min Max
Clocks
Clock High
Clock Low TCH
TCL
3.0
3.0 2.5
2.5 ns
ns
Propagation Delays
Clock (OK) to Pad
Out put (O) to Pad
3-state to Pad hi-Z (slew-rate independent)
3-state to Pad active and valid
Output (O) to Pad via Fast Output MUX
Select (OK) to Pad via Fast MUX
TOKPOF
TOPF
TTSHZ
TTSONF
TOFPF
TOKFPF
5.0
4.1
4.4
4.1
5.5
5.1
3.8
3.1
3.0
3.3
4.2
3.9
ns
ns
ns
ns
ns
ns
Setup and Hold Times
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
TOOK
TOKO
TECOK
TOKEC
0.5
0.0
0.0
0.3
0.3
0.0
0.0
0.1
ns
ns
ns
ns
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Pad
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
TMRW
TRPO
19.8
20.5
27.1
33.7
-
15.0
-
-
-
29.5
ns
ns
ns
ns
ns
Slew Rate Adjustment
For output SLOW option add T SLOW 3.0 2.0 ns
Note 1: Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads.
ds029_1_2.fm Page 15 Monday, February 14, 2000 9:08 AM
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
16 DS029 (v1.2) Februar y 9, 2000
Pinouts
CB228 Package for
XQ4013XL/4036XL/4062XL/4085XL
PIN_NAME CB228
VTT
VSS P1
BUFGP_TL_A16_GCK1_IO P2
A17_IO P3
IO P4
IO P5
TDI_IO P6
TCK_IO P7
IO P8
IO P9
IO P10
IO P11
IO P12
IO P13
VSS P14
IO_FCLK1 P15
IO P16
TMS_IO P17
IO P18
IO P19
IO P20
IO P21
IO P22
IO P23
IO P24
IO P25
IO P26
VSS P27
VCC P28
IO P29
IO P30
IO P31
IO P32
IO P33
IO P34
IO P35
IO P36
VCC P37
IO P38
IO P39
IO P40
IO_FCLK2 P41
VSS P42
IO P43
IO P44
IO P45
IO P46
IO P47
IO P48
IO P49
IO P50
IO P51
IO P52
IO P53
BUFGS_BL_GCK2_IO P54
M1 P55
VSS P56
M0 P57
VCC P58
M2 P59
BUFGP_BL_GCK3_IO P60
HDC_IO P61
IO P62
IO P63
IO P64
LDC_IO P65
IO P66
IO P67
IO P68
IO P69
IO P70
IO P71
VSS P72
IO P73
IO P74
IO P75
IO P76
IO P77
IO P78
IO P79
IO P80
IO P81
IO P82
IO P83
/ERR_INIT_IO P84
VCC P85
VSS P86
IO P87
IO P88
PIN_NAME CB228
ds029_1_2.fm Page 16 Monday, February 14, 2000 9:08 AM
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DS029 (v1.2) February 9, 2000 17
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
IO P89
IO P90
IO P91
IO P92
IO P93
IO P94
VCC P95
IO P96
IO P97
IO P98
IO P99
VSS P100
IO P101
IO P102
IO P103
IO P104
IO P105
IO P106
IO P107
IO P108
IO P109
IO P110
IO P111
BUFGS_BR_GCK4_IO P112
VSS P113
DONE P114
VCC P115
/PROG P116
D7_IO P117
BUFGP_BR_GCK5_IO P118
IO P119
IO P120
IO P121
IO P122
D6_IO P123
IO P124
IO P125
IO P126
IO P127
IO P128
VSS P129
IO P130
IO P131
IO_FCLK3 P132
IO P133
D5_IO P134
/CS0_IO P135
IO P136
PIN_NAME CB228 IO P137
IO P138
IO P139
D4_IO P140
IO P141
VCC P142
VSS P143
D3_IO P144
/RS_IO P145
IO P146
IO P147
IO P148
IO P149
D2_IO P150
IO P151
VCC P152
IO P153
IO_FCLK4 P154
IO P155
IO P156
VSS P157
IO P158
IO P159
IO P160
IO P161
IO P162
IO P163
D1_IO P164
BUSY_/RDY_RCLK_IO P165
IO P166
IO P167
D0_DIN_IO P168
BUFGS_TR_GCK6_DOUT_IO P169
CCLK P170
VCC P171
TDO P172
VSS P173
A0_/WS_IO P174
BUFGP_TR_GCK7_A1_IO P175
IO P176
IO P177
CSI_A2_IO P178
A3_IO P179
IO P180
IO P181
IO P182
IO P183
IO P184
PIN_NAME CB228
ds029_1_2.fm Page 17 Monday, February 14, 2000 9:08 AM
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
18 DS029 (v1.2) Februar y 9, 2000
IO P185
VSS P186
IO P187
IO P188
IO P189
IO P190
VCC P191
A4_IO P192
A5_IO P193
IO P194
IO P195
A21_IO P196
A20_IO P197
A6_IO P198
A7_IO P199
VSS P200
VCC P201
A8_IO P202
A9_IO P203
A19_IO P204
A18_IO P205
IO P206
IO P207
A10_IO P208
A11_IO P209
VCC P210
IO P211
IO P212
IO P213
IO P214
VSS P215
IO P216
IO P217
IO P218
IO P219
A12_IO P220
A13_IO P221
IO P222
IO P223
IO P224
IO P225
A14_IO P226
BUFGS_TL_GCK8_A15_IO P227
VCC P228
PIN_NAME CB228
ds029_1_2.fm Page 18 Monday, February 14, 2000 9:08 AM
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DS029 (v1.2) February 9, 2000 19
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
Ordering Information
Revision Control
Device Type
XQ4085XL
XQ4062XL
XQ4036XL
XQ4013XL
Package Type
CB = Top Brazed Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
PQ/HQ = Plastic Quad Flat Back
BG = Plastic Ball Grid Array
Temperature Range
M = Military Ceramic (TC = -55oC to +125 oC)
N = Military Plastic (TJ = -55°C to +125°C)
Mil-PRF-38535
(QML) Processed
Number of Pins
Speed Grade
XQ 4062XL -3 PG 475 M
Example for QPRO™ military temperature part:
-3
-1 (XQ4085XL only)
Date Version Description
5/98 1.0 Original document release.
1/99 1.1 Addition of new packages, clarification of parameters.
2/9/00 1.2 Addition of XQ4085XL -1 speed grade part
Device Type
XQ4028EX = 98509
XQ4013XL = 98513
XQ4036XL = 98510
XQ4062XL = 98511
XQ4085XL = 99575
Package Type
X = Pin Grid
Y = Ceramic Quad Flat Pack (Base Mark)
Z = Ceramic Quad Flat Pack (Lid Mark)
T = Plastic Quad Flat Pack
U = Plastic Ball Grid
Lead Finish
C = Gold
B = Solder
Generic Standard
Microcircuit Drawing (SMD)
Prefix
5962 98511 01 Q X C
Q = QML Certified
N = QML Plastic (N - Grade)
Example for SMD part:
Speed Grade
01 = -4 for XQ4028EX
01 = -3 for XQ4103XL/4036XL/4062XL
01 = -1 for XQ4085XL
ds029_1_2.fm Page 19 Monday, February 14, 2000 9:08 AM
