General Description
The GD16578 is a high performance low
power 2.5 Gbit/s Laser Driver with
optional on chip retiming of data.
The GD16578 is designed to meet and
exceed ITU-T STM-16 or SONET OC-48
fiberoptic communication systems re-
quirements.
The GD16578 is designed to sink a
Modulation Current into the IOUT pin and
a Pre-Bias Current into the IPRE pin. The
Modulation Current is adjustable up to
200 mA by means of the pin VMOD. The
Pre-Bias Current may be adjusted up to
60 mA by means of the VPRE pin.
Retiming of the data signal connected to
the pins DIN, DINQ is made by means of
a DFF clocked by an external clock sig-
nal at the data rate fed to the pins CKIN
and CKINQ.
A Mark-Space monitor is available on the
pins MARKP and MARKN. Together with
the symmetry adjustment pin (SYM) this
may be used to control the mark space
ratio of the output signal.
The GD16578 can operate on a single
+5 V supply or a single -5.2 V supply.
The circuit is available in a thermally
enhanced 32-pin TQFP plastic package.
an Intel company
Data Sheet Rev.: 10
Preliminary
Features
lComplies with ITU-T STM-16 and
SONET OC-48 standards.
lIntended for driving a 25 Wload, e.g.
a laser diode or Mach Zender modu-
lator with 25 Winput impedance.
lClocked or non-clocked operation.
lLarge modulation current adjustment
range from 70 mA to 200 mA.
lOutput voltage over / under shoot
less than ±5 % respectively ±10 %.
lRise / fall times less than 100 ps.
lLaser diode pre-bias adjustable up to
60 mA.
lMark-Space monitor.
lSymmetry adjustment
lInternal 50 Wtermination of data and
clock inputs.
lPower dissipation: 1 W (typ.).
(excluding Modulation Current and
Pre-bias Current).
l32 pin thermally enhanced TQFP
plastic package.
Applications
lTele Communication:
–SDH STM-16
–SONET OC-48
lData Communication.
lElectro Absorption laser driver.
lDirect Modulation laser driver.
lMach Zender modulator driver.
2.5 Gbit/s
Retiming
Laser Driver
GD16578
D
Q
Input
Buffer
Input
Buffer
DIN
CKSEL
SPOL
CKIN
DINQ
CKINQ
DINT
CKINT
MARKP
VEEP
VEER
VEEB
VEE
IOUTN
IOUT
VDDR
VDD
IPRE
VPREVMOD
50
50
50
50
MARKN
SYM
Modulation
Current
Control
Pre-Bias
Current
Control
Output
Driver
Mark/Space
Monitor
MUX
Functional Details
GD16578 is a 2.5 Gbit/s laser driver with
an optional retiming of the data signal. It
is capable of driving high power laser di-
odes, typically having input impedance of
25 W, at a maximum modulation current
of 200 mA and a maximum pre-bias cur-
rent of 60 mA.
Data (DIN, DINQ) is input to GD16578
and retimed within a DFF clocked by an
external clock (CKIN, CKINQ). Optionally
the retiming may be bypassed controlled
by a select pin (CKSEL).
Both the differential data (DIN, DINQ)
and clock inputs (CKIN, CKINQ) are in-
ternally terminated to 50 W. Termination
is made with a 50 Wresistor from the two
differential inputs to a common pin called
DINT and CKINT respectively. Each of
these termination pins is DC biased inter-
nally via 750 Wto -1.3 V, hence there is
no need for external bias network. The
input sensitivity when driven with a single
ended signal is better than 150 mV on
both clock and data inputs.
The GD16578 can be used e.g. to boost
the output from the GD16553 MUX. This
differential output can be DC coupled to
the GD16578 input. A signal of 200 mVPP
at a common mode level of -100 mV has
been observed to provide good perfor-
mance.
Figure 1. Application Diagram
The output pin (IOUT) is an open collec-
tor output designed for driving external
loads with 25 Wcharacteristic imped-
ance. Because of the nature of an open
collector the output therefore may be re-
garded as a current switch, with infinite
output impedance. The characteristic im-
pedance through the package is approxi-
mately 25 W. Optimum performance of
GD16578 therefore is achieved if the out-
put is terminated into a 25 Wimpedance.
The output modulation current is con-
trolled by the pin VMOD and can be con-
trolled in the range from 0 mA to 200 mA,
however the specifications is only valid in
the range from 70 mA to 200 mA. The
output voltage swing across the external
load may be varied accordingly. The
modulation current control on pin VMOD
is implemented as a current mirror and
therefore sinks a current proportional to
the modulation current. The current sink
into the VMOD pin is approximately
1/210 of the modulation current.
Figure 2. Equivalent schematic of the
VMOD input
When DC coupled the output swing will
be limited by the specification for the
minimum voltage of VDD -3Vonthe
IOUT and IOUTN pins. Since 120 mA
into 25 Wgives 3 V swing it will not be
possible to terminate the output with a
25 Wload to VDD.
If more than 120 mA modulation current
is required, either the load (i.e. the laser)
must be supplied from a positive supply
voltage, or AC coupling with a bias tee
must be used (see Figure 3).
Data Sheet Rev.: 10 GD16578 Page 2 of 10
Input
Buffer
Input
Buffer
DIN/27
SPOL / 9
CKSEL / 1
CKIN / 31
DINQ / 26
CKINQ / 32
DINT / 28
CKINT / 30
Differential or
Single-ended
Clock Signal
Differential or
Single-ended
Data Signal
Control Voltage from
Modulation Current
Control System
Control Voltage from
Pre-Bias Current
Control System Laser Diode Equivalent
25 Input ImpedanceW
MARKP / 7
VEEP / 18
IOUTN / 11, 12
VTT
VTT
VDD
IOUT / 13, 14
IPRE / 19
VPRE / 16VMOD / 20
50
750
750
-1.3V
-1.3V
25
25
L
L
C
C
25
50
50
50
50
50
50
50
100n
100n
Negative
Supply
Ref.
+
-
100n
MARKN / 6
Modulation
Current
Control
Pre-Bias
Current
Control
Output
Driver
Mark/Space
Monitor
MUX
D
Q
VMOD
2kW
VEE
2V
Figure 3. AC Coupled Output
For high modulation currents it may be
necessary to use a positive supply for the
bias tee, depending on the resistance in
the bias coils. Measurements with the
set-up in Figure 3 with bias coils with 7 W
resistance show that a positive supply is
required for modulation current above
approximately 150 mA, and a voltage
VTT = +1,0 V is sufficient to give 200 mA
with VEE =–5.2 V supply. Less negative
VEE voltage must be compensated by
correspondingly higher VTT supply.
In the configuration shown in Figure 3
two coils in series are used for each
branch of the output for effective blocking
of high and low frequencies. Low fre-
quency ciols generally have high para-
sitic parallel capacitance.
Figure 4. Output waveform at 200 mA,
-4.7 V supply, AC coupled
load.
The pre-bias current is controlled by the
pin VPRE and can be controlled from
0 mA to 60 mA. The pre-bias current
control on pin VPRE is implemented as a
current mirror and therefore sinks a cur-
rent proportional to the pre-bias current.
The current sink into the VPRE pin is
approximately 3/500 of the pre-bias
current.
An important parameter for laser drivers
is voltage overshoot on the output pin
(IOUT), because it determines the extinc-
tion ratio. GD16578 has been designed
with special emphasis on achieving a
very small voltage overshoot. For
GD16578 the voltage overshoot is less
than 5 % across the full modulation cur-
rent range, when driving a 25 Wload.
Similarly the voltage undershoot is less
than 10 %.
A mark-space monitor is provided
through the pins MARKP and MARKN.
These may be connected as shown in
the application diagram below, with a ca-
pacitor across the two outputs and a
comparator (or Op-amp) to determine the
mark density. Symmetry input (SYM) is
available which may be used to control
the mark-space ratio.
Data Sheet Rev.: 10 GD16578 Page 3 of 10
L1
220uH
L3
220uH
L2
10uH
IOUT
IOUTN
L4
10uH
100nF
100nF
To
Ext.
Load
25W
VTTVTT
VDD
Pin List
Mnemonic: Pin No.: Pin Type: Description:
DIN
DINQ
27
26
AC IN Data inputs. Internally terminated in 50 Wto DINT.
DINT 28 ANL IN Termination voltage for DIN and DINQ.
Internally biased to -1.3 V with 750 W.
CKIN
CKINQ
31
32
AC IN Clock inputs. Internally terminated in 50 Wto CKINT. Data is sam-
pled on the positive going edge of the clock (CKIN).
CKINT 30 ANL IN Termination voltage for CKIN and CKINQ.
Internally biased to -1.3 V with 750 W.
IOUT
IOUTN
13, 14
11, 12
OPEN
COLLECTOR
Laser Driver Output (2.5 Gbit/s). IOUT and IOUTN sink a modula-
tion current, which is controlled by the pin VMOD. The polarity of
the output depends on the settings of SPOL, see below.
IPRE 19 OPEN
COLLECTOR
Pre-bias current output. IPRE sinks a current, which is controlled
by the pin VPRE.
VMOD 20 ANL IN Modulation current control input. The control system is made as a
current mirror. VMOD sinks a current proportional to the modula-
tion current. This current is approximately 1/210 times “The modu-
lation current”.
VPRE 16 ANL IN Pre-bias current control input. The control system is made as a
current mirror. VPRE sinks a current proportional to the pre-bias
current. This current is approximately 3/500 times “The pre-bias
current”.
CKSEL 1 ECL IN When CKSEL is low data is retimed. Otherwise data is bypassed
the retiming. May be connected to rails.
SPOL 9 ECL IN Data polarity select pin. When SPOL is high, a high level on DIN
will cause the IOUT output to sink current, i.e. causing the voltage
on IOUT to be low. SPOL is internally pulled to VDD witha5kre-
sistor. May be connected to rails.
SYM 24 ANL IN SYM controls the mark-space ratio of the output. Decreasing the
voltage of the SYM pin decreases the pulse width of a current
high into the IOUT pin. When SYM is left open the output cross-
over will be 50%.
MARKP
MARKN
7
6
ANL OUT Mark-space monitor outputs. High impedance CML outputs. The
output voltage of the MARKP pin is the same polarity as the volt-
age on the IOUT pin.
VDD 2, 3, 4, 10, 15 PWR Ground pins for laser driver part.
VDDR 29 PWR Ground pin for retiming part.
VEE 5, 8, 23 PWR Negative supply pins for laser driver part. Package back is VEE.
VEEB 17 PWR Negative supply pin for pre-bias circuitry.
VEEP 18 PWR Negative supply pin for output driver.
VEER 25 PWR Negative supply pin for retiming part.
NC 21, 22 Not Connected.
Heat sink Package back Connected to VEE.
Data Sheet Rev.: 10 GD16578 Page 4 of 10
Package Pinout
Figure 5. Package 32 TQFP, Top View
Maximum Ratings
These are the limits beyond which the component may be damaged.
All voltages in table are referred to VDD.
All currents in table are defined positive out of the pin.
Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:
VEE Power Supply -6 0 V
VOApplied Voltage (All Outputs) VEE -0.5 0.5 V
VOIOUT/N Applied Voltage IOUT and IOUTN VEE -0.5 3 V
VIApplied Voltage (All Inputs) VEE -0.5 0.5 V
IIAC IN Input Current (AC IN) -1 1 mA
IIVMOD Input Current (VMOD) -2 0.1 mA
IIVPRE Input Current (VPRE) Note 1 -1 1 mA
TOOperating Temperature Case -40 +110 °C
TSStorage Temperature -65 +125 °C
Note 1: Voltage and/or current should be externally limited to specified range.
Data Sheet Rev.: 10 GD16578 Page 5 of 10
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CKINQ
CKIN
CKINT
VDDR
DINT
DIN
DINQ
VEER
SYM
VEE
NC
NC
VMOD
IPRE
VEEP
VEEB
VPRE
VDD
IOUT
IOUT
IOUTN
IOUTN
VDD
SPOL
VEE
MARKP
MARKN
VEE
VDD
VDD
VDD
CKSEL
DC Characteristics
TCASE =-40 °Cto85°C, appropriate heat sinking may be required. Device is DC-tested in the temperature range 0 °Cto85°C,
specifications from -40 °Cto0°C are guaranteed by design, and evaluated during the engineering test.
All voltages in table are referred to VDD.
All currents in table are defined positive out of the pin.
Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:
VEE Power Supply -5.5 -4.7 V
IEE Negative Supply Current VEE = -5.2 V
IOUT =0A
IPRE =0A
160 180 mA
PDISS Power Dissipation VEE =-5.0 V,
IOUT =0A,
IPRE = 0 A, Note 4
1W
Vpp AN IN Peak-peak Voltage when Input is Driven Single
ended.
VVTH =-1.3 V 150 800 mV
VCAN IN Common Mode Voltage Range for Data and
Clock Inputs
-1.5 -0.5 V
VIH ECL ECL Input HI Voltage -1.1 0 V
VIL ECL ECL Input LO Voltage VEE -1.5 V
VVMOD Voltage Range for VMOD VEE VDD V
IVMOD Sink Current into Pin VMOD -1.3 0 mA
VIN NN Input Voltage Range for VPRE and SYM VEE VDD V
ISINK NN Sink Current into pin VPRE and SYM -10mA
VIN SYM Input Voltage Range for SYM VEE VDD V
ILEAK SYM Leakage Current for SYM -11mA
ILEAK CKSEL,SPOL Leakage Current for CKSEL and SPOL -2 < VI< -0.7 -11mA
VLO MARK Low Output Voltage for Mark-Space Monitor -2.0 V
ROMARK Output Impedance for Mark-Space Monitor 4.0 kW
VOIPRE IPRE Output Voltage -3.0 V
IIPRE IPRE Current -60 0 mA
VOIOUT IOUT Output Voltage Note 1 -3.0 V
IMod,HI IOUT IOUT High Modulation Current Note 1, 2 -200 0 mA
IMod,LO IOUT IOUT Low Modulation Current Note 1, 3 -6 1 mA
IOUT/I(VMOD) Modulation Control Current to Modulation
Current Gain
200 210 220
Note 1: RLOAD =25Wto VDD +2 V connected to pin IOUT and IOUTN. Sink current is controlled by the VMOD pin, and may be
adjusted in the range as specified. Notice that high modulation current means that the output voltage level is low.
Note 2: The AC parameters are only specified in the range from -200 mA to -70 mA.
Note 3: This is a leakage current. Maximum leakage current is present at max modulation current (i.e. at 200 mA modulation
current). The leakage current decreases for smaller modulation currents.
Note 4: Please observe that the heat dissipation in the GD16578 is the sum of contributions from the modulation current, the
pre-bias current, and the device’s own power consumption. Furthermore, the GD16578’s own power consumption de-
pends on the modulation current. Please refer to Figure 6 and example on page 7 .
Data Sheet Rev.: 10 GD16578 Page 6 of 10
Figure 6. Equivalent of power dissipation
Example:
With VEE = -5,2 V, IPRE =50mAfroma25Wload to 0 V, and IMOD = 200 mA from bias coils (»0W) connected to 0 V, and a base
consumption for the device itself at 160 mA + 0.1 ×IMOD the total power equals
uPrebias:
(5.2V - (25 W×50 mA)) ×50 mA »0.2 W
uModulation current:
5.2 V ×200 mA »1.04 W
uOwn consumption:
5.2 V ×(160 + 0.1 ×200 mA) »0.94 W
uThis amounts to a total of:
2.2 W.
Please observe that the heat sink is connected to VEE to obtain best thermal contact between die and heat sink of the package.
Data Sheet Rev.: 10 GD16578 Page 7 of 10
IPREIPRE
IPRE
IEE
IMOD
VDD
VEE
IOUT
IOUTN
AC Characteristics
TCASE = -40 °Cto+85°C, appropriate heat sinking may be required. Device is AC-tested in the temperature range 0 °Cto85°C,
specifications from -40 °Cto0°C are guaranteed by design, and evaluated during the engineering test.
Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:
fMAX OUT Data Output Frequency 2700 Mbit/s
Jpp OUT Added Output Jitter Note 1, 2, 3 30 ps
tRISE OUT Output Rise Time Note 1, 2 125 ps
tFALL OUT Output Fall Time Note 1, 2 125 ps
tPM Phase Margin Clock to Data Note 2, 4 300 ps
tSU Data Set-up Time Note 2, 4 60 30 ps
tHData Hold Time Note 2, 4 20 5 ps
DCROSS_OVER Output Cross Over Control Range, Dhx/H Note 1, 2 ±30 %
h1 Ringing h1/H Note 2, 4 5 %
h2 Ringing h2/H Note 2, 4 5 %
h3 Ringing h3/H Note 2, 4 10 %
h4 Ringing h4/H Note 2, 4 10 %
Note 1: ILD = 140 mA. Rise/Fall times at 20 –80 % of HI/LO voltage levels.
Note 2: Measured in GIGA evaluation board GD90571. IOUT and IOUTN are terminated to 25 Wand DC terminated to VDD
through a biastee.
Note 3: Added jitter. Measured as a peak-peak jitter value on a sampling oscilloscope in 60 s period. Measured with the data re-
timing enabled, and using the retiming clock signal as trigger for the oscilloscope.
Note 4: ILD = 70 mA. Engineering test has shown that this is the worst case corner.
Data Sheet Rev.: 10 GD16578 Page 8 of 10
h2
hx
h1
h3
h4
H
CKIN
tCLK
tSU
tH
DIN
Ordering Information
To order, please specify as shown below:
Product Name: Intel Order Number: Package Type: Case Temperature Range:
GD16578-32BA FAGD1657832BA
MM#: 836128
32L TQFP EDQUAD -40..85 °C
GD16578, Data Sheet Rev.: 10 - Date: 20 June 2001
The information herein is assumed to be
reliable. GIGA assumes no responsibility
for the use of this information, and all such
information shall be at the users own risk.
Prices and specifications are subject to
change without notice. No patent rights or
licenses to any of the circuits described
herein are implied or granted to any third
party. GIGA does not authorise or warrant
any GIGA Product for use in life support
devices and/or systems.
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Phone : +45 7010 1062
Fax : +45 7010 1063
E-mail : sales@giga.dk
Web site : http://www.intel.com/ixa
Please check our Internet web site
for latest version of this data sheet.
Distributor:
Copyright © 2001 GIGA ApS
An Intel company
All rights reserved
an Intel company
