PIN CONFIGURATIONS
20-Lead Plastic DIP (N)
20-Lead Cerdip (Q)
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD641
–INPUT
RG1
CKT COM
ATN OUT
+INPUT
ATN LO
ATN COM
ATN COM
LOG OUT
RG2
RG0
ATN IN
BL1
–V
S
ITC
BL2
–OUTPUT +OUTPUT
+V
S
LOG COM
20-Lead PLCC (P)
20 19123
18
14
15
16
17
4
5
6
7
8
9 10111213
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
ATN COM
ATN IN
BL1
–V
S
ITC
CKT COM
RG1
RG0
RG2
LOG OUT
ATN COM
ATN LO
–INPUT
+INPUT
AIN OUT
BL2
SIG –OUT
SIG +OUT
+V
S
LOG COM
AD641
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
250 MHz Demodulating
Logarithmic Amplifier
AD641
FEATURES
Logarithmic Amplifier Performance
Usable to 250 MHz
44 dB Dynamic Range
±2.0 dB Log Conformance
37.5 mV/dB Voltage Output
Stable Slope and Intercepts
2.0 nV/√Hz Input Noise Voltage
50 µV Input Offset Voltage
Low Power
±5 V Supply Operation
9 mA (+VS), 35 mA (–VS) Quiescent Current
Onboard Resistors
Onboard 10X Attenuator
Dual Polarity Current Outputs
Direct Coupled Differential Signal Path
APPLICATIONS
IF/RF Signal Processing
Received Signal Strength Indicator (RSSI)
High Speed Signal Compression
High Speed Spectrum Analyzer
ECM/Radar
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
PRODUCT DESCRIPTION
The AD641 is a 250 MHz, demodulating logarithmic amplifier
with an accuracy of ±2.0 dB and 44 dB dynamic range. The
AD641 uses a successive detection architecture to provide an
output current that is logarithmically proportional to its input
voltage. The output current can be converted to a voltage using
one of several on-chip resistors to select the slope. A single
AD641 provides up to 44 dB of dynamic range at speeds up to
250 MHz, and two cascaded AD641s together can provide
58 dB of dynamic range at speeds up to 250 MHz. The AD641
is fully stable and well characterized over either the industrial or
military temperature ranges.
The AD641 is not a logarithmic building block, but rather a
complete logarithmic solution for compressing and measuring
wide dynamic range signals. The AD641 is comprised of five
stages and each stage has a full wave rectifier, whose current de-
pends on the absolute value of its input voltage. The output of
these stages are summed together to provide the demodulated
output current scaled at 1 mA per decade (50 µA/dB).
Without utilizing the 10× input attenuator, log conformance of
2.0 dB is maintained over the input range –44 dBm to 0 dBm.
The attenuator offers the most flexibility without significantly
impacting performance.
The 250 MHz bandwidth and temperature stability make this
product ideal for high speed signal power measurement in RF/IF
systems. ECM/Radar and Communication applications are
routinely in the 100 MHz–180 MHz range for power measure-
ment. The bandwidth and accuracy, as well as dynamic range,
make this part ideal for high speed, wide dynamic range signals.
The AD641 is offered in industrial (–40°C to +85°C) and mili-
tary (–55°C to +125°C) package temperature ranges. Industrial
versions are available in plastic DIP and PLCC; MIL versions
are packaged in cerdip.
ELECTRICAL CHARACTERISTICS
AD641A AD641S
Parameter Conditions Min Typ Max Min Typ Max Units
TRANSFER FUNCTION
1
(I
OUT
= I
Y
LOG |V
IN
/V
X
|for V
IN
= 0.75 mV to ±200 mV dc)
LOG AMPLIFIER PERFORMANCE
3 dB Bandwidth 250 250 MHz
Voltage Compliance Range –0.3 +V
S
– 1 –0.3 +V
S
– 1 V
Slope Current, I
Y
0.98 1.00 1.02 0.98 1.00 1.02 mA
Accuracy vs. Temperature 0.002 0.002 %/°C
Over Temperature T
MIN
to T
MAX
0.98 1.02 mA
Intercept dBm 250 MHz –40.84 –40.43 –39.96 –40.84 –40.43 –39.96 dBm
Over Temperature T
MIN
to T
MAX
,
250 MHz –40.59 –39.47 dBm
Zero Signal Output Current
2
–0.2 –0.2 mA
ITC Disabled Pin 8 to COM –0.27 –0.27 mA
Maximum Output Current 2.3 2.3 mA
DYNAMIC RANGE
Single Configuration 44 44 dB
Over Temperature T
MIN
to T
MAX
40 38 dB
Dual Configuration 58 58 dB
Over Temperature T
MIN
to T
MAX
52 52 dB
LOG CONFORMANCE f = 250 MHz
Single Configuration –44 dBm to 0 dBm ±0.5 ±2.0 ±0.5 ±2.0 dB
Over Temperature S: –42 dBm to –4 dBm; ±1.0 ±2.5 ±1.0 ±2.5 dB
A: –42 dBm to –2 dBm, T
MIN
to T
MAX
Dual Configuration S: –60 dBm to –2 dBm; ±0.5 ±2.0 ±0.5 ±2.0 dB
Over Temperature A: –56 dBm to –4 dBm, T
MIN
to T
MAX
±1.0 ±2.5 ±1.0 ±2.5 dB
LIMITER CHARACTERISTICS
Flatness –44 dBm to 0 dBm @ 10.7 MHz ±1.6 ±1.6 dB
Phase Variation –44 dBm to 0 dBm @ 10.7 MHz ±2.0 ±2.0 Degrees
INPUT CHARACTERISTICS
Input Resistance Differential 500 500 kΩ
Input Offset Voltage Differential 50 200 50 200 µV
vs. Temperature 0.8 0.8 µV/°C
Over Temperature T
MIN
to T
MAX
300 µV
vs. Supply 22µV/V
Input Bias Current 7 25 7 25 µA
Input Bias Offset 11µA
Common Mode Input Range –2 +0.3 –2 +0.3 V
SIGNAL INPUT (Pins 1, 20)
Input Capacitance Either Pin to COM 2 2 pF
Noise Spectral Density 1 kHz to 10 MHz 2 2 nV/√Hz
Tangential Sensitivity BW = 100 MHz –72 –72 dBm
INPUT ATTENUATOR
(Pins 2, 3, 4, 5 & 19)
Attenuation
3
Pins 5 to Pin 19 20 20 dB
Input Resistance Pins 5 to 3/4 300 300 Ω
APPLICATION RESISTORS
(Pins 15, 16, 17) 0.995 1.000 1.005 0.995 1.000 1.005 kΩ
OUTPUT CHARACTERISTICS
(Pins 10, 11)
Peak Differential Output
4
±180 ±180 mV
Output Resistance Either Pin to COM 75 75 Ω
Quiescent Output Voltage Either Pin to COM –90 –90 mV
POWER SUPPLY
Voltage Supply Range ±4.5 ±7.5 ±4.5 ±7.5 V
Quiescent Current
+V
S
(Pin 12) T
MIN
to T
MAX
915 9 15 mA
–V
S
(Pin 7) T
MIN
to T
MAX
35 60 35 60 mA
NOTES
1
Logarithms to base 10 are used throughout. The response is independent of the sign of V
IN
.
2
The zero-signal current is a function of temperature unless internal temperature compensation (ITC) pin is grounded.
3
Attenuation ratio trimmed to calibrate intercept to 10 mV when in use. It has a temperature coefficient of +0.3%/°C.
4
The fully limited signal output will appear to be a square wave; its amplitude is proportional to absolute temperature.
Specifications subject to change wi
thout notice.
AD641–SPECIFICATIONS
REV. A
–2–
(VS = ±5 V; TA = +25°C, unless otherwise noted)
AD641
REV. A –3–
ORDERING GUIDE
Package Package
Model Description Option
AD641AN Plastic DIP N-20
AD641AP Plastic Leaded Chip Carrier P-20A
5962-9559801MRA Cerdip Q-20
THERMAL CHARACTERISTICS
θ
JC
θ
JA
(°C/W) (°C/W)
20-Pin Plastic DIP Package (N) 24 61
20-Pin Cerdip Package (Q) 25 85
20-Pin Plastic Leadless Chip Carrier (P) 28 75
ABSOLUTE MAXIMUM RATINGS*
Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7.5 V
Input Voltage (Pin 1 or Pin 20 to COM) . . . –3 V to +300 mV
Attenuator Input Voltage (Pin 5 to Pin 3/4) . . . . . . . . . . . ±4 V
Storage Temperature Range, Q . . . . . . . . . . –65°C to +150°C
Storage Temperature Range, N, P . . . . . . . . –65°C to +125°C
Ambient Temperature Range, Rated Performance
Industrial, AD641A . . . . . . . . . . . . . . . . . . –40°C to +85°C
Military, AD641S . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 60sec) . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may adversely affect device
reliability.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD641 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–4–
AD641–Typical DC Performance
1.015
1.010
1.005
1
0.995
0.990
0.985
0.980
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – °C
SLOPE CURRENT – mA
Figure 1. Slope Current, I
Y
, vs.
Temperature
4.5 5.0 5.5 6.0 6.5 7.0 7.5
POWER SUPPLY VOLTAGES – ± Volts
INTERCEPT VOLTAGE – mV
1.015
1.010
1.005
1.000
0.995
0.990
0.985
Figure 4. Intercept Voltage, V
X
, vs.
Supply Voltages
INPUT VOLTAGE – mV
(EITHER SIGN)
OUTPUT CURRENT – mA
2
1.0
0.1 1.0 1000.010.0 100.0
1
1.2
1.4
1.6
1.8
2.0
2.2
2.4
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR – dB
0
Figure 7. DC Logarithmic Transfer
Function and Error Curve for Single
AD641
1.20
1.15
1.10
1.05
1.00
0.95
0.90
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – °C
INTERCEPT – mV
Figure 2. Intercept Voltage, V
X
, vs.
Temperature
14
13
12
11
10
9
8
7
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – °C
INTERCEPT – mV
Figure 5. Intercept Voltage (Using
Attenuator) vs. Temperature
2.5
2.0
1.5
1.0
0.5
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – °C
0
ABSOLUTE ERROR – dB
Figure 8. Absolute Error vs. Tempera-
ture, V
IN
=
±
1 mV to
±
100 mV
4.5 5.0 5.5 6.0 6.5 7.0 7.5
POWER SUPPLY VOLTAGES – ± Volts
SLOPE CURRENT – mV
1.006
1.004
1.002
1.000
0.998
0.996
0.994
Figure 3. Slope Current, I
Y
, vs. Supply
Voltages
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – °C
DEVIATION OF INPUT OFFSET VOLTAGE – mV
0
–0.1
+0.4
+0.3
+0.2
+0.1
–0.2
–0.3
INPUT OFFSET VOLTAGE
DEVIATION WILL BE WITHIN
SHADED AREA.
Figure 6. Input Offset Voltage Devia-
tion vs. Temperature
2.5
2.0
1.5
1.0
0.5
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – °C
0
ABSOLUTE ERROR – dB
Figure 9. Absolute Error vs. Tempera-
ture, Using Attenuator. V
IN
=
±
10 mV
to
±
1 V, Pin 8 Grounded to Disable ITC
Bias
INPUT LEVEL – dBm
–2.25
–2.00
0.25 2–48 –44 –40 –4
–1.25
–0.50
–0.25
0.00
–1.75
–1.50
–0.75
–1.00
OUTPUT CURRENT – mA
–52 –36 –32 –28 –24 –20 –16 –12 –8 0
50MHz
150MHz
190MHz
210MHz
250MHz
Figure 10. AC Response at 50 MHz, 150 MHz, 190 MHz,
210 MHz at 250 MHz, vs. dBm Input (Sinusoidal Input)
INPUT FREQUENCY – MHz
1
0.95
0.7550 250150 190 210
0.9
0.85
0.8
SLOPE CURRENT – mA
Figure 12. Slope Current, I
Y
, vs. Input Frequency
10
0%
10nS
20mV
100
90
Figure 14. Baseband Pulse Response of Single AD641,
Inputs of 1 mV, 10 mV and 100 mV
REV. A –5–
ERROR IN – dB
INPUT LEVEL – dBm
–2.00
–1.75
0.50 2–48 –44 –40 –4
–1.00
–0.25
–0.00
0.25
–1.50
–1.25
–0.50
–0.75
OUTPUT – mA
–52 –36 –32 –28 –24 –20 –16 –12 –8 0
25°C
125°C
–55°C
25°C
125°C
–55°C
OUTPUT
25°C
125°C
–55°C
125°C
ERROR
25°C
–55°C
5
4
3
2
1
0
–1
–2
–3
–4
–5
Figure 11. Logarithmic Response and Linearity at
200 MHz, T
A
for T
A
= –55
°
C, +25
°
C, +125
°
C
INPUT FREQUENCY – MHz
INTERCEPT LEVEL – dBm
87.5
70.050 250100 150 170 190 210 230
85.0
80.0
77.5
75.0
72.5
82.5
Figure 13. Intercept Level (dBm) vs. Frequency (Cascaded
AD641s—Sinusoidal Input)
10
0%
5µs
5µs
20mV
20mV
100
90
10
0%
20nS
50mV
100
90
Figure 15. Baseband Pulse Response of Cascaded AD641s
at Inputs of 0.2 mV, 2 mV, 20 mV and 200 mV
Typical AC Performance–AD641
REV. A
–6–
AD641
CIRCUIT DESCRIPTION
The AD641 uses five cascaded limiting amplifiers to approxi-
mate a logarithmic response to an input signal of wide dynamic
range and wide bandwidth. This type of logarithmic amplifier
has traditionally been assembled from several small scale ICs
and numerous external components. The performance of these
semidiscrete circuits is often unsatisfactory. In particular, the
logarithmic slope and intercept (see FUNDAMENTALS OF
LOGARITHMIC CONVERSION) are usually not very stable
in the presence of supply and temperature variations even after
laborious and expensive individual calibration. The AD641 em-
ploys high precision analog circuit techniques to ensure stability
of scaling over wide variations in supply voltage and tempera-
ture. Laser trimming, using ac stimuli and operating conditions
similar to those encountered in practice, provides fully cali-
brated logarithmic conversion.
Each of the amplifier/limiter stages in the AD641 has a small
signal voltage gain of 10 dB (×3.162) and a –3 dB bandwidth of
350 MHz. Fully differential direct coupling is used throughout.
This eliminates the many interstage coupling capacitors usually
required in ac applications, and simplifies low frequency signal
processing, for example, in audio and sonar systems. The
AD641 is intended for use in demodulating applications. Each
stage incorporates a detector (a full-wave transconductance rec-
tifier) whose output current depends on the absolute value of its
input voltage.
Figure 16 is a simplified schematic of one stage of the AD641.
All transistors in the basic cell operate at near zero collector to
base voltage and low bias currents, resulting in low levels of
thermally induced distortion. These arise when power shifts
from one set of transistors to another during large input signals.
Rapid recovery is essential when a small signal immediately fol-
lows a large one. This low power operation also contributes sig-
nificantly to the excellent long term calibration stability of the
AD641.
The complete AD641, shown in Figure 17, includes two bias
regulators. One determines the small signal gain of the ampli-
fier stages; the other determines the logarithmic slope. These
bias regulators maintain a high degree of stability in the re-
sulting function by compensating for potentially large uncer-
tainties in transistor parameters, temperature and supply
voltages. A third biasing block is used to accurately control
the logarithmic intercept.
COMMON
SIG
IN
R1
85ΩR2
85Ω
R3
75ΩR4
75Ω
SIG
OUT
LOG OUT LOG COM
Q1
Q2
Q3 Q4 Q5 Q6 Q7 Q8
Q10
Q9
–VS
1.09mA
PTAT 1.09mA
PTAT 565µA 565µA 2.18mA
PTAT
Figure 16. Simplified Schematic of a Single AD641 Stage
By summing the signals at the output of the detectors, a good
approximation to a logarithmic transfer function can be
achieved. The lower the stage gain, the more accurate the ap-
proximation, but more stages are then needed to cover a given
dynamic range. The choice of 10 dB results in a theoretical peri-
odic deviation or ripple in the transfer function of ±0.15 dB
from the ideal response when the input is either a dc voltage or a
square wave. The slope of the transfer function is unaffected by
the input waveform; however, the intercept and ripple are wave-
form dependent (see EFFECT OF WAVEFORM ON INTER-
CEPT). The input will usually be an amplitude modulated
sinusoidal carrier. In these circumstances the output is a fluctu-
ating current at twice the carrier frequency (because of the full
wave detection) whose average value is extracted by an external
low pass filter, which recovers a logarithmic measure of the
baseband signal.
Circuit Operation
With reference to Figure 16, the transconductance pair Q7, Q8
and load resistors R3 and R4 form a limiting amplifier having a
small signal gain of 10 dB, set by the tail current of nominally
2.18 mA at 27°C. This current is basically proportional to abso-
lute temperature (PTAT) but includes additional current to
compensate for finite beta and junction resistance. The limiting
output voltage is ±180 mV at 27°C and is PTAT. Emitter fol-
lowers Q1 and Q2 raise the input resistance of the stage, provide
level shifting to introduce collector bias for the gain stage and
detectors, reduce offset drift by forming a thermally balanced
ATN LO
ATN COM
SIG +IN
SIG –IN
ATN COM
COM
27Ω
30Ω270Ω
ATN IN
1kΩ1kΩ
RG1 RG0 RG2
–V
S
BL1
+V
S
LOG OUT LOG COM
SIG +OUT
SIG –OUT
BL2
ITC
20
GAIN BIAS REGULATOR
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
ATN OUT
1
2
3
6
45
19
18
7
13
9
8
11
10
12
SLOPE BIAS REGULATOR
INTERCEPT POSITIONING BIAS
14
151617
Figure 17. Block Diagram of the Complete AD641
AD641
REV. A –7–
quad with Q7 and Q8 and generate the detector biasing across
resistors R1 and R2.
Transistors Q3 through Q6 form the full wave detector, whose
output is buffered by the cascodes Q9 and Q10. For zero input
Q3 and Q5 conduct only a small amount (a total of about
32 µA) of the 565 µA tail currents supplied to pairs Q3–Q4 and
Q5–Q6. This “pedestal” current flows in output cascode Q9 to
the LOG OUT node (Pin 14). When driven to the peak output
of the preceding stage, Q3 or Q5 (depending on signal polarity)
conducts most of the tail current, and the output rises to
532 µA. The LOG OUT current has thus changed by 500µA
as the input has changed from zero to its maximum value.
Since the detectors are spaced at 10 dB intervals, the output in-
creases by 50 µA/dB, or 1 mA per decade. This scaling param-
eter is trimmed to absolute accuracy using a 2 kHz square
wave. At frequencies near the system bandwidth, the slope is
reduced due to the reduced output of the limiter stages, but it
is still relatively insensitive to temperature variations so that a
simple external slope adjustment can restore scaling accuracy.
The intercept position bias generator (Figure 17) removes the
pedestal current from the summed detector outputs. It is ad-
justed during manufacture such that the output (flowing into
Pin 14) is 1 mA when a 2 kHz square-wave input of exactly
±10 mV is applied to the AD641. This places the dc intercept
at precisely 1 mV. The LOG COM output (Pin 13) is the
complement of LOG OUT. It also has a 1 mV intercept, but
with an inverted slope of –1 mA/decade. Because its pedestal is
very large (equivalent to about 100 dB), its intercept voltage is
not guaranteed. The intercept positioning currents include a
special internal temperature compensation (ITC) term which
can be disabled by connecting Pin 8 to ground.
The logarithmic function of the AD641 is absolutely calibrated
to within ±0.3 dB (or ±15 µA) for 2 kHz square-wave inputs of
±1 mV to ±100 mV, and to within ±1 dB between ±750 µV and
±200 mV. Figure 18 is a typical plot of the dc transfer function,
2.5
–0.5 1000.0
0.5
0
1.00.1
1.0
1.5
2.0
100.010.0
INPUT VOLTAGE – mV
OUTPUT CURRENT – mA
2
1
0
–1
–2
3
ABSOLUTE ERROR – dB
–55°C
+125°C
+25°C
+125°C
–55°C
+25°C
Figure 18. Logarithmic Output and Absolute Error vs. DC
or Square Wave Input at T
A
= –55
°
C, +25
°
C, and +125
°
C,
Input Direct to Pins 1 and 20
2.5
–0.5 10000
0.5
0
100.1
1.0
1.5
2.0
1000100
INPUT VOLTAGE – mV
OUTPUT CURRENT – mA
1
0
–1
–2
ABSOLUTE ERROR – dB
+25°C
–55°C
+85°C+125°C
Figure 19. Logarithmic Output and Absolute Error vs. DC
or Square Wave Input at T
A
= –55
°
C, +25
°
C, +85
°
C and
+125
°
C. Input via On-Chip Attenuator
showing the outputs at temperatures of –55°C, +25°C and
+125°C. While the slope and intercept are seen to be little af-
fected by temperature, there is a lateral shift in the end points of
the “linear” region of the transfer function, which reduces the
effective dynamic range.
The on chip attenuator can be used to handle input levels 20dB
higher, that is, from ±7.5 mV to ±2 V for dc or square wave in-
puts. It is specially designed to have a positive temperature coef-
ficient and is trimmed to position the intercept at 10mV dc (or
–24 dBm for a sinusoidal input) over the full temperature range.
When using the attenuator the internal bias compensation
should be disabled by grounding Pin 8. Figure 19 shows the
output at –55°C, +25°C, +85°C and +125°C for a single,
AD641 with the attenuator in use; the curves overlap almost
perfectly, and the lateral shift in the transfer function does not
occur. Therefore, the full dynamic range is available at all tem-
peratures.
The output of the final limiter is available in differential form at
Pins 10 and 11. The output impedance is 75 Ω to ground from
either pin. For most input levels, this output will appear to have
roughly a square waveform. The signal path may be extended
using these outputs (see OPERATION OF CASCADED
AD641s). The logarithmic outputs from two or more AD641s
can be directly summed with full accuracy.
A pair of 1 kΩ applications resistors, RG1 and RG2 (Figure 17)
are accessed via Pins 15, 16 and 17. These can be used to con-
vert an output current to a voltage, with a slope of 1V/decade
(using one resistor), 2 V/decade (both resistors in series) or
0.5 V/decade (both in parallel). Using all the resistors from two
AD641s (for example, in a cascaded configuration) ten slope
options from 0.25 V to 4 V/decade are available.
REV. A
–8–
AD641
FUNDAMENTALS OF LOGARITHMIC CONVERSION
The conversion of a signal to its equivalent logarithmic value in-
volves a nonlinear operation, the consequences of which can be
very confusing if not fully understood. It is important to realize
from the outset that many of the familiar concepts of linear cir-
cuits are of little relevance in this context. For example, the in-
cremental gain of an ideal logarithmic converter approaches
infinity as the input approaches zero. Further, an offset at the
output of a linear amplifier is simply equivalent to an offset at the
input, while in a logarithmic converter it is equivalent to a
change of amplitude at the input—a very different relationship.
We assume a dc signal in the following discussion to simplify the
concepts; ac behavior and the effect of input waveform on cali-
bration are discussed later. A logarithmic converter having a volt-
age input V
IN
and output V
OUT
must satisfy a transfer function of
the form
V
OUT
= V
Y
LOG (V
IN
/V
X
)Equation (1)
where V
Y
and V
X
are fixed voltages which determine the scaling
of the converter. The input is divided by a voltage because the ar-
gument of a logarithm has to be a simple ratio. The logarithm
must be multiplied by a voltage to develop a voltage output.
These operations are not, of course, carried out by explicit com-
putational elements, but are inherent in the behavior of the con-
verter. For stable operation, V
X
and V
Y
must be based on sound
design criteria and rendered stable over wide temperature and
supply voltage extremes. This aspect of RF logarithmic amplifier
design has traditionally received little attention.
When V
IN
= V
X
, the logarithm is zero. V
X
is, therefore, called the
Intercept Voltage, because a graph of V
OUT
versus LOG (V
IN
)—
ideally a straight line—crosses the horizontal axis at this point
(see Figure 20). For the AD641, V
X
is calibrated to exactly
1 mV. The slope of the line is directly proportional to V
Y
. Base
10 logarithms are used in this context to simplify the relationship
to decibel values. For V
IN
= 10 V
X
, the logarithm has a value of
1, so the output voltage is V
Y.
At V
IN
= 100 V
X
, the output is
2V
Y
, and so on. V
Y
can therefore be viewed either as the Slope
Voltage or as the Volts per Decade Factor.
The AD641 conforms to Equation (1) except that its two outputs
are in the form of currents, rather than voltages:
I
OUT
= I
Y
LOG (V
IN
/V
X
)Equation (2)
ACTUAL
0
INPUT ON
LOG SCALE
Y
Y
2V
Y
IDEAL
V
Y
LOG (V
IN
/V
X
)
V
IN
= V
X
V
IN
= 100V
X
V
IN
= 10V
X
ACTUAL
SLOPE = V
Y
IDEAL
+
–
Figure 20. Basic DC Transfer Function of the AD641
I
Y
, the Slope Current, is 1 mA. The current output can readily
be converted to a voltage with a slope of 1 V/decade, for ex-
ample, using one of the 1 kΩ resistors provided for this purpose,
in conjunction with an op amp, as shown in Figure 21.
9
12
8
13
7
14
6
15
10
11
LOG
OUT LOG
COM SIG
+OUT
+V
S
–V
S
ITC BL2 SIG
–OUT
AD641
CI
330pF
1mA PER DECADE
AD846
R1
48.7Ω
R2
OUTPUT VOLTAGE
1V PER DECADE
FOR R2 = 1kΩ
100mV PER dB
FOR R2 = 2kΩ
Figure 21. Using an External Op Amp to Convert the
AD641 Output Current to a Buffered Voltage Output
Intercept Stabilization
Internally, the intercept voltage is a fraction of the thermal volt-
age kT/q, that is, V
X
= V
XO
T/T
O
, where V
XO
is the value of V
X
at a reference temperature T
O
. So the uncorrected transfer func-
tion has the form:
I
OUT
= I
Y
LOG (V
IN
T
O
/V
XO
T) Equation (3)
Now, if the amplitude of the signal input V
IN
could somehow be
rendered PTAT, the intercept would be stable with tempera-
ture, since the temperature dependence in both the numerator
and denominator of the logarithmic argument would cancel.
This is what is actually achieved by interposing the on-chip at-
tenuator, which has the necessary temperature dependence to
cause the input to the first stage to vary in proportion to abso-
lute temperature. The end limits of the dynamic range are now
totally independent of temperature. Consequently, this is the pre-
ferred method of intercept stabilization for applications where
the input signal is sufficiently large.
When the attenuator is not used, the PTAT variation in V
X
will
result in the intercept being temperature dependent. Near 300K
(27°C) it will vary by 20 LOG (301/300) dB/°C, about 0.03 dB/
°C. Unless corrected, the whole output function would drift up
or down by this amount with changes in temperature. In the
AD641 a temperature compensating current I
Y
LOG(T/T
O
) is
added to the output. This effectively maintains a constant inter-
cept V
XO
. This correction is active in the default state (Pin 8
open circuited). When using the attenuator, Pin 8 should be
grounded, which disables the compensation current. The drift
term needs to be compensated only once; when the outputs of
two AD641s are summed, Pin 8 should be grounded on at least
one of the two devices (both if the attenuator is used).
Conversion Range
Practical logarithmic converters have an upper and lower limit
on the input, beyond which errors increase rapidly. The upper
limit occurs when the first stage in the chain is driven into limit-
ing. Above this, no further increase in the output can occur and
the transfer function flattens off. The lower limit arises because
a finite number of stages provide finite gain, and therefore at
low signal levels the system becomes a simple linear amplifier.
AD641
REV. A –9–
Note that this lower limit is not determined by the intercept volt-
age, V
X
; it can occur either above or below V
X
, depending on
the design. When using two AD641s in cascade, input offset
voltage and wideband noise are the major limitations to low
level accuracy. Offset can be eliminated in various ways. Noise
can only be reduced by lowering the system bandwidth, using a
filter between the two devices.
EFFECT OF WAVEFORM ON INTERCEPT
The absolute value response of the AD641 allows inputs of
either polarity to be accepted. Thus, the logarithmic output in
response to an amplitude-symmetric square wave is a steady
value. For a sinusoidal input the fluctuating output current will
usually be low-pass filtered to extract the baseband signal. The
unfiltered output is at twice the carrier frequency, simplifying the
design of this filter when the video bandwidth must be maxi-
mized. The averaged output depends on waveform in a roughly
analogous way to waveform dependence of rms value. The effect
is to change the apparent intercept voltage. The intercept volt-
age appears to be doubled for a sinusoidal input, that is, the av-
eraged output in response to a sine wave of amplitude (not rms
value) of 20 mV would be the same as for a dc or square wave
input of 10 mV. Other waveforms will result in different inter-
cept factors. An amplitude-symmetric-rectangular waveform has
the same intercept as a dc input, while the average of a base-
band unipolar pulse can be determined by multiplying the
response to a dc input of the same amplitude by the duty cycle.
It is important to understand that in responding to pulsed RF
signals it is the waveform of the carrier (usually sinusoidal) not
the modulation envelope, that determines the effective intercept
voltage. Table I shows the effective intercept and resulting deci-
bel offset for commonly occurring waveforms. The input wave-
form does not affect the slope of the transfer function. Figure 22
shows the absolute deviation from the ideal response of cascaded
AD641s for three common waveforms at input levels from
–80 dBV to –10 dBV. The measured sine wave and triwave
responses are 6 dB and 8.7 dB, respectively, below the square
wave response—in agreement with theory.
Table I.
Input Peak Intercept Error (Relative
Waveform or rms Factor to a DC Input)
Square Wave Either 1 0.00 dB
Sine Wave Peak 2 –6.02 dB
Sine Wave rms 1.414 (√2) –3.01 dB
Triwave Peak 2.718 (e) –8.68 dB
Triwave rms 1.569 (e/√3) –3.91 dB
Gaussian Noise rms 1.887 –5.52 dB
Logarithmic Conformance and Waveform
The waveform also affects the ripple, or periodic deviation from
an ideal logarithmic response. The ripple is greatest for dc or
square wave inputs because every value of the input voltage
maps to a single location on the transfer function and thus
traces out the full nonlinearities in the logarithmic response.
2
0
–2
–4
–6
–8
–10 –70 –60 –50 –40 –30 –20 –10–80 INPUT AMPLITUDE IN dB ABOVE 1V, AT 10kHz
SQUARE
WAVE INPUT
SINE WAVE
INPUT
TRIWAVE
INPUT
DEVIATION FROM EXACT LOGARITHMIC
TRANSFER FUNCTION – dB
Figure 22. Deviation from Exact Logarithmic Transfer
Function for Two Cascaded AD641s, Showing Effect of
Waveform on Calibration and Linearity
By contrast, a general time varying signal has a continuum of
values within each cycle of its waveform. The averaged output is
thereby “smoothed” because the periodic deviations away from
the ideal response, as the waveform “sweeps over” the transfer
function, tend to cancel. This smoothing effect is greatest for a
triwave input, as demonstrated in Figure 22.
The accuracy at low signal inputs is also waveform dependent.
The detectors are not perfect absolute value circuits, having a
sharp “corner” near zero; in fact they become parabolic at low
levels and behave as if there were a dead zone. Consequently,
the output tends to be higher than ideal. When there are enough
stages in the system, as when two AD641s are connected in cas-
cade, most detectors will be adequately loaded due to the high
overall gain, but a single AD641 does not have sufficient gain to
maintain high accuracy for low level sine wave or triwave inputs.
Figure 23 shows the absolute deviation from calibration for the
same three waveforms for a single AD641. For inputs between
–10 dBV and –40 dBV the vertical displacement of the traces for
the various waveforms remains in agreement with the predicted
dependence, but significant calibration errors arise at low signal
levels.
4
2
0
–2
–4
–6
–8
–10
–70 INPUT AMPLITUDE IN dB ABOVE 1V, AT 10kHz
–60 –50 –40 –30 –20 –10
–12
DEVIATION FROM EXACT LOGARITHMIC
TRANSFER FUNCTION – dB
SQUARE
WAVE INPUT
SINE WAVE
INPUT
TRIWAVE
INPUT
Figure 23. Deviation from Exact Logarithmic Transfer
Function for a Single AD641, Compare Low Level
Response with That of Figure 22
REV. A
–10–
AD641
SIGNAL MAGNITUDE
The AD641 is a calibrated device. It is, therefore, important to
be clear in specifying the signal magnitude under all waveform
conditions. For dc or square wave inputs there is, of course, no
ambiguity. Bounded periodic signals, such as sinusoids and
triwaves, can be specified in terms of their simple amplitude
(peak value) or alternatively by their rms value (which is a mea-
sure of power when the impedance is specified). It is generally bet-
ter to define this type of signal in terms of its amplitude because
the AD641 response is a consequence of the input voltage, not
power. However, provided that the appropriate value of inter-
cept for a specific waveform is observed, rms measures may be
used. Random waveforms can only be specified in terms of rms
value because their peak value may be unbounded, as is the case
for Gaussian noise. These must be treated on a case-by-case
basis. The effective intercept given in Table I should be used for
Gaussian noise inputs.
On the other hand, for bounded signals the amplitude can be
expressed either in volts or dBV (decibels relative to 1V). For
example, a sine wave or triwave of 1 mV amplitude can also be
defined as an input of –60 dBV, one of 100 mV amplitude as
–20 dBV, and so on. RMS value is usually expressed in dBm
(decibels above 1 mW) for a specified impedance level. Through-
out this data sheet we assume a 50
Ω
environment, the customary im-
pedance level for high speed systems, when referring to signal powers
in dBm. Bearing in mind the above discussion of the effect of
waveform on the intercept calibration of the AD641, it will be
apparent that a sine wave at a power of, say, –10dBm will not
produce the same output as a triwave or square wave of the
same power. Thus, a sine wave at a power level of –10dBm has
an rms value of 70.7 mV or an amplitude of 100 mV (that is, √2
times as large, the ratio of amplitude to rms value for a sine
wave), while a triwave of the same power has an amplitude
which is √3 or 1.73 times its rms value, or 122.5mV.
“Intercept” and “Logarithmic Offset”
If the signals are expressed in dBV, we can write the output cur-
rent in a simpler form, as:
I
OUT
= 50
µ
A (Input
dBV
– X
dBV
)Equation (4)
where Input
dBV
is the input voltage amplitude (not rms) in dBV
and X
dBV
is the appropriate value of the intercept (for a given
waveform) in dBV. This form shows more clearly why the inter-
cept is often referred to as the logarithmic offset. For dc or square
wave inputs, V
X
is 1 mV so the numerical value of X
dBV
is –60,
and Equation (4) becomes
I
OUT
= 50
µ
A (Input
dBV
+ 60) Equation (5)
Alternatively, for a sinusoidal input measured in dBm (power in
dB above 1 mW in a 50 Ω system) the output can be written
I
OUT
= 50
µ
A (Input
dBm
+ 44) Equation (6)
because the intercept for a sine wave expressed in volts rms is at
1.414 mV (from Table I) or –44 dBm.
OPERATION OF A SINGLE AD641
Figure 24 shows the basic connections for a single device, using
100 Ω load resistors. Output A is a negative going voltage with a
slope of –100 mV per decade; output B is positive going with a
slope of +100 mV per decade. For applications where absolute
calibration of the intercept is essential, the main output (from
LOG OUT, Pin 14) should be used; the LOG COM output can
then be grounded. To evaluate the demodulation response, a
simple low pass output filter having a time constant of roughly
500 µs (3 dB corner of 320 Hz) is provided by a 4.7 µF (–20%
+80%) ceramic capacitor (Erie type RPE117-Z5U-475-K50V)
placed across the load. A DVM may be used to measure the
averaged output in verification tests. The voltage compliance at
Pins 13 and 14 extends from 0.3 V below ground up to 1 V
below +V
S
. Since the current into Pin 14 is from –0.2mA at
zero signal to +2.3 mA when fully limited (dc input of
>300 mV) the output never drops below –230 mV. On the other
hand, the current out of Pin 13 ranges from –0.2mA to
+2.3 mA, and if desired, a load resistor of up to 2 kΩ can be
used on this output; the slope would then be 2V per decade.
Use of the LOG COM output in this way provides a numeri-
cally correct decibel reading on a DVM (+100mV = +1.00 dB).
Board layout is very important. The AD641 has both high gain
and wide bandwidth; therefore every signal path must be very
carefully considered. A high quality ground plane is essential,
but it should not be assumed that it behaves as an equipotential
plane. Even though the application may only call for modest
bandwidth, each of the three differential signal interface pairs
(SIG IN, Pins l and 20, SIG OUT, Pins 10 and 11, and LOG,
Pins 13 and 14) must have their own “starred” ground points to
avoid oscillation at low signal levels (where the gain is highest).
OUTPUT A
10Ω
11
DENOTES A SHORT, DIRECT CONNECTION
TO THE GROUND PLANE.
16181920 17
9
87
610
53214
LOG
OUT LOG
COM SIG
+OUT
RG2
–V
S
SIG
–OUT
AD641
RG0RG1CKT
COM
ATN
OUT
SIG
+IN +V
S
ITCBL1
ATN
IN
ATN
COM
ATN
COM
ATN
LO
SIG
–IN BL2
1k 1k
NC NC
4.7Ω–5V
NC
ALL UNMARKED CAPACITORS ARE
0.1µF CERAMIC (SEE TEXT). OUTPUT B
4.7µ
R
LA
100Ω
0.1%
R
LB
+5V
OPTIONAL
OFFSET BALANCE
RESISTOR
OPTIONAL
TERMINATION
RESISTOR
SIGNAL
INPUT
12
1314
15
4.7µ 100Ω
0.1%
Figure 24. Connections for a Single AD641 to Verify Basic Performance
AD641
REV. A –11–
Unused pins (excluding Pins 8, 10 and 11) such as the attenua-
tor and applications resistors should be grounded close to the
package edge. BL1 (Pin 6) and BL2 (Pin 9) are internal bias
lines a volt or two above the –V
S
node; access is provided solely
for the addition of decoupling capacitors, which should be con-
nected exactly as shown (not all of them connect to the ground).
Use low impedance ceramic 0.1 µF capacitors (for example,
Erie RPE113-Z5U-105-K50V). Ferrite beads may be used in-
stead of supply decoupling resistors in cases where the supply
voltage is low.
Active Current-to-Voltage Conversion
The compliance at LOG OUT limits the available output volt-
age swing. The output of the AD641 may be converted to a
larger, buffered output voltage by the addition of an operational
amplifier connected as a current-to-voltage (transresistance)
stage, as shown in Figure 21. Using a 2kΩ feedback resistor
(R2) the 50 µA/dB output at LOG OUT is converted to a volt-
age having a slope of +100 mV/dB, that is, 2 V per decade.
This output ranges from roughly –0.4 V for zero signal inputs
to the AD641, crosses zero at a dc input of precisely +1 mV
(or –1 mV) and is +4 V for a dc input of 100 mV. A passive
prefilter, formed by R1 and C1, minimizes the high frequency
energy conveyed to the op amp. The corner frequency is here
shown as 10 MHz. The AD846 is recommended for this appli-
cation because of its excellent performance in transresistance
modes. Its bandwidth of 35 MHz (with the 2 kΩ feedback resis-
tor) will exceed the baseband response of the system in most ap-
plications. For lower bandwidth applications other op amps and
multipole active filters may be substituted.
Effect of Frequency on Calibration
The slope and intercept of the AD641 are calibrated during
manufacture using a 2 kHz square wave input. Calibration
depends on the gain of each stage being 10 dB. When the input
frequency is an appreciable fraction of the 350 MHz bandwidth
of the amplifier stages, their gain becomes less precise and the
logarithmic slope and intercept are no longer as calibrated. Fig-
ure 10 shows the averaged output current versus input level at
50 MHz, 150 MHz, 190 MHz, 210 MHz, and 250 MHz. Fig-
ure 11 shows the absolute error in the response at 200 MHz
and at temperatures of –55°C, +25°C and +125°C. Figure 12
shows the variation in the slope current, and Figure 13 shows
the variation in the intercept level (sinusoidal input) versus
frequency.
If absolute calibration is essential, or some other value of slope
or intercept is required, there will usually be some point in the
user’s system at which an adjustment may be easily introduced.
For example, the 5% slope deficit at 50 MHz (see Figure 12)
may be restored by a 5% increase in the value of the load resis-
tor in the passive loading scheme shown in Figure 24, or by
inserting a trim potentiometer of 100 Ω in series with the feed-
back resistor in the scheme shown in Figure 21. The intercept
can be adjusted by adding or subtracting a small current to the
output. Since the slope current is 1 mA/decade, a 50 µA incre-
ment will move the intercept by 1 dB. Note that any error in
this current will invalidate the calibration of the AD641. For
example, if one of the 5 V supplies were used with a resistor to
generate the current to reposition the intercept by 20 dB, a
±10% variation in this supply will cause a ±2 dB error in the
absolute calibration. Of course, slope calibration is unaffected.
Source Resistance and Input Offset
The bias currents at the signal inputs (Pins 1 and 20) are typi-
cally 7 µA. These flow in the source resistances and generate
input offset voltages which may limit the dynamic range because
the AD641 is direct coupled and an offset is indistinguishable
from a signal. It is good practice to keep the source resistances
as low as possible and to equalize the resistance seen at each
input. For example, if the source resistance to Pin 20 is 100 Ω, a
compensating resistor of 100 Ω should be placed in series with
Pin 1. The residual offset is then due to the bias current offset,
which is typically under 1 µA, causing an extra offset uncertainty
of 100 µV in this example. For a single AD641 this will rarely be
troublesome, but in some applications it may need to be nulled
out, along with the internal voltage offset component. This may
be achieved by adding an adjustable voltage of up to ±250 µV
at the unused input. (Pins 1 and 20 may be interchanged with
no change in function.)
In most applications there will be no need to use any offset ad-
justment. However, a general offset trimming circuit is shown in
Figure 25. R
S
is the source resistance of the signal. Note: 50
Ω
rf
sources may include a blocking capacitor and have no dc path to
ground, or may be transformer coupled and have a near zero resis-
tance to ground. Determine whether the source resistance is zero,
25 Ω or 50 Ω (with the generator terminated in 50 Ω) to find
the correct value of bias compensating resistor, R
B
, which
should optimally be equal to R
S
, unless R
S
= 0, in which case
use R
B
= 5 Ω. The value of R
OS
should be set to 20,000 RB to
provide a ±250 µV trim range. To null the offset, set the source
voltage to zero and use a DVM to observe the logarithmic out-
put voltage. Recall that the LOG OUT current of the AD641
exhibits an absolute value response to the input voltage, so the off-
set potentiometer is adjusted to the point where the logarithmic
output “turns around” (reaches a local maximum or minimum).
At high frequencies it may be desirable to insert a coupling ca-
pacitor and use a choke between Pin 20 and ground, when Pin 1
should be taken directly to ground. Alternatively, transformer
coupling may be used. In these cases, there is no added offset
due to bias currents. When using two dc coupled AD641s
(overall gain 100,000), it is impractical to maintain a sufficiently
low offset voltage using a manual nulling scheme. The section
CASCADED OPERATION explains how the offset can be
automatically nulled to submicrovolt levels by the use of a nega-
tive feedback network.
Figure 25. Optional Input Offset Voltage Nulling Circuit;
See Text for Component Values
REV. A
–12–
AD641
Using Higher Supply Voltages
The AD641 is calibrated using ±5 V supplies. Scaling is very
insensitive to the supply voltages and higher supply voltages will
not directly cause significant errors. However, the AD641 power
dissipation must be kept below 500 mW in the interest of reli-
ability and long term stability. When using well regulated supply
voltages above ±6 V, the decoupling resistors shown in the ap-
plication schematics can be increased to maintain ±5 V at the
IC. The resistor values are calculated using the specified maxi-
mum of 15 mA current into the +V
S
terminal (Pin 12) and a
maximum of 60 mA into the –V
S
terminal (Pin 7). For example,
when using ±9 V supplies, a resistor of (9 V – 5 V)/15 mA,
about 261 Ω, should be included in the +V
S
lead to each AD641
and (9 V – 5 V)/60 mA, about 64.9 Ω in each –V
S
lead. Of
course, asymmetric supplies may be dealt with in a similar way.
Using the Attenuator
In applications where the signal amplitude is sufficient, the on-
chip attenuator should be used because it provides a tempera-
ture independent dynamic range (compare Figures 18 and 19).
Figure 26 shows this attenuator in more detail. R1 is a thin-film
4
17
3
18
2
19
1
20
5
ATN
COM
16
SIG
–IN
SIG
+IN
ATN
COM
ATN
LO
ATN
IN
R3
R4
R1
R2
ATN
OUT
FIRST
AMPLIFIER
INPUT
Figure 26. Details of the Input Attenuator
resistor of nominally 270 Ω and low temperature coefficient
(TC). It is trimmed to calibrate the intercept to 10mV dc (or
–24 dBm for sinusoidal inputs), that is, to an attenuation of
nominally 20 dBs at 27°C. R2 has a nominal value of 30Ω and
has a high positive TC, such that the overall attenuation factor
is 0.33%/°C at 27°C. This results in a transmission factor that is
proportional to absolute temperature, or PTAT. (See Intercept
Stabilization for further explanation.) To improve the accuracy
of the attenuator, the ATN COM nodes are bonded to both Pin
3 and Pin 4. These should be connected directly to the “SlGNAL
LOW” of the source (for example, to the grounded side of the
signal connector, as shown in Figure 32) not to an arbitrary
point on the ground plane.
R4 is identical to R2, and in shunt with R3 (270Ω thin film)
forms a 27 Ω resistor with the same TC as the output resistance
of the attenuator. By connecting Pin 1 to ATN LOW (Pin 2)
this resistance minimizes the offset caused by bias currents. The
offset nulling scheme shown in Figure 25 may still be used, with
the external resistor R
B
omitted and R
OS
= 500 kΩ. Offset stabil-
ity is improved because the compensating voltage introduced at
Pin 20 is now PTAT. Drifts of under 1µV/°C (referred to Pins
1 and 20) can be maintained using the attenuator.
It may occasionally be desirable to attenuate the signal even fur-
ther. For example, the source may have a full-scale value of
±10 V, and since the basic range of the AD641 extends only to
±200 mV dc, an attenuation factor of ×50 might be chosen.
This may be achieved either by using an independent external
attenuator or more simply by adding a resistor in series with
ATN IN (Pin 5). In the latter case the resistor must be trimmed
to calibrate the intercept, since the input resistance at Pin 5 is
not guaranteed. A fixed resistor of 1 kΩ in series with a 500 Ω
variable resistor calibrate to an intercept of 50 mV (or –26dBV)
for dc or square wave inputs and provide a ±10 V input range.
The intercept stability will be degraded to about 0.003dB/°C.
NC
DENOTES A CONNECTION TO THE
GROUND PLANE; OBSERVE COMMON
CONNECTIONS WHERE SHOWN.
ALL UNMARKED CAPACITORS ARE
0.1µF CERAMIC. FOR VALUES OF
NUMBERED COMPONENTS SEE TEXT 10Ω
NC
NC
R1
R2
SIGNAL
INPUT C1 C2
4.7Ω
4.7Ω
–5V
+5V
10Ω
1mA/DECADE OUTPUT
–50mV/DECADE
C3 R
L
= 50Ω
10Ω10Ω
9
87
610
53214
12
1314
15 11
16181920 17 LOG
OUT LOG
COM SIG
+OUT
RG2
–V
S
SIG
–OUT
RG0RG1CKT
COM
ATN
OUT
SIG
+IN +V
S
ITCBL1
ATN
IN
ATN
COM
ATN
COM
ATN
LO
SIG
–IN BL2
1k 1k
U1 AD641
9
87
610
53214
12
1314
15 11
16181920 17 LOG
OUT LOG
COM SIG
+OUT
RG2
–V
S
SIG
–OUT
RG0RG1CKT
COM
ATN
OUT
SIG
+IN +V
S
ITCBL1
ATN
IN
ATN
COM
ATN
COM
ATN
LO
SIG
–IN BL2
1k 1k
U2 AD641
Figure 27. Basic Connections for Cascaded AD641s
AD641
REV. A –13–
OPERATION OF CASCADED AD641S
Frequently, the dynamic range of the input will be 50 dB or
more. Two AD641s can be cascaded, as shown in Figure 27.
The balanced signal output from U1 becomes the input to U2.
Resistors are included in series with each LOG OUT pin and
capacitors C1 and C2 are placed directly between Pins 13 and 14
to provide a local path for the RF current at these output pairs.
C1 through C3 are chosen to provide the required low pass cor-
ner in conjunction with the load R
L
. Board layout and ground-
ing disciplines are critically important at the high gain (X100,000)
and bandwidth (~ 150 MHz) of this system.
The intercept voltage is calculated as follows. First, note that if
its LOG OUT is disconnected, U1 simply inserts 50 dB of gain
ahead of U2. This would lower the intercept by 50 dB, to
–110 dBV for square wave calibration. With the LOG OUT of
U1 added in, there is a finite zero signal current which slightly
shifts the intercept. With the intercept temperature compensa-
tion on U1 disabled this zero signal output is –270µA equiva-
lent to a 5.4 dB upward shift in the intercept, since the slope is
50 µA/dB. Thus, the intercept is at –104.6 dBV (–88 dBm for
50 Ω sine calibration). ITC may be disabled by grounding Pin 8
of either U1 or U2.
Cascaded AD641s can be used in dc applications, but input off-
set voltage will limit the dynamic range. The dc intercept is
6µV. The offset should not be confused with the intercept, which is
found by extrapolating the transfer function from its central “log
linear” region. This can be understood by referring to Equation
(1) and noting that an input offset is simply additive to the value
of V
IN
in the numerator of the logarithmic argument; it does not
affect the denominator (or intercept) V
X
. In dc coupled applica-
tions of wide dynamic range, special precautions must be taken
to null the input offset and minimize drift due to input bias off-
set. It is recommended that the input attenuator be used, pro-
viding a practical input range of –74 dBV (±200 µV dc) to
+6 dBV (±2 V dc) when nulled using the adjustment circuit
shown in Figure 25.
1920
21
U2
12 11
910
U1
1920
21
U2
12 11
910
U1
(a)
(b)
Figure 28. Two Methods for AC Coupling AD641s
Eliminating the Effect of First Stage Offset
Usually, the input signal will be sinusoidal and U1 and U2 can
be ac coupled. Figure 28a shows a low resistance choke at the
input of U2 which shorts the dc output of U1 while preserving
the hf response. Coupling capacitors may be inserted (Figure
28b) in which case two chokes are used to provide bias paths for
U2. These chokes must exhibit high impedance over the operat-
ing frequency range.
Alternatively, the input offset can be nulled by a negative feed-
back network from the SIG OUT nodes of U2 to the SIG IN
nodes of U1, as shown in Figure 29. The low pass response of
the feedback path transforms to a closed-loop high pass
response. The high gain (×100,000) of the signal path results in
a commensurate reduction in the effective time constant of this
network. For example, to achieve a high pass corner of 100kHz,
the low pass corner must be at 1 Hz.
In fact, it is somewhat more complicated than this. When the ac
input sufficiently exceeds that of the offset, the feedback be-
comes ineffective and the response becomes essentially dc
coupled. Even for quite modest inputs the last stage will be lim-
iting and the output (Pins 10 and 11) of U2 will be a square
wave of about ±180 mV amplitude, dwelling approximately
equal times at its two limit values, and thus having a net average
value near zero. Only when the input is very small does the high
pass behavior of this nulling loop become apparent. Consequently,
the low pass time constant can usually be reduced considerably
without serious performance degradation.
The resistor values are chosen such that the dc feedback is
adequate to null the worst case input offset, say, 500 µV. There
must be some resistance at Pins 1 and 20 across which the offset
compensation voltage is developed. The values shown in the fig-
ure assume that we wish to terminate a 50Ω source at Pin 20.
The 50 Ω resistor at Pin 1 is essential, both to minimize offsets
due to bias current mismatch and because the outputs at Pins
10 and 11 can only swing negatively (from ground to –180mV)
whereas we need to cater for input offsets of either polarity.
For a sine input of 1 µV amplitude (–120 dBV) and in the ab-
sence of offset, the differential voltage at Pins 10 and 11 of U2
would be almost sinusoidal but 100,000 times larger, or
100 mV. The last limiter in U2 would be entering saturation. A
1µV input offset added to this signal would put the last limiter
well into saturation, and its output would then have a different
average value, which is extracted by the low pass network and
delivered back to the input. For larger signals, the output
approaches a square wave for zero input offset and becomes
rectangular when offset is present. The duty cycle modulation of
this output now produces the nonzero average value. Assume a
maximum required differential output of 100 mV (after averag-
ing in C1 and C2) as shown in Figure 29. R3 through R6 can
now be chosen to provide ±500 µV of correction range, and with
these values the input offset is reduced by a factor of 500. Using
4.7 µF capacitors, the time constant of the network is about
1.2 ms, and its corner frequency is at 13.5 Hz. The closed loop
high pass corner (for small signals) is, therefore, at 1.35 MHz.
20
110
11
U1
A
VE
= –140mV
INPUT
20
110
11
U2
R1
50Ω
R2
50Ω
C1
C2
A
VE
= –140mV
R3
4.99k
R5
4.99k
–200µV
–700µV
4µA
14µA
R4
4.99k
R6
4.99k
Figure 29. Feedback Offset Correction Network
REV. A
–14–
AD641
RSSI APPLICATIONS
The AD641 can be used to perform an RSSI (Received Signal
Strength Indicator) function. This is a commonly used function
in radio receivers, but can be used in other instrumentation such
as photomultiplier tubes. The signal strength indicator on FM
radios is one example of an RSSI application. It is this signal
that is monitored to determine where to stop during seek or
scan operations.
The AD641 is used to measure the strength of the incoming RF
signal and outputs a current that is proportional to the loga-
rithm of its ac amplitude. In this manner signal amplitudes with
a wide dynamic range and wide bandwidth can be measured.
250 MHz RSSI Converter with 44 dB Dynamic Range
Figure 30 shows the schematic for an RSSI circuit that uses a
single AD641. The dynamic range for this circuit using a single
AD641 is 44 dB. The AD641 amplifies and full wave rectifies
(detects) the input and outputs a current. The AD846 is used to
convert the current to a ground referenced voltage. With a 1kΩ
feedback resistor, the output varies by 1 V/decade or 50 mV/dB.
PRACTICAL APPLICATIONS
We show here two applications, using AD641s to achieve a wide
dynamic range. As already mentioned, the use of a differential
signal path and differential logarithmic outputs diminishes the
risk of instability due to poor grounding. Nevertheless, it must
be remembered that at high frequencies even very small lengths
of wire, including the leads to capacitors, have significant im-
pedance. The ground plane itself can also generate small but
troublesome voltages due to circulating currents in a poor lay-
out. A printed circuit evaluation board is available from Analog
Devices (Part Number AD641-EB) to facilitate the prototyping
of an application using one or two AD641s, plus various exter-
nal components.
At very low signal levels various effects can cause significant
deviation from the ideal response, apart from the inherent
nonlinearities of the transfer function already discussed. Note
that any spurious signal presented to the AD641s is demodulated and
added to the output. Thus, in the absence of thorough shielding,
emissions from any radio transmitters or RFI from equipment
operating in the locality will cause the output to appear too
high. The only cure for this type of error is the use of very care-
ful grounding and shielding techniques.
6
7
4
3
–6V
4.7Ω
U3
AD846
RSSI
OUTPUT
+50mV/dB
(LO)
+6V
2
C1
47pF
4.7Ω
NC
DENOTES A CONNECTION TO THE
GROUND PLANE; OBSERVE COMMON
CONNECTIONS WHERE SHOWN.
ALL UNMARKED CAPACITORS ARE
0.1µF CERAMIC. FOR VALUES OF
NUMBERED COMPONENTS SEE TEXT.
R1
R2
SIGNAL
INPUT
18Ω
68Ω
1.0kΩ
9
87
610
53214
12
1314
15 11
16181920 17
LOG
OUT LOG
COM SIG
+OUT
RG2
–V
S
SIG
–OUT
RG0RG1CKT
COM
ATN
OUT
SIG
+IN +V
S
ITC
BL1
ATN
IN
ATN
COM
ATN
COM
ATN
LO
SIG
–IN BL2
1k 1k
U1 AD641
–6V
+6V
R3
100Ω
Figure 30. RSSI Using Single AD641
AD641
REV. A –15–
FREQUENCY – MHz
3
2.5
–0.51 100010 100
2
1.5
1
0.5
0
VOLTS – LOG OUT into 1k
0dBm
–20dBm
–35dBm
–50dBm
Figure 31. Single AD641 RSSI vs. Frequency
Figure 31 shows a plot of RSSI vs. frequency for various input
signal amplitudes. It can be seen that at higher frequencies the
output drops off as explained in the section “Effect of Fre-
quency on Calibration.’’ If the RSSI circuit is to be operated at
a known frequency with limited bandwidth, the compensation
techniques described in that section can be used to enhance
accuracy.
250 MHz RSSI Converter with 58 dB Dynamic Range
For a larger dynamic range two AD641s can be cascaded, as
shown in Figure 32. The low end usefulness of the circuit will
be set by the noise floor of the overall environment that the cir-
cuit sees. This includes all sources of both radiated and con-
ducted noise. Proper layout to avoid conducted noise and good
shielding to minimize radiated noise are essential for good low
signal operation.
FREQUENCY – MHz
4.5
3.5
01 100010 100
2
2.5
1
1.5
0.5
VOLTS – LOG OUT into 1k
0dBm
–20dBm
–50dBm
–80dBm
4
3
Figure 33. Cascaded AD641s RSSI vs. Frequency
Filtering between the devices and input offset nulling techniques
described elsewhere are also useful for extending the dynamic
range of two cascaded devices.
Figure 33 shows a plot of this circuit vs. frequency for various
input amplitudes. The drop off at high frequency can be seen to
be greater than for the single device case due to the compound-
ing effects of the bandwidth limiting of the extra stages.
6
7
4
3
U3
AD846
2
–6V
4.7Ω
LOG
OUTPUT
+50mV/dB
(LO)
+6V
4.7Ω
L1
(SEE
TEXT)
(SEE TEXT)
R5
1.13kΩ
C2
47pF
C1
47pF
+6V 68ΩR4
100Ω
–6V
18Ω
18Ω
NC
DENOTES A CONNECTION TO THE
GROUND PLANE; OBSERVE COMMON
CONNECTIONS WHERE SHOWN.
ALL UNMARKED CAPACITORS ARE
0.1µF CERAMIC. FOR VALUES OF
NUMBERED COMPONENTS SEE TEXT
R3
100Ω
NC
NC
R1
R2
SIGNAL
INPUT
9
87
610
53214
12
1314
15 11
16181920 17
LOG
OUT LOG
COM SIG
+OUT
RG2
–V
S
SIG
–OUT
RG0RG1CKT
COM
ATN
OUT
SIG
+IN +V
S
ITC
BL1
ATN
IN
ATN
COM
ATN
COM
ATN
LO
SIG
–IN BL2
1k 1k
U1 AD641
9
87
610
53214
12
1314
15 11
16181920 17 LOG
OUT LOG
COM SIG
+OUT
RG2
–V
S
SIG
–OUT
RG0RG1CKT
COM
ATN
OUT
SIG
+IN +V
S
ITCBL1
ATN
IN
ATN
COM
ATN
COM
ATN
LO
SIG
–IN BL2
1k 1k
U2 AD641
68Ω
Figure 32. Complete 58 dB Dynamic Range Converter for 250 MHz Operation
REV. A
–16–
AD641
PRINTED IN U.S.A. C2014–6–4/95
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Pin Cerdip
(Q-20)
20
110
11
0.310 (7.87)
0.220 (5.56)
PIN 1
0.005 (0.13) MIN 0.098 (2.49) MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
MAX
1.280 (32.51) MAX
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18) 0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
20-Pin Plastic DIP
(N-20)
20
110
11
1.060 (26.90)
0.925 (23.50)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX 0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
20-Lead PLCC
(P-20A)
3PIN 1
IDENTIFIER
41918
8914
13
TOP VIEW
(PINS DOWN)
0.395 (10.02)
0.385 (9.78) SQ
0.356 (9.04)
0.350 (8.89)SQ
0.048 (1.21)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
0.050
(1.27)
BSC
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.290 (7.37)
0.032 (0.81)
0.026 (0.66)
0.180 (4.57)
0.165 (4.19)
0.040 (1.01)
0.025 (0.64)
0.056 (1.42)
0.042 (1.07) 0.025 (0.63)
0.015 (0.38)
0.110 (2.79)
0.085 (2.16)