PCF8563 Real time clock/calendar Rev. 04 -- 12 March 2004 Product data 1. General description The PCF8563 is a CMOS real time clock/calendar optimized for low power consumption. A programmable clock output, interrupt output and voltage-low detector are also provided. All address and data are transferred serially via a two-line bidirectional I2C-bus. Maximum bus speed is 400 kbit/s. The built-in word address register is incremented automatically after each written or read data byte. 2. Features Provides year, month, day, weekday, hours, minutes and seconds based on 32.768 kHz quartz crystal Century flag Clock operating voltage: 1.8 V to 5.5 V Low backup current; typical 0.25 A at VDD = 3.0 V and Tamb = 25 C 400 kHz two-wire I2C-bus interface (at VDD = 1.8 V to 5.5 V) Programmable clock output for peripheral devices (32.768 kHz, 1024 Hz, 32 Hz and 1 Hz) Alarm and timer functions Integrated oscillator capacitor Internal power-on reset I2C-bus slave address: read A3H and write A2H Open-drain interrupt pin. 3. Applications Mobile telephones Portable instruments Fax machines Battery powered products. PCF8563 Philips Semiconductors Real time clock/calendar 4. Quick reference data Table 1: Quick reference data Symbol Parameter supply voltage VDD Conditions Min Typ Max Unit 1.0 - 5.5 V active; fSCL = 400 kHz; operating; Tamb = -40 C to +125 C 1.8 - 5.5 V timer and clock output disabled; fSCL = 400 kHz - - 800 A timer and clock output disabled; fSCL = 100 kHz - - 200 A VDD = 5 V - - 550 nA VDD = 2 V - - 450 nA -40 - +85 C -65 - +150 C operating; I2C-bus inactive; Tamb = 25 C I2C-bus IDD supply current timer and clock output disabled; fSCL = 0 Hz; Tamb = 25 C Tamb ambient temperature Tstg storage temperature operating 5. Ordering information Table 2: Ordering information Type number Package Name Description Version PCF8563P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 PCF8563T SO8 plastic dual in-line package; 8 leads; body width 3.9 mm SOT96-1 PCF8563TS TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 2 of 30 PCF8563 Philips Semiconductors Real time clock/calendar 6. Block diagram CLKOUT 7 OSCI OSCO 1 CONTROL/STATUS 1 0 CONTROL/STATUS 2 1 SECONDS/VL 2 3 MINUTES 3 4 HOURS 4 DAYS 5 WEEKDAYS 6 MONTHS/CENTURY 7 YEARS 8 2 OSCILLATOR 32.768 kHz 1 Hz DIVIDER INT VSS VDD 8 VOLTAGE DETECTOR OSCILLATOR MONITOR SCL SDA CONTROL LOGIC POR 6 5 I2C-BUS INTERFACE ADDRESS REGISTER PCF8563 MINUTE ALARM 9 HOUR ALARM A DAY ALARM B WEEKDAY ALARM C CLKOUT CONTROL D TIMER CONTROL E TIMER F MGM662 Fig 1. Block diagram. 7. Pinning information 7.1 Pinning 8 VDD OSCI 1 OSCO 2 7 CLKOUT 8 VDD OSCI 1 OSCO 2 PCF8563P 7 CLKOUT 8 VDD OSCI 1 OSCO 2 PCF8563T 7 CLKOUT PCF8563TS INT 3 6 SCL INT 3 6 SCL INT 3 6 SCL VSS 4 5 SDA VSS 4 5 SDA VSS 4 5 SDA MCE403 Fig 2. Pin configuration DIP8. MCE198 Fig 3. Pin configuration SO8. Fig 4. Pin configuration TSSOP8. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data MCE199 Rev. 04 -- 12 March 2004 3 of 30 PCF8563 Philips Semiconductors Real time clock/calendar handbook, halfpage OSCI OSCO INT VSS 1 8 2 7 3 6 4 5 VDD CLKOUT SCL SDA PCF8563 MGR886 Fig 5. Device diode protection diagram. 7.2 Pin description Table 3: Pin description Symbol Pin Description OSCI 1 oscillator input OSCO 2 oscillator output INT 3 interrupt output (open-drain; active LOW) VSS 4 ground SDA 5 serial data input and output SCL 6 serial clock input CLKOUT 7 clock output, open-drain VDD 8 positive supply voltage 8. Functional description The PCF8563 contains sixteen 8-bit registers with an auto-incrementing address register, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the Real Time Clock/calender (RTC), a programmable clock output, a timer, an alarm, a voltage-low detector and a 400 kHz I2C-bus interface. All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers (memory address 00H and 01H) are used as control and/or status registers. The memory addresses 02H through 08H are used as counters for the clock function (seconds up to years counters). Address locations 09H through 0CH contain alarm registers which define the conditions for an alarm. Address 0DH controls the CLKOUT output frequency. 0EH and 0FH are the timer control and timer registers, respectively. The seconds, minutes, hours, days, weekdays, months, years as well as the minute alarm, hour alarm, day alarm and weekday alarm registers are all coded in BCD format. When one of the RTC registers is read the contents of all counters are frozen. Therefore, faulty reading of the clock/calendar during a carry condition is prevented. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 4 of 30 PCF8563 Philips Semiconductors Real time clock/calendar 8.1 Alarm function modes By clearing the MSB of one or more of the alarm registers (bit AE = alarm enable), the corresponding alarm condition(s) will be active. In this way an alarm can be generated from once per minute up to once per week. The alarm condition sets the Alarm Flag (AF). The asserted AF can be used to generate an interrupt (INT). The AF can only be cleared by software. 8.2 Timer The 8-bit countdown timer at address 0FH is controlled by the timer control register at address 0EH. The timer control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or 160 Hz), and enables or disables the timer. The timer counts down from a software-loaded 8-bit binary value. At the end of every countdown, the timer sets the Timer Flag (TF). The TF may only be cleared by software. The asserted TF can be used to generate an interrupt (INT). The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of TF. Bit TI/TP is used to control this mode selection. When reading the timer, the current countdown value is returned. 8.3 Clock output A programmable square wave is available at pin CLKOUT. Operation is controlled by the CLKOUT control register at address 0DH. Frequencies of 32.768 kHz (default), 1024 Hz, 32 Hz and 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes high-impedance. 8.4 Reset The PCF8563 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the I2C-bus logic is initialized and all registers, including the address pointer, are cleared with the exception of bits FE, VL, TD1, TD0, TESTC and AE which are set to logic 1. 8.5 Voltage-low detector The PCF8563 has an on-chip voltage-low detector. When VDD drops below Vlow, bit VL in the seconds register is set to indicate that the integrity of the clock information is no longer guaranteed. The VL flag can only be cleared by software. Bit VL is intended to detect the situation when VDD is decreasing slowly, for example under battery operation. Should VDD reach Vlow before power is re-asserted then bit VL will be set. This will indicate that the time may be corrupted. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 5 of 30 PCF8563 Philips Semiconductors Real time clock/calendar MGR887 handbook, halfpage VDD normal power operation period of battery operation Vlow t VL set Fig 6. Voltage-low detection. 8.6 Register organization Table 4: Binary formatted registers overview Bit positions labelled as x are not implemented. Bit positions labelled with 0 should always be written with logic 0; if read they could be either logic 0 or logic 1. Address Register name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00H control/status 1 TEST1 0 STOP 0 TESTC 0 0 0 01H control/status 2 0 0 0 TI/TP AF TF AIE TIE 0DH CLKOUT control FE x x x x x FD1 FD0 0EH timer control TE x x x x x TD1 TD0 0FH timer <timer countdown value> Table 5: BCD formatted registers overview Bit positions labelled as x are not implemented. Address Register name BCD format tens nibble Bit 7 23 Bit 6 22 Bit 5 21 BCD format units nibble Bit 4 20 Bit 3 23 Bit 2 22 Bit 1 21 02H seconds VL <seconds 00 to 59 coded in BCD> 03H minutes x <minutes 00 to 59 coded in BCD> 04H hours x 05H days x x 06H weekdays x x x 07H months/century C x x 08H years 09H minute alarm AE 0AH hour alarm AE x <hour alarm 00 to 23 coded in BCD> 0BH day alarm AE x <day alarm 01 to 31 coded in BCD> 0CH weekday alarm AE x x <hours 00 to 23 coded in BCD> <days 01 to 31 coded in BCD> x x <weekdays 0 to 6> <months 01 to 12 coded in BCD> <years 00 to 99 coded in BCD> <minute alarm 00 to 59 coded in BCD> x x x <weekday alarm 0 to 6> (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Bit 0 20 Rev. 04 -- 12 March 2004 6 of 30 PCF8563 Philips Semiconductors Real time clock/calendar 8.6.1 Table 6: Control/status 1 register Control/status 1 (address 00H) bits description Bit Symbol 7 TEST1 6 0 5 STOP 4 0 3 TESTC 2 to 0 Value Description 0 normal mode 1 EXT_CLK test mode default value is logic 0 0 RTC source clock runs 1 all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC clock is stopped (CLKOUT at 32.768 kHz is still available) default value is logic 0 0 Power-on reset override facility is disabled; set to logic 0 for normal operation 1 Power-on reset override may be enabled 0 default value is logic 0 8.6.2 Control/status 2 register Bits TF and AF: When an alarm occurs, AF is set to 1. Similarly, at the end of a timer countdown, TF is set to 1. These bits maintain their value until overwritten by software. If both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading these bits. To prevent one flag being overwritten while clearing another a logic AND is performed during a write access. Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when TF or AF is asserted, respectively. The interrupt is the logical OR of these two conditions when both AIE and TIE are set. Table 7: Control/status 2 (address 01H) bits description Bit Symbol 7 to 5 0 4 TI/TP 3 2 1 0 AF TF AIE TIE Value Description default value is logic 0 0 INT is active when TF is active (subject to the status of TIE) 1 INT pulses active according to Table 8 (subject to the status of TIE); note that if AF and AIE are active then INT will be permanently active 0 (read) alarm flag inactive 1 (read) alarm flag active 0 (write) alarm flag is cleared 1 (write) alarm flag remains unchanged 0 (read) timer flag inactive 1 (read) timer flag active 0 (write) timer flag is cleared 1 (write) timer flag remains unchanged 0 alarm interrupt disabled 1 alarm interrupt enabled 0 timer interrupt disabled 1 timer interrupt enabled (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 7 of 30 PCF8563 Philips Semiconductors Real time clock/calendar Table 8: INT operation (bit TI/TP = 1) INT period (s)[1] Source clock (Hz) n = 1[2] n>1 4 096 1 8192 1 4096 64 1 128 1 64 1 1 64 1 64 1 60 1 64 1 64 [1] [2] 8.6.3 Table 9: TF and INT become active simultaneously. n = loaded countdown value. Timer stopped when n = 0. Time and date registers Seconds/VL (address 02H) bits description Bit Symbol Value Description 7 VL 0 clock integrity is guaranteed 1 integrity of the clock information is no longer guaranteed 00 to 59 this register holds the current seconds coded in BCD format; example: seconds register contains x101 1001 = 59 seconds 6 to 0 Table 10: seconds Minutes (address 03H) bits description Bit Symbol Value Description 6 to 0 minutes 00 to 59 this register holds the current minutes coded in BCD format Table 11: Hours (address 04H) bits description Bit Symbol Value Description 5 to 0 hours 00 to 23 this register holds the current hours coded in BCD format Table 12: Days (address 05H) bits description Bit Symbol Value Description 5 to 0 days[1] 01 to 31 this register holds the current day coded in BCD format [1] The PCF8563 compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00. Table 13: Weekdays (address 06H) bits description Bit Symbol Value Description 2 to 0 weekdays[1] 0 to 6 this register holds the current weekday coded in BCD format, see Table 14 [1] These bits may be re-assigned by the user. Table 14: Weekday assignments Day Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sunday x x x x x 0 0 0 Monday x x x x x 0 0 1 Tuesday x x x x x 0 1 0 Wednesday x x x x x 0 1 1 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 8 of 30 PCF8563 Philips Semiconductors Real time clock/calendar Table 14: Table 15: Day Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Thursday x x x x x 1 0 0 Friday x x x x x 1 0 1 Saturday x x x x x 1 1 0 Months/century (address 07H) bits description Bit Symbol 7 century[1] 4 to 0 [1] Weekday assignments...continued month Value Description this bit is toggled when the years register overflows from 99 to 00 0 indicates the century is 20xx 1 indicates the century is 19xx 01 to 12 this register holds the current month coded in BCD format, see Table 16 These bits may be re-assigned by the user. Table 16: Table 17: Month assignments Month Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January C x x 0 0 0 0 1 February C x x 0 0 0 1 0 March C x x 0 0 0 1 1 April C x x 0 0 1 0 0 May C x x 0 0 1 0 1 June C x x 0 0 1 1 0 July C x x 0 0 1 1 1 August C x x 0 1 0 0 0 September C x x 0 1 0 0 1 October C x x 1 0 0 0 0 November C x x 1 0 0 0 1 December C x x 1 0 0 1 0 Years (address 08H) bits description Bit Symbol Value Description 7 to 0 years 00 to 99 this register holds the current year coded in BCD format 8.6.4 Alarm registers When one or more of these registers are loaded with a valid minute, hour, day or weekday and its corresponding bit Alarm Enable (AE) is logic 0, then that information will be compared with the current minute, hour, day and weekday. When all enabled comparisons first match, the Alarm Flag (AF) is set. AF will remain set until cleared by software. Once AF has been cleared it will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their bit AE at logic 1 will be ignored. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 9 of 30 PCF8563 Philips Semiconductors Real time clock/calendar Table 18: Minute alarm (address 09H) bits description Bit Symbol Value Description 7 AE 0 minute alarm is enabled 1 minute alarm is disabled 6 to 0 alarm minutes 00 to 59 this register holds the minute alarm information coded in BCD format Table 19: Hour alarm (address 0AH) bits description Bit Symbol Value Description 7 AE 0 hour alarm is enabled 1 hour alarm is disabled 00 to 23 this register holds the hour alarm information coded in BCD format 5 to 0 Table 20: alarm hours Day alarm (address 0BH) bits description Bit Symbol Value Description 7 AE 0 day alarm is enabled 1 day alarm is disabled 5 to 0 alarm days 01 to 31 this register holds the day alarm information coded in BCD format Table 21: Weekday alarm (address 0CH) bits description Bit Symbol Value Description 7 AE 0 weekday alarm is enabled 1 weekday alarm is disabled 0 to 6 this register holds the weekday alarm information coded in BCD format 2 to 0 alarm weekdays 8.6.5 Table 22: Clock output control register CLKOUT control (address 0DH) bits description Bit Symbol Value Description 7 FE 0 the CLKOUT output is inhibited and CLKOUT output is set to high-impedance 1 the CLKOUT output is activated 1 to 0 FD1 and FD0 these bits control the frequency output at pin CLKOUT; see Table 23 Table 23: 8.6.6 FD1 and FD0: CLKOUT frequency selection FD1 FD0 CLKOUT frequency 0 0 32.768 kHz 0 1 1024 Hz 1 0 32 Hz 1 1 1 Hz Countdown timer The timer register is an 8-bit binary countdown timer. It is enabled and disabled via the timer control register bit TE. The source clock for the timer is also selected by the timer control register. Other timer properties such as interrupt generation are controlled via control/status 2 register. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 10 of 30 PCF8563 Philips Semiconductors Real time clock/calendar For accurate read back of the countdown value, the I2C-bus clock (SCL) must be operating at a frequency of at least twice the selected timer clock. Table 24: Timer control (address 0EH) bits description Bit Symbol Value Description 7 TE 0 timer is disabled 1 timer is enabled 1 to 0 TD1 and TD0 timer source clock frequency select; these bits determine the source clock for the countdown timer, see Table 25; when not in use, TD1 and TD0 should be set to 1 Hz for power saving 60 Table 25: Table 26: TD1 and TD0: Timer frequency selection TD1 TD0 TIMER Source clock frequency 0 0 4096 Hz 0 1 64 Hz 1 0 1 Hz 1 1 1 60 Hz Timer (address 0FH) bits description Bit Symbol Value Description 7 to 0 timer 00 to FF n countdown value = n; CountdownPeriod = --------------------------------------------------------------SourceClockFrequency 8.7 EXT_CLK test mode A test mode is available which allows for on-board testing. In such a mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit TEST1 in control/status1 register. Then pin CLKOUT becomes an input. The test mode replaces the internal 64 Hz signal with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then generate an increment of one second. The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is divided down to 1 Hz by a 26 divide chain called a pre-scaler. The pre-scaler can be set into a known state by using bit STOP. When bit STOP is set, the pre-scaler is reset to 0 (STOP must be cleared before the pre-scaler can operate again). From a STOP condition, the first 1 second increment will take place after 32 positive edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment. Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the pre-scaler can be made. Operation example: 1. Set EXT_CLK test mode (control/status 1, bit TEST1 = 1) 2. Set STOP (control/status 1, bit STOP = 1) (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 11 of 30 PCF8563 Philips Semiconductors Real time clock/calendar 3. Clear STOP (control/status 1, bit STOP = 0) 4. Set time registers to desired value 5. Apply 32 clock pulses to CLKOUT 6. Read time registers to see the first change 7. Apply 64 clock pulses to CLKOUT 8. Read time registers to see the second change. Repeat 7 and 8 for additional increments. 8.8 Power-On Reset (POR) override The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device. The setting of this mode requires that the I2C-bus pins, SDA and SCL, be toggled in a specific order as shown in Figure 7. All timings are required minimums. Once the override mode has been entered, the device immediately stops being reset and normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus access. The override mode may be cleared by writing a logic 0 to TESTC. TESTC must be set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0 during normal operation has no effect except to prevent entry into the POR override mode. 500 ns handbook, full pagewidth 2000 ns SDA SCL 8 ms power up override active MGM664 Fig 7. POR override sequence. 9. Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 9.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 8). (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 12 of 30 PCF8563 Philips Semiconductors Real time clock/calendar SDA SCL data line stable; data valid change of data allowed MBC621 Fig 8. Bit transfer. 9.2 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P); see Figure 9. SDA SDA SCL SCL S P START condition STOP condition MBC622 Fig 9. Definition of start and stop conditions. 9.3 System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Figure 10). SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER / RECEIVER MBA605 Fig 10. System configuration. 9.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 13 of 30 PCF8563 Philips Semiconductors Real time clock/calendar clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig 11. Acknowledgement on the I2C-bus. 9.5 I2C-bus protocol 9.5.1 Addressing Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. The PCF8563 slave address is shown in Figure 12. 1 0 1 group 1 0 0 0 1 R/W group 2 MCE189 Fig 12. Slave address. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 14 of 30 PCF8563 Philips Semiconductors Real time clock/calendar 9.5.2 Clock/calendar read/write cycles The I2C-bus configuration for the different PCF8563 read and write cycles is shown in Figure 13, Figure 14 and Figure 15. The word address is a 4-bit value that defines which register is to be accessed next. The upper four bits of the word address are not used. acknowledgement from slave acknowledgement from slave S SLAVE ADDRESS 0 A WORD ADDRESS A acknowledgement from slave DATA R/W A P n bytes auto increment memory word address MBD822 Fig 13. Master transmits to slave receiver (write mode). acknowledgement from slave acknowledgement from slave S SLAVE ADDRESS 0 A WORD ADDRESS A S acknowledgement from slave SLAVE ADDRESS R/W acknowledgement from master DATA 1 A A n bytes R/W at this moment master transmitter becomes master receiver and PCA8565 slave receiver becomes slave transmitter auto increment memory word address no acknowledgement from master DATA 1 P last byte auto increment memory word address MCE172 Fig 14. Master reads after setting word address (write word address; read data). acknowledgement from master acknowledgement from slave handbook, full pagewidth S SLAVE ADDRESS 1 A R/W DATA A n bytes no acknowledgement from master DATA 1 P last byte auto increment word address auto increment word address MGL665 Fig 15. Master reads slave immediately after first byte (read mode). (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 15 of 30 PCF8563 Philips Semiconductors Real time clock/calendar 10. Limiting values Table 27: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Min Max Unit VDD supply voltage -0.5 +6.5 V IDD supply current -50 +50 mA VI input voltage on pins SCL and SDA -0.5 +6.5 V input voltage on pin OSCI -0.5 VDD + 0.5 V VO output voltage on pins CLOCKOUT and INT -0.5 +6.5 V II DC input current at any input -10 +10 mA IO DC output current at any output -10 +10 mA Ptot total power dissipation - 300 mW Tamb ambient temperature -40 +85 C Tstg storage temperature -65 +150 C 11. Static characteristics Table 28: Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit supply voltage interface inactive; Tamb = 25 C [1] 1.0 - 5.5 V interface active; fSCL = 400 kHz [1] 1.8 - 5.5 V Vlow - 5.5 V - - 800 A - - 200 A VDD = 5.0 V - 275 550 nA VDD = 3.0 V - 250 500 nA - 225 450 nA VDD = 5.0 V - 500 750 nA VDD = 3.0 V - 400 650 nA VDD = 2.0 V - 400 600 nA Supplies VDD VDD(clock) supply voltage for clock data integrity Tamb = 25 C IDD1 supply current 1 interface active fSCL = 400 kHz fSCL = 100 kHz IDD2 supply current 2 interface inactive (fSCL = 0 Hz); CLKOUT disabled; Tamb = 25 C [2] VDD = 2.0 V interface inactive (fSCL = 0 Hz); CLKOUT disabled; Tamb = -40 to +85 C (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data [2] Rev. 04 -- 12 March 2004 16 of 30 PCF8563 Philips Semiconductors Real time clock/calendar Table 28: Static characteristics...continued VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise specified. Symbol IDD3 Parameter supply current 3 Conditions Min Typ Max Unit VDD = 5.0 V - 825 1600 nA VDD = 3.0 V - 550 1000 nA - 425 800 nA VDD = 5.0 V - 950 1700 nA VDD = 3.0 V - 650 1100 nA VDD = 2.0 V - 500 900 nA interface inactive (fSCL = 0 Hz); CLKOUT enabled at 32 kHz; Tamb = 25 C [2] VDD = 2.0 V interface inactive (fSCL = 0 Hz); CLKOUT enabled at 32 kHz; Tamb = -40 to +85 C [2] Inputs VIL LOW-level input voltage VSS - 0.3VDD V VIH HIGH-level input voltage 0.7VDD - VDD V ILI input leakage current -1 0 +1 A - - 7 pF VI = VDD or VSS [3] input capacitance Ci Outputs IOL(SDA) SDA LOW-level output current VOL = 0.4 V; VDD = 5 V -3 - - mA IOL(INT) INT LOW-level output current VOL = 0.4 V; VDD = 5 V -1 - - mA IOL(CLKOUT) CLKOUT LOW-level output current VOL = 0.4 V; VDD = 5 V -1 - - mA IOH(CLKOUT) CLKOUT HIGH-level output current VOH = 4.6 V; VDD = 5 V 1 - - mA ILO output leakage current VO = VDD or VSS -1 0 +1 A Tamb = 25 C - 0.9 1.0 V Voltage detector Vlow [1] [2] [3] low voltage detection For reliable oscillator start-up at power-up: VDD(min)power-up = VDD(min) + 0.3 V. Timer source clock = 160 Hz, level of pins SCL and SDA is VDD or VSS. Tested on sample basis. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 17 of 30 PCF8563 Philips Semiconductors Real time clock/calendar 12. Dynamic characteristics Table 29: Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 15 25 35 pF - 2 x 10-7 - - Oscillator CINT integrated load capacitance fosc/fosc oscillator stability VDD = 200 mV; Tamb = 25 C Quartz crystal parameters (f = 32.768 kHz) Rs series resistance - - 40 k CL parallel load capacitance - 10 - pF CT trimmer capacitance 5 - 25 pF [1] - 50 - % [4] - - 400 kHz CLKOUT output CLKOUT I2C-bus CLKOUT duty cycle timing characteristics[2][3] fSCL SCL clock frequency tHD;STA START condition hold time 0.6 - - s tSU;STA set-up time for a repeated START condition 0.6 - - s tLOW SCL LOW time 1.3 - - s tHIGH SCL HIGH time 0.6 - - s tr SCL and SDA rise time - - 0.3 s tf SCL and SDA fall time - - 0.3 s Cb capacitive bus line load - - 400 pF tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns tSU;STO set-up time for STOP condition 0.6 - - s tSW tolerable spike width on bus - - 50 ns [1] [2] [3] [4] Unspecified for fCLKOUT = 32.768 kHz. All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD. A detailed description of the I2C-bus specification, with applications, is given in brochure The I2C-bus and how to use it. This brochure may be ordered using the code 9398 393 40011. I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 18 of 30 PCF8563 Philips Semiconductors Real time clock/calendar SDA t BUF tf t LOW SCL t HD;STA t HD;DAT tr t SU;DAT t HIGH SDA t SU;STA MGA728 t SU;STO Fig 16. I2C-bus timing waveforms. MGR888 1 handbook, halfpage MGR889 1 handbook, halfpage IDD (A) IDD (A) 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 0 2 4 VDD (V) 6 Tamb = 25 C; Timer = 1 minute. 0 4 VDD (V) 6 Tamb = 25 C; Timer = 1 minute. Fig 17. IDD as a function of VDD; CLKOUT disabled. Fig 18. IDD as a function of VDD; CLKOUT = 32 kHz. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data 2 Rev. 04 -- 12 March 2004 19 of 30 PCF8563 Philips Semiconductors Real time clock/calendar MGR891 MGR890 1 handbook, halfpage handbook, halfpage IDD (A) 4 frequency deviation (ppm) 2 0.8 0.6 0 0.4 -2 0.2 -4 0 -40 0 40 0 80 T (C) 120 2 4 VDD (V) 6 Tamb = 25 C; normalized to VDD = 3 V. VDD = 3 V; Timer = 1 minute. Fig 19. IDD as a function of T; CLKOUT = 32 kHz. Fig 20. Frequency deviation as a function of VDD. 13. Application information VDD handbook, full pagewidth SDA 1F SCL VDD MASTER TRANSMITTER/ RECEIVER SCL CLOCK CALENDAR OSCI PCF8563 OSCO VSS SDA VDD R R R: pull-up resistor tr R= SDA SCL (I2C-bus) Cb MGM665 Fig 21. Application diagram. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 20 of 30 PCF8563 Philips Semiconductors Real time clock/calendar 13.1 Quartz frequency adjustment 13.1.1 Method 1: fixed OSCI capacitor By evaluating the average capacitance necessary for the application layout, a fixed capacitor can be used. The frequency is best measured via the 32.768 kHz signal available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average 5 x 10-6). Average deviations of 5 minutes per year can be easily achieved. 13.1.2 Method 2: OSCI trimmer Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a trimmer is possible. 13.1.3 Method 3: OSCO output Direct measurement of OSCO out (accounting for test probe capacitance). (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 21 of 30 PCF8563 Philips Semiconductors Real time clock/calendar 14. Package outline DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1 ME seating plane D A2 A A1 L c Z w M b1 e (e 1) b MH b2 5 8 pin 1 index E 1 4 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.14 0.53 0.38 1.07 0.89 0.36 0.23 9.8 9.2 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 1.15 inches 0.17 0.02 0.13 0.068 0.045 0.021 0.015 0.042 0.035 0.014 0.009 0.39 0.36 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.045 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT97-1 050G01 MO-001 SC-504-8 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 22. Package outline SOT97-1. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 22 of 30 PCF8563 Philips Semiconductors Real time clock/calendar SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 inches 0.010 0.057 0.069 0.004 0.049 0.05 0.244 0.039 0.028 0.041 0.228 0.016 0.024 0.01 0.01 0.028 0.004 0.012 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 23. Package outline SOT96-1. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 23 of 30 PCF8563 Philips Semiconductors Real time clock/calendar TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm D E SOT505-1 A X c y HE v M A Z 5 8 A2 pin 1 index (A3) A1 A Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.94 0.7 0.4 0.1 0.1 0.1 0.70 0.35 6 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 SOT505-1 Fig 24. Package outline SOT505-1. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 24 of 30 PCF8563 Philips Semiconductors Real time clock/calendar 15. Soldering 15.1 Introduction This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. 15.2 Through-hole mount packages 15.2.1 Soldering by dipping or by solder wave Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.2.2 Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 15.3 Surface mount packages 15.3.1 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all the BGA and SSOP-T packages (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 25 of 30 PCF8563 Philips Semiconductors Real time clock/calendar - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3.2 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.3.3 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 26 of 30 PCF8563 Philips Semiconductors Real time clock/calendar 15.4 Package related soldering information Table 30: Suitability of IC packages for wave, reflow and dipping soldering methods Mounting Package[1] Wave Reflow[2] Dipping - suitable Through-hole mount DBS, DIP, HDIP, RDBS, SDIP, SIL suitable[3] Through-holesurface mount PMFP[4] not suitable not suitable - Surface mount BGA, LBGA, LFBGA, SQFP, SSOP-T[5], TFBGA, VFBGA not suitable suitable - DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable[6] suitable - PLCC[7], SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP [1] [2] [3] [4] [5] [6] [7] [8] [9] suitable - not recommended[7][8] suitable - not recommended[9] suitable - For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. Hot bar soldering or manual soldering is suitable for PMFP packages. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Soldering method Rev. 04 -- 12 March 2004 27 of 30 PCF8563 Philips Semiconductors Real time clock/calendar 16. Revision history Table 31: Revision history Rev Date 04 20040312 CPCN Description - Product data (9397 750 12999) Modifications: * Corrections in the unit column of Table 1. 03 20030414 - Product data (9397 750 11158) 02 19990416 - Product data (9397 750 04855) (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Product data Rev. 04 -- 12 March 2004 28 of 30 PCF8563 Philips Semiconductors Real time clock/calendar 17. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19. Disclaimers 20. Licenses Purchase of Philips I2C components Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. Product data Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12999 Rev. 04 -- 12 March 2004 29 of 30 PCF8563 Philips Semiconductors Real time clock/calendar Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 8.7 8.8 9 9.1 9.2 9.3 9.4 9.5 9.5.1 9.5.2 10 11 12 13 13.1 13.1.1 13.1.2 13.1.3 14 15 15.1 15.2 15.2.1 15.2.2 15.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Alarm function modes. . . . . . . . . . . . . . . . . . . . 5 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Voltage-low detector . . . . . . . . . . . . . . . . . . . . . 5 Register organization . . . . . . . . . . . . . . . . . . . . 6 Control/status 1 register . . . . . . . . . . . . . . . . . . 7 Control/status 2 register . . . . . . . . . . . . . . . . . . 7 Time and date registers . . . . . . . . . . . . . . . . . . 8 Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . . 9 Clock output control register . . . . . . . . . . . . . . 10 Countdown timer. . . . . . . . . . . . . . . . . . . . . . . 10 EXT_CLK test mode . . . . . . . . . . . . . . . . . . . . 11 Power-On Reset (POR) override . . . . . . . . . . 12 Characteristics of the I2C-bus. . . . . . . . . . . . . 12 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Start and stop conditions . . . . . . . . . . . . . . . . 13 System configuration . . . . . . . . . . . . . . . . . . . 13 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 14 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock/calendar read/write cycles . . . . . . . . . . 15 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 Static characteristics. . . . . . . . . . . . . . . . . . . . 16 Dynamic characteristics . . . . . . . . . . . . . . . . . 18 Application information. . . . . . . . . . . . . . . . . . 20 Quartz frequency adjustment . . . . . . . . . . . . . 21 Method 1: fixed OSCI capacitor . . . . . . . . . . . 21 Method 2: OSCI trimmer. . . . . . . . . . . . . . . . . 21 Method 3: OSCO output . . . . . . . . . . . . . . . . . 21 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Through-hole mount packages . . . . . . . . . . . . 25 Soldering by dipping or by solder wave . . . . . 25 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 25 Surface mount packages . . . . . . . . . . . . . . . . 25 (c) Koninklijke Philips Electronics N.V. 2004. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 12 March 2004 Document order number: 9397 750 12999 15.3.1 15.3.2 15.3.3 15.4 16 17 18 19 20 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 26 26 27 28 29 29 29 29