PCF8563TD - Philips Semiconductors / NXP Semiconductors

PCF8563

Real time clock/calendar

Rev. 04 — 12 March 2004 Product data

1. General description

The PCF8563 is a CMOS real time clock/calendar optimized for low power

consumption. A programmable clock output, interrupt output and voltage-low detector

are also provided. All address and data are transferred serially via a two-line

bidirectional I2C-bus. Maximum bus speed is 400 kbit/s. The built-in word address

2. Features

■Provides year, month, day, weekday, hours, minutes and seconds based on

32.768 kHz quartz crystal

■Century ﬂag

■Clock operating voltage: 1.8 V to 5.5 V

■Low backup current; typical 0.25 µA at VDD = 3.0 V and Tamb =25°C

■400 kHz two-wire I2C-bus interface (at VDD = 1.8 V to 5.5 V)

■Programmable clock output for peripheral devices (32.768 kHz, 1024 Hz,

32 Hz and 1 Hz)

■Alarm and timer functions

■Integrated oscillator capacitor

■Internal power-on reset

■I2C-bus slave address: read A3H and write A2H

■Open-drain interrupt pin.

3. Applications

■Mobile telephones

■Portable instruments

■Fax machines

■Battery powered products.

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 2 of 30

4. Quick reference data

5. Ordering information

Table 1: Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage operating; I2C-bus inactive; Tamb =25°C 1.0 - 5.5 V

operating; I2C-bus active; fSCL = 400 kHz;

Tamb =−40 °C to +125 °C1.8 - 5.5 V

IDD supply current timer and clock output disabled;

fSCL = 400 kHz - - 800 µA

timer and clock output disabled;

fSCL = 100 kHz - - 200 µA

timer and clock output disabled;

fSCL = 0 Hz; Tamb =25°C

VDD = 5 V - - 550 nA

VDD = 2 V - - 450 nA

Tamb ambient temperature operating −40 - +85 °C

Tstg storage temperature −65 - +150 °C

Table 2: Ordering information

Type number Package

Name Description Version

PCF8563P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1

PCF8563T SO8 plastic dual in-line package; 8 leads; body width 3.9 mm SOT96-1

PCF8563TS TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 3 of 30

6. Block diagram

7. Pinning information

7.1 Pinning

Fig 1. Block diagram.

MGM662

CONTROL/STATUS 1

OSCILLATOR

32.768 kHz 1

CONTROL/STATUS 2 2

SECONDS/VL 3

MINUTES 4

HOURS 5

DAYS 6

WEEKDAYS 7

MONTHS/CENTURY 8

YEARS 9

MINUTE ALARM A

HOUR ALARM B

DAY ALARM C

WEEKDAY ALARM D

CLKOUT CONTROL

TIMER CONTROL

TIMER

OSCILLATOR

MONITOR

VOLTAGE

DETECTOR

C-BUS

INTERFACE

DIVIDER

CONTROL

LOGIC

ADDRESS

POR

PCF8563

VDD

CLKOUT

1 Hz

OSCO

SCL

SDA

VSS

INT

OSCI 1

Fig 2. Pin conﬁguration DIP8. Fig 3. Pin conﬁguration SO8. Fig 4. Pin conﬁguration TSSOP8.

MCE403

PCF8563P

VDD

CLKOUTOSCO

SCL

SDA

VSS

INT

OSCI 1

MCE198

PCF8563T

VDD

CLKOUTOSCO

SCL

SDA

VSS

INT

OSCI 1

MCE199

PCF8563TS

VDD

CLKOUTOSCO

SCL

SDA

VSS

INT

OSCI

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 4 of 30

7.2 Pin description

8. Functional description

The PCF8563 contains sixteen 8-bit registers with an auto-incrementing address

divider which provides the source clock for the Real Time Clock/calender (RTC), a

programmable clock output, a timer, an alarm, a voltage-low detector and a 400 kHz

I2C-bus interface.

All 16 registers are designed as addressable 8-bit parallel registers although not all

bits are implemented. The ﬁrst two registers (memory address 00H and 01H) are

used as control and/or status registers. The memory addresses 02H through 08H are

used as counters for the clock function (seconds up to years counters). Address

locations 09H through 0CH contain alarm registers which deﬁne the conditions for an

alarm. Address 0DH controls the CLKOUT output frequency. 0EH and 0FH are the

timer control and timer registers, respectively.

The seconds, minutes, hours, days, weekdays, months, years as well as the minute

alarm, hour alarm, day alarm and weekday alarm registers are all coded in BCD

format.

When one of the RTC registers is read the contents of all counters are frozen.

Therefore, faulty reading of the clock/calendar during a carry condition is prevented.

Fig 5. Device diode protection diagram.

handbook, halfpage

MGR886

SDA

VSS

SCL

INT

CLKOUT

OSCO

VDD

OSCI

PCF8563

Table 3: Pin description

Symbol Pin Description

OSCI 1 oscillator input

OSCO 2 oscillator output

INT 3 interrupt output (open-drain; active LOW)

VSS 4 ground

SDA 5 serial data input and output

SCL 6 serial clock input

CLKOUT 7 clock output, open-drain

VDD 8 positive supply voltage

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 5 of 30

8.1 Alarm function modes

By clearing the MSB of one or more of the alarm registers (bit AE = alarm enable),

the corresponding alarm condition(s) will be active. In this way an alarm can be

generated from once per minute up to once per week. The alarm condition sets the

Alarm Flag (AF). The asserted AF can be used to generate an interrupt (INT). The AF

can only be cleared by software.

8.2 Timer

The 8-bit countdown timer at address 0FH is controlled by the timer control register at

address 0EH. The timer control register determines one of 4 source clock

frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or 1⁄60 Hz), and enables or disables

the timer. The timer counts down from a software-loaded 8-bit binary value. At the

end of every countdown, the timer sets the Timer Flag (TF). The TF may only be

cleared by software. The asserted TF can be used to generate an interrupt (INT). The

interrupt may be generated as a pulsed signal every countdown period or as a

permanently active signal which follows the condition of TF. Bit TI/TP is used to

control this mode selection. When reading the timer, the current countdown value is

returned.

8.3 Clock output

A programmable square wave is available at pin CLKOUT. Operation is controlled by

the CLKOUT control register at address 0DH. Frequencies of 32.768 kHz (default),

1024 Hz, 32 Hz and 1 Hz can be generated for use as a system clock,

microcontroller clock, input to a charge pump, or for calibration of the oscillator.

CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes

high-impedance.

8.4 Reset

The PCF8563 includes an internal reset circuit which is active whenever the oscillator

is stopped. In the reset state the I2C-bus logic is initialized and all registers, including

the address pointer, are cleared with the exception of bits FE, VL, TD1, TD0, TESTC

and AE which are set to logic 1.

8.5 Voltage-low detector

The PCF8563 has an on-chip voltage-low detector. When VDD drops below Vlow,

bit VL in the seconds register is set to indicate that the integrity of the clock

information is no longer guaranteed. The VL ﬂag can only be cleared by software.

Bit VL is intended to detect the situation when VDD is decreasing slowly, for example

under battery operation. Should VDD reach Vlow before power is re-asserted then

bit VL will be set. This will indicate that the time may be corrupted.

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 6 of 30

8.6 Register organization

Fig 6. Voltage-low detection.

handbook, halfpage

VL set

normal power

operation

period of battery

operation

VDD

Vlow

MGR887

Table 4: Binary formatted registers overview

Bit positions labelled as x are not implemented. Bit positions labelled with 0 should always be written with logic 0; if read they

could be either logic 0 or logic 1.

Address Register name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00H control/status 1 TEST1 0 STOP 0 TESTC 0 0 0

01H control/status 2 0 0 0 TI/TP AF TF AIE TIE

0DH CLKOUT control FE xxxxxFD1FD0

0EH timer control TE xxxxxTD1TD0

0FH timer <timer countdown value>

Table 5: BCD formatted registers overview

Bit positions labelled as x are not implemented.

Address Register name BCD format tens nibble BCD format units nibble

Bit 7

23Bit 6

22Bit 5

21Bit 4

20Bit 3

23Bit 2

22Bit 1

21Bit 0

02H seconds VL <seconds 00 to 59 coded in BCD>

03H minutes x <minutes 00 to 59 coded in BCD>

04H hours x x <hours 00 to 23 coded in BCD>

05H days x x <days 01 to 31 coded in BCD>

06H weekdays xxxxx <weekdays 0 to 6>

07H months/century C x x <months 01 to 12 coded in BCD>

08H years <years 00 to 99 coded in BCD>

09H minute alarm AE <minute alarm 00 to 59 coded in BCD>

0AH hour alarm AE x <hour alarm 00 to 23 coded in BCD>

0BH day alarm AE x <day alarm 01 to 31 coded in BCD>

0CH weekday alarm AE xxxx <weekday alarm 0 to 6>

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 7 of 30

8.6.1 Control/status 1 register

8.6.2 Control/status 2 register

Bits TF and AF: When an alarm occurs, AF is set to 1. Similarly, at the end of a timer

countdown, TF is set to 1. These bits maintain their value until overwritten by

software. If both timer and alarm interrupts are required in the application, the source

of the interrupt can be determined by reading these bits. To prevent one ﬂag being

overwritten while clearing another a logic AND is performed during a write access.

Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt

when TF or AF is asserted, respectively. The interrupt is the logical OR of these two

conditions when both AIE and TIE are set.

Table 6: Control/status 1 (address 00H) bits description

Bit Symbol Value Description

7 TEST1 0 normal mode

1 EXT_CLK test mode

6 0 default value is logic 0

5 STOP 0 RTC source clock runs

1 all RTC divider chain ﬂip-ﬂops are asynchronously set to logic 0; the RTC clock is

stopped (CLKOUT at 32.768 kHz is still available)

4 0 default value is logic 0

3 TESTC 0 Power-on reset override facility is disabled; set to logic 0 for normal operation

1 Power-on reset override may be enabled

2 to 0 0 default value is logic 0

Table 7: Control/status 2 (address 01H) bits description

Bit Symbol Value Description

7 to 5 0 default value is logic 0

4 TI/TP 0 INT is active when TF is active (subject to the status of TIE)

1INT pulses active according to Table 8 (subject to the status of TIE); note that if

AF and AIE are active then INT will be permanently active

3 AF 0 (read) alarm ﬂag inactive

1 (read) alarm ﬂag active

0 (write) alarm ﬂag is cleared

1 (write) alarm ﬂag remains unchanged

2 TF 0 (read) timer ﬂag inactive

1 (read) timer ﬂag active

0 (write) timer ﬂag is cleared

1 (write) timer ﬂag remains unchanged

1 AIE 0 alarm interrupt disabled

1 alarm interrupt enabled

0 TIE 0 timer interrupt disabled

1 timer interrupt enabled

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 8 of 30

[1] TF and INT become active simultaneously.

[2] n = loaded countdown value. Timer stopped when n = 0.

8.6.3 Time and date registers

[1] The PCF8563 compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly

divisible by 4, including the year 00.

[1] These bits may be re-assigned by the user.

Table 8: INT operation (bit TI/TP = 1)

Source clock (Hz) INT period (s)[1]

n=1

[2] n>1

4096 1⁄8192 1⁄4096

64 1⁄128 1⁄64

11⁄64 1⁄64

1⁄60 1⁄64 1⁄64

Table 9: Seconds/VL (address 02H) bits description

Bit Symbol Value Description

7 VL 0 clock integrity is guaranteed

1 integrity of the clock information is no longer guaranteed

6 to 0 seconds 00 to 59 this register holds the current seconds coded in BCD format; example: seconds

Table 10: Minutes (address 03H) bits description

Bit Symbol Value Description

6 to 0 minutes 00 to 59 this register holds the current minutes coded in BCD format

Table 11: Hours (address 04H) bits description

Bit Symbol Value Description

5 to 0 hours 00 to 23 this register holds the current hours coded in BCD format

Table 12: Days (address 05H) bits description

Bit Symbol Value Description

5 to 0 days[1] 01 to 31 this register holds the current day coded in BCD format

Table 13: Weekdays (address 06H) bits description

Bit Symbol Value Description

2 to 0 weekdays[1] 0 to 6 this register holds the current weekday coded in BCD format, see Table 14

Table 14: Weekday assignments

Day Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Sunday xxxxx000

Monday xxxxx001

Tuesday xxxxx010

Wednesday xxxxx011

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 9 of 30

[1] These bits may be re-assigned by the user.

8.6.4 Alarm registers

When one or more of these registers are loaded with a valid minute, hour, day or

weekday and its corresponding bit Alarm Enable (AE) is logic 0, then that information

will be compared with the current minute, hour, day and weekday. When all enabled

comparisons ﬁrst match, the Alarm Flag (AF) is set. AF will remain set until cleared

by software. Once AF has been cleared it will only be set again when the time

increments to match the alarm condition once more. Alarm registers which have their

bit AE at logic 1 will be ignored.

Thursday xxxxx100

Friday xxxxx101

Saturday xxxxx110

Table 14: Weekday assignments

…continued

Day Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Table 15: Months/century (address 07H) bits description

Bit Symbol Value Description

7 century[1] this bit is toggled when the years register overﬂows from 99 to 00

0 indicates the century is 20xx

1 indicates the century is 19xx

4 to 0 month 01 to 12 this register holds the current month coded in BCD format, see Table 16

Table 16: Month assignments

Month Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

January Cxx00001

February Cxx00010

March C x x 00011

April Cxx00100

May Cxx00101

June Cxx00110

July Cxx00111

August C x x 01000

September C x x 01001

October C x x 10000

November C x x 10001

December C x x 10010

Table 17: Years (address 08H) bits description

Bit Symbol Value Description

7 to 0 years 00 to 99 this register holds the current year coded in BCD format

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 10 of 30

8.6.5 Clock output control register

8.6.6 Countdown timer

The timer register is an 8-bit binary countdown timer. It is enabled and disabled via

the timer control register bit TE. The source clock for the timer is also selected by the

timer control register. Other timer properties such as interrupt generation are

controlled via control/status 2 register.

Table 18: Minute alarm (address 09H) bits description

Bit Symbol Value Description

7 AE 0 minute alarm is enabled

1 minute alarm is disabled

6 to 0 alarm minutes 00 to 59 this register holds the minute alarm information coded in BCD format

Table 19: Hour alarm (address 0AH) bits description

Bit Symbol Value Description

7 AE 0 hour alarm is enabled

1 hour alarm is disabled

5 to 0 alarm hours 00 to 23 this register holds the hour alarm information coded in BCD format

Table 20: Day alarm (address 0BH) bits description

Bit Symbol Value Description

7 AE 0 day alarm is enabled

1 day alarm is disabled

5 to 0 alarm days 01 to 31 this register holds the day alarm information coded in BCD format

Table 21: Weekday alarm (address 0CH) bits description

Bit Symbol Value Description

7 AE 0 weekday alarm is enabled

1 weekday alarm is disabled

2 to 0 alarm

weekdays 0 to 6 this register holds the weekday alarm information coded in BCD format

Table 22: CLKOUT control (address 0DH) bits description

Bit Symbol Value Description

7 FE 0 the CLKOUT output is inhibited and CLKOUT output is set to high-impedance

1 the CLKOUT output is activated

1 to 0 FD1 and

FD0 these bits control the frequency output at pin CLKOUT; see Table 23

Table 23: FD1 and FD0: CLKOUT frequency selection

FD1 FD0 CLKOUT frequency

0 0 32.768 kHz

0 1 1024 Hz

1032Hz

111Hz

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 11 of 30

For accurate read back of the countdown value, the I2C-bus clock (SCL) must be

operating at a frequency of at least twice the selected timer clock.

8.7 EXT_CLK test mode

A test mode is available which allows for on-board testing. In such a mode it is

possible to set up test conditions and control the operation of the RTC.

The test mode is entered by setting bit TEST1 in control/status1 register. Then

pin CLKOUT becomes an input. The test mode replaces the internal 64 Hz signal

with the signal applied to pin CLKOUT. Every 64 positive edges applied to

pin CLKOUT will then generate an increment of one second.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and

a minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT,

is divided down to 1 Hz by a 26divide chain called a pre-scaler. The pre-scaler can be

set into a known state by using bit STOP. When bit STOP is set, the pre-scaler is

reset to 0 (STOP must be cleared before the pre-scaler can operate again).

From a STOP condition, the ﬁrst 1 second increment will take place after 32 positive

edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1 second

increment.

Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz

clock. When entering the test mode, no assumption as to the state of the pre-scaler

can be made.

Operation example:

1. Set EXT_CLK test mode (control/status 1, bit TEST1 = 1)

2. Set STOP (control/status 1, bit STOP = 1)

Table 24: Timer control (address 0EH) bits description

Bit Symbol Value Description

7 TE 0 timer is disabled

1 timer is enabled

1 to 0 TD1 and

TD0 timer source clock frequency select; these bits determine the source clock for the

countdown timer, see Table 25; when not in use, TD1 and TD0 should be set to

1⁄60 Hz for power saving

Table 25: TD1 and TD0: Timer frequency selection

TD1 TD0 TIMER Source clock frequency

0 0 4096 Hz

0164Hz

101Hz

111⁄60 Hz

Table 26: Timer (address 0FH) bits description

Bit Symbol Value Description

7 to 0 timer 00 to FF countdown value = n; CountdownPeriod n

SourceClockFrequency

---------------------------------------------------------------

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 12 of 30

3. Clear STOP (control/status 1, bit STOP = 0)

4. Set time registers to desired value

5. Apply 32 clock pulses to CLKOUT

6. Read time registers to see the ﬁrst change

7. Apply 64 clock pulses to CLKOUT

8. Read time registers to see the second change.

Repeat 7 and 8 for additional increments.

8.8 Power-On Reset (POR) override

The POR duration is directly related to the crystal oscillator start-up time. Due to the

long start-up times experienced by these types of circuits, a mechanism has been

built in to disable the POR and hence speed up on-board test of the device. The

setting of this mode requires that the I2C-bus pins, SDA and SCL, be toggled in a

speciﬁc order as shown in Figure 7. All timings are required minimums.

Once the override mode has been entered, the device immediately stops being reset

and normal operation may commence i.e. entry into the EXT_CLK test mode via

I2C-bus access. The override mode may be cleared by writing a logic 0 to TESTC.

TESTC must be set to logic 1 before re-entry into the override mode is possible.

Setting TESTC to logic 0 during normal operation has no effect except to prevent

entry into the POR override mode.

9. Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or

modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both

lines must be connected to a positive supply via a pull-up resistor. Data transfer may

be initiated only when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must

remain stable during the HIGH period of the clock pulse as changes in the data line at

this time will be interpreted as a control signal (see Figure 8).

Fig 7. POR override sequence.

handbook, full pagewidth

MGM664

SCL

500 ns 2000 ns

SDA

8 ms

override active

power up

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 13 of 30

9.2 Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is deﬁned as the START condition

(S). A LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as

the STOP condition (P); see Figure 9.

9.3 System conﬁguration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master and the devices which

are controlled by the master are the slaves (see Figure 10).

9.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an

acknowledge bit. The acknowledge bit is a HIGH-level signal put on the bus by the

transmitter during which time the master generates an extra acknowledge related

Fig 8. Bit transfer.

MBC621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 9. Deﬁnition of start and stop conditions.

MBC622

SDA

SCL P

STOP condition

SDA

SCL

START condition

Fig 10. System conﬁguration.

MBA605

MASTER

TRANSMITTER /

RECEIVER SLAVE

TRANSMITTER /

RECEIVER MASTER

TRANSMITTER MASTER

TRANSMITTER /

RECEIVER

SDA

SCL

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 14 of 30

clock pulse. A slave receiver which is addressed must generate an acknowledge after

the reception of each byte. Also a master receiver must generate an acknowledge

after the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges must pull down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration). A master receiver must signal an end of data to the transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In

this event the transmitter must leave the data line HIGH to enable the master to

generate a stop condition.

9.5 I2C-bus protocol

9.5.1 Addressing

Before any data is transmitted on the I2C-bus, the device which should respond is

addressed ﬁrst. The addressing is always carried out with the ﬁrst byte transmitted

after the start procedure.

The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal

SCL is only an input signal, but the data signal SDA is a bidirectional line.

The PCF8563 slave address is shown in Figure 12.

Fig 11. Acknowledgement on the I2C-bus.

MBC602

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

Fig 12. Slave address.

MCE189

1 0 1 0 0 0 1 R/W

group 1 group 2

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 15 of 30

9.5.2 Clock/calendar read/write cycles

The I2C-bus conﬁguration for the different PCF8563 read and write cycles is shown in

Figure 13,Figure 14 and Figure 15. The word address is a 4-bit value that deﬁnes

which register is to be accessed next. The upper four bits of the word address are not

used.

Fig 13. Master transmits to slave receiver (write mode).

S0ASLAVE ADDRESS WORD ADDRESS A ADATA P

acknowledgement

from slave acknowledgement

from slave

R/W

auto increment

memory word address

MBD822

n bytes

Fig 14. Master reads after setting word address (write word address; read data).

S0ASLAVE ADDRESS WORD ADDRESS A A

SLAVE ADDRESS

acknowledgement

from slave acknowledgement

from slave

R/W

acknowledgement

from master

DATA

auto increment

memory word address

MCE172

no acknowledgement

from master

1DATA

auto increment

memory word address

last byte

R/W

n bytes

at this moment master transmitter

becomes master receiver and

PCA8565 slave receiver

becomes slave transmitter

Fig 15. Master reads slave immediately after ﬁrst byte (read mode).

handbook, full pagewidth

S1A

SLAVE ADDRESS DATA A1DATA

acknowledgement

from slave acknowledgement

from master no acknowledgement

from master

R/W

auto increment

word address

MGL665

auto increment

word address

n bytes last byte

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 16 of 30

10. Limiting values

11. Static characteristics

Table 27: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Min Max Unit

VDD supply voltage −0.5 +6.5 V

IDD supply current −50 +50 mA

VIinput voltage on pins SCL and SDA −0.5 +6.5 V

input voltage on pin OSCI −0.5 VDD + 0.5 V

VOoutput voltage on pins CLOCKOUT

and INT −0.5 +6.5 V

IIDC input current at any input −10 +10 mA

IODC output current at any output −10 +10 mA

Ptot total power dissipation - 300 mW

Tamb ambient temperature −40 +85 °C

Tstg storage temperature −65 +150 °C

Table 28: Static characteristics

= 1.8 V to 5.5 V; V

=0V; T

amb

−

C to +85

C; f

osc

= 32.768 kHz; quartz R

=40k

Ω

; C

= 8 pF; unless otherwise

speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage interface inactive;

Tamb =25°C[1] 1.0 - 5.5 V

interface active;

fSCL = 400 kHz [1] 1.8 - 5.5 V

VDD(clock) supply voltage for clock

data integrity Tamb =25°CV

low - 5.5 V

IDD1 supply current 1 interface active

fSCL = 400 kHz - - 800 µA

fSCL = 100 kHz - - 200 µA

IDD2 supply current 2 interfaceinactive(fSCL = 0 Hz);

CLKOUT disabled;

Tamb =25°C

[2]

VDD = 5.0 V - 275 550 nA

VDD = 3.0 V - 250 500 nA

VDD = 2.0 V - 225 450 nA

interfaceinactive (fSCL = 0 Hz);

CLKOUT disabled;

Tamb =−40 to +85 °C

[2]

VDD = 5.0 V - 500 750 nA

VDD = 3.0 V - 400 650 nA

VDD = 2.0 V - 400 600 nA

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 17 of 30

[1] For reliable oscillator start-up at power-up: VDD(min)power-up =V

DD(min) + 0.3 V.

[2] Timer source clock = 1⁄60 Hz, level of pins SCL and SDA is VDD or VSS.

[3] Tested on sample basis.

IDD3 supply current 3 interfaceinactive(fSCL = 0 Hz);

CLKOUT enabled at 32 kHz;

Tamb =25°C

[2]

VDD = 5.0 V - 825 1600 nA

VDD = 3.0 V - 550 1000 nA

VDD = 2.0 V - 425 800 nA

interfaceinactive (fSCL = 0 Hz);

CLKOUT enabled at 32 kHz;

Tamb =−40 to +85 °C

[2]

VDD = 5.0 V - 950 1700 nA

VDD = 3.0 V - 650 1100 nA

VDD = 2.0 V - 500 900 nA

Inputs

VIL LOW-level input voltage VSS - 0.3VDD V

VIH HIGH-level input voltage 0.7VDD -V

DD V

ILI input leakage current VI=V

DD or VSS −10 +1µA

Ciinput capacitance [3] --7pF

Outputs

IOL(SDA) SDA LOW-level output

current VOL = 0.4 V; VDD =5V −3- - mA

IOL(INT) INT LOW-level output

current VOL = 0.4 V; VDD =5V −1- - mA

IOL(CLKOUT) CLKOUT LOW-level

output current VOL = 0.4 V; VDD =5V −1- - mA

IOH(CLKOUT) CLKOUT HIGH-level

output current VOH = 4.6 V; VDD =5V 1 - - mA

ILO output leakage current VO=V

DD or VSS −10 +1µA

Voltage detector

Vlow low voltage detection Tamb =25°C - 0.9 1.0 V

Table 28: Static characteristics

…continued

= 1.8 V to 5.5 V; V

=0V; T

amb

−

C to +85

C; f

osc

= 32.768 kHz; quartz R

=40k

Ω

; C

= 8 pF; unless otherwise

speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 18 of 30

12. Dynamic characteristics

[1] Unspeciﬁed for fCLKOUT = 32.768 kHz.

[2] All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage

swing of VSS to VDD.

[3] A detailed description of the I2C-bus speciﬁcation, with applications, is given in brochure

The I2C-bus and how to use it

. This brochure

may be ordered using the code 9398 393 40011.

[4] I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.

Table 29: Dynamic characteristics

= 1.8 V to 5.5 V; V

=0V; T

amb

−

C to +85

C; f

osc

= 32.768 kHz; quartz R

=40k

Ω

; C

= 8 pF; unless otherwise

speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Oscillator

CINT integrated load

capacitance 15 25 35 pF

∆fosc/fosc oscillator stability ∆VDD = 200 mV; Tamb =25°C- 2×10-7 --

Quartz crystal parameters (f = 32.768 kHz)

Rsseries resistance - - 40 kΩ

CLparallel load capacitance - 10 - pF

CTtrimmer capacitance 5 - 25 pF

CLKOUT output

δCLKOUT CLKOUT duty cycle [1] -50-%

I2C-bus timing characteristics[2][3]

fSCL SCL clock frequency [4] - - 400 kHz

tHD;STA START condition hold time 0.6 - - µs

tSU;STA set-up time for a repeated

START condition 0.6 - - µs

tLOW SCL LOW time 1.3 - - µs

tHIGH SCL HIGH time 0.6 - - µs

trSCL and SDA rise time - - 0.3 µs

tfSCL and SDA fall time - - 0.3 µs

Cbcapacitive bus line load - - 400 pF

tSU;DAT data set-up time 100 - - ns

tHD;DAT data hold time 0 - - ns

tSU;STO set-up time for STOP

condition 0.6 - - µs

tSW tolerable spike width on

bus --50ns

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 19 of 30

Fig 16. I2C-bus timing waveforms.

SDA

MGA728

SDA

SCL

tSU;STA tSU;STO

tHD;STA

tBUF tLOW

tHD;DAT tHIGH

tSU;DAT

Tamb =25°C; Timer = 1 minute. Tamb =25°C; Timer = 1 minute.

Fig 17. IDD as a function of VDD; CLKOUT disabled. Fig 18. IDD as a function of VDD; CLKOUT = 32 kHz.

handbook, halfpage

02 6

MGR888

4VDD (V)

0.4

0.2

0.8

0.6

IDD

(µA)

handbook, halfpage

02 6

MGR889

4VDD (V)

0.4

0.2

0.8

0.6

IDD

(µA)

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 20 of 30

13. Application information

VDD = 3 V; Timer = 1 minute. Tamb =25°C; normalized to VDD =3V.

Fig 19. IDD as a function of T; CLKOUT = 32 kHz. Fig 20. Frequency deviation as a function of VDD.

handbook, halfpage

−40 0 40 120

MGR890

80 T (°C)

0.4

0.2

0.8

0.6

IDD

(µA)

handbook, halfpage

02 6

−4

−2

MGR891

4VDD (V)

frequency

deviation

(ppm)

Fig 21. Application diagram.

handbook, full pagewidth

MGM665

SCL

SDA

VSS

OSCI

OSCO

CLOCK CALENDAR

PCF8563

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

VDD

SDA SCL

VDD

(I2C-bus)

R: pull-up resistor

R =

1 F

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 21 of 30

13.1 Quartz frequency adjustment

13.1.1 Method 1: ﬁxed OSCI capacitor

By evaluating the average capacitance necessary for the application layout, a ﬁxed

capacitor can be used. The frequency is best measured via the 32.768 kHz signal

available after power-on at pin CLKOUT. The frequency tolerance depends on the

quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance

(on average ±5×10−6). Average deviations of ±5 minutes per year can be easily

achieved.

13.1.2 Method 2: OSCI trimmer

Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a

trimmer is possible.

13.1.3 Method 3: OSCO output

Direct measurement of OSCO out (accounting for test probe capacitance).

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 22 of 30

14. Package outline

Fig 22. Package outline SOT97-1.

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT97-1 99-12-27

03-02-13

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.14 0.53

0.38 0.36

0.23 9.8

9.2 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 1.154.2 0.51 3.2

inches 0.068

0.045 0.021

0.015 0.014

0.009

1.07

0.89

0.042

0.035 0.39

0.36 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0450.17 0.02 0.13

050G01 MO-001 SC-504-8

(e )

seating plane

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

pin 1 index

DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 23 of 30

Fig 23. Package outline SOT96-1.

UNIT A

max. A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 5.0

4.8 4.0

3.8 1.27 6.2

5.8 1.05 0.7

0.6 0.7

0.3 8

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

detail X

vMA

(A )

pin 1 index

076E03 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.20

0.19 0.16

0.15 0.05 0.244

0.228 0.028

0.024 0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

99-12-27

03-02-18

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 24 of 30

Fig 24. Package outline SOT505-1.

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.45

0.25 0.28

0.15 3.1

2.9 3.1

2.9 0.65 5.1

4.7 0.70

0.35 6°

0°

0.1 0.10.10.94

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT505-1 99-04-09

03-02-18

0.25

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

1.1

pin 1 index

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 25 of 30

15. Soldering

15.1 Introduction

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit

Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all IC packages. Wave soldering is often

preferred when through-hole and surface mount components are mixed on one

printed-circuit board. Wave soldering can still be used for certain surface mount ICs,

but it is not suitable for ﬁne pitch SMDs. In these situations reﬂow soldering is

recommended. Driven by legislation and environmental forces the worldwide use of

lead-free solder pastes is increasing.

15.2 Through-hole mount packages

15.2.1 Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or

265 °C, depending on solder material applied, SnPb or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the

plastic body must not exceed the speciﬁed maximum storage temperature (Tstg(max)).

If the printed-circuit board has been pre-heated, forced cooling may be necessary

immediately after soldering to keep the temperature within the permissible limit.

15.2.2 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron

bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit

temperature is between 300 and 400 °C, contact may be up to 5 seconds.

15.3 Surface mount packages

15.3.1 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 270 °C depending on solder

paste material. The top-surface temperature of the packages should preferably be

kept:

•below 225 °C (SnPb process) or below 245 °C (Pb-free process)

–for all the BGA and SSOP-T packages

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 26 of 30

–for packages with a thickness ≥2.5 mm

–for packages with a thickness < 2.5 mm and a volume ≥350 mm3 so called

thick/large packages.

•below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with

a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all

times.

15.3.2 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

•Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

–larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

–smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

•For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or

265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in

most applications.

15.3.3 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 27 of 30

15.4 Package related soldering information

[1] For more detailed information on the BGA packages refer to the

(LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods

[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the

printed-circuit board.

[4] Hot bar soldering or manual soldering is suitable for PMFP packages.

[5] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must

on no account be processed through more than one soldering cycle or subjected to infrared reﬂow

soldering with peak temperature exceeding 217 °C±10 °C measured in the atmosphere of the reﬂow

oven. The package body peak temperature must be kept as low as possible.

[6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom

side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with

the heatsink on the top side, the solder might be deposited on the heatsink surface.

[7] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[8] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it

is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[9] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

Table 30: Suitability of IC packages for wave, reﬂow and dipping soldering methods

Mounting Package[1] Soldering method

Wave Reﬂow[2] Dipping

Through-hole

mount DBS, DIP, HDIP, RDBS,

SDIP, SIL suitable[3] −suitable

Through-hole-

surface mount PMFP[4] not suitable not

suitable −

Surface mount BGA, LBGA, LFBGA,

SQFP, SSOP-T[5],

TFBGA, VFBGA

not suitable suitable −

DHVQFN, HBCC, HBGA,

HLQFP, HSQFP, HSOP,

HTQFP, HTSSOP,

HVQFN, HVSON, SMS

not suitable[6] suitable −

PLCC[7], SO, SOJ suitable suitable −

LQFP, QFP, TQFP not recommended[7][8] suitable −

SSOP, TSSOP, VSO,

VSSOP not recommended[9] suitable −

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 28 of 30

16. Revision history

Table 31: Revision history

Rev Date CPCN Description

04 20040312 - Product data (9397 750 12999)

Modiﬁcations:

•Corrections in the unit column of Table 1.

03 20030414 - Product data (9397 750 11158)

02 19990416 - Product data (9397 750 04855)

9397 750 12999

Philips Semiconductors PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 29 of 30

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.Fax: +31 40 27 24825

17. Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

18. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

19. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

20. Licenses

Level Data sheet status[1] Product status[2][3] Deﬁnition

I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

Purchase of Philips I2C components

Purchase of Philips I2C components conveys a license

under the Philips’ I2C patent to use the components in the

I2C system provided the system conforms to the I2C

speciﬁcation deﬁned by Philips. This speciﬁcation can be

ordered using the code 9398 393 40011.

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 12 March 2004 Document order number: 9397 750 12999

Contents

Philips Semiconductors PCF8563

Real time clock/calendar

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

5 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Functional description . . . . . . . . . . . . . . . . . . . 4

8.1 Alarm function modes. . . . . . . . . . . . . . . . . . . . 5

8.2 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

8.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

8.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

8.5 Voltage-low detector . . . . . . . . . . . . . . . . . . . . . 5

8.6 Register organization . . . . . . . . . . . . . . . . . . . . 6

8.6.1 Control/status 1 register . . . . . . . . . . . . . . . . . . 7

8.6.2 Control/status 2 register . . . . . . . . . . . . . . . . . . 7

8.6.3 Time and date registers . . . . . . . . . . . . . . . . . . 8

8.6.4 Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . . 9

8.6.5 Clock output control register. . . . . . . . . . . . . . 10

8.6.6 Countdown timer. . . . . . . . . . . . . . . . . . . . . . . 10

8.7 EXT_CLK test mode. . . . . . . . . . . . . . . . . . . . 11

8.8 Power-On Reset (POR) override . . . . . . . . . . 12

9 Characteristics of the I2C-bus. . . . . . . . . . . . . 12

9.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

9.2 Start and stop conditions . . . . . . . . . . . . . . . . 13

9.3 System conﬁguration . . . . . . . . . . . . . . . . . . . 13

9.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 13

9.5 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 14

9.5.1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

9.5.2 Clock/calendar read/write cycles . . . . . . . . . . 15

10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16

11 Static characteristics. . . . . . . . . . . . . . . . . . . . 16

12 Dynamic characteristics . . . . . . . . . . . . . . . . . 18

13 Application information. . . . . . . . . . . . . . . . . . 20

13.1 Quartz frequency adjustment . . . . . . . . . . . . . 21

13.1.1 Method 1: ﬁxed OSCI capacitor . . . . . . . . . . . 21

13.1.2 Method 2: OSCI trimmer. . . . . . . . . . . . . . . . . 21

13.1.3 Method 3: OSCO output. . . . . . . . . . . . . . . . . 21

14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22

15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 25

15.2 Through-hole mount packages. . . . . . . . . . . . 25

15.2.1 Soldering by dipping or by solder wave . . . . . 25

15.2.2 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 25

15.3 Surface mount packages . . . . . . . . . . . . . . . . 25

15.3.1 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 25

15.3.2 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 26

15.3.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 26

15.4 Package related soldering information. . . . . . 27

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 28

17 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 29

18 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

20 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29