-ACT-SF41632 High Speed 128Kx32 SRAM / 512Kx32 Flash Multichip Module FEATURES CIRCUIH TECHNOLOGY www.aeroflex.com m 4- 128K x 8 SRAMs & 4- 512K x 8 Flash Die in FLASH MEMORY FEATURES One MCM m= Access Times of 25ns, 35ns (SRAM) and 60ns, 70ns, 90ns (Flash) m Sector Architecture (Each Die) m Organized as 128K x 32 of SRAM and 512K x 32 one command sequence. of Flash Memory with Common Data Bus m +5V Programing, +5V Supply = Low Power CMOS g Input and Output TTL Compatible Design gs MIL-PRF-38534 Compliant MCMs Available = Decoupling Capacitors and Multiple Grounds for Low Noise = Commercial, Industrial and Military Temperature Ranges g Industry Standard Pinouts = TTL Compatible Inputs and Outputs m Packaging e 66Lead, PGA-Type, 1.385"SQ x 0.245"max, Aeroflex code# "P1,P5 with/without shoulders)" e 68Lead, Dual-Cavity CQFP(F2), 0.88"SQ x .20"max (.18 max thickness available, contact factory for details) (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint) Control Time. = 10,000 Erase/Program Cycles Hermetic Ceramic e 8 Equal Sectors of 64K bytes each e Any combination of sectors can be erased with m= Embedded Erase and Program Algorithms m= Hardware and Software Write Protection m= Page Program Operation and Internal Program OE A0-A18 SCE Block Diagram PGA Type Package(P1 & P5) & CQFP(F2) FWE1 SWE1 FWE3 SWE3 FWE4 SWE4 PIN DESCRIPTION FCE 1/O0-31 Data I/O A0-18 Address Inputs FWE1-4 | Flash Write Enables SWE1-4 | SRAM Write Enables 512K X 8 FLASH 512K x 8 FLASH 512K X 8 FLASH 512K xX 8 FLASH FCE Flash Chip Enable 128K x 8 SRAM 128K x 8 SRAM 128K xX 8 SRAM 128K xX 8 SRAM SCE SRAM Chip Enable OE Output Enable NC Not Connected Vec Power Supply GND Ground 1/00-7 1/08-15 1/016-23 1/024-31 Aeroflex Circuit Technology - Advanced Multichip Modules SCD3851 REV A 5/21/98Absolute Maximum Ratings Symbol Rating Range Units Te Case Operating Temperature -55 to +125 C Tsta Storage Temperature -65 to +150 C Ve Maximum Signal Voltage to Ground -0.5 to +7 Vv TL Maximum Lead Temperature (10 seconds) 300 C Parameter Flash Data Retention 10 Years Flash Endurance (Write/Erase Cycles) 10,000 Normal Operating Conditions Symbol Parameter Minimum Maximum Units Voc Power Supply Voltage +4.5 +5.5 Vv Vin Input High Voltage +2.2 Voc + 0.3 V Vit Input Low Voltage -0.5 +0.8 V Capacitance (Vin = OV, f = 1MHz, Ta = 25C) Symbol | Parameter Maximum Units Cao | Ao-Ais Capacitance 80 pF Coe | OE Capacitance 80 pF Cwet-4 | F/S Write Enable Capacitance 30 pF Cce |F/S Chip Enable Capacitance 50 pF Cio | \/Oo - 1/031 Capacitance 30 pF This parameter is guaranteed by design but not tested DC Characteristics (Vcc = 5.0V, Vss = OV, Te = -55C to +125C) Parameter Sym Conditions Min Max} Units Input Leakage Current lui |Voc = Max, Vin = 0 to Voc 10 |_ HA FCE = SCE =V,,, OE=V | IH> IH, 10 A Output Leakage Current LO Vour = 0 to Veg HJ SRAM Operating Supply Current x 32] | go [SCE = Vir, OE = Vin, f = 5MHZ, Voc = 500 A Mode COME) Max FCE = Vy m FCE = SCE = Viy, OE = Viy, f = SMHz | IH IH , 80 A Standby Current SB Voc = Max m SRAM Output Low Voltage VoL Jlop =8 MA, Vocg = Min, FCE = Viy 04) V SRAM Output High Voltage VoH |loy =-4.0 mA, , Veg = Min, FCE = Vij 2.4 Vv Flash Vcc Active Current for Read (1)| lcci |FCE = Vy, OE = Viy, SCE = Viy 260} mA Flash Vcc Active Current for Program = a= aE or Erase (2) g loco |FCE = V,,, OE = Vy, SCE = Vy 300] mA Flash Output Low Voltage VoL Jlop = 12 MA, Voc = Min, SCE = Viy 0.45) V Flash Output High Voltage Vout |loy =-2.5 mA, , Voc = Min, SCE =Vy, =| 0.85 x Voc V Flash Low Vcc Lock Out Voltage ViKo 3.2 4.2 Vv Notes: 1) The Icc current listed includes both the DC operating current and the frequency dependent component (at SMHz). The frequency component typically is less than 2mA/MHz, with OE at VIH 2) Icc active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = Vcc - 0.3V Aeroflex Circuit Technology 2 $CD3851 REV A 5/21/98 Plainview NY (516) 694-6700SRAM AC Characteristics (Vcc = 5.0V, Vss= OV, Tc = -55C to +125C) Read Cycle 025 035 Parameter Symbol Min Max Min Max Units Read Cycle Time tre 25 35 ns Address Access Time tan 25 35 ns Chip Select Access Time tace 25 35 ns Output Hold from Address Change tou ) 0 ns Output Enable to Output Valid tor 15 20 ns Chip Select to Output in Low Z * teLz ns Output Enable to Output in Low Z * toLz ) 0 ns Chip Deselect to Output in High Z * touz 12 20 ns Output Disable to Output in High Z * touz 12 20 ns * Parameters guaranteed by design but not tested Write Cycle 025 035 : Parameter Symbol Min Max Min Max Units Write Cycle Time twe 25 35 ns Chip Select to End of Write tow 20 25 ns Address Valid to End of Write taw 20 25 ns Data Valid to End of Write tow 15 20 ns Write Pulse Width twe 20 25 ns Address Setup Time tas ns Output Active from End of Write * tow ns Write to Output in High Z * twuz 10 20 ns Data Hold from Write Time tou ns Address Hold Time taH ns * Parameters guaranteed by design but not tested SRAM Truth Table Mode SCE OE SWE Data I/O Power Standby H x x High Z Standby Read L L H Data Out Active Output Disable L H H High Z Active Write L x L Data In Active Aeroflex Circuit Technology SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700Timing Diagrams SRAM Read Cycle Timing Diagrams Read Cycle 1 (SCE = OE = VIL, SWE = Vin) tac Ao-18 =\!_ ta tox Dio Previous Data Valid Data Valid Read Cycle 2 (SWE = Vi) tac | Ao-18 *K a TAA SCE tace TCHZ tclz SEE NOTE _ SEE NOTE OE TOHZ toe SEE NoTE to.z> SEE NOTE Duo High Z Data Valid UNDEFINED LT DONT CARE Write Cycle Timing Diagrams Write Cycle (SWE Controlled, OE = Vix) x twc Ao-18 tWHZ-~ SEE NOTE Duo Data Valid Write Cycle (SCE Controlled, OE = VIH ) twc twRe: >+ SWE =< tbw tDH Dro { Data Valid Note: Guaranteed by design, but not tested. AC Test Circuit Current Source | Io. To Device Under Test sae T Vz ~ 1.5 V (Bipolar Supply) l. Current Source Notes: AC Test Conditions Parameter Typical Units Input Pulse Level 0-3.0 Vv Input Rise and Fall 5 ns Input and Output Timing Reference Level 1.5 Vv 1) Vz is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO = 75Q. 4) VZ is typically the midpoint of VOH and VoL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance. Aeroflex Circuit Technology SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700Flash AC Characteristics Read Only Operations (Vcc = 5.0V, Vss = OV, Tc = -55C to +125C) Parameter Symbol ~60 770 90 Units JEDEC Standd| Min Max} Min Max| Min Max Read Cycle Time TAVAV tre 60 70 90 ns Address Access Time tavav tacc 60 70 90 ns Chip Enable Access Time tELav tce 60 70 90 ns Output Enable to Output Valid taLav toe 30 35 35 ns Chip Enable to Output High Z (1) tEHOZ tor 20 20 20 ns Output Enable High to Output High 2(1) taHaz tor 20 20 20 ns Output Hold from Address, CE or OE Change, Whichever is First taxax tou 0 0) 0) ns Note 1. Guaranteed by design, but not tested Flash AC Characteristics Write / Erase / Program Operations, FWE Controlled (Vcc = 5.0V, Vss = OV, Tc = -55C to +125C) Parameter Symbol ~60 770 90 Units JEDEC Standd | Min Max| Min Max| Min Max Write Cycle Time tavac twe 60 70 90 ns Chip Enable Setup Time tELWL tcE 0 0 0 ns Write Enable Pulse Width tWLWH twp 40 45 45 ns Address Setup Time TAVWL tas 0 0 0 ns Data Setup Time tpvwH tos 40 45 45 ns Data Hold Time twHDXx {DH 0 0 0 ns Address Hold Time tWLAX tAH 45 45 45 ns Write Enable Pulse Width High tWHWL twPH 20 20 20 ns Duration of Byte Programming Operation tWHWH1 14 | TYP| 14 ] TYP] 14 | TYP ys Sector Erase Time twHWH2 30 30 30 Sec Read Recovery Time before Write TaHWL 0 0 0 ys Vcc Setup Time tvcE 50 50 50 ys Chip Programming Time 50 50 50 Sec Chip Enable Hold Time toEH 1 10 10 10 ns Chip Erase Time tWHWH3 120 120 120 Sec 1. Toggle and Data Polling only. Flash AC Characteristics Write / Erase / Program Operations, FCE Controlled (Vcc = 5.0V, Vss = OV, Tc = -55C to +125C) Parameter Symbol ~60 70 ~90 Units JEDEC Standd | Min Max} Min Max| Min Max Write Cycle Time tavac twe 60 70 90 ns Write Enable Setup Time tWLeL tws 0 0 0 ns Chip Enable Pulse Width tELEH tep 40 45 45 ns Address Setup Time TAVEL tas 0 0 0 ns Data Setup Time {tDVEH tos 40 45 45 ns Data Hold Time tEHDX {oH 0 0 0 ns Address Hold Time tELAX tAH 45 45 45 ns Chip Enable Pulse Width High tEHEL tcPH 20 20 20 ns Duration of Byte Programming tWHWH1 14 | TYP| 14 ] TYP] 14 | TYP ys Sector Erase Time tWHWH2 30 30 30 Sec Read Recovery Time T@HEL ) ) ) ns Chip Programming Time 50 50 50 Sec Chip Erase Time tWHWH3 120 120 120 Sec 5 Aeroflex Circuit Technology SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700AC Waveforms for Flash Memory Read Operations tre Addresses X Addresses Stable X tace. > FCE \ | \ +> tor OE \ V \ FWE _/ \L tce > toH>| High Z Outputs g Output Valid Write/Erase/Program Operation for Flash Memory, FWE Controlled Data Polling Addresses twHw1 > b| f* tou Data prot 5.0V Notes: 1. PAis the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the Output of the complement of the data written to the deviced. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Aeroflex Circuit Technology 6 $CD3851 REV A 5/21/98 Plainview NY (516) 694-6700AC Waveforms Chip/Sector Erase Operations for Flash Memory r| e tan Data Polling Addresses X ssssH 2AAAH 5555H XK 5555H X 2AAAH x SA x tas} a en a ee j taHwi+> OE j \ aa # twp me [NF AS \S \S VS NS Te -\ -\ \ \ Data / LAF AAH \__/ 55H \__/ 80H \__/AAH \__/55H \__/10H/30H ~| letpos Vec L tvcE>} Notes: 1. SAis the sector address for sector erase. AC Waveforms for Data Pollin During Embedded Algorithm Operations for Flash Memory =, be-tDF-| toEH > be twHwH1 or 2. _ DQO0-DQ6 DQO-DQ6z=Invalid DQ7= High Z Valid Data * DQ7=Valid Data (The device has completed the Embedded operation). Aeroflex Circuit Technology 7 SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700Write/Erase/Program Operation for Flash Memory, FCE Controlled Data Polling Addresses X 5555H X PA be two rr] [tase TAH-m} + twHwH1 + =) d Data / 5.0V Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the Output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Aeroflex Circuit Technology 8 $CD3851 REV A 5/21/98 Plainview NY (516) 694-6700Function 1/08 /O9 1/O10 A14 A16 Ait Ao A18 /Oo O41 1/02 FWE2 SWE2 GND O11 A10 Ag Rloalmlalolele[n[elal[a]oe]r [= Pin Numbers & Functions 66 Pins PGA-T Function Pin # A15 Vcc FCE SCE 1/03 1/015 014 1/013 1/012 OE A17 FWE1 1/07 1/06 O05 1/04 1/024 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Function 1/025 1/026 A7 A12 SWE1 A13 A8 //016 /O017 1/018 Vec SWEa4 FWEa4 1/027 A4 A5 A6 Function FWE3 SWE3 GND O19 1/031 1/030 1/029 1/028 At A2 A3 "P1" 1.385" SQ PGA Type Package Standard (with shoulders on Pins 1, 11, 56 & 66) "P5" 1.385" SQ PGA Type Special Order Package (without shoulders) Side View (P1) .245 ~ MAX > 025 .035 -100 __| typ + |b 145 MIN -020 .016 All dimensions in inches Side View (P5) Bottom View (P1 & P5) 1.400 SQ MAX 1.000 TYP .600 ' Pin 1 TYP a or OROKO) OROKO) | QO@ | 1.000 -O@-@_-++_@@@+ svp @o@O@ @@ @ O Pin 11 Aeroflex Circuit Technology SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700Pin Numbers & Functions 68 Pins Dual-Cavity CQFP Pin # Function Pin # Function Pin # Function Pin # Function 1 GND 18 GND 35 OE 52 GND 2 SWE3 19 1/08 36 SWE2 53 Fl/O23 3 A5 20 /O9 37 A17 54 Fl/O22 4 A4 21 1/010 38 FWE2 55 Fl/O21 5 A3 22 O11 39 FWE3 56 Fl/O20 6 A2 23 O12 40 FWE4 57 Fl/O19 7 At 24 1/013 41 A18 58 Fl/O18 8 Ao 25 O14 42 SCE 59 Fl/O17 9 NC 26 O15 43 SWE1 60 Fl/O16 10 /Oo 27 Vee 44 FI/O31 61 Vcc 11 /O1 28 A11 45 Fl/O30 62 A10 12 /O2 29 A12 46 Fl/O29 63 AQ 13 1/03 30 A13 47 Fl/O28 64 A8 14 1/04 31 A14 48 Fl/O27 65 A7 15 1/05 32 A15 49 Fl/O26 66 AG 16 1/06 33 A16 50 FI/O25 67 FWE1 17 /O7 34 FCE 51 Fl/O24 68 SWE4 Package Outline Dual-Cavity CQFP "F2" Top View -990 SQ +.010 |_____ .890 SQ. ______}1 y Ping MAX Pin 61> 200 MAX ~~ + .010 REF esp MIDI OOOO | oo Lt E- ( = a #502 a +.002 a - ft a a a a oo I +3/-3 a \ 010 +.005 = =o | ob fee i {ft TYP . TI i. 5 \ Je i} Detail A Pin ool Teh 44 ay : Pin 27 | 800 REF All dimensions in inches VOU UU Pin 43 *s 222-7 \_ gee petal A *.180 MAX available, call factory for details Aeroflex Circuit Technology 10 SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700(\EROFLEX CIRCUIT TECHNOLOGY, Ordering Information Model Number DESC Part Number Speed Package ACT-SF41632N-26P 1X TBD 25(S) / 60(F) ns 1.385"sq PGA-Type ACT-SF41632N-37P1X TBD 35(S) / 70(F) ns 1.385"sq PGA-Type ACT-SF41632N-39P 1X TBD 35(S) / 90(F) ns 1.385"sq PGA-Type ACT-SF41632N-26F2X TBD 25(S) / 60(F) ns .88"sq CQFP ACT-SF41632N-37F2X TBD 35(S) / 70(F) ns .88"sq CQFP ACT-SF41632N-39F2X TBD 35(S) / 90(F) ns .88"sq CQFP Note: (S) = Speed for SRAM, (F) = Speed for FLASH Part Number Breakdown ACT- SF 416 32 N 26 Pl M Aeroflex Circuit _ ] Technology Memory Type SF = SRAM Flash Combo Module Memory Depth, Locations 4=4M SRAM, 16 = 16M Flash Memory Width, Bits Screening C = Commercial Temp, 0C to +70C | = Industrial Temp, -40C to +85C T = Military Temp, -55C to +125C M = Military Temp, -55C to +125C Screened * Q = MIL-PRF-38534 ComplianvSMD Pinout Options Package Types & Sizes N = None Surface Mount Packages F2 =0.88"SQ 68 Leads Dual-Cavity CQFP Thru-Hole Packages Memory Speed (Code) P1 = 1.385"SQ PGA 66 Pins W/Shoulder 26 = 25ns SRAM & 60ns FLASH 37 = 35ns SRAM & 70ns FLASH 39 = 35ns SRAM & 90ns FLASH P5 = 1.385"SQ PGA 66 Pins WO/Shoulder * Screened to the individual test methods of MIL-STD-883 Specifications subject to change without notice. Aeroflex Circuit Technology 35 South Service Road Plainview New York 11830 Aeroflex Circuit Technology Telephone: (516) 694-6700 (516) 694-6715 FAX: Toll Free Inquiries: 1-(800) 843-1553 11 SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700