WS512K32-XXX 512Kx32 SRAM MODULE, SMD 5962-94611 FEATURES Access Times of 15, 17, 20, 25, 35, 45, 55ns TTL Compatible Inputs and Outputs Packaging 5 Volt Power Supply Low Power CMOS * 66 pin, PGA Type, 1.075" square, Hermetic Ceramic HIP (Package 400). Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation * 68 lead, 40mm Hermetic Low Profile CQFP, 3.5mm (0.140") (Package 502)1 Weight * 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880") square (Package 510) 3.56mm (0.140") height. WS512K32N-XH1X - 13 grams typical WS512K32-XG2UX - 8 grams typical WS512K32-XG4TX1 - 20 grams typical WS512K32-XG2LX - 8 grams typical * 68 lead, Hermetic CQFP (G2L), 22.4mm (0.880") square, 5.08mm (0.200") high (Package 528). Organized as 512Kx32, User Configurable as 1Mx16 or 2Mx8 * This product is subject to change without notice. Note 1: Package Not Recommended For New Design Commercial, Industrial and Military Temperature Ranges FIGURE 1 - PIN CONFIGURATION FOR WS512K32N-XH1X Top View 1 12 34 45 56 I/O8 WE2# I/O15 I/O24 VCC I/O31 I/O9 CS2# I/O14 I/O25 CS4# I/O30 I/O10 GND I/O13 I/O26 WE4# I/O29 A13 I/O11 I/O12 A6 I/O27 I/O28 A14 A10 OE# A7 A3 A0 A15 A11 A18 NC A4 A1 A16 A12 WE1# A8 A5 A2 A17 VCC I/O7 A9 WE3# I/O23 I/O0 CS1# I/O6 I/O16 CS3 I/O22 I/O1 NC I/O5 I/O17 GND I/O21 I/O4 I/O18 I/O2 11 23 Pin Description I/O3 22 33 I/O19 44 I/O0-31 A0-18 WE1-4# CS1-4# OE# VCC GND NC Block Diagram WE1# CS1# WE2# CS2# WE3# CS3# WE4# CS4# OE# A0-18 512K X 8 I/O20 55 Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected 8 66 I/O0 - 7 512K X 8 8 I/O8 - 15 512K X 8 8 I/O16 - 23 512K X 8 8 I/O24 - 31 Microsemi Corporation reserves the right to change products or specifications without notice. May 2014 Rev. 20 (c) 2014 Microsemi Corporation. All rights reserved. 1 Microsemi Corporation * (602) 437-1520 * www.microsemi.com/pmgp WS512K32-XXX FIGURE 2 - PIN CONFIGURATION FOR WS512K32-XG4TX1 Top View Pin Description NC A0 A1 A2 A3 A4 A5 CS3# GND CS4# WE# A6 A7 A8 A9 A10 VCC I/O0-31 A0-18 WE# CS1-4# OE# VCC GND NC 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected Block Diagram CS1# WE# OE# A0-18 CS2# 512K X 8 512K X 8 CS3# 512K X 8 CS4# 512K X 8 8 NC A18 NC NC NC NC A15 A16 CS1# OE# CS2# A17 A13 A14 VCC A11 A12 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 8 I/O8 - 15 I/O0 - 7 8 I/O16 - 23 8 I/O24 - 31 Note 1: Package Not Recommended For New Design FIGURE 3 - PIN CONFIGURATION FOR WS512K32-XG2UX AND WS512K32-XG2LX Pin Description NC A0 A1 A2 A3 A4 A5 CS3# GND CS4# WE1# A6 A7 A8 A9 A10 VCC Top View I/O0-31 A0-18 WE1-4# CS1-4# OE# VCC GND NC 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 Block Diagram WE1# CS1# WE2# CS2# WE3# CS3# WE4# CS4# OE# A0-18 512K X 8 VCC A11 A12 A13 A14 A15 A16 CS1# OE# CS2# A17 WE2# WE3# WE4# A18 NC NC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected 8 I/O0 - 7 512K X 8 8 I/O8 - 15 512K X 8 8 I/O16 - 23 512K X 8 8 I/O24 - 31 Microsemi Corporation reserves the right to change products or specifications without notice. May 2014 Rev. 20 (c) 2014 Microsemi Corporation. All rights reserved. 2 Microsemi Corporation * (602) 437-1520 * www.microsemi.com/pmgp WS512K32-XXX ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Junction Temperature Supply Voltage Symbol TA TSTG VG TJ VCC Min -55 -65 -0.5 -0.5 TRUTH TABLE Max +125 +150 VCC+0.5 150 7.0 Unit C C V C V CS H L L L OE X L H X WE X H H L Mode Standby Read Out Disable Write Data I/O High Z Data Out High Z Data In Power Standby Active Active Active CAPACITANCE RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temp (Mil) Symbol VCC VIH VIL TA Min 4.5 2.2 -0.5 -55 Max 5.5 VCC + 0.3 +0.8 +125 Ta = +25C Unit V V V C Parameter OE# capacitance WE1-4# capacitance HIP (PGA) CQFP G4T CQFP G2U/G2L CS1-4# capacitance Data I/O capacitance Address input capacitance Symbol COE CWE CCS CI/O CAD Conditions VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VI/O = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz Max 50 20 50 20 20 20 50 Unit pF pF pF pF pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Symbol Conditions Min Max Units Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 A Output Leakage Current ILO CS# = VIH, OE# = VIH, VOUT = GND to VCC 10 A ICC x 32 CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5 660 mA Standby Current Operating Supply Current x 32 Mode ISB CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5 80 mA Output Low Voltage VOL IOL = 6mA for 15 - 35ns, IOL = 2.1mA for 45 - 55ns, VCC = 4.5 0.4 V Output High Voltage VOH IOH = -4.0mA for 15 - 35ns, IOH = -1.0mA for 45 - 55ns, VCC = 4.5 2.4 V NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V DATA RETENTION CHARACTERISTICS (Ta = -55C to +125C) Parameter Symbol Conditions Min Max CS VCC - 0.2V 2.0 Units 5.5 V Data Retention Current ICCDR1 VCC = 3V 28 mA Low Power Data Retention Current (WS512K32L-XXX) ICCDR2 VCC = 3V 16 mA Data Retention Supply Voltage VDR Microsemi Corporation reserves the right to change products or specifications without notice. May 2014 Rev. 20 (c) 2014 Microsemi Corporation. All rights reserved. 3 Microsemi Corporation * (602) 437-1520 * www.microsemi.com/pmgp WS512K32-XXX AC CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Read Cycle Read Cycle Time Address Access Time Output Hold from Address Change Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z -15 Symbol tRC tAA tOH tACS tOE tCLZ1 tOLZ1 tCHZ1 tOHZ1 Min 15 -17 Max Min 17 15 0 -20 Max Min 20 17 Min 25 4 0 12 12 -55 Max Max 55 0 45 25 4 0 12 12 Min 55 45 35 25 2 0 12 12 Min 45 0 25 12 2 0 12 12 0 20 10 2 0 -45 Max 35 0 17 9 Min 35 25 0 15 8 -35 Max 20 0 2 0 -25 Max 55 25 4 0 15 15 20 20 20 20 Units ns ns ns ns ns ns ns ns ns 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Write Cycle Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Address Hold Time Output Active from End of Write Write Enable to Output in High Z Data Hold Time -15 Symbol tWC tCW tAW tDW tWP tAS tAH tOW1 tWHZ1 tDH Min 15 13 13 10 13 2 0 2 -17 Max Min 17 15 15 11 15 2 0 2 8 0 -20 Max Min 20 15 15 12 15 2 0 3 9 -25 Max Min 25 17 17 13 17 2 0 4 11 0 0 -35 Max Min 35 25 25 20 25 2 0 4 13 0 -45 Max Min 45 35 35 25 35 2 5 5 -55 Max 15 0 Min 55 50 50 25 40 2 5 5 20 0 Max 20 0 Units ns ns ns ns ns ns ns ns ns ns 1. This parameter is guaranteed by design but not tested. 2. The Address Setup Time of minimum 2ns is for the G2U, G1U and H1 packages. tAS minimum for the G4T package is 0ns. FIGURE. 4 - AC TEST CIRCUIT AC Test Conditions Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level IOL Current Source VZ 1.5V (Bipolar Supply) D.U.T. Ceff = 50 pf Current Source Typ VIL = 0, VIH = 3.0 5 1.5 1.5 Unit V ns V V Notes: V Z is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . V Z is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. IOH Microsemi Corporation reserves the right to change products or specifications without notice. May 2014 Rev. 20 (c) 2014 Microsemi Corporation. All rights reserved. 4 Microsemi Corporation * (602) 437-1520 * www.microsemi.com/pmgp WS512K32-XXX FIGURE 5 - TIMING WAVEFORM - READ CYCLE CS# OE# READ CYCLE 2, (CS# = OE# = VIL, WE# = VIH) READ CYCLE 2 (WE# = VIH) FIGURE 6 - WRITE CYCLE - WE# CONTROLLED CS# WE# WRITE CYCLE 2, CS# CONTROLLED FIGURE 7 - WRITE CYCLE - CS# CONTROLLED CS# WE# WRITE CYCLE 2, CS# CONTROLLED Microsemi Corporation reserves the right to change products or specifications without notice. May 2014 Rev. 20 (c) 2014 Microsemi Corporation. All rights reserved. 5 Microsemi Corporation * (602) 437-1520 * www.microsemi.com/pmgp WS512K32-XXX PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1) 4.60 (0.181) MAX ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES PACKAGE 502: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G4T)1 Note 1: Package Not Recommended For New Design ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES Microsemi Corporation reserves the right to change products or specifications without notice. May 2014 Rev. 20 (c) 2014 Microsemi Corporation. All rights reserved. 6 Microsemi Corporation * (602) 437-1520 * www.microsemi.com/pmgp WS512K32-XXX PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U) ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES PACKAGE 528: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2L) 25.15 (0.990) 0.25 (0.010) MAX 5.10 (0.200) MAX 22.36 (0.880) 0.25 (0.010) MAX 0.25 (0.010) 0.10 (0.002) 0.23 (0.009) REF 24.0 (0.946) 0.25 (0.010) R 0.127 (0.005) 1.37 (0.054) MIN 0.004 2O / 9O 1.01 (0.040) 0.13 (0.005) 1.27 (0.050) TYP 0.38 (0.015) 0.05 (0.002) 20.31 (0.800) REF 0.940" TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES Microsemi Corporation reserves the right to change products or specifications without notice. May 2014 Rev. 20 (c) 2014 Microsemi Corporation. All rights reserved. 7 Microsemi Corporation * (602) 437-1520 * www.microsemi.com/pmgp WS512K32-XXX ORDERING INFORMATION W S 512K 32 X - XXX X X X MICROSEMI CORPORATION SRAM ORGANIZATION, 512Kx32 User configurable as 1Mx16 or 2Mx8 IMPROVEMENT MARK: Blank = Standard Power N = No Connect at pin 21 and 39 in HIP for Upgrades L = Low Power Data Retention ACCESS TIME (ns) PACKAGE TYPE: H1 = Ceramic Hex-In-line Package, HIP (Package 400) G2U = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510) G2L = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 528) G4T1 = 40mm Low Profile CQFP (Package 502) DEVICE GRADE: Q = MIL-PRF-38534 Class H Compliant M = Military Screened I = Industrial -55C to +125C -40C to 85C C = Commercial 0C to +70C LEAD FINISH: Blank = Gold plated leads A = Solder dip leads Note 1: Package Not Recommended For New Design Microsemi Corporation reserves the right to change products or specifications without notice. May 2014 Rev. 20 (c) 2014 Microsemi Corporation. All rights reserved. 8 Microsemi Corporation * (602) 437-1520 * www.microsemi.com/pmgp WS512K32-XXX DEVICE TYPE SPEED PACKAGE SMD NO. 512K x 32 SRAM Module 55ns 66 pin HIP (H1) 5962-94611 05HTX 512K x 32 SRAM Module 45ns 66 pin HIP (H1) 5962-94611 06HTX 512K x 32 SRAM Module 35ns 66 pin HIP (H1) 5962-94611 07HTX 512K x 32 SRAM Module 25ns 66 pin HIP (H1) 5962-94611 08HTX 512K x 32 SRAM Module 20ns 66 pin HIP (H1) 5962-94611 09HTX 512K x 32 SRAM Module 17ns 66 pin HIP (H1) 5962-94611 10HTX 512K x 32 SRAM Module 15ns 66 pin HIP (H1) 5962-94611 19HTX 512K x 32 SRAM Module 55ns 68 lead CQFP Low Profile (G4T)1 5962-94611 05HYX 512K x 32 SRAM Module 45ns 68 lead CQFP Low Profile (G4T)1 5962-94611 06HYX 512K x 32 SRAM Module 35ns 1 68 lead CQFP Low Profile (G4T) 5962-94611 07HYX 512K x 32 SRAM Module 25ns 68 lead CQFP Low Profile (G4T)1 5962-94611 08HYX 512K x 32 SRAM Module 20ns 1 68 lead CQFP Low Profile (G4T) 5962-94611 09HYX 512K x 32 SRAM Module 17ns 68 lead CQFP Low Profile (G4T)1 5962-94611 10HYX 512K x 32 SRAM Module 55ns 68 lead CQFP (G2U) 5962-94611 05HMX 512K x 32 SRAM Module 45ns 68 lead CQFP (G2U) 5962-94611 06HMX 512K x 32 SRAM Module 35ns 68 lead CQFP (G2U) 5962-94611 07HMX 512K x 32 SRAM Module 25ns 68 lead CQFP (G2U) 5962-94611 08HMX 512K x 32 SRAM Module 20ns 68 lead CQFP (G2U) 5962-94611 09HMX 512K x 32 SRAM Module 17ns 68 lead CQFP (G2U) 5962-94611 10HMX 512K x 32 SRAM Module 15ns 66 pin HIP (H1) 5962-94611 19HMX 512K x 32 SRAM Module 55ns 68 lead CQFP (G2L) 5962-94611 05HAX 512K x 32 SRAM Module 45ns 68 lead CQFP (G2L) 5962-94611 06HAX 512K x 32 SRAM Module 35ns 68 lead CQFP (G2L) 5962-94611 07HAX 512K x 32 SRAM Module 25ns 68 lead CQFP (G2L) 5962-94611 08HAX 512K x 32 SRAM Module 20ns 68 lead CQFP (G2L) 5962-94611 09HAX 512K x 32 SRAM Module 17ns 68 lead CQFP (G2L) 5962-94611 10HAX 512K x 32 SRAM Module 15ns 66 pin HIP (H1) 5962-94611 19HAX Note 1: Package Not Recommended For New Design Microsemi Corporation reserves the right to change products or specifications without notice. May 2014 Rev. 20 (c) 2014 Microsemi Corporation. All rights reserved. 9 Microsemi Corporation * (602) 437-1520 * www.microsemi.com/pmgp WS512K32-XXX Document Title 512K x 32 SRAM Multi-Chip Package Revision History Rev # History Release Date Status Rev 0 Initial October 1996 Preliminary Rev 1 Change (Pg. 1, 3) September 2002 Advanced November 1997 Preliminary February 1998 Preliminary April 1998 Preliminary December 1998 Preliminary March 1999 Preliminary May 1999 Final June 1999 Final November 1999 Final 1.1 Change Operation Supply Current from 520mA To 540mA 1.2 Change Data Retention Current from 12mA to 28mA. Change (Pg. 1, 2, 8, 10, 11) 1.1 Delete G2 Package Change (Pg. 1, 9) 1.1 Add SMD Case Outline M for G2T Change (Pg. 1, 3, 8) 1.1 Remove Low Capacitance package option Change (Pg. 1, 6, 8) 1.1 Add H1 package Change (Pg. 1, 4, 6, 9, 10) 1.1 Remove H2 package 1.2 Change logo to WEDC logo Rev 2 Change (Pg. 1, 3, 4, 8) 2.1 Change status from Preliminary to Final 2.2 Make package descriptions consistent 2.3 Add 15ns as available in Commercial and Industrial Temperatures only. Rev 4 Change (Pg. 1, 3) 4.1 Change Standby Current (Isb) from 60mA to 80mA Maximum Rev 5 Change (Pg. 1, 2, 3, 4, 7, 8) 5.1 Add G1U package Rev 6 Change (Pg. 1, 8) 6.1 Change G1U lead foot length from 0.64mm to 0.84mm Ref February 2000 Final Rev 7 Change (Pg. 1, 3, 9) 7.1 Change Operating Supply Current from 540mA to 660mA Maximum October 2000 Final 7.2 Add Low Power Data Retention Current of 16mA to Data Retention Characteristics table 7.3 Add Low Power Data Retention (L) option to Ordering Information Microsemi Corporation reserves the right to change products or specifications without notice. May 2014 Rev. 20 (c) 2014 Microsemi Corporation. All rights reserved. 10 Microsemi Corporation * (602) 437-1520 * www.microsemi.com/pmgp WS512K32-XXX Document Title 512K x 32 SRAM Multi-Chip Package Revision History Rev # History Release Date Status Rev 8 October 2001 Final November 2001 Final August 2002 Final February 2002 Final May 2003 Final December 2003 Final May 2004 Final November 2004 Final March 2006 Final May 2006 Final November 2010 Final September 2011 Final May 2014 Final Change (Pg. 1, 2, 6, 7, 9, 10) 8.1 Change G2T and G4T package status to Not Recommended For New Design Rev 9 Change (Pg. 1, 2, 3, 8, 9, 10) 9.1 Add G1T package 9.2 Remove `Hi-Reliability Product' Title Rev 10 Change (Pg. 1, 2, 3, 4, 7, 8, 9, 10, 11) 10.1 Remove G2T package 10.2 Add G2U package 10.3 Remove `Package to be Developed' note for G4T Rev 11 Change (Pg. 1,2,4,8,10,11,13) 11.1 Change G1U package status to Not Recommended For New Designs Rev 12 Change (Pg. 1,2,3,7,8,10,11,13) 12.1 Add G2L package Rev 13 Change (Pg. 1,2,3,7,8,10,11,13) 13.1 Remove all reference to G1U package 13.2 Remove all reference to G1T package Rev 14 Change (Pg. 1,3,11) 14.1 Change IOL to 6mA for 15-35 ns Rev 15 Change (Pg. 1,4,11) 15.1 Add 15ns for Military Temperature Rev 16 Change (Pg. 1, 6, 11) 16.1 Correct thickness to 0.181"per PCN#140A00143 Rev 17 Change ( Pg. 1, 2, 11) 17.1 Correct pinout of G4T 17.2 Correct G2L foot length Rev 18 Change (Pg. 6) 18.1 Change drawing on HIP to generic square drawing Rev 19 Change (Pg. 8) 19.1 Swap positions with 'Access Time' and 'Improvement Mark' in the 'Ordering Information' chart Rev 20 Change (Pg. 8) 20.1 Changed Device Grade "Q" description from "MIL-STD-883 Compliant" to "MIL-PRF-38534 Class H Compliant." Microsemi Corporation reserves the right to change products or specifications without notice. May 2014 Rev. 20 (c) 2014 Microsemi Corporation. All rights reserved. 11 Microsemi Corporation * (602) 437-1520 * www.microsemi.com/pmgp