MC74HC74A Dual D Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS The MC74HC74A is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip-flops with individual Set, Reset, and Clock inputs. Information at a D-input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip-flop. The Set and Reset inputs are asynchronous. * * * * * * * http://onsemi.com MARKING DIAGRAMS 14 PDIP-14 N SUFFIX CASE 646 1 Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 128 FETs or 32 Equivalent Gates 14 SOIC-14 D SUFFIX CASE 751A 14 CLOCK 1 2 5 3 6 Q1 Q1 PIN ASSIGNMENT 4 SET 1 PIN 14 = VCC PIN 7 = GND 13 RESET 2 9 12 DATA 2 Q2 8 11 CLOCK 2 RESET 1 1 14 VCC DATA 1 2 13 RESET 2 CLOCK 1 3 12 DATA 2 SET 1 4 11 CLOCK 2 Q1 5 10 SET 2 Q1 6 9 Q2 GND 7 8 Q2 Q2 10 SET 2 HC 74A ALYW TSSOP-14 DT SUFFIX CASE 948G 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week 1 DATA 1 HC74A AWLYWW 1 LOGIC DIAGRAM RESET 1 MC74HC74AN AWLYYWW FUNCTION TABLE Inputs Outputs Set Reset Clock Data L H L H H H H H H L L H H H H H X X X L H X X X H L X X X Q Q H L L H H* H* H L L H No Change No Change No Change ORDERING INFORMATION Device *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. Semiconductor Components Industries, LLC, 2000 March, 2000 - Rev. 8 1 Package Shipping MC74HC74AN PDIP-14 2000 / Box MC74HC74AD SOIC-14 55 / Rail MC74HC74ADR2 SOIC-14 2500 / Reel MC74HC74ADT TSSOP-14 96 / Rail MC74HC74ADTR2 TSSOP-14 2500 / Reel Publication Order Number: MC74HC74A/D MC74HC74A IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0 V Vin DC Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air, 750 500 450 mW Tstg Storage Temperature - 65 to + 150 _C Iin TL Plastic DIP SOIC Package TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) 260 300 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III III II IIII IIIIIIIIIIIIIII IIIII IIIIIIIIIIII IIII IIIIIIIII IIIIIIIII IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIIIIIIII IIII IIIIIIIII IIIIIIIII IIII IIII III v IIII v III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII III IIII III v IIII IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min DC Supply Voltage (Referenced to GND) Max Unit 2.0 6.0 V 0 VCC V - 55 + 125 _C 0 0 0 0 1000 600 500 400 ns DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figures 1, 2, 3) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V - 55 to 25_C 85_C 125_C Unit VIH Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| 20 A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 VOH Vin = VIH or VIL |Iout| |Iout| |Iout| 2.4 mA 4.0 mA 5.2 mA http://onsemi.com 2 MC74HC74A IIII IIIIIIIII IIIIIIIII IIII IIIIIIIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII IIIIIIIII v v III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII III IIII III v IIII IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIIIIIIII III IIII III IIII IIIII IIIIIIIIIIIIIIII IIII IIIIIIIII III v IIII v III IIIII IIIIIIIIIIIIIIII IIII IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol VOL Parameter Test Conditions Maximum Low-Level Output Voltage Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| |Iout| |Iout| Iin ICC 2.4 mA 4.0 mA 5.2 mA VCC V - 55 to 25_C 2.0 4.5 6.0 85_C 125_C 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 Unit V Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 A Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 A 6.0 2.0 20 80 A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter VCC V - 55 to 25_C 85_C 125_C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 3.0 4.5 6.0 6.0 15 30 35 4.8 10 24 28 4.0 8.0 20 24 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4) 2.0 3.0 4.5 6.0 100 75 20 17 125 90 25 21 150 120 30 26 ns tPLH, tPHL Maximum Propagation Delay, Set or Reset to Q or Q (Figures 2 and 4) 2.0 3.0 4.5 6.0 105 80 21 18 130 95 26 22 160 130 32 27 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns Maximum Input Capacitance -- 10 10 10 pF Cin NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 32 pF 2 * Used to determine the no-load dynamic power consumption: P D = C PD V CC f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). CPD Power Dissipation Capacitance (Per Flip-Flop)* http://onsemi.com 3 MC74HC74A IIIII IIIIIIIIIIIIIIII IIII IIIIIIIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIIIIIII v v IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III TIMING REQUIREMENTS (Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter VCC V - 55 to 25_C 85_C 125_C Unit tsu Minimum Setup Time, Data to Clock (Figure 3) 2.0 3.0 4.5 6.0 80 35 16 14 100 45 20 17 120 55 24 20 ns th Minimum Hold Time, Clock to Data (Figure 3) 2.0 3.0 4.5 6.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 ns Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2) 2.0 3.0 4.5 6.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 3.0 4.5 6.0 60 25 12 10 75 30 15 13 90 40 18 15 ns tw Minimum Pulse Width, Set or Reset (Figure 2) 2.0 3.0 4.5 6.0 60 25 12 10 75 30 15 13 90 40 18 15 ns tr, tf Maximum Input Rise and Fall Times (Figures 1, 2, 3) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns trec http://onsemi.com 4 MC74HC74A SWITCHING WAVEFORMS tf CLOCK tw tr VCC 90% 50% 10% tw GND Q or Q GND tPHL 50% Q OR Q 1/fmax tPLH tPHL tPLH 90% 50% 10% 50% Q OR Q tTLH VCC 50% SET OR RESET trec tTHL VCC 50% CLOCK Figure 1. GND Figure 2. TEST POINT VALID DATA VCC 50% OUTPUT GND tsu DEVICE UNDER TEST th VCC CL* 50% CLOCK GND Figure 3. *Includes all probe and jig capacitance Figure 4. EXPANDED LOGIC DIAGRAM SET 4, 10 2, 12 5, 9 Q DATA 3, 11 CLOCK 6, 8 Q 1, 13 RESET http://onsemi.com 5 MC74HC74A PACKAGE DIMENSIONS PDIP-14 N SUFFIX CASE 646-06 ISSUE L 14 8 1 7 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. B A F DIM A B C D F G H J K L M N L C J N H G D SEATING PLANE K M INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 SOIC-14 D SUFFIX CASE 751A-03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 -B- 1 P 7 PL 0.25 (0.010) 7 G B M M R X 45 _ C F -T- SEATING PLANE D 14 PL 0.25 (0.010) M K M T B S A S http://onsemi.com 6 J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 MC74HC74A PACKAGE DIMENSIONS TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S S N 2X 14 L/2 0.25 (0.010) 8 M B -U- L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K EE CC CC EE A -V- K1 J J1 SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E http://onsemi.com 7 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HC74A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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