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KH29LV400C T/B
4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
• Ready/Busy# pin (RY/BY#)
- Provides a hardware method of detecting program or
erase operation completion
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors
• CFI (Common Flash Interface) compliant
- Flash device parameters stored on the device and
provide the host system to access
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Package type:
- 48-pin TSOP
- All Pb-free devices are RoHS Compliant
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
• 20 years data retention
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 524,288 x 8/262,144 x 16 switchable
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 70/90ns
• Low power consumption
- 30mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte/word Programming (9us/11us typical)
- Sector Erase (Sector structure 16K-Byte x 1,
8K-Byte x 2, 32K-Byte x1, and 64K-Byte x7)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
• Status Reply
- Data# Polling & Toggle bit for detection of program
and erase operation completion
GENERAL DESCRIPTION
The KH29LV400C T/B is a 4-mega bit Flash memory
organized as 512K bytes of 8 bits or 256K words of 16
bits. MXIC's Flash memories offer the most cost-effec-
tive and reliable read/write non-volatile random access
memor y. The KH29LV400C T/B is packaged in 44-pin
SOP, 48-pin TSOP and 48-ball CSP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
The standard KH29LV400C T/B offers access time as
fast as 55ns, allowing operatio n of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the KH29LV400C T/B has separate chip enable
(CE#) and o utput enable (OE#) co ntrols.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and pro gramming. The
KH29LV400C T/B uses a co mmand register to manage
this functio nality . The command register allows fo r 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and pro gram cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The KH29LV400C T/B uses a 2.7V~3.6V VCC
supply to perform the High Reliability Erase and auto
Pro gram/Erase algo rithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
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PIN CONFIGURATIONS
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A17 Address Input
Q0~Q14 Data Input/Output
Q15/A-1 Q15 (Word mo de)/LSB addr(Byte mode)
CE# Chip Enable Input
WE# Write Enable Input
BYTE# Wo rd/Byte Selection input
RESET# Hardware Reset Pin/Secto r Protect
Unlock
OE# Output Enable Input
R Y/BY# Ready/Busy Output
VCC P ower Supply Pin (2.7V~3.6V)
GND Ground Pin
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
KH29LV400C T/B
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BLOCK STRUCTURE
Table 1: KH29LV400CT SECTOR ARCHITECTURE
Note: Byte mode:address range A17:A-1, word mode:address range A17:A0.
Sector Sector Size Address range Sector Address
Byte Mode W ord Mode Byte Mode (x8) W ord Mode (x16) A17 A16 A15 A14 A13 A 12
SA0 64Kbytes 32Kwords 00000-0FFFF 00000-07FFF 0 0 0 X X X
SA1 64Kbytes 32Kwords 10000-1FFFF 08000-0FFFF 0 0 1 X X X
SA2 64Kbytes 32Kwords 20000-2FFFF 10000-17FFF 0 1 0 X X X
SA3 64Kbytes 32Kwords 30000-3FFFF 18000-1FFFF 0 1 1 X X X
SA4 64Kbytes 32Kwords 40000-4FFFF 20000-27FFF 1 0 0 X X X
SA5 64Kbytes 32Kwords 50000-5FFFF 28000-2FFFF 1 0 1 X X X
SA6 64Kbytes 32Kwords 60000-6FFFF 30000-37FFF 1 1 0 X X X
SA7 32Kbytes 16Kwords 70000-77FFF 38000-3BFFF 1 1 1 0 X X
SA8 8Kbytes 4Kwords 78000-79FFF 3C000-3CFFF 1 11100
SA9 8Kbytes 4Kwords 7A000-7BFFF 3D000-3DFFF 1 11101
SA10 16Kbytes 8Kwords 7C000-7FFFF 3E000-3FFFF 1 1111X
Sector Sector Size Address range Sector Address
Byte Mode W ord Mode Byte Mode (x8) W ord Mode (x16) A17 A16 A15 A14 A13 A 12
SA0 16Kbytes 8Kwords 00000-03FFF 00000-01FFF 0 0000X
SA1 8Kbytes 4Kwords 04000-05FFF 02000-02FFF 0 00010
SA2 8Kbytes 4Kwords 06000-07FFF 03000-03FFF 0 00011
SA3 32Kbytes 16Kwords 08000-0FFFF 04000-07FFF 0 0 0 1 X X
SA4 64Kbytes 32Kwords 10000-1FFFF 08000-0FFFF 0 0 1 X X X
SA5 64Kbytes 32Kwords 20000-2FFFF 10000-17FFF 0 1 0 X X X
SA6 64Kbytes 32Kwords 30000-3FFFF 18000-1FFFF 0 1 1 X X X
SA7 64Kbytes 32Kwords 40000-4FFFF 20000-27FFF 1 0 0 X X X
SA8 64Kbytes 32Kwords 50000-5FFFF 28000-2FFFF 1 0 1 X X X
SA9 64Kbytes 32Kwords 60000-6FFFF 30000-37FFF 1 1 0 X X X
SA10 64Kbytes 32Kwords 70000-7FFFF 38000-3FFFF 1 1 1 X X X
Table 2: KH29LV400CB SECTOR ARCHITECTURE
Note: Byte mode:address range A17:A-1, word mode:address range A17:A0.
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BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH V OLTA GE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15/A-1
A0-A17
CE#
OE#
WE#
RESET#
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KH29LV400C T/B
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AUTOMATIC PROGRAMMING
The KH29LV400C T/B is b yte progr ammable using the
Automatic Pro gramming algo rithm. The Auto matic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature o f the KH29L V400C T/B is less than 10 sec-
onds.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at ro om temperature is acco mplished in
less than 4 seco nd. The Auto matic Erase algo rithm au-
tomatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
AUTOMATIC SECTOR ERASE
The KH29LV400C T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. The Automatic Sector
Erase algorithm automatically programs the specified
secto r(s) prio r to electrical erase . The timing and verifi-
cation of electrical erase are controlled internally within
the device. An erase operation can erase one sector,
multiple sectors, or the entire device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The de vice automatically
times the programming pulse width, provides the pro-
gram v erificatio n, and counts the number of sequences.
A status bit similar to Data# Polling and a status bit
to ggling between consecutive read cycles, pro vide feed-
back to the user as to the status of the programming
o peration. Refer to write operation status, table7, fo r more
inf o rmatio n on these status bits.
AUTOMATIC ERASE ALGORITHM
MXIC's A utomatic Erase algorithm requires the user to
write commands to the command register using stan-
dard micro processo r write timings. The de vice will auto-
matically pre-progr am and verify the entire arra y. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the erasing operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the co mmand register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE# or CE#, whichever
happens first.
MXIC's Flash technology combines years of EPROM
e xperience to pro duce the highest le v els of quality, reli-
ability, and cost effectiveness. The KH29LV400C T/B
electrically erases all bits simultaneously using F owler-
No rdheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC SELECT
The automatic select mode provides manufacturer and
device identification, and sector protection verification,
thro ugh identifier co des o utput on Q7~Q0. This mo de is
mainly adapted for programming equipment on the de-
vice to be programmed with its programming algorithm.
When programming by high voltage method, automatic
select mode requires VID (11.5V to 12.5V) on address
pin A9 and o ther address pin A6, A1 as referring to Table
3. In addition, to access the automatic select codes in-
system, the host can issue the automatic select com-
mand through the command register without requiring VID,
as shown in table4.
To verify whether o r not secto r being protected, the sec-
tor address must appear o n the appropriate highest o rder
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REV. 1.3, DEC. 09, 2005
address bit (see Table 1 and Table 2). The rest of address
bits, as sho wn in table3, are do n't care. Once all neces-
sary bits have been set as required, the programming
equipment may read the corresponding identifier code on
Q7~Q0.
TABLE 3. KH29LV400C T/B AUTO SELECT MODE OPERATION
NO TE:SA=Secto r Address , X=Do n't Care , L=Lo gic Low, H=Lo gic High
A17 A11 A8 A5
Description Mode CE# OE# WE# RE- | | A9 | A6 | A1 A0 Q15~Q0
SET# A12 A10 A7 A2
Manufacture L L H H X X VID X L X L L C2H
Code
Read Device ID W or d L L H H X X VID X L X L H 2 2 B9 H
Silicon (Top Bo o t Block) Byte L L H H X X VID X L X L H XXB9H
I D De vice ID (Bo tto m Wor d L L H H X X V ID X L X L H 22BAH
Bo ot Blo c k) Byte L L H H X X VID X L X L H XXBAH
XX01H
Sector Protection L L H H SA X VID X L X H L (protected)
Verification XX00H
(unprotected)
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First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus
Command Bus Cycle Cycle Cycle Cycle Cycle Cycle
Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXXH F0H
Read 1 RA RD
Read Silicon ID Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI
Byte 4 AAAH AAH 555H 55H AAAH 90H ADI DDI
Sector Protect Word 4 555H AAH 2AAH 55H 555H 90H (SA) XX00H
Verify x02H XX01H
Byte 4 AAAH AAH 555H 55H AAAH 90H (SA) 00H
x04H 01H
Program Word 4 555H AAH 2AAH 55H 555H A0H PA PD
Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD
Chip Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H
Sector Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H
Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA 30H
Sector Erase Suspend 1 XXXH B0H
Sector Erase Resume 1 XXXH 3 0H
TABLE 4. KH29LV400C T/B COMMAND DEFINITIONS
Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A17=do not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, B9H/BAH (x8) and 22B9H/22BAH (x16) for device code.
X = X can be VIL or VIH
RA=Address of memor y location to be read.
RD=Data to be read at location RA.
2. PA = Address of memor y location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector to be erased.
3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or
555H to Address A10~A-1 in byte mode.
Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A17 in either state.
4. For Secto r Protect Verify o peration: If read out data is 01H, it means the secto r has been protected. If read out data is 00H, it
means the sector is still not being protected.
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ADDRESS Q8~Q15
DESCRIPTION CE# OE # WE# RE- A17 A10 A9 A8 A6 A5 A 1 A0 Q0~Q7 BYTE BYTE
SET# A11 A7 A2 =VIH =VIL
Read L L H H AIN Dout Dout Q8~Q14=High Z
Q15=A-1
Write L H L H AIN DIN(3) DIN Q8~Q14=High Z
Q15=A-1
Re se t X X X L X High Z High Z High Z
Temporary sector unlock X X X VID AIN DIN DIN High Z
Output Disable L H H H X High Z High Z High Z
Standby Vcc±X X Vcc±X High Z High Z High Z
0.3V 0.3V
Sector Protect L H L VID SA X X X L X H L DIN X X
Chip Unprotect L H L VID X X X X H X H L DIN X X
Sector Protection Verify L L H H SA X VID X L X H L CODE(5) X X
TABLE 5. KH29LV400C T/B BUS OPERATION
NOTES:
1. Manufacturer and device codes may also be accessed via a command register wr ite sequence. Refer to Table 4.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 4 for valid Data-In during a wr ite operation.
4. X can be VIL or VIH.
5. Code=00H/XX00H means unprotected.
Code=01H/XX01H means protected.
6. A17~A12=Sector address for sector protect.
7. The sector protect and chip unprotect functions may also be implemented via programming equipment.
sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress.
COMMAND DEFINITIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them
in the improper sequence will reset the device to the
read mo de. Table 4 defines the v alid register co mmand
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REQUIREMENTS FOR READING ARRAY
DATA
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
co ntro l and selects the de vice. OE# is the o utput co ntro l
and gates array data to the output pins. WE# should remain
at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content
occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
micro processo r read cycles that assert valid address o n
the device address inputs produce valid data on the device
data outputs. The device remains enabled fo r read access
until the command register contents are altered.
WRITE COMMANDS/COMMAND SEQUENCES
To program data to the device or erase secto rs of memory
, the system must driv e WE# and CE# to VIL, and OE#
to VIH.
An erase o peration can erase one sector , multiple secto rs
, o r the entire device . Table indicates the address space
that each sector occupies. A "sector address" consists
of the address bits required to uniquely select a secto r.
The "Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 1 defines the valid register command
sequences. Writing incorrect address and data values o r
writing them in the improper sequence resets the device
to reading array data. Section has details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal
register (which is separate from the memory array) on
Q7-Q0. Standard read cycle timings apply in this mo de.
Refer to the Auto select Mode and Auto select Co mmand
Sequence sectio n fo r more info rmation.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification table
and timing diagrams for write operatio ns.
STANDBY MODE
When using both pins of CE# and RESET#, the device
enter CMOS Standby with both pins held at Vcc ± 0.3V.
If CE# and RESET# are held at VIH, but not within the
range o f VCC ± 0.3V, the device will still be in the standby
mo de, but the standby current will be larger . During Auto
Algo rithm o peration, Vcc active current (Icc2) is required
even CE# = "H" until the operation is completed. The
device can be read with standard access time (tCE) from
either of these standby modes, before it is ready to read
data.
OUTPUT DISABLE
With the OE# input at a logic high level (VIH), output
fro m the devices are disabled. This will cause the output
pins to be in a high impedance state.
RESET# OPERATION
The RESET# pin pro vides a hardware method of resetting
the device to reading array data. When the RESET# pin
is driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write
commands for the duration of the RESET# pulse. The
device also resets the internal state machine to reading
array data. The o peration that was interrupted sho uld be
reinitiated once the device is ready to accept another
command sequence, to ensure data integrity
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at VSS±0.3V, the device draws
CMOS standby current (ICC4). If RESET# is held at VIL
but not within VSS±0.3V, the standby current will be
greater.
The RESET# pin ma y be tied to system reset circuitry.
A system reset wo uld that also reset the Flash memo ry ,
enabling the system to read the boo t-up firm-ware fro m
the Flash memo ry.
If RESET# is asserted during a program or erase
o peratio n, the RY/BY# pin remains a "0" (b usy) until the
internal reset operatio n is complete, which requires a time
o f tREADY (during Embedded Algo rithms). The system
can thus mo nitor RY/BY# to determine whether the reset
operation is complete. If RESET# is asserted when a
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pro gram o r erase o peratio n is completed within a time o f
tREAD Y (no t during Embedded Algo rithms). The system
can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 24 f or the timing diagram.
READ/RESET COMMAND
The read or reset o peration is initiated by writing the read/
reset command sequence into the command register.
Micro processor read cycles retrie ve array data. The de-
vice remains enabled fo r reads until the command regis-
ter co ntents are altered.
If pro gram-f ail or erase-fail happen, the write o f F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
SILICON-ID READ COMMAND
Flash memories are intended for use in applications where
the lo cal CPU alters memo ry co ntents. As such, manu-
facturer and device co des must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high vo ltage (VID). However , multiplexing high voltage
onto address lines is not generally desired system de-
sign practice.
The KH29L V400C T/B contains a Silicon-ID-Read o pera-
tio n to supple traditional PROM pro gramming metho dol-
o gy. The o peratio n is initiated by writing the read silico n
ID co mmand sequence into the command register. Fo l-
lowing the command wr ite, a read cycle with A1=VIL,
A0=VIL retrieves the manufacturer co de of C2H/00C2H.
A read cycle with A1=VIL, A0=VIH returns the device
co de of B9H/22B9H fo r KH29LV400CT, BAH/22BAH fo r
KH29LV400CB.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlo c k" write cycles. These are f o llo wed by writing the
"set-up" co mmand 80H. Two mo re "unlo ck" write cycles
are then followed by the chip erase command 10H or
secto r erase co mmand 30H.
The Auto matic Chip Erase do es not require the device to
be entirely pre-pro grammed prio r to executing the Auto-
matic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory fo r an all-zero data pattern. When the
device is automatically verified to contain an all-zero pat-
tern, a self-timed chip erase and verify begin. The erase
and ver ify operations are completed when the data on
Q7 is "1" at which time the device returns to the Read
mo de. The system is not required to pro vide any co ntrol
o r timing during these operatio ns.
When using the Automatic Chip Erase algor ithm, note
that the erase auto matically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required).
If the Erase o peratio n was unsuccessful, the data o n Q5
is "1"(see Table 7), indicating the erase operation ex-
ceed internal timing limit.
The automatic erase begins o n the rising edge o f the last
WE# o r CE# pulse, whiche ver happens first in the co m-
mand sequence and terminates when the data on Q7 is
"1" at which time the de vice returns to the Read mo d e,
o r the data on Q6 stops to ggling fo r two consecutive read
cycles at which time the device returns to the Read mode.
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Pins A0 A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)
Manufacture code Word VIL VIL 00H 1 1 0 0 0 0 1 0 00C2H
Byte VIL VIL X 1 1 0 0 0 0 1 0 C2H
Device code Word VIH VIL 22H 1 0 1 1 1 0 0 1 22B9H
for KH29LV400CT Byte VIH VIL X 1 0 1 1 1 0 0 1 B9H
Device code Word VIH VIL 22H 1 0 1 1 1 0 1 0 22BAH
for KH29LV400CB Byte VIH VIL X 1 0 1 1 1 0 1 0 BAH
Sector Protection X VIH X 0 0 0 0 0 0 0 1 01H (Protected)
Verification X VIH X 0 0 0 0 0 0 0 0 00H (Unprotected)
TABLE 6. EXPANDED SILICON ID CODE
READING ARRAY DATA
The device is automatically set to reading array data
after device power-up. No co mmands are required to re-
trieve data. The device is also ready to read array data
after completing an Automatic Program or Automatic
Erase algo rithm.
After the de vice accepts an Erase Suspend co mmand,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. Af-
ter completing a programming operation in the Erase
Suspend mo d e, the system ma y o nce again read arr ay
data with the same exception. See Erase Suspend/Erase
Resume Co mmands” fo r more infor-mation on this mode.
The system must issue the reset command to re-en-
able the de vice fo r reading array data if Q5 goes high, o r
while in the auto select mode. See the "Reset Command"
section, next.
RESET COMMAND
Writing the reset co mmand to the de vice resets the de-
vice to reading array data. Address bits are don't care fo r
this co mmand.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading arra y
data. Once erasure begins, however, the device igno res
reset co mmands until the o peratio n is co mplete.
The reset command may be written between the se-
quence cycles in a pro gram co mmand sequence be-fo re
programming begins. This resets the device to reading
array data (also applies to programming in Erase Sus-
pend mode). Once programming begins, however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the se-
quence cycles in an SILICON ID READ command se-
quence. Once in the SILICON ID READ mo de, the reset
co mmand must be written to return to reading array data
(also applies to SILICON ID READ during Erase Sus-
pend).
If Q5 go es high during a program or erase operatio n, writ-
ing the reset command returns the device to read-ing
array data (also applies during Erase Suspend).
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erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two "un-
lo ck" write cycles. These are fo llowed by writing the set-
up command 80H. Two more "unlock" write cycles are
then followed by the sector erase command 30H. The
sector address is latched on the falling edge of WE# o r
CE#, whichever happens later, while the command (data)
is latched o n the rising edge o f WE# o r CE#, whiche ver
happens first. Sector addresses selected are loaded
into internal register o n the sixth f alling edge o f WE# o r
CE#, whichever happens later. Each successive secto r
load cycle star ted by the falling edge of WE# or CE#,
whichever happens later must begin within 50us from
the rising edge of the preceding WE# o r CE#, whichever
happens first. Otherwise, the loading period ends and
internal auto sector erase cycle star ts. (Monitor Q3 to
determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command other
than Sector Erase(30H) or Erase Suspend(B0H) during
the time-out period resets the device to read mode.
SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the de-
vice to be entirely pre-programmed prior to executing
the Automatic Sector Erase Set-up command and Au-
tomatic Sector Erase command. Upon executing the
Automatic Sector Erase command, the device will auto-
matically program and verify the sector(s) memory for
an all-zero data pattern. The system is not required to
provide any control or timing during these operations.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when either the data on Q7 is "1" at which time the de-
vice returns to the Read mode, or the data on Q6 stops
toggling for two consecutive read cycles at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.
When using the Automatic sector Erase algorithm, note
that the erase automatically terminates when adequate
Status Q7 Q6 Q5 Q3 Q2 RY/
(Note1) (Note2) BY#
Byte Program in Auto Program Algorithm Q7 # Toggle 0 N/A No 0
Toggle
Auto Erase Algorithm 0 Toggle 0 1 Toggle 0
Erase Suspend Read 1 No 0 N/A Toggle 1
(Erase Suspended Sector) Toggle
In Progress Erase Suspended Mode Erase Suspend Read Data Data Data Data Data 1
(Non-Erase Suspended Sector)
Erase Suspend Program Q7# Toggle 0 N/A N/A 0
Byte Program in Auto Program Algorithm Q7 # Toggle 1 N/A No 0
Toggle
Exceeded
Time Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle 0
Erase Suspend Program Q7# Toggle 1 N/A N/A 0
Table 7. Write Operation Status
Note:
1. Q7 and Q2 require a valid address when reading status infor mation. Refer to the appropriate subsection for fur ther details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.
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ERASE SUSPEND
This command only has meaning while the state ma-
chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Secto r Erase o peratio n. When the Erase Suspend com-
mand is written during a sector erase operation, the de-
vice requires a maximum of 20us to suspend the erase
operations. However, When the Erase Suspend co mmand
is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends
the erase operation. After this command has been ex-
ecuted, the command register will initiate erase suspend
mo de. The state machine will return to read mode auto-
matically after suspend is ready. At this time, state ma-
chine only allows the command register to respond to
the Read Memor y Array, Erase Resume and program
commands.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro-
gram operation is complete, the system can once again
read array data within non-suspended sectors.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing. However ,
a 10ms time delay must be required after the erase re-
sume command, if the system implements an endless
erase suspend/resume loop, or the number of erase sus-
pend/resume is exceeded 1024 times . The erase times
will be expended if the erase behavior always be sus-
pended. (Please refer to MXIC Flash Application Note
for details.)
AUTOMATIC PROGRAM COMMANDS
To initiate Automatic Pro gram mode, A three-cycle co m-
mand sequence is required. There are two "unlock" write
cycles. These are fo llowed by writing the Auto matic Pro-
gram command A0H.
Once the Automatic Program command is initiated, the
next WE# pulse causes a transition to an active pro-
gramming o peratio n. Addresses are latched on the fall-
ing edge, and data are internally latched o n the rising
edge o f the WE# o r CE#, whichev er happens first. The
rising edge of WE# or CE#, whichever happens first,
also begins the programming operation. The system is
not required to provide further controls or timings. The
device will auto matically pro vide an adequate internally
generated pro gram pulse and verify margin.
The de vice provides Q2, Q3, Q5, Q6, Q7, and RY/BY#
to determine the status of a wr ite operation. If the pro-
gram operation was unsuccessful, the data on Q5 is
"1"(see Table 7), indicating the program o peration exceed
internal timing limit. The auto matic pro gramming o pera-
tion is completed when the data read on Q6 stops tog-
gling fo r two consecutive read cycles and the data o n Q7
and Q6 are equivalent to data written to these two bits,
at which time the de vice returns to the Read mode (no
pro gram verify co mmand is required).
WORD/BYTE PROGRAM COMMAND SEQUENCE
The device programs one byte of data for each program
operation. The command sequence requires four bus
cycles, and is initiated by writing two unlock write cycles,
followed by the program set-up command. The program
address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically generates the program pulses and verifies
the programmed cell margin. Table 1 shows the address
and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
Q7, Q6, or RY/BY#. See "Write Operation Status" for
information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming
operation. The Byte Program command sequence should
be reinitiated once the device has reset to reading array
data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may halt the
operation and set Q5 to "1", or cause the Data# Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
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still "0". Only erase operations can convert a "0" to a
"1".
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/
BY#. Table 10 and the following subsections describe
the functio ns of these bits. Q7, R Y/BY#, and DQ6 each
offer a metho d fo r determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
Q7: Data# Polling
The Data# P o lling bit, Q7, indicates to the ho st sys-tem
whether an Automatic Algorithm is in progress or com-
pleted, o r whether the device is in Erase Suspend. Data#
Polling is valid after the rising edge of the final WE# pulse
in the program or erase command sequence.
During the Automatic Program algorithm, the device out-
puts on Q7 the complement of the datum programmed
to Q7. This Q7 status also applies to pro gramming dur-
ing Erase Suspend. When the Auto matic Pro gram algo-
rithm is complete, the device outputs the datum pro-
gr ammed to Q7. The system must provide the pro gram
address to read valid status information on Q7. If a pro-
gram address f alls within a protected secto r, Data# P oll-
ing on Q7 is active for approximately 1 us , then the de-
vice returns to reading array data.
During the Auto matic Erase algo rithm, Data# Polling pro-
duces a "0" on Q7. When the Automatic Erase algo-
rithm is complete, or if the device enters the Erase Sus-
pend mo de , Data# P o lling pro duces a "1" o n Q7. This is
analogous to the complement/true datum output de-
scribed for the Automatic Program algorithm: the erase
function changes all the bits in a sector to "1" prior to
this, the device outputs the "complement," or "0". The
system must provide an address within any of the sec-
tors selected for erasure to read valid status information
on Q7.
After an erase command sequence is written, if all sec-
to rs selected fo r erasing are pro tected, Data# Polling o n
Q7 is active for approximately 100 us, then the device
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchronously with Q0-Q6 while Output En-
ab le (OE#) is asserted low .
RY/BY#:Ready/Busy
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY# status is valid
after the rising edge o f the final WE# o r CE#, whichever
happens first, in the command sequence. Since RY/BY#
is an o pen-drain output, several RY/BY# pins can be tied
to gether in par allel with a pull-up resistor to Vcc.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the de-
vice is ready to read array data (including during the
Erase Suspend mode), or is in the standby mode.
Table 7 shows the outputs for RY/BY# during write op-
eration.
Q6:Toggle BIT I
Toggle Bit I on Q6 indicates whether an A uto matic Pro-
gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge o f the final WE# o r CE#, whichever
happens first, in the command sequence (prior to the
program or erase operation), and during the sector time-
out.
During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE# or CE# to
co ntrol the read cycles. When the o peratio n is complete,
Q6 sto ps to ggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
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Q2:Toggle Bit II
The "To ggle Bit II" o n Q2, when used with Q6, indicates
whether a par ticular sector is actively erasing (that is,
the Automatic Erase alorithm is in process), or whether
that sector is erase-suspended. Toggle Bit II is valid
after the rising edge o f the final WE# o r CE#, whichever
happens first, in the command sequence.
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE# or CE# to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-
parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus , bo th status bits
are required for sectors and mode information. Refer to
Tab le 7 to co mpare outputs for Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a to ggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
co mpleted the pro gram o r erase o peratio n. The system
can read array data on Q7-Q0 on the following read cycle.
How ever, if after the initial two read cycles , the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase op-
eration. If it is still toggling, the device did not complete
the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta-
tus as described in the previous paragraph. Alterna-
tively, it may choose to perform other system tasks. In
this case, the system m ust start at the beginning o f the
algorithm when it returns to determine the status of the
operation.
Q5
Exceeded Timing Limits
Q5 will indicate if the program or erase time has ex-
ceeded the specified limits (internal pulse count). Under
these conditions Q5 will produce a "1". This time-out
condition indicates that the program or erase cycle was
not successfully completed. Data# Polling and Toggle
Bit are the only operating functions of the device under
this co nditio n.
If this time-out condition occurs during sector erase op-
eratio n, it specifies that a particular secto r is bad and it
may no t be reused. However , other sectors are still func-
tional and may be used for the program or erase opera-
tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com-
bination of sectors are bad.
The system can use Q6 and Q2 to gether to determine
whether a sector is actively erasing or is erase sus-
pended. When the device is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-sus-
pended. Alternatively, the system can use Q7.
If a program address f alls within a protected sector , Q6
toggles for approximately 2 us after the program com-
mand sequence is written, then returns to reading array
data.
Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo-
rithm is complete.
Tab le 7 sho ws the outputs f or Toggle Bit I on Q6.
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Q3
Sector Erase Timer
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-o ut is co mplete. Data# P o lling
and T o ggle Bit are valid after the initial secto r erase co m-
mand sequence.
If Data# P olling o r the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is co mpleted as indicated b y Data# Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com-
mand has been accepted, the system software should
check the status of Q3 prior to and following each sub-
sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.
DATA PROTECTION
The KH29LV400C T/B is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transition. During power up the device automatically re-
sets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific command sequences. The device also
incorpo rates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down tran-
sition or system noise.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE# or WE#
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE# = VIL,
CE# = VIH or WE# = VIH. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND .
POWER-UP SEQUENCE
The KH29L V400C T/B powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously
pro tected secto r to change data in-system. The Tempo-
rary Sector Unprotect mode is activated by setting the
RESET# pin to VID(11.5V -12.5V). During this mode, for-
merly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET# pin, all the previously protected sectors are pro-
tected again.
SECTOR PROTECTION
The KH29LV400C T/B features hardware secto r pro tec-
tion. This feature will disable both program and erase
operations for these sectors protected. To activate this
mode, the programming equipment must force VID on
address pin A9 and OE# (suggest VID = 12V). Program-
ming of the protection circuitry begins on the falling edge
of the WE# pulse and is terminated on the rising edge.
Please refer to sector protect algorithm and waveform.
If this time-o ut condition occurs during the byte pro gram-
ming operation, it specifies that the entire sector con-
taining that byte is bad and this sector maynot be re-
used, (other sectors are still functional and can be re-
used).
The time-out condition will not appear if a user tries to
program a non blank location without erasing. Please
note that this is not a device failure condition since the
device was incorrectly used.
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CHIP UNPROTECT
The KH29LV400C T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in the
code. It is recommended to protect all sectors before
activating chip unprotect mode.
To activate this mode, the programming equipment must
force VID on control pin OE# and address pin A9. The
CE# pins must be set at VIL. Pins A6 must be set to
VIH.(see Table 2) Refer to chip unprotect algorithm and
waveform for the chip unprotect algorithm. The
unprotection mechanism begins on the falling edge of the
WE# pulse and is terminated on the rising edge.
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected sector.
It is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
To verify programming o f the pro tection circuitry , the pro-
gramming equipment must force VID on address pin A9
( with CE# and OE# at VIL and WE# at VIH). When
A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1"
code at de vice output Q0 f or a pro tected sector . Other-
wise the device will produce 00H f or the unprotected sec-
to r. In this mode, the addresses, except for A1, are don't
care. Address locations with A1 = VIL are reserved to
read manuf acturer and device co des. (Read Silico n ID)
It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
P erfo rming a read o peratio n with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
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ABSOLUTE MAXIMUM RATINGS
Storage T emperature
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
Vo ltage with Respect to Gro und
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
A9, OE#, and
RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may over-
shoot VSS to -2.0 V for periods of up to 20 ns. Maxi-
mum DC voltage on input or I/O pins is VCC +0.5 V.
During vo ltage transitio ns, input o r I/O pins may o ver-
sho ot to VCC +2.0 V f or perio ds up to 20 ns.
2. Minimum DC input vo ltage o n pins A9, OE#, and RE-
SET# is -0.5 V. Dur ing voltage transitions, A9, OE#,
and RESET# may o vershoot VSS to -2.0 V fo r periods
o f up to 20 ns. Maximum DC input vo ltage on pin A9 is
+12.5 V which may o versho o t to 14.0 V fo r periods up
to 20 ns.
3. No mo re than one output may be sho rted to gro und at
a time. Duration of the short circuit should not be
greater than one second.
Stresses abo v e tho se listed under "Abso lute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.
OPERATING RATINGS
Commercial (C) Devices
Ambient Temperature (TA ) . . . . . . . . . . . . 0°C to +70°C
VCC Supply Voltages
VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
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Table 8. CAPACITANCE TA = 25 oC, f = 1.0 MHz
SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS
CIN1 Input Capacitance 8 pF VIN = 0V
CIN2 Control Pin Capacitance 12 pF VIN = 0V
COUT Output Capacitance 12 pF VOUT = 0V
NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.
2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.
4. VIH min.=0.7xVCC. The VIH min. voltage is less than 2.4V.
Symbol PARAMETER MIN. TYP MAX. UNIT CONDITIONS
ILI Input Leakage Current ± 1 uA VIN = VSS to VCC
ILIT A9 Input Leakage Current 3 5 uA VCC=VCC max; A9=12.5V
ILO Output Leakage Current ± 1 uA V OUT = VSS to VCC, VCC=VCC max
ICC1 VCC Active Read Current 7 12 mA CE#=VIL, OE#=VIH @5MHz
2 4 mA (Byte Mode) @1MHz
7 12 mA CE#=VIL, OE#=VIH @5MHz
2 4 mA (Word Mode) @1MHz
ICC2 VCC Active write Currect 1 5 3 0 mA CE#=VIL, OE#=VIH
ICC3 VCC Standby Currect 0.2 5 uA CE#; RESET#=VCC ± 0.3V
ICC4 VCC Standby Currect 0.2 5 uA RESET#=VSS ± 0.3V
During Reset
ICC5 Automatic sleep mode 0.2 5 uA VIH=VCC ± 0.3V;VIL=VSS ± 0.3V
VIL Input Low Voltage(Note 1) -0.5 0.8 V
VIH Input High Voltage 0.7xVCC VCC+ 0.3 V
(Note 4)
VID Voltage for Automative
Select and Temporary 11.5 12.5 V VCC=3.3V
Chip Unprotect
VOL Output Low Voltage 0.45 V IOL = 4.0mA, VCC= VCC min
VOH1 Output High Voltage(TTL) 0.85xVCC IOH = -2mA, VCC=VCC min
VOH2 Output High Voltage VCC-0.4 IOH = -100uA, VCC min
(CMOS)
Table 9. DC CHARACTERISTICS
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29LV400C-70 29LV400C-90
SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS
tRC Read Cycle Time (Note 1) 7 0 90 ns
tACC Address to Output Delay 7 0 90 ns CE#=OE#=VIL
tCE CE# to Output Delay 7 0 9 0 ns OE#=VIL
tOE OE# to Output Delay 30 35 ns CE#=VIL
tDF OE# High to Output Float (Note 2) 0 25 0 30 ns CE#=VIL
tOEH Output Enable Read 0 0 ns
Hold Time Toggle and 10 10 ns
Data# Polling
tOH Address to Output hold 0 0 ns CE#=OE#=VIL
Notes :
1. Not 100% tested.
2. tDF is defined as the time at which the output achieves
the open circuit condition and data is no longer driven.
TEST CONDITIONS:
•Input pulse levels: 0V/3.0V.
•Input rise and fall times is equal to or less than 5ns.
•Output load: 1 TTL gate + 100pF (Including scope and
jig), for 29LV400CT/B-90. 1 TTL gate + 30pF (Including
scope and jig) for 29LV400CT/B-70.
•Reference levels for measuring timing: 1.5V.
AC CHARACTERISTICS
Table 10. READ OPERATIONS
21
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 1. SWITCHING TEST CIRCUITS
Figure 2. SWITCHING TEST WAVEFORMS
TEST POINTS
3.0V
0V
AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".
Input pulse rise and fall times are < 5ns.
OUTPUT
1.5V1.5V
INPUT
DEVICE UNDER
TEST
DIODES=IN3064
OR EQUIVALENT
CL 6.2K ohm
2.7K ohm +3.3V
CL=100pF Including jig capacitance
CL=30pF for KH29LV400C T/B-70
22
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 3. READ TIMING WAVEFORMS
Addresses
CE#
OE#
tACC
WE#
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
HIGH Z HIGH Z
D ATA V alid
tOE
tOEH tDF
tCE
tACC
tRC
Outputs
RESET#
tOH
ADD V alid
23
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Parameter Speed Options
Std. Description 70 90 Unit
tWC Write Cycle Time (Note 1) Mi n 7 0 9 0 ns
tAS Address Setup Time Min 0 ns
tAH Address Hold Time Min 4 5 ns
tDS Data Setup Time Min 3 5 4 5 ns
tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHWL Read Recovery Time Before Write Min 0 ns
(OE# High to WE# Low)
tCS CE# Setup Time Min 0 ns
tCH CE# Hold Time Min 0 ns
tWP Write Pulse Width Min 3 5 ns
tWPH Write Pulse Width High Min 3 0 ns
tWHWH1 Programming Operation (Note 2) Typ 9/11 us
(Byte/Word program time)
tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec
tVCS VCC Setup Time (Note 1) Min 5 0 us
tRB Recovery Time from RY/BY# Mi n 0 ns
tBUSY Program/Erase Vaild to RY/BY# Delay Max 9 0 ns
tWPP1 Write Pulse Width for Sector Protect Mi n 1 0 0 ns
(A9, OE# Control) Typ 10 us
tWPP2 Write Pulse Width for Sector Unprotect Mi n 1 0 0 ns
(A9, OE# Control) Typ 12 ms
tBAL Sector Address Load Time Max 5 0 us
NOTES:
1. Not 100% tested.
2. See the "Erase and Programming P erf ormance" sectio n f or more inf ormation.
AC CHARACTERISTICS
Table 11. Erase/Program Operations
24
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Parameter Speed Options
Std. Description 70 90 Unit
tWC Write Cycle Time (Note 1) Min 7 0 9 0 ns
tAS Address Setup Time Min 0 ns
tAH Address Ho ld Time Min 4 5 ns
tDS Data Setup Time Min 35 4 5 ns
tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHEL Read Reco very Time Befo re Write Min 0 ns
tWS WE# Setup Time Min 0 ns
tWH WE# Hold Time Min 0 ns
tCP CE# Pulse Width Min 3 5 ns
tCPH CE# Pulse Width High Min 30 ns
tWHWH1 Programming Byte Typ 9 us
Operatio n (no te2) W o rd Typ 1 1 us
tWHWH2 Sector Erase Operatio n (note2) Typ 0.7 sec
NOTE:
1. Not 100% tested.
2. See the "Erase and Programming P erf ormance" sectio n f or more inf ormation.
AC CHARACTERISTICS
Table 12. Alternate CE# Controlled Erase/Program Operations
25
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 4. COMMAND WRITE TIMING WAVEFORM
Addresses
CE#
OE#
WE#
DIN
tDS
tAH
Data
tDH
tCS tCH
tCWC
tWPH
tWP
tOES
tAS
VCC 3V
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
ADD V alid
26
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
AUTOMATIC PROGRAMMING TIMING WAVEFORM
Figure 5. AUTOMATIC PROGRAMMING TIMING WAVEFORM
One byte data is programmed. Verify in fast algorithm
and additional verification by external control are not re-
quired because these operations are executed automati-
cally by internal control circuit. Programming comple-
tio n can be verified by Data# Polling and toggle bit check-
ing after auto matic programming starts. Device o utputs
DA TA# during programming and DATA# after programming
o n Q7.(Q6 is f o r to ggle bit; see toggle bit, Data# P o lling,
timing waveform)
tWC
Address
OE#
CE#
A0h
555h PA
PD Status DOUT
PA PA
NOTES:
1.PA=Program Address, PD=Program Data, DOUT is the true data the program address
tAS
tAH
tGHWL
tCH
tWP
tDS tDH
tWHWH1
Read Status Data (last two cycle)Program Command Sequence(last two cycle)
tBUSY tRB
tCS tWPH
tVCS
WE#
Data
RY/BY#
VCC
27
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Program Data/Address
Write Data A0H Address 555H
YES
Verify Word Ok ?
YES
Auto Program Completed
Data Poll
from system
Increment
Address
Last Address ?
No
No
28
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 7. CE# CONTROLLED PROGRAM TIMING WAVEFORM
tWC
tWH
tGHEL
tWHWH1 or 2
tCP
Address
WE#
OE#
CE#
Data Q7
PA
Data# Polling
DOUT
RESET#
RY/BY#
NOTES:
1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.
2.Figure indicates the last two bus cycles of the command sequence.
tAH
tAS
PA for program
SA for sector erase
555 for chip erase
tRH
tDH
tDS
tWS
A0 for program
55 for erase
tCPH
tBUSY
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
29
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
All data in chip are erased. External erase verification is
not required because data is verified automatically by
internal control circuit. Erasure completion can be veri-
fied by Data# P o lling and to ggle bit checking after auto-
matic erase starts. Device outputs 0 during erasure
and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle
bit, Data# P olling, timing wavefo rm)
Figure 8. AUTOMATIC CHIP ERASE TIMING WAVEFORM
AUTOMATIC CHIP ERASE TIMING WAVEFORM
tWC
Address
OE#
CE#
55h
2AAh 555h
10h In
Progress Complete
VA VA
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
tAS
tAH
tGHWL
tCH
tWP
tDS tDH
tWHWH2
Read Status Data Erase Command Sequence(last two cycle)
tBUSY tRB
tCS tWPH
tVCS
WE#
Data
RY/BY#
VCC
30
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 9. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
YES
NO Data=FFh ?
Write Data 10H Address 555H
Write Data 55H Address 2AAH
Data Pall from System
Auto Chip Erase Completed
31
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 10. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector indicated by A12 to A17 are erased. External
erase verify is not required because data are verified
automatically by internal control circuit. Erasure comple-
tion can be verified by Data# Po lling and toggle bit check-
ing after automatic erase starts. De vice outputs 0 dur-
ing erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see to ggle bit, Data# P o lling, timing wa vef o rm)
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
tWC
Address
OE#
CE#
55h
2AAh Sector
Address 1
Sector
Address 0
30h
In
Progress Complete
VA VA
30h
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
Sector
Address n
tAS
tAH
tBAL
tGHWL
tCH
tWP
tDS tDH
tWHWH2
Read Status Data Erase Command Sequence(last two cycle)
tBUSY tRB
tCS tWPH
tVCS
WE#
Data
RY/BY#
VCC
30h
32
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
Write Data 30H Sector Address
Write Data 55H Address 2AAH
Data Poll from System
Auto Sector Erase Completed
NO
Last Sector
to Erase
YES
YES
NO
Data=FFh
33
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 12. ERASE SUSPEND/ERASE RESUME FLOWCHART
Note: If the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is
exceeded 1024 times, then the 10ms time delay must be put into consideration.
START
Write Data B0H
Toggle Bit checking Q6
not toggled
ERASE SUSPEND
YES
NO
Write Data 30H
Delay 10ms (note)
Continue Erase
Reading or
Programming End
Read Array or
Program
Another
Erase Suspend ? NO
YES
YES
NO
ERASE RESUME
34
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 13. IN-SYSTEM SECTOR PROTECT/UNPROTECT TIMING WAVEFORM (RESET# Control)
Sector Protect =150us
Sector Unprotect =15ms
1us
VID
VIH
Data
SA, A6
A1, A0
CE#
WE#
OE#
Valid* Valid*
Status
Valid*
Sector Protect or Sector Unprotect
40h60h60h
Verify
RESET#
Note: When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0.
35
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 14. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control)
tOE
Data
OE#
WE#
12V
3V
12V
3V
CE#
A9
A1
A6
tOESP
tWPP 1
tVLHT
tVLHT
tVLHT
Verify
01H F0H
A18-A12 Sector Address
36
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 15. SECTOR PROTECTION ALGORITHM (A9, OE# Control)
START
Set Up Sector Addr
PLSCNT=1
Sector Protection
Complete
Data=01H?
Yes
OE#=VID, A9=VID, CE#=VIL
A6=VIL
Activate WE# Pulse
Time Out 150us
Set WE#=VIH, CE#=OE#=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1
Protect Another
Sector?
Remove VID from A9
Write Reset Command
Device Failed
PLSCNT=32?
Yes
No
No
37
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 16. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID
START
PLSCNT=1
First Write
Cycle=60H
Yes
No
RESET#=VID
Wait 1us
Set up sector address
Write 60H to sector address
with A6=0, A1=1, A0=0
Verify sector protect :
write 40H with A6=0,
A1=1, A0=0
Wait 150us
Increment PLSCNT
Read from sector address
Remove VID from RESET#
Temporary Sector
Unprotect Mode
Reset PLSCNT=1
Data=01H
Yes
Yes
Yes
No
No
No
?
PLSCNT=25?
Protect another
sector?
Write reset command
Sector protect complete
Device failed
38
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 17. IN-SYSTEM SECTOR UNPROTECTION ALGORITHM WITH RESET#=VID
START
PLSCNT=1
First Write
Cycle=60H ?
Yes
No
RESET#=VID
Wait 1us
Set up first sector address
Chip unprotect :
write 60H with
A6=1, A1=1, A0=0
Verify chip unprotect
write 40H to sector address
with A6=1, A1=1, A0=0
Wait 50ms
Increment PLSCNT
Read from sector address
with A6=1, A1=1, A0=0
Remove VID from RESET#
Temporary Sector
Unprotect Mode
Set up next sector address
All sector
protected?
Yes
Data=00H
Yes
Yes
Yes
No
No
No
No Protect all sectors
?
PLSCNT=1000?
Last sector
verified?
Write reset command
Chip unprotect complete
Device failed
39
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 18. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control)
Notes: tWPP1 (Write pulse width f o r sector pro tect)=100ns min, 10us(Typ .)
tWPP2 (Write pulse width for secto r unpro tect)=100ns min, 12ms(Typ .)
tOE
Data
OE#
WE#
12V
3V
12V
3V
CE#
A9
A1
tOESP
tWPP 2
tVLHT
tVLHT
tVLHT
Verify
00H
A6
Sector Address
A18-A12
F0H
40
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 19. CHIP UNPROTECTION ALGORITHM (A9, OE# Control)
START
Protect All Sectors
PLSCNT=1
Chip Unprotect
Complete
Data=00H?
Yes
Set OE#=A9=VID
CE#=VIL, A6=1
Activate WE# Pulse
Time Out 50ms
Set OE#=CE#=VIL
A9=VID,A1=1
Set Up First Sector Addr
All sectors have
been verified?
Remove VID from A9
Write Reset Command
Device Failed
PLSCNT=1000?
No
Increment
PLSCNT
No
Read Data from Device
Yes
Yes
No
Increment
Sector Addr
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
41
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 20. DATA# POLLING ALGORITHM
WRITE OPERATION STATUS
Read Q7~Q0
Add.=VA(1)
Read Q7~Q0
Add.=VA
Start
Q7 = Data ?
Q5 = 1 ?
Q7 = Data ?
FAIL Pass
No
No
(2)
No
Yes
Yes
Yes
NOTE : 1.VA=Valid address for programming
2.Q7 should be re-checked even Q5="1" because Q7 may change
simultaneously with Q5.
42
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 21. TOGGLE BIT ALGORITHM
Read Q7-Q0
Read Q7-Q0
Q5= 1?
Read Q7~Q0 Twice
Program/Erase Operation
Not Complete,Write
Reset Command
Program/Erase
operation Complete
Toggle bit Q6=
Toggle?
Toggle Bit Q6 =
Toggle ? NO
(Note 1)
(Note 1,2)
YES
NO
NO
YES
YES
Note:1.Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 change to "1".
Start
43
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 22. DATA# POLLING TIMINGS (DURING AUTOMATIC ALGORITHMS)
RY/BY#
NOTES:
1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.
tDF
tCE
tACC
tRC
tCH
tOE
tOEH
tOH
tBUSY
Address
CE#
OE#
WE#
Q7
Q0-Q6 Status Data Status Data
Complement Complement Valid DataTrue
VAVAVA
High Z
High Z
Valid DataTrue
44
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 23. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
NOTES:
1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
tDF
tCE
tACC
tRC
tCH
tOE
tOEH
tBUSY
High Z
tOH
Address
CE#
OE#
WE#
Q6/Q2
RY/BY#
Valid Status
(first read)
Valid Status
(second read) (stops toggling)
Valid Data
VA VA
VA
VA
Valid Data
45
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 24. RESET# TIMING WAVEFORM
Table 13. AC CHARACTERISTICS
Parameter Std Description T est Setup All Speed Options Unit
tREAD Y1 RESET# PIN Low (During Automatic Algorithms) MAX 2 0 us
to Read o r Write (See No te)
tREAD Y2 RESET# PIN Low (NOT During Auto matic MAX 500 ns
Algo rithms) to Read o r Write (See No te)
tRP RESET# Pulse Width (During Auto matic Algo rithms) MIN 500 ns
tRH RESET# High Time Befo re Read(See No te) MIN 5 0 ns
tRB R Y/BY# Reco very Time(to CE#, OE# go low) MIN 0 ns
Note:Not 100% tested
tRH
tRB
tREADY1
tRP
tRP
tREADY2
RY/BY#
CE#, OE#
RESET#
Reset Timing NOT during Automatic Algorithms
Reset Timing during Automatic Algorithms
RY/BY#
CE#, OE#
RESET#
46
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 25. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte
mode to word mode)
AC CHARACTERISTICS
WORD/BYTE CONFIGURATION (BYTE#)
Parameter Description Speed Options Unit
JEDEC Std -70 -90
tELFL/tELFH CE# to BYTE# Switching Low o r High Max 5 ns
tFLQZ BYTE# Switching Low to Output HIGH Z Max 2 5 3 0 ns
tFHQV BYTE# Switching High to Output Active M in 70 90 ns
tFHQV
tELFH
DOUT
(Q0-Q7) DOUT
(Q0-Q14)
VA DOUT
(Q15)
CE#
OE#
BYTE#
Q0~Q14
Q15/A-1
47
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 26. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from word
mode to byte mode)
Figure 27. BYTE# TIMING WAVEFORM FOR PROGRAM OPERATIONS
tAS tAH
The falling edge of the last WE# signal
CE#
WE#
BYTE#
tFLQZ
tELFH
DOUT
(Q0-Q7)
DOUT
(Q0-Q14)
VA
DOUT
(Q15)
CE#
OE#
BYTE#
Q0~Q14
Q15/A-1
48
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Table 14. TEMPORARY SECTOR UNPROTECT
Parameter Std. Description T est Setup All Speed Options Unit
tVI DR VID Rise and F all Time (See No te) Mi n 5 0 0 ns
tRSP RESET# Setup Time for T emporary Sector Unprotect Min 4 us
Note:
Not 100% tested
Figure 28. TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM
Figure 29. Q6 vs Q2 for Erase and Erase Suspend Operations
RESET#
CE#
WE#
RY/BY#
tVIDR tVIDR
Program or Erase Command Sequence
12V
0 or Vcc 0 or Vcc
tRSP
NOTES:
The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended
WE#
Enter Embedded
Erasing Erase
Suspend Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read Erase
Erase
Resume
Erase
Complete
Erase
Q6
Q2
49
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 30. TEMPORARY SECTOR UNPROTECT ALGORITHM
Start
RESET# = VID (Note 1)
Perform Erase or Program Operation
RESET# = VIH
Temporary Sector Unprotect Completed(Note 2)
Note : 1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V
2. All previously protected sectors are protected again.
Operation Completed
50
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
Figure 31. ID CODE READ TIMING WAVEFORM
tACC
tCE
tACC
tOE
tOH tOH
tDF
DATA OUT
C2H/00C2H B9H/BAH (Byte)
22B9H/22BAH (Word)
VID
VIH
VIL
ADD
A9
ADD
A2-A8
A10-A17
CE#
OE#
WE#
ADD
A0
DATA OUT
DATA
Q0-Q15
VCC
A1
3V
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
51
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is reco mmended fo r the supply vo ltages and the co ntro l signals at device power-up .
If the timing in the figure is igno red, the device may not o perate correctly.
Figure A. AC Timing at Device P ower-Up
No tes :
1. Sampled, not 100% tested.
2. This specificatio n is applied for no t o nly the device pow er-up but also the no rmal o peratio ns.
Symbol Parameter Notes Min. Max. Unit
tVR VCC Rise Time 1 2 0 500000 us/V
tR Input Signal Rise Time 1,2 2 0 us/V
tF Input Signal F all Time 1 ,2 2 0 us/V
VCC
ADDRESS
CE#
WE#
OE#
DATA
tVR
tACC
tR or tF
tCE
tF
VCC(min)
GND
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
High Z
VOL
WP#/ACC
VIH
VIL
Valid
Ouput
Valid
Address
tR or tF
tR
tOE
tF tR
52
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
MIN. MAX.
Input Voltage with respect to GND on all pins except I/O pins -1.0V 12.5V
Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V
Current -100mA +100mA
Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.
LIMITS
PARAMETER MIN. TYP.(2) MAX.(3) UNITS
Sector Erase Time 0.7 1 5 sec
Chip Erase Time 4 3 2 sec
Byte Programming Time 9 30 0 us
Word Programming Time 11 360 us
Chip Programming Time Byte Mode 4.5 13.5 sec
Word Mode 3 9 sec
Erase/Program Cycles 100,000 Cycles
Table 16. LATCH-UP CHARACTERISTICS
Table 15. ERASE AND PROGRAMMING PERFORMANCE (1)
Note: 1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25°C, 3V.
3.Maximum values measured at 25°C, 2.7V.
Table 17. DATA RETENTION
Parameter Description Test Conditions Min Unit
150°C 10 Years
Data Retention Time 125°C 20 Years
53
P/N:PM1219
KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
QUERY COMMAND AND COMMON FLASH
INTERFACE (CFI) MODE ( for KH29LV400CT/
CB)
KH29LV400CT/CB is capable of operating in the CFI
mode. This mode all the host system to determine the
manufacturer of the device such as operating param-
eters and co nfigur atio n. Two co mmands are required in
CFI mo de . Query co mmand o f CFI mo de is placed first,
then the Reset command exits CFI mode. These are
TABLE 18-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description Address Address Data
(Byte Mode) (Word Mode)
Query-unique ASCII string "QRY" 2 0 10 0051
22 11 0052
24 12 0059
Primary vendor command set and control interface ID code 2 6 1 3 0002
28 14 0000
Address for primary algorithm extended query table 2A 15 0040
2C 16 0000
Alternate vendor command set and control interface ID code (none) 2E 1 7 0000
30 18 0000
Address for secondary algorithm extended query table (none) 32 19 0000
34 1A 0000
TABLE 18-2. CFI Mode: System Interface Data Values
(All values in these tables are in hexadecimal)
Description Address Address Data
(Byte Mode) (Word Mode)
VCC supply, minimum (2.7V) 3 6 1B 0027
VCC supply, maximum (3.6V) 3 8 1 C 0036
VPP supply, minimum (none) 3A 1D 0000
VPP supply, maximum (none) 3 C 1 E 0000
Typical timeout for single word/byte write (2N us) 3E 1F 0004
Typical timeout for Minimum size buffer write (2N us) 4 0 20 0000
Typical timeout for individual block erase (2N ms) 4 2 21 000A
Typical timeout for full chip erase (2N ms) 4 4 2 2 0000
Maximum timeout for single word/byte write times (2N X Typ) 46 23 0005
Maximum timeout for buffer write times (2N X Typ) 4 8 24 0000
Maximum timeout for individual block erase times (2N X Typ) 4A 2 5 0004
Maximum timeout for full chip erase times (not supported) 4C 2 6 0000
described in T able 18.
The single cycle Query co mmand is valid only when the
device is in the Read mode, including Erase Suspend,
Standby mode, and Read ID mo de; however, it is ignored
otherwise.
The Reset command exits from the CFI mode to the
Read mo de , o r Erase Suspend mo de , o r read ID mo de.
The co mmand is valid o nly when the device is in the CFI
mode.
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
TABLE 18-3. CFI Mode: Device Geometry Data Values
(All values in these tables are in hexadecimal)
Description Address Address Data
(Byte Mode) (Word Mode)
Device size (2N bytes) 4E 27 0013
Flash device interface code (refer to the CFI publication 100) 5 0 2 8 0002
52 29 0000
Maximum number of bytes in multi-byte write (not supported) 5 4 2A 0000
56 2B 0000
Number of erase block regions 5 8 2 C 0004
Erase block region 1 information (refer to the CFI publication 100) 5A 2 D 0000
5C 2E 0000
5E 2F 0040
60 30 0000
Erase block region 2 information 6 2 3 1 0001
64 32 0000
66 33 0020
68 34 0000
Erase block region 3 information 6A 3 5 0000
6C 36 0000
6E 37 0080
70 38 0000
Erase block region 4 information 7 2 3 9 0006
74 3A 0000
76 3B 0000
78 3C 0001
TABLE 18-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
(All values in these tables are in hexadecimal)
Description Address Address Data
(Byte Mode) (Word Mode)
Query-unique ASCII string "PRI" 8 0 4 0 0050
82 41 0052
84 42 0049
Major version number, ASCII 8 6 43 0031
Minor version number, ASCII 8 8 44 0030
Address sensitive unlock (0=required, 1= not required) 8A 45 0000
Erase suspend (2= to read and write) 8 C 4 6 0002
Sector protect (N= # of sectors/group) 8E 4 7 0001
Temporary sector unprotected (1=supported) 90 48 0001
Sector protect/unprotected scheme 92 49 0004
Simultaneous R/W operation (0=not supported) 94 4A 0000
Burst mode type (0=not supported) 9 6 4B 0000
Page mode type (0=not supported) 98 4 C 0000
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
ORDERING INFORMATION
P ART NO. ACCESS OPERA TING STANDBY PACKA GE Remark
TIME (ns) Current MAX. (mA) Current MAX. (uA)
KH29LV400CTTC-70 7 0 3 0 5 48 Pin TSOP
(Normal T ype)
KH29LV400CBTC-70 7 0 3 0 5 48 Pin TSOP
(Normal T ype)
KH29LV400CTTC-90 9 0 3 0 5 48 Pin TSOP
(Normal T ype)
KH29LV400CBTC-90 9 0 3 0 5 48 Pin TSOP
(Normal T ype)
KH29LV400CTTC-70G 7 0 3 0 5 48 Pin TSOP PB free
(Normal T ype)
KH29LV400CBTC-70G 7 0 30 5 48 Pin TSOP PB free
(Normal T ype)
KH29LV400CTTC-90G 9 0 3 0 5 48 Pin TSOP PB free
(Normal T ype)
KH29LV400CBTC-90G 9 0 30 5 48 Pin TSOP PB free
(Normal T ype)
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
PART NAME DESCRIPTION
KH 29 LV 70C T T C G
OPTION:
G: Lead-free package
blank: normal
SPEED:
70: 70ns
90: 90ns
TEMPERATURE RANGE:
C: Commercial (0˚C to 70˚C)
PACKAGE:
T: TSOP
BOOT BLOCK TYPE:
T: Top Boot
B: Bottom Boot
REVISION:
C
DENSITY & MODE:
400: 4M, x8/x16 Boot Block
TYPE:
L, LV: 3V
DEVICE:
29:Flash
400
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
PACKAGE INFORMATION
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KH29LV400C T/B
REV. 1.3, DEC. 09, 2005
REVISION HISTORY
Revision No. Description Page Date
1. 1 1. Modified "Package Information" P57 JUL/01/2005
1.2 1. Modified "Low power co nsumption--active current" fro m 20mA(Max.) P1 A UG/30/2005
to 30mA(Max.)
2. Added descriptio n abo ut Pb-free devices are RoHS Co mpliant P1
1.3 1. Mo dified content erro r P44,45,51 DEC/09/2005
KH29LV400C T/B
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