Technology Licensed from International Rectifier APU3137 8-PIN SYNCHRONOUS PWM CONTROLLER FEATURES DESCRIPTION 1A Peak Output Drive Capability 0.8V Reference Voltage Shuts off both drivers at shorted output and shutdown Operating with single 5V or 12V supply voltage Stable with ceramic capacitors Internal 200KHz Oscillator Soft-Start Function Protects the output when control FET is shorted Synchronous Controller in 8-Pin Package RoHS Complaint APPLICATIONS DDR Memory Application Low voltage distributed DC-DC Graphic Cards Low cost on-board DC to DC such as 5V to 2.5V, 1.8V or 0.8V The APU3137 controller IC is designed to provide a low cost and high performance synchronous Buck regulator for on-board DC to DC converter applications. The output voltage can be set as low as 0.8V and higher voltage can be obtained with an external voltage divider. High peak current gate drivers provide fast switching transition for applications requiring high output current in the range of 15A to 20A. This device features an internal 200KHz oscillator, under-voltage lockout for both Vcc and Vc supplies, an external programmable soft-start function as well as output under-voltage detection that latches off the device when an output short is detected. TYPICAL APPLICATION Optional 12V C3 1uF C4 1uF L1 C2 4x 150uF Q1 IRF7832 HDrv L2 D1 SS/SD Q2 IRF7832 Comp C7 3x 330uF 40m , Poscap R3 Fb Gnd R4 30K 2.5V @ 15A 2.2uH U1 APU3137 LDrv C9 3300pF Optional 5V C1 47uF Vc Vcc C8 0.1uF 1uH 2.15K R5 1K, 1% Figure 1 - Typical application of APU3137. PACKAGE ORDER INFORMATION TA (C) 0 To 70 DEVICE APU3137M Data and specifications subject to change without notice. PACKAGE 8-Pin Plastic SOIC NB (M) FREQUENCY 200KHz 200510061-1/17 APU3137 ABSOLUTE MAXIMUM RATINGS Vcc Supply Voltage .................................................. Vc Supply Voltage .................................................... Storage Temperature Range ...................................... Operating Junction Temperature Range ..................... -0.5V - 25V -0.5V - 25V -65C To 150C 0C To 125C CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. PACKAGE INFORMATION 8-PIN PLASTIC SOIC NB (M) Fb 1 8 SS Vcc 2 7 Comp LDrv 3 6 Vc Gnd 4 5 HDrv JA=160C/W ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc=5V, Vc=12V and TA=0 to 70C. Typical values refer to TA=25 C. PARAMETER Reference Voltage Fb Voltage Fb Voltage Line Regulation UVLO UVLO Threshold - Vcc UVLO Hysteresis - Vcc UVLO Threshold - Vc UVLO Hysteresis - Vc UVLO Threshold - Fb UVLO Hysteresis - Fb Supply Current Vcc Dynamic Supply Current Vc Dynamic Supply Current Vcc Static Supply Current Vc Static Supply Current Soft-Start Section Charge Current SYM TEST CONDITION V FB LREG MIN TYP MAX UNITS 0.784 0.800 0.816 1.6 V mV 4.25 0.25 3.5 0.25 0.4 0.25 4.5 V V V V V V 5<Vcc<12 UVLO Vcc Supply Ramping Up 4.0 UVLO Vc Supply Ramping Up 3.0 UVLO Fb Fb Ramping Down 0.3 Dyn Icc Dyn Ic ICCQ ICQ SSIB Freq=200KHz, CL=3000pF Freq=200KHz, CL=3000pF SS=0V SS=0V SS=0V 15 3.65 0.5 6.5 11 4 2.5 8 14 6 4 mA mA mA mA 22 30 A 2/17 APU3137 PARAMETER Error Amp Fb Voltage Input Bias Current Fb Voltage Input Bias Current Transconductance Oscillator Frequency Ramp-Amplitude Voltage Output Drivers Rise Time Fall Time Dead Band Time Max Duty Cycle Min Duty Cycle SYM IFB1 IFB2 TEST CONDITION Tf 600 0.1 50 850 180 Freq Tr TYP SS=3V, Fb=1V SS=0V, Fb=1V GM V RAMP MIN Note 1 1.25 CL=3000pF (10% to 90%) CL=3000pF (90% to 10%) 35 35 100 90 TDB TON TOFF Fb=0.7V, Freq=200KHz Fb=1.5V 85 MAX UNITS 1100 A A mho 240 KHz V 70 70 ns ns ns % % 0 Note 1: Guaranteed by design but not tested in production. PIN DESCRIPTIONS PIN# 1 PIN SYMBOL PIN DESCRIPTION Fb This pin is connected directly to the output of the switching regulator via resistor divider to provide feedback to the Error amplifier. 2 Vcc This pin provides biasing for the internal blocks of the IC as well as power for the low side driver. A minimum of 1F, high frequency capacitor must be connected from this pin to ground to provide peak drive current capability. 3 LDrv Output driver for the synchronous power MOSFET. 4 Gnd This pin serves as the ground pin and must be connected directly to the ground plane. A high frequency capacitor (0.1 to 1F) must be connected from VCC and Vc pins to this pin for noise free operation. 5 HDrv Output driver for the high side power MOSFET. This pin should not go negative (below ground), this may cause problem for the gate drive circuit. It can happen when the inductor current goes negative (Source/Sink), soft-start at no load and for the fast load transient from full load to no load. To prevent negative voltage at gate drive, a low forward voltage drop diode might be connected between this pin and ground. 6 Vc This pin is connected to a voltage that must be at least 4V higher than the bus voltage of the switcher (assuming 5V threshold MOSFET) and powers the high side output driver. A minimum of 1F, high frequency capacitor must be connected from this pin to ground to provide peak drive current capability. 7 Comp Compensation pin of the error amplifier. An external resistor and capacitor network is typically connected from this pin to ground to provide loop compensation. 8 SS / SD This pin provides soft-start for the switching regulator. An internal current source charges an external capacitor that is connected from this pin to ground which ramps up the output of the switching regulator, preventing it from overshooting as well as limiting the input current. The converter can be shutdown by pulling this pin below 2.8V. 3/17 APU3137 BLOCK DIAGRAM Vcc 2 3V Bias Generator 3V 0.8V POR 4.25V 20uA Vc 6 Vc 3.5V SS/SD 8 64uA Max Ct Oscillator 5 HDrv POR S Q Error Comp 0.8V Fb 1 Comp 7 25K Error Amp Vcc R Reset Dom 25K 3 LDrv 0.4V FbLo Comp 2.8V 4 Gnd POR SS Figure 2 - Simplified block diagram of the APU3137. 4/17 APU3137 THEORY OF OPERATION Introduction The APU3137 is a fixed frequency, voltage mode synchronous controller and consists of a precision reference voltage, an error amplifier, an internal oscillator, a PWM comparator, 1A peak gate driver, soft-start and shutdown circuits (see Block Diagram). The output voltage of the synchronous converter is set and controlled by the output of the error amplifier; this is the amplified error signal from the sensed output voltage and the reference voltage. This voltage is compared to a fixed frequency linear sawtooth ramp and generates fixed frequency pulses of variable duty-cycle, which drives the two N-channel external MOSFETs.The timing of the IC is provided through an internal oscillator circuit which uses on-chip capacitor to set the oscillation frequency to 200 KHz. Soft-Start The APU3137 has a programmable soft-start to control the output voltage rise and limit the current surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when the Vc and Vcc rise above their threshold (3.5V and 4.25V respectively) and generates the Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the soft-start function clamps the E/A's output of the PWM converter and disables the short circuit protection. During the power up, the output starts at zero and voltage at Fb is below 0.4V. The feedback UVLO is disabled during this time by injecting a current (64A) into the Fb. This generates a voltage about 1.6V (64Ax25K) across the negative input of E/A and positive input of the feedback UVLO comparator (see Fig3). 3V 20uA HDrv 64uA Max SS/SD POR Comp 0.8V 25K Error Amp LDrv The magnitude of this current is inversely proportional to the voltage at soft-start pin. The 20A current source starts to charge up the external capacitor. In the mean time, the soft-start voltage ramps up, the current flowing into Fb pin starts to decrease linearly and so does the voltage at the positive pin of feedback UVLO comparator and the voltage negative input of E/A. When the soft-start capacitor is around 1V, the current flowing into the Fb pin is approximately 32A. The voltage at the positive input of the E/A is approximately: 32Ax25K = 0.8V The E/A will start to operate and the output voltage starts to increase. As the soft-start capacitor voltage continues to go up, the current flowing into the Fb pin will keep decreasing. Because the voltage at pin of E/A is regulated to reference voltage 0.8V, the voltage at the Fb is: VFB = 0.8-25Kx(Injected Current) The feedback voltage increases linearly as the injecting current goes down. The injecting current drops to zero when soft-start voltage is around 2V and the output voltage goes into steady state. As shown in Figure 4, the positive pin of feedback UVLO comparator is always higher than 0.4V, therefore, feedback UVLO is not functional during soft-start. Output of UVLO POR 3V 2V Soft-Start Voltage Current flowing into Fb pin 1V 0V 64uA 0uA Voltage at negative input 1.6V of Error Amp and Feedback UVLO comparator 0.8V 0.8V 25K Fb Voltage at Fb pin 0V 0.4V 64uAx 25K=1.6V When SS=0 Feeback UVLO Comp POR Figure 4 - Theoretical operational waveforms during soft-start. Figure 3 - Soft-start circuit for APU3137. 5/17 APU3137 the output start-up time is the time period when softstart capacitor voltage increases from 1V to 2V. The startup time will be dependent on the size of the external soft-start capacitor. The start-up time can be estimated by: 20AxTSTART/CSS = 2V-1V For a given start up time, the soft-start capacitor can be estimated as: CSS 20AxTSTART/1V MOSFET Drivers The driver capabilities of both high and low side drivers are optimized to maintain fast switching transitions. They are sized to drive a MOSFET that can deliver up to 20A output current. The low side MOSFET driver is supplied directly by VCC while the high side driver is supplied by VC. An internal dead time control is implemented to prevent cross-conduction and allows the use of several kinds of MOSFETs. Short-Circuit Protection The outputs are protected against the short-circuit. The APU3137 protects the circuit for shorted output by sensing the output voltage (through the external resistor divider). The APU3137 turns off both drivers, when the output voltage drops below 0.4V. The APU3137 also protects the output from over-voltaging when the control FET is shorted. This is done by turning on the sync FET with the maximum duty cycle. Under-Voltage Lockout The under-voltage lockout circuit assures that the MOSFET driver outputs remain in the off state whenever the supply voltage drops below set parameters. Lockout occurs if Vc and Vcc fall below 3.5V and 4.25V respectively. Normal operation resumes once Vc and Vcc rise above the set values. Shutdown The converter can be shutdown by pulling the soft-start pin below 2.8V. This can be easily done by using an external small signal transistor. During shutdown both MOSFET drivers turn off. 6/17 APU3137 APPLICATION INFORMATION Design Example: The following example is a typical application for APU3137, the schematic is Figure 13 on page 15. Supply Voltage VIN = 5V VCC = VC = 12V VOUT = 2.5V IOUT = 15A VOUT = 75mV (output voltage ripple 3% of VOUT) fS = 200KHz Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is referenced to the voltage on non-inverting pin of error amplifier. The output voltage is defined by using the following equation: ( VOUT = VREFx 1 + R6 R5 ) ---(7) Css = 20xtSTART (F) ---(8) Where tSTART is the desired start-up time (ms) For a start-up time of 5ms, the soft-start capacitor will be 0.1F. Choose a ceramic capacitor at 0.1F. Boost Supply Vc To drive the high side switch, it is necessary to supply a gate voltage at least 4V grater than the bus voltage. For single supply applications, this is achieved by using a charge pump configuration as shown in Figure 6. This method is simple and inexpensive. The operation of the circuit is as follows: when the lower MOSFET is turned on, the capacitor (C1) is pulled down to ground and charges, up to VBUS value, through the diode (D1). The bus voltage will be added to this voltage when upper MOSFET turns on in next cycle, and providing supply voltage (Vc) through diode (D2). Vc is approximately: VC 2 x VBUS - (VD1 + VD2) VREF = 0.8V When an external resistor divider is connected to the output as shown in Figure 5. VOUT APU3137 R6 Fb R5 Capacitors in the range of 0.1F and 1F are generally adequate for most applications. The diode must be a fast recovery device to minimize the amount of charge fed back from the charge pump capacitor into Vc. The diodes need to be able to block the full power rail voltage, which is seen when the high side MOSFET is switched on. For low voltage application, schottky diodes can be used to minimize forward drop across the diodes at start up. For this application, Vc is biased by an external 12V supply. Figure 5 - Typical application of the APU3137 for programming the output voltage. Equation (7) can be rewritten as: R6 = R5 x ( ) VOUT -1 VREF Choose R5 = 1K This will result to R6 = 2.125K If the high value feedback resistors are used, the input bias current of the Fb pin could cause a slight increase in output voltage. The output voltage set point can be more accurate by using precision resistor. Soft-Start Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. The start-up time of the converter can be calculated by using: VBUS APU3137 D2 Vc C2 D1 C1 Q1 L2 HDrv Q2 Figure 6 - Charge pump circuit. Input Capacitor Selection The input filter capacitor should be based on how much ripple the supply can tolerate on the DC input line. The ripple current generated during the on time of upper MOSFET should be provided by input capacitor. The RMS value of this ripple is expressed by: 7/17 APU3137 IRMS = IOUT Dx(1-D) ---(9) Where: D is the Duty Cycle, D=VOUT/VIN. IRMS is the RMS value of the input capacitor current. IOUT is the output current for each channel. For VIN=5V, IOUT=15A and D=0.5, the IRMS=7.5A For higher efficiency, a low ESR capacitor is recommended. Choose four Poscap from Sanyo 6TPC150M (6.3V, 150F, 40m) with a maximum allowable ripple current of 7.6A. Inductor Selection The inductor is selected based on operating frequency, transient performance and allowable output voltage ripple. Low inductor value results to faster response to step load (high i/t) and smaller size but will cause larger output ripple due to increase of inductor ripple current. As a rule of thumb, select an inductor that produces a ripple current of 10-40% of full load DC. For the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: i VOUT 1 VIN - VOUT = Lx ; t = Dx ;D= t VIN fS VOUT L = (VIN - VOUT)x ---(11) VINxixfS Where: VIN = Maximum Input Voltage VOUT = Output Voltage i = Inductor Ripple Current fS = Switching Frequency t = Turn On Time D = Duty Cycle If i = 20%(IO), then the output inductor will be: L = 2H The Panasonic PCCN6B series provides a range of inductors in different values, low profile suitable for large currents, 2.17H, 17A is a good choice for this application. This will result to a ripple approximately 19.2% of output current. Output Capacitor Selection The criteria to select the output capacitor is normally based on the value of the Effective Series Resistance (ESR). In general, the output capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements. The ESR of the output capacitor is calculated by the following relationship: ESR VO IO ---(10) Where: VO = Output Voltage Ripple i = Inductor Ripple Current VO = 75mV and I 20% of 15A = 3A This results to: ESR=25m The Sanyo TPC series, Poscap capacitor is a good choice. The 6TPC330M, 330F, 6.3V has an ESR 40m. Selecting three of these capacitors in parallel, results to an ESR of 13.3m which achieves our low ESR goal. The capacitor value must be high enough to absorb the inductor's ripple current. The larger the value of capacitor, the lower will be the output ripple voltage. Power MOSFET Selection The APU3137 uses two N-Channel MOSFETs. The selections criteria to meet power transfer requirements is based on maximum drain-source voltage (VDSS), gatesource drive voltage (VGS), maximum output current, Onresistance RDS(ON) and thermal management. The MOSFET must have a maximum operating voltage (VDSS) exceeding the maximum input voltage (VIN). The gate drive requirement is almost the same for both MOSFETs. Logic-level transistor can be used and caution should be taken with devices at very low VGS to prevent undesired turn-on of the complementary MOSFET, which results a shoot-through current. The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter, the average inductor current is equal to the DC load current. The conduction loss is defined as: 2 PCOND(Upper Switch) = ILOADxRDS(ON)xDx 2 PCOND(Lower Switch) = ILOADxRDS(ON)x(1 - D)x = RDS(ON) Temperature Dependency The RDS(ON) temperature dependency should be considered for the worst case operation. This is typically given in the MOSFET data sheet. Ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. 8/17 APU3137 Choose IRF7832 for both control MOSFET and synchronous MOSFET. This device provides low on-resistance in a compact SOIC 8-Pin package. These values are taken under a certain condition test. For more details please refer to the IRF7466 and IRF7458 data sheets. The MOSFET has the following data: By using equation (12), we can calculate the total switching losses. IRF7832 VDSS = 30V ID = 20A @ 25 C RDS(ON) = 4m @ VGS=10V PSW(TOTAL) = 250mW The total conduction losses will be: PCON(TOTAL) = PCON(UPPER) + PCON(LOWER) PCON(TOTAL) = 1.166W The switching loss is more difficult to calculate, even though the switching transition is well understood. The reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turnoff delays and rise and fall times. The control MOSFET contributes to the majority of the switching losses in synchronous Buck converter. The synchronous MOSFET turns on under zero voltage conditions, therefore, the turn on losses for synchronous MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as: VDS(OFF) tr + tf ---(12) x x ILOAD T 2 Where: VDS(OFF) = Drain to Source Voltage at off time tr = Rise Time tf = Fall Time T = Switching Period ILOAD = Load Current PSW = Feedback Compensation The APU3137 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45 ). The output LC filter introduces a double pole, -40dB/ decade gain slope above its corner resonant frequency, and a total phase lag of 180 (see Figure 8). The Resonant frequency of the LC filter is expressed as follows: 1 FLC = ---(13) 2x LOxCO Figure 9 shows gain and phase of the LC filter. Since we already have 180 phase shift just from the output filter, the system risks being unstable. Gain Phase 0 0dB -40dB/decade The switching time waveform is shown in Figure 7. FLC Frequency VDS 90% -180 FLC Frequency Figure 8 - Gain and phase of LC filter. 10% VGS td(ON) tr td(OFF) tf Figure 7 - Switching time waveforms. From IRF7832 data sheet we obtain: IRF7832 tr = 12.3ns tf = 21ns 9/17 APU3137 The APU3137's error amplifier is a differential-input transconductance amplifier. The output is available for DC gain control or AC phase compensation. The E/A can be compensated with or without the use of local feedback. When operated without local feedback, the transconductance properties of the E/A become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp pin to ground as shown in Figure 9. Note that this method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general, the output capacitor's ESR generates a zero typically at 5KHz to 50KHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor expressed as follows: 1 FESR = ---(14) 2xESRxCo VOUT R6 Fb R5 Vp=VREF Ve C9 R4 Fo > FESR and FO (1/5 ~ 1/10)xfS Use the following equation to calculate R4: 1 VOSC FoxFESR R5 + R6 R4 = x x x gm VIN FLC2 R5 Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R5 and R6 = Resistor Dividers for Output Voltage Programming gm = Error Amplifier Transconductance For: VIN = 5V VOSC = 2.5V Fo = 20KHz FESR = 12KHz This results to R4=26.7K Choose R4=30K Optional FZ 0.75x The transfer function (Ve / VOUT) is given by: R5 1 + sR4C9 x R6 + R5 sC9 ) |H(s=jx2xFO)| = gmx 1 2xR4xC9 R5 xR4 R6xR5 ---(17) |H(s)| is the gain at zero cross frequency. ---(19) FZ = 2.57KHz R4 = 20K C9 2006pF; Choose C9 =3300pF One more capacitor is sometimes added in parallel with C9 and R4. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: ---(15) FP = The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: FZ = LO x CO 2 Using equations (17) and (19) to calculate C9, we get: Frequency Figure 9 - Compensation network without local feedback and its asymptotic gain plot. ( 1 For: Lo = 2.17H Co = 990F H(s) dB H(s) = gmx FLC = 3.43KHz R5 = 1K R6 = 2.15K gm = 600mho FZ 75%FLC Gain(dB) FZ ---(18) To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: Comp E/A First select the desired zero-crossover frequency (Fo): ---(16) 1 2xR4x C9xCPOLE C9 + CPOLE The pole sets to one half of switching frequency which results in the capacitor CPOLE: 1 1 CPOLE = xR4xfS 1 xR4xfS C9 For FP << fS/2 R4=30K and FS=200KHz will result to CPOLE=53pF. Choose CPOLE=47pF. 10/17 APU3137 For a general solution for unconditionally stability for ceramic capacitor with very low ESR and any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network. The typically used compensation network for voltage-mode controller is shown in Figure 10. VOUT ZIN C12 C10 R7 R8 FP1 = 0 FP2 = C11 Zf 1 FP3 = (CC xC +C ) 2xR7x FZ1 = R6 1 2xR8xC10 12 12 11 1 2xR7xC12 11 1 2xR7xC11 1 1 FZ2 = 2xC10x(R6 + R8) 2xC10xR6 Cross Over Frequency: Fb E/A R5 Comp Ve Gain(dB) H(s) dB FZ2 FP2 FP3 Frequency Figure 10 - Compensation network with local feedback and its asymptotic gain plot. In such configuration, the transfer function is given by: Ve 1 - gmZf = VOUT 1 + gmZIN The error amplifier gain is independent of the transconductance under the following condition: gmZf >> 1 and gmZIN >>1 ---(20) By replacing ZIN and Zf according to Figure 7, the transformer function can be expressed as: H(s) = (1+sR7C11)x[1+sC10(R6+R8)] 1 x sR6(C12+C11) C12C11 1+sR7 C12+C11 x(1+sR8C10) [ ( VIN 1 x VOSC 2xLoxCo ---(21) Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Lo = Output Inductor Co = Total Output Capacitors Vp=VREF FZ1 FO = R7xC10x )] As known, transconductance amplifier has high impedance (current source) output, therefore, consider should be taken when loading the E/A output. It may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows: The stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. The consideration has been taken to satisfy condition (20) regarding transconductance error amplifier. These design rules will give a crossover frequency approximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load transient speed. The gain margin will be large enough to provide high DC-regulation accuracy (typically -5dB to 12dB). The phase margin should be greater than 45 for overall stability. Based on the frequency of the zero generated by ESR versus crossover frequency, the compensation type can be different. The table below shows the compensation type and location of crossover frequency. Compensator Location of Zero Typical Type Crossover Frequency Output (FO) Capacitor Type II (PI) FPO < FZO < FO < fS/2 Electrolytic, Tantalum Type III (PID) FPO < FO < FZO < fS/2 Tantalum, Method A Ceramic Type III (PID) FPO < FO < fS/2 < FZO Ceramic Method B Table - The compensation type and location of zero crossover frequency. Detail information is dicussed in application Note AN1043 which can be downloaded from the IR Web-Site. 11/17 APU3137 Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components. Make all the connections in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET. To reduce the ESR, replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources and be placed close to the IC. In multilayer PCB, use one layer as power ground plane and have a separate control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. 12/17 APU3137 TYPICAL APPLICATION Single Supply 5V Input 5V D2 BAT54 D1 BAT54S 1uH C2 3x 6TPB150M, 150uF, 40m C4 1uF C3 0.1uF Vcc Q1 IRF7457 D3 BAT54 U1 APU3137 SS/SD L2 3.3uH Q2 IRF7457 LDrv Comp 3.3V @ 12A C7 2x 6TPC330M, 330uF, 40m R6 Fb C9 3.3nF C6 68pF C1 47uF C5 0.1uF Vc HDrv C8 0.1uF L1 3.16K, 1% Gnd R4 18K R5 1K, 1% Figure 11 - Typical application of APU3137 in an on-board DC-DC converter using a single 5V supply. 13/17 APU3137 TYPICAL APPLICATION 5V 12V C1 0.1uF L1 1uH C2 1uF Vcc Vc HDrv SS C6 0.1uF C5 4x 150uF 6TPB150M U1 APU3137 D1 1N4148 Q1 IRF3711S Q2 IRF3711S Comp Gnd R3 1K 12V 5V C9 0.1uF C10 1uF Vcc VREF SS C12 0.15uF HDrv U2 APU3038 C16 47pF C14 6800pF D2 1N4148 Q3 IRF7460 L3 2.2uH LDrv Rt Comp C11 3x 150uF 6TPB150M Vc VP R5 1K C7 3x 330uF 6TPC330M 1K R2 20K R4 1K VDDQ 1.8V @ 15A R1 Fb C8 3300pF L2 2.2uH LDrv C15 68pF 5V C4 47uF PGnd Q4 IRF7457 VTT (0.9V @ 10A) C13 3x 330uF 6TPC330M Fb Gnd R6 12K Figure 12 - Typical application of APU3137 for DDR memory when the termination voltage, generated by APU3038, tracks the core voltage. 14/17 APU3137 DEMO-BOARD APPLICATION 5V to 2.5V @ 15A L1 VIN 5V 1uH C1 150uF Gnd C19 150uF C18 150uF C23 150uF C20 150uF 12V C4 1uF Vcc Vc C3 1uF Q1 IRF7832 L2 HDrv D3 SS/SD C8 0.1uF C6 1uF VOUT 2.5V @ 15A 2.17uH U1 APU3137 LDrv Q2 IRF7832 C9 470pF R6 4.7 C10 330uF C11 330uF C12 C21 330uF 1uF Comp Gnd C15 3300pF C13 47pF Gnd R8 Fb 2.15K R11 1K R9 30K Figure 13 - Demo-board application of APU3137. Application Parts List Ref Desig Q1, Q2 U1 D3 L1 L2 C1,C18,C19,C20,C23 C10,C11,C21 C8 C3,C4,C12,C6 C9 C15 C13 R8 R6 R11 R9 Description MOSFET Controller Diode Inductor Inductor Capacitor, Poscap Capacitor, Poscap Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Resistor Resistor Resistor Resistor Value Qty Part# 30V, 4m, 15A 2 IRF7832 Synchronous PWM 1 APU3137 Fast Switching 1 BAT54 1H, 10A 1 D03316P-102HC 2.17H, 17A 1 ETQP6F2R5BFA 150F, 6.3V, 40m 5 6TPC150M 330F, 6.3V, 40m 3 6TPC330M 0.1F, Y5V, 25V 1 ECJ-2VF1E104Z 1F, Y5V, 16V 4 ECJ-3YB1E105K 470pF, X7R 1 ECJ-2VB2D471K 3300pF, X7R, 50V 1 ECJ-2VB1H332K 47pF, NPO 1 ECJ-2VC1H470J 2.15K, 1% 1 4.7, 5% 1 1K, 1% 1 30K, 1% 1 Manuf IR APEC IR Coilcraft Panasonic Sanyo Sanyo Panasonic Panasonic Panasonic Panasonic Panasonic 15/17 APU3137 TYPICAL OPERATING CHARACTERISTICS Figure 14 - Transient load response at IOUT=0A - 8A. Ch1: VOUT Ch4: IOUT (5A/div) Figure 15 - Normal condition at N/L. Ch1: Output Voltage Ripple (20mV/div) Ch2: HDrv Ch3: LDrv Ch4: Inductor Current (2A/div) Figure 16 - Transient load response at IOUT=0A - 15A. Ch1: VOUT Ch4: IOUT (5A/div) Figure 17 - Normal condition at 15A. Ch1: Output Voltage Ripple (20mV/div) Ch2: HDrv Ch3: LDrv Ch4: Inductor Current (5A/div) 16/17 APU3137 TYPICAL OPERATING CHARACTERISTICS Figure 18 - Shutdown by pulling down the soft-start pin. Ch1: VOUT Ch2: HDrv Ch3: LDrv Ch4: IOUT (10A/div) Figure 19 - Start-Up. Ch2: VSS (Soft-Start Voltage) Ch3: VOUT Ch4: IOUT (5A/div) 120 100 Efficiency (%) 80 60 40 20 0 0 2 4 6 8 10 12 14 16 18 Output Current (A) Figure 20 - Application circuit efficiency at ambient temperature. 5V to 2.5V 17/17