APU3137M - Advanced Power Electronics Corp. USA

APU3137

200510061-1/17

Data and specifications subject to change without notice.

DESCRIPTION

The APU3137 controller IC is designed to provide a low

cost and high performance synchronous Buck regulator

for on-board DC to DC converter applications. The out-

put voltage can be set as low as 0.8V and higher voltage

can be obtained with an external voltage divider. High

peak current gate drivers provide fast switching transi-

tion for applications requiring high output current in the

range of 15A to 20A.

This device features an internal 200KHz oscillator, un-

der-voltage lockout for both Vcc and Vc supplies, an

external programmable soft-start function as well as

output under-voltage detection that latches off the de-

vice when an output short is detected.

1A Peak Output Drive Capability

0.8V Reference Voltage

Shuts off both drivers at shorted output

and shutdown

Operating with single 5V or 12V supply voltage

Stable with ceramic capacitors

Internal 200KHz Oscillator

Soft-Start Function

Protects the output when control FET is shorted

Synchronous Controller in 8-Pin Package

PACKAGE ORDER INFORMATION

FEATURES

8-PIN SYNCHRONOUS PWM CONTROLLER

APPLICATIONS

DDR Memory Application

Low voltage distributed DC-DC

Graphic Cards

Low cost on-board DC to DC such as 5V to 2.5V,

1.8V or 0.8V

RoHS Complaint

TA (°C) DEVICE PACKAGE FREQUENCY

0 To 70 APU3137M 8-Pin Plastic SOIC NB (M) 200KHz

Technology Licensed from International Rectifier

Figure 1 - Typical application of APU3137.

TYPICAL APPLICATION

APU3137

Vcc Vc

HDrv

LDrv

Gnd

Comp

SS/SD

1uF C4

1uF

0.1uF

3300pF

30K

IRF7832

1K, 1%

2.15K

2.2uH

1uH

4x 150uF

47uF

2.5V

@ 15A

3x 330uF

40m

Ω

, Poscap

12V 5V

Optional

2/17

APU3137

ABSOLUTE MAXIMUM RA TINGS

Vcc Supply Voltage .................................................. -0.5V - 25V

Vc Supply Voltage .................................................... -0.5V - 25V

Storage Temperature Range ...................................... -65°C To 150°C

Operating Junction Temperature Range ..................... 0°C To 125°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device.

PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS

Vcc

LDrv

Gnd HDrv

Comp

Reference Voltage

Fb V oltage

Fb V oltage Line Regulation

UVLO

UVLO Threshold - Vcc

UVLO Hysteresis - Vcc

UVLO Threshold - Vc

UVLO Hysteresis - Vc

UVLO Threshold - Fb

UVLO Hysteresis - Fb

Supply Current

Vcc Dynamic Supply Current

Vc Dynamic Supply Current

Vcc Static Supply Current

Vc Static Supply Current

Soft-Start Section

Charge Current

5<Vcc<12

Supply Ramping Up

Fb Ramping Down

Freq=200KHz, CL=3000pF

SS=0V

0.784

4.0

3.0

0.3

0.800

4.25

0.25

3.5

0.25

0.4

0.25

6.5

2.5

0.816

1.6

4.5

3.65

0.5

µA

VFB

LREG

UVLO Vcc

UVLO Vc

UVLO Fb

Dyn Icc

Dyn Ic

ICCQ

ICQ

SSIB

θJA=160°C/W

ELECTRICAL SPECIFICA TIONS

Unless otherwise specified, these specifications apply over Vcc=5V , Vc=12V and TA=0 to 70°C. T ypical values refer

to TA=25C.

P ACKAGE INFORMATION

8-PIN PLASTIC SOIC NB (M)

APU3137

3/17

PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS

PIN DESCRIPTIONS

This pin is connected directly to the output of the switching regulator via resistor divider to

provide feedback to the Error amplifier .

This pin provides biasing for the internal blocks of the IC as well as power for the low side

driver. A minimum of 1µF, high frequency capacitor must be connected from this pin to

ground to provide peak drive current capability .

Output driver for the synchronous power MOSFET.

This pin serves as the ground pin and must be connected directly to the ground plane. A

high frequency capacitor (0.1 to 1µF) must be connected from VCC and Vc pins to this

pin for noise free operation.

Output driver for the high side power MOSFET. This pin should not go negative (below

ground), this may cause problem for the gate drive circuit. It can happen when the inductor

current goes negative (Source/Sink), soft-start at no load and for the fast load transient

from full load to no load. To prevent negative voltage at gate drive, a low forward voltage

drop diode might be connected between this pin and ground.

This pin is connected to a voltage that must be at least 4V higher than the bus voltage of

the switcher (assuming 5V threshold MOSFET) and powers the high side output driver . A

minimum of 1µF, high frequency capacitor must be connected from this pin to ground to

provide peak drive current capability .

Compensation pin of the error amplifier. An external resistor and capacitor network is

typically connected from this pin to ground to provide loop compensation.

This pin provides soft-start for the switching regulator . An internal current source charges

an external capacitor that is connected from this pin to ground which ramps up the output

of the switching regulator, preventing it from overshooting as well as limiting the input

current. The converter can be shutdown by pulling this pin below 2.8V .

Error Amp

Fb Voltage Input Bias Current

Transconductance

Oscillator

Frequency

Ramp-Amplitude V oltage

Output Drivers

Rise Time

Fall Time

Dead Band Time

Max Duty Cycle

Min Duty Cycle

SS=3V, Fb=1V

SS=0V, Fb=1V

Note 1

CL=3000pF (10% to 90%)

CL=3000pF (90% to 10%)

Fb=0.7V , Freq=200KHz

Fb=1.5V

600

180

0.1

850

1.25

100

µA

µmho

KHz

PIN# PIN SYMBOL PIN DESCRIPTION

Vcc

LDrv

Gnd

HDrv

Comp

SS / SD

IFB1

IFB2

Freq

VRAMP

TDB

TON

TOFF

1100

240

Note 1: Guaranteed by design but not tested in production.

4/17

APU3137

BLOCK DIAGRAM

Figure 2 - Simplified block diagram of the APU3137.

20uA

64uA Max

POR

Oscillator

E rro r A mp

Error Comp

Reset Dom

POR

0.4V FbLo Comp

HDrv

Vcc

LDrv

Gnd

Vcc

4.25V

3.5V

Bias

Generator 3V

0.8V

POR

SS/SD

Comp

25K

0.8V

2.8V

APU3137

5/17

THEORY OF OPERA TION

Introduction

The APU3137 is a fixed frequency, voltage mode syn-

chronous controller and consists of a precision refer-

ence voltage, an error amplifier , an internal oscillator , a

PWM comparator, 1A peak gate driver, soft-start and

shutdown circuits (see Block Diagram).

The output voltage of the synchronous converter is set

and controlled by the output of the error amplifier; this is

the amplified error signal from the sensed output voltage

and the reference voltage.

This voltage is compared to a fixed frequency linear

sawtooth ramp and generates fixed frequency pulses of

variable duty-cycle, which drives the two N-channel ex-

ternal MOSFETs.The timing of the IC is provided through

an internal oscillator circuit which uses on-chip capaci-

tor to set the oscillation frequency to 200 KHz.

Soft-Start

The APU3137 has a programmable soft-start to control

the output voltage rise and limit the current surge at the

start-up. To ensure correct start-up, the soft-start se-

quence initiates when the Vc and Vcc rise above their

threshold (3.5V and 4.25V respectively) and generates

the Power On Reset (POR) signal. Soft-start function

operates by sourcing an internal current to charge an

external capacitor to about 3V . Initially , the soft-start func-

tion clamps the E/A’ s output of the PWM converter and

disables the short circuit protection. During the power

up, the output starts at zero and voltage at Fb is below

0.4V. The feedback UVLO is disabled during this time

by injecting a current (64µA) into the Fb. This generates

a voltage about 1.6V (64µA×25K) across the negative

input of E/A and positive input of the feedback UVLO

comparator (see Fig3).

Figure 3 - Soft-start circuit for APU3137.

The magnitude of this current is inversely proportional to

the voltage at soft-start pin.

The 20µA current source starts to charge up the exter-

nal capacitor. In the mean time, the soft-start voltage

ramps up, the current flowing into Fb pin starts to de-

crease linearly and so does the voltage at the positive

pin of feedback UVLO comparator and the voltage nega-

tive input of E/A.

When the soft-start cap acitor is around 1V, the current

flowing into the Fb pin is approximately 32µA. The volt-

age at the positive input of the E/A is approximately:

The E/A will start to operate and the output voltage starts

to increase. As the soft-start capacitor voltage contin-

ues to go up, the current flowing into the Fb pin will keep

decreasing. Because the voltage at pin of E/A is regu-

lated to reference voltage 0.8V, the voltage at the Fb is:

The feedback voltage increases linearly as the injecting

current goes down. The injecting current drops to zero

when soft-start voltage is around 2V and the output volt-

age goes into steady state.

As shown in Figure 4, the positive pin of feedback UVLO

comparator is always higher than 0.4V, therefore, feed-

back UVLO is not functional during soft-start.

Figure 4 - Theoretical operational waveforms

during soft-start.

32µA×25K = 0.8V

VFB = 0.8-25K×(Injected Current)

20uA

64uA

Max

POR

Erro r A m p

64uA

25K=1.6V

When SS=0 POR

0.4V

Feeback

UVLO Comp

SS/SD

Comp 25K

0.8V

25K

HDrv

LDrv

S oft - Start

Voltage

Voltage at negative input

of Error Amp and Feedback

UVLO com parator

Voltage at Fb pin

Current flowing

into F b pi n

64uA

0uA

0.8V

≅

1.6V 0.8V

≅

Output of UVL O

POR

6/17

APU3137

Short-Circuit Protection

The outputs are protected against the short-circuit. The

APU3137 protects the circuit for shorted output by sens-

ing the output voltage (through the external resistor di-

vider). The APU3137 turns off both drivers, when the out-

put voltage drops below 0.4V .

The APU3137 also protects the output from over-voltaging

when the control FET is shorted. This is done by turning

on the sync FET with the maximum duty cycle.

Under-V oltage Lockout

The under-voltage lockout circuit assures that the

MOSFET driver outputs remain in the off state whenever

the supply voltage drops below set parameters. Lockout

occurs if Vc and Vcc fall below 3.5V and 4.25V respec-

tively . Normal operation resumes once Vc and Vcc rise

above the set values.

Shutdown

The converter can be shutdown by pulling the soft-start

pin below 2.8V. This can be easily done by using an

external small signal transistor. During shutdown both

MOSFET drivers turn off.

the output start-up time is the time period when soft-

start capacitor voltage increases from 1V to 2V . The start-

up time will be dependent on the size of the external

soft-start capacitor . The start-up time can be estimated

by:

For a given start up time, the soft-start capacitor can be

estimated as:

MOSFET Drivers

The driver capabilities of both high and low side drivers

are optimized to maintain fast switching transitions. They

are sized to drive a MOSFET that can deliver up to 20A

output current.

The low side MOSFET driver is supplied directly by VCC

while the high side driver is supplied by VC.

An internal dead time control is implemented to prevent

cross-conduction and allows the use of several kinds of

MOSFETs.

CSS ≅ 20µA×TSTART/1V

20µA×TSTART/CSS = 2V -1V

APU3137

7/17

APPLICATION INFORMA TION

Design Example:

The following example is a typical application for APU3137,

the schematic is Figure 13 on page 15.

Output Voltage Programming

Output voltage is programmed by reference voltage and

external voltage divider . The Fb pin is the inverting input

of the error amplifier , which is referenced to the voltage

on non-inverting pin of error amplifier. The output voltage

is defined by using the following equation:

When an external resistor divider is connected to the

output as shown in Figure 5.

Figure 5 - Typical application of the APU3137 for

programming the output voltage.

Equation (7) can be rewritten as:

Choose R5 = 1K

This will result to R6 = 2.125K

If the high value feedback resistors are used, the input

bias current of the Fb pin could cause a slight increase

in output voltage. The output voltage set point can be

more accurate by using precision resistor .

Soft-Start Programming

The soft-start timing can be programmed by selecting

the soft-start capacitance value. The start-up time of the

converter can be calculated by using:

Where tSTART is the desired start-up time (ms)

For a start-up time of 5ms, the soft-start capacitor will

be 0.1µF. Choose a ceramic capacitor at 0.1µF.

Boost Supply Vc

To drive the high side switch, it is necessary to supply a

gate voltage at least 4V grater than the bus voltage. For

single supply applications, this is achieved by using a

charge pump configuration as shown in Figure 6. This

method is simple and inexpensive. The operation of the

circuit is as follows: when the lower MOSFET is turned

on, the capacitor (C1) is pulled down to ground and

charges, up to VBUS value, through the diode (D1). The

bus voltage will be added to this voltage when upper

MOSFET turns on in next cycle, and providing supply

voltage (Vc) through diode (D2). Vc is approximately:

Capacitors in the range of 0.1µF and 1µF are generally

adequate for most applications. The diode must be a

fast recovery device to minimize the amount of charge

fed back from the charge pump capacitor into Vc. The

diodes need to be able to block the full power rail volt-

age, which is seen when the high side MOSFET is

switched on. For low voltage application, schottky di-

odes can be used to minimize forward drop across the

diodes at start up. For this application, Vc is biased by

an external 12V supply .

Figure 6 - Charge pump circuit.

Input Capacitor Selection

The input filter capacitor should be based on how much

ripple the supply can tolerate on the DC input line. The

ripple current generated during the on time of upper

MOSFET should be provided by input capacitor. The RMS

value of this ripple is expressed by:

VC ≅ 2 × VBUS - (VD1 + VD2)

VOUT = VREF× 1 +

---(7)

VREF = 0.8V

( )

R6 = R5 ×

- 1

VOUT

VREF

( )

APU3137

OUT

APU3137

HDrv

BUS

D2 D1

Css = 20×tSTART (µF) ---(8)

VIN = 5V

VOUT = 2.5V

IOUT = 15A

∆VOUT = 75mV

(output voltage ripple ≅ 3% of VOUT)

fS = 200KHz

Supply V oltage

VCC = VC = 12V

8/17

APU3137

For higher efficiency, a low ESR capacitor is recom-

mended. Choose four Poscap from Sanyo 6TPC150M

(6.3V, 150µF, 40mΩ) with a maximum allowable ripple

current of 7.6A.

Inductor Selection

The inductor is selected based on operating frequency ,

transient performance and allowable output voltage ripple.

Low inductor value results to faster response to step

load (high ∆i/∆t) and smaller size but will cause larger

output ripple due to increase of inductor ripple current.

As a rule of thumb, select an inductor that produces a

ripple current of 10-40% of full load DC.

For the buck converter, the inductor value for desired

operating ripple current can be determined using the fol-

lowing relation:

If ∆i = 20%(IO), then the output inductor will be:

The Panasonic PCCN6B series provides a range of in-

ductors in different values, low profile suitable for large

currents, 2.17µH, 17A is a good choice for this applica-

tion. This will result to a ripple approximately 19.2% of

output current.

Output Capacitor Selection

The criteria to select the output capacitor is normally

based on the value of the Effective Series Resistance

(ESR). In general, the output capacitor must have low

enough ESR to meet output ripple and load transient

L = 2µH2

PCOND(Upper Switch) = ILOAD×RDS(ON)×D×ϑ

PCOND(Lower Switch) = ILOAD×RDS(ON)×(1 - D)×ϑ

ϑ = RDS(ON) Temperature Dependency

For VIN=5V, IOUT=15A and D=0.5, the IRMS=7.5A

IRMS = IOUT D×(1-D) ---(9)

Where:

D is the Duty Cycle, D=VOUT/VIN.

IRMS is the RMS value of the input capacitor current.

IOUT is the output current for each channel.

VIN - VOUT = L× ; ∆t = D× ; D =

fSVOUT

VIN

∆i

∆t

L = (VIN - VOUT)× ---(11)

VOUT

VIN×∆i×fS

Where:

VIN = Maximum Input V olt age

VOUT = Output V olt age

∆i = Inductor Ripple Current

fS = Switching Frequency

∆t = Turn On Time

D = Duty Cycle

Where:

∆VO = Output V oltage Ripple

∆i = Inductor Ripple Current

∆VO = 75mV and ∆I ≅ 20% of 15A = 3A

This results to: ESR=25mΩ

ESR ≤ ---(10)

∆VO

∆IO

requirements, yet have high enough ESR to satisfy sta-

bility requirements. The ESR of the output capacitor is

calculated by the following relationship:

The Sanyo TPC series, Poscap capacitor is a good choice.

The 6TPC330M, 330µF, 6.3V has an ESR 40mΩ. Se-

lecting three of these capacitors in parallel, results to an

ESR of ≅ 13.3mΩ which achieves our low ESR goal.

The capacitor value must be high enough to absorb the

inductor's ripple current. The larger the value of capaci-

tor , the lower will be the output ripple voltage.

Power MOSFET Selection

The APU3137 uses two N-Channel MOSFETs. The se-

lections criteria to meet power transfer requirements is

based on maximum drain-source voltage (VDSS), gate-

source drive voltage (VGS), maximum output current, On-

resistance RDS(ON) and thermal management.

The MOSFET must have a maximum operating voltage

(VDSS) exceeding the maximum input voltage (VIN).

The gate drive requirement is almost the same for both

MOSFETs. Logic-level transistor can be used and cau-

tion should be taken with devices at very low VGS to pre-

vent undesired turn-on of the complementary MOSFET,

which results a shoot-through current.

The total power dissipation for MOSFETs includes con-

duction and switching losses. For the Buck converter,

the average inductor current is equal to the DC load cur-

rent. The conduction loss is defined as:

The RDS(ON) temperature dependency should be consid-

ered for the worst case operation. This is typically given

in the MOSFET data sheet. Ensure that the conduction

losses and switching losses do not exceed the package

ratings or violate the overall thermal budget.

APU3137

9/17

Choose IRF7832 for both control MOSFET and synchro-

nous MOSFET. This device provides low on-resistance

in a compact SOIC 8-Pin package.

The MOSFET has the following data:

The total conduction losses will be:

The switching loss is more difficult to calculate, even

though the switching transition is well understood. The

reason is the effect of the parasitic components and

switching times during the switching procedures such

as turn-on / turnoff delays and rise and fall times. The

control MOSFET contributes to the majority of the switch-

ing losses in synchronous Buck converter. The synchro-

nous MOSFET turns on under zero voltage conditions,

therefore, the turn on losses for synchronous MOSFET

can be neglected. With a linear approximation, the total

switching loss can be expressed as:

The switching time waveform is shown in Figure 7.

Figure 7 - Switching time waveforms.

From IRF7832 data sheet we obtain:

These values are taken under a certain condition test.

For more details please refer to the IRF7466 and IRF7458

data sheets.

By using equation (12), we can calculate the total switch-

ing losses.

Feedback Compensation

The APU3137 is a voltage mode controller; the control

loop is a single voltage feedback path including error

amplifier and error comparator . To achieve fast transient

response and accurate output regulation, a compensa-

tion circuit is necessary. The goal of the compensation

network is to provide a closed loop transfer function with

the highest 0dB crossing frequency and adequate phase

margin (greater than 45).

The output LC filter introduces a double pole, –40dB/

decade gain slope above its corner resonant frequency ,

and a total phase lag of 180 (see Figure 8). The Reso-

nant frequency of the LC filter is expressed as follows:

Figure 9 shows gain and phase of the LC filter. Since we

already have 180 phase shift just from the output filter ,

the system risks being unstable.

Figure 8 - Gain and phase of LC filter .

PCON(TOTAL) = PCON(UPPER) + PCON(LOWER)

PCON(TOTAL) = 1.166W

PSW(TOTAL) = 250mW

IRF7832

VDSS = 30V

ID = 20A @ 25C

RDS(ON) = 4mΩ @ VGS=10V

Where:

VDS(OFF) = Drain to Source V olt age at of f time

tr = Rise Time

tf = Fall Time

T = Switching Period

ILOAD = Load Current

PSW = ILOAD ---(12)

VDS(OFF)

2tr + tf

T×

IRF7832

tr = 12.3ns

tf = 21ns

FLC = ---(13)

2π× LO×CO

10%

90%

(ON)

(OFF)

Gain

0dB

Phase



-180



Frequency Frequency

-40dB/decade

10/17

APU3137

The APU3137’s error amplifier is a differential-input

transconductance amplifier. The output is available for

DC gain control or AC phase compensation.

The E/A can be compensated with or without the use of

local feedback. When operated without local feedback,

the transconductance properties of the E/A become evi-

dent and can be used to cancel one of the output filter

poles. This will be accomplished with a series RC circuit

from Comp pin to ground as shown in Figure 9.

Note that this method requires that the output capacitor

should have enough ESR to satisfy stability requirements.

In general, the output capacitor’s ESR generates a zero

typically at 5KHz to 50KHz which is essential for an

acceptable phase margin.

The ESR zero of the output capacitor expressed as fol-

lows:

Figure 9 - Compensation network without local

feedback and its asymptotic gain plot.

The transfer function (V e / VOUT) is given by:

The (s) indicates that the transfer function varies as a

function of frequency . This configuration introduces a gain

and zero, expressed by:

|H(s)| is the gain at zero cross frequency .

First select the desired zero-crossover frequency (Fo):

Use the following equation to calculate R4:

To cancel one of the LC filter poles, place the zero be-

fore the LC filter resonant frequency pole:

Using equations (17) and (19) to calculate C9, we get:

One more capacitor is sometimes added in parallel with

C9 and R4. This introduces one more pole which is mainly

used to suppress the switching noise. The additional

pole is given by:

The pole sets to one half of switching frequency which

results in the capacitor CPOLE:

C9 ≅ 2006pF; Choose C9 =3300pF

FESR = ---(14)

2π×ESR×Co

H(s) = gm× × ---(15)

( )

R6 + R51 + sR4C9

sC9

R4 = × × × ---(18)

Fo×FESR

FLC2

VOSC

VIN R5 + R6

Fo > FESR and FO ≤ (1/5 ~ 1/10)×fS

For:

Lo = 2.17µH

Co = 990µF

FZ ≅ 75%FLC

FZ ≅ 0.75×1

2π LO × CO---(19)

FZ = 2.57KHz

R4 = 20K

FP = 2π×R4×

1C9×CPOLE

C9 + CPOLE

FZ = ---(17)

2π×R4×C9

|H(s=j×2π×FO)| = gm× ×R4 ---(16)

R6×R5

OUT

Vp=V

REF

E/A

H(s) dB

Frequency

Gain(dB)

Fb Comp

Optional

FLC = 3.43KHz

R5 = 1K

R6 = 2.15K

gm = 600µmho

For:

VIN = 5V

VOSC = 2.5V

Fo = 20KHz

FESR = 12KHz

This results to R4=26.7K

Choose R4=30K

Where:

VIN = Maximum Input V olt age

VOSC = Oscillator Ramp V olt age

Fo = Crossover Frequency

FESR = Zero Frequency of the Output Capacitor

FLC = Resonant Frequency of the Output Filter

R5 and R6 = Resistor Dividers for Output V oltage

Programming

gm = Error Amplifier Transconductance

For FP << fS/2

R4=30K and FS=200KHz will result to CPOLE=53pF.

Choose CPOLE=47pF.

CPOLE = ≅1

π×R4×fS

π×R4×fS -

APU3137

11/17

For a general solution for unconditionally stability for

ceramic capacitor with very low ESR and any type of

output capacitors, in a wide range of ESR values we

should implement local feedback with a compensation

network. The typically used compensation network for

voltage-mode controller is shown in Figure 10.

Figure 10 - Compensation network with local

feedback and its asymptotic gain plot.

In such configuration, the transfer function is given by:

The error amplifier gain is independent of the transcon-

ductance under the following condition:

By replacing ZIN and Zf according to Figure 7, the trans-

former function can be expressed as:

As known, transconductance amplifier has high imped-

ance (current source) output, therefore, consider should

be taken when loading the E/A output. It may exceed its

source/sink output current capability, so that the ampli-

fier will not be able to swing its output voltage over the

necessary range.

The compensation network has three poles and two ze-

ros and they are expressed as follows:

Cross Over Frequency:

The stability requirement will be satisfied by placing the

poles and zeros of the compensation network according

to following design rules. The consideration has been

taken to satisfy condition (20) regarding transconduc-

tance error amplifier .

These design rules will give a crossover frequency ap-

proximately one-tenth of the switching frequency. The

higher the band width, the potentially faster the load tran-

sient speed. The gain margin will be large enough to

provide high DC-regulation accuracy (typically -5dB to -

12dB). The phase margin should be greater than 45 for

overall stability .

Based on the frequency of the zero generated by ESR

versus crossover frequency , the compensation type can

be different. The table below shows the compensation

type and location of crossover frequency .

OUT

Vp=V

REF

E/A

Frequency

Gain(dB)

H(s) dB

Fb Comp

H(s) = 1+sR7

×(1+sR8C10)

(1+sR7C11)×[1+sC10(R6+R8)]

×[ ( )]

sR6(C12+C11)C12C11

C12+C11

gmZf >> 1 and gmZIN >>1 ---(20)

1 - gmZf

1 + gmZIN

VOUT =

Where:

VIN = Maximum Input V olt age

VOSC = Oscillator Ramp V oltage

Lo = Output Inductor

Co = Tot al Output Capacitors

FO = R7×C10× ×

VIN

VOSC 1

2π×Lo×Co ---(21)

FP1 = 0

2π×C10×(R6 + R8)

FZ2 = ≅1

2π×C10×R6

FZ1 = 1

2π×R7×C11

FP3 = ≅

2π×R7×

2π×R7×C12

FP2 = 1

2π×R8×C10

( )

C12×C11

C12+C11

Detail information is dicussed in application Note AN-

1043 which can be downloaded from the IR Web-Site.

Compensator

Type

Type II (PI)

Type III (PID)

Method A

Type III (PID)

Method B

Location of Zero

Crossover Frequency

(FO)

FPO < FZO < FO < f S/2

FPO < FO < FZO < f S/2

FPO < FO < fS/2 < FZO

Typical

Output

Capacitor

Electrolytic,

Tantalum

Tantalum,

Ceramic

Table - The compensation type and location of zero

crossover frequency .

12/17

APU3137

Layout Consideration

The layout is very important when designing high fre-

quency switching converters. Layout will affect noise

pickup and can cause a good design to perform with

less than expected results.

Start to place the power components. Make all the con-

nections in the top layer with wide, copper filled areas.

The inductor , output capacitor and the MOSFET should

be close to each other as possible. This helps to reduce

the EMI radiated by the power traces due to the high

switching currents through them. Place input capacitor

directly to the drain of the high-side MOSFET. To reduce

the ESR, replace the single input capacitor with two par-

allel units. The feedback part of the system should be

kept away from the inductor and other noise sources

and be placed close to the IC. In multilayer PCB, use

one layer as power ground plane and have a separate

control circuit ground (analog ground), to which all sig-

nals are referenced. The goal is to localize the high cur-

rent path to a separate loop that does not interfere with

the more sensitive analog control function. These two

grounds must be connected together on the PC board

layout at a single point.

APU3137

13/17

TYPICAL APPLICATION

Single Supply 5V Input

Figure 11 - Typical application of APU3137 in an on-board DC-DC converter

using a single 5V supply.

APU3137

Vcc Vc

HDrv

LDrv

Gnd

Comp

SS/SD

0.1uF C4

1uF

0.1uF

3.3nF

18K

IRF7457

1K, 1%

3.16K, 1%

1uH

3x 6TPB150M,

150uF, 40m

Ω

47uF

3.3V

@ 12A

2x 6TPC 3 30M ,

330uF, 40m

Ω

0.1uF

BAT54S

BAT54

3.3uH

68pF

BAT54

14/17

APU3137

TYPICAL APPLICATION

Figure 12 - Typical application of APU3137 for DDR memory when the termination voltage,

generated by APU3038, tracks the core voltage.

APU3137

Vcc Vc

HDrv

LDrv

Comp

0.1uF C2

1uF

0.1uF

3300pF

20K

IRF3711S L2

1uH C4

47uF

DDQ

1.8V @ 15A

3x 330uF

6TPC330M

12V 5V

APU3038

Vcc Vc

HDrv

LDrv

Gnd

Comp

0.1uF C10

1uF

C12

0.15uF

C14

6800pF

12K

IRF7460

IRF7457

2.2uH

(0.9V @ 10A)

C13

3x 330uF

6TPC330M

12V

PGnd

REF

Gnd

2.2uH

C11

3x 150uF

6TPB150M

1N4148

C15

68pF

C16

47pF

1N4148

IRF3711S

4x 150uF

6TPB150M

APU3137

15/17

DEMO-BOARD APPLICATION

5V to 2.5V @ 15A

Ref Desig Description Value Qty Part# Manuf

Q1, Q2

C1,C18,C19,C20,C23

C10,C11,C21

C3,C4,C12,C6

C15

C13

R11

MOSFET

Controller

Diode

Inductor

Capacitor , Poscap

Capacitor , Ceramic

Resistor

IRF7832

APU3137

BAT54

D03316P-102HC

ETQP6F2R5BFA

6TPC150M

6TPC330M

ECJ-2VF1E104Z

ECJ-3YB1E105K

ECJ-2VB2D471K

ECJ-2VB1H332K

ECJ-2VC1H470J

APEC

Coilcraft

Panasonic

Sanyo

Panasonic

Application Parts List

30V , 4mΩ, 15A

Synchronous PWM

Fast Switching

1µH, 10A

2.17µH, 17A

150µF, 6.3V, 40mΩ

330µF, 6.3V, 40mΩ

0.1µF, Y5V, 25V

1µF, Y5V, 16V

470pF , X7R

3300pF, X7R, 50V

47pF, NPO

2.15K, 1%

4.7Ω, 5%

1K, 1%

30K, 1%

Figure 13 - Demo-board application of APU3137.

470pF

APU3137

Vcc Vc

HDrv

LDrv

Gnd

Comp

SS/SD

Gnd

IRF7832

C18

150uF C23

150uF

30K

150uF

D3 2.17uH

4.7

Ω

C10

330uF C12

1uF

1uH

1uF C6

1uF

0.1uF

C15

3300pF 2.15K

OUT

2.5V

@ 15A

R11

C11

330uF

12V

C13

47pF

C21

330uF

C19

150uF C20

150uF

16/17

APU3137

Figure 17 - Normal condition at 15A.

Ch1: Output Voltage Ripple (20mV/div)

Ch2: HDrv

Ch3: LDrv

Ch4: Inductor Current (5A/div)

Figure 15 - Normal condition at N/L.

Ch1: Output Voltage Ripple (20mV/div)

Ch2: HDrv

Ch3: LDrv

Ch4: Inductor Current (2A/div)

Figure 16 - Transient load response at IOUT=0A - 15A.

Ch1: VOUT

Ch4: IOUT (5A/div)

Figure 14 - Transient load response at IOUT=0A - 8A.

Ch1: VOUT

Ch4: IOUT (5A/div)

TYPICAL OPERA TING CHARACTERISTICS

APU3137

17/17

Figure 18 - Shutdown by pulling down

the soft-start pin.

Ch1: VOUT

Ch2: HDrv

Ch3: LDrv

Ch4: IOUT (10A/div)

TYPICAL OPERA TING CHARACTERISTICS

Figure 19 - Start-Up.

Ch2: VSS (Soft-S tart V oltage)

Ch3: VOUT

Ch4: IOUT (5A/div)

Figure 20 - Application circuit efficiency

at ambient temperature.

5V to 2.5V

100

120

0 2 4 6 8 10 12 14 16 18

Output Current (A)

Efficiency (%)