LM10QML
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LM10QML Operational Amplifier and Voltage Reference
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1FEATURES DESCRIPTION
The LM10 is a monolithic linear IC consisting of a
2• Input Offset Voltage: 2.0 mV (max) precision reference, an adjustable reference buffer
• Input Offset Current: 0.7 nA (max) and an independent, high quality op amp.
• Input Bias Current: 20 nA (max) The unit can operate from a total supply voltage as
• Reference Regulation: 0.1% (max) low as 1.1V or as high as 40V, drawing only 270μA.
• Offset Voltage Drift: 2μV/°C A complementary output stage swings within 15 mV
of the supply terminals or will deliver ±20 mA output
• Reference Drift: 0.002%/°C current with ±0.4V saturation. Reference output can
be as low as 200 mV.
The circuit is recommended for portable equipment
and is completely specified for operation from a
single power cell. In contrast, high output-drive
capability, both voltage and current, along with
thermal overload protection, suggest it in demanding
general-purpose applications.
The device is capable of operating in a floating mode,
independent of fixed supplies. It can function as a
remote comparator, signal conditioner, SCR controller
or transmitter for analog signals, delivering the
processed signal on the same line used to supply
power. It is also suited for operation in a wide range
of voltage- and current-regulator applications, from
low voltages to several hundred volts, providing
greater precision than existing ICs.
Connection and Functional Diagram
Figure 1. TO Package (NEV)
Package Number NEV0008A
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2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Figure 2. Operational Amplifier Schematic — (Pin numbers are for 8-pin packages)
Figure 3. Reference and Internal Regulator Schematic — (Pin numbers are for 8-pin packages)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)
Total Supply Voltage 45V
Differential Input Voltage (2) ±40V
Power Dissipation (PDmax)(3) Internally Limited
Output Short-circuit Duration (4) Continuous
Storage Temperature Range −55°C ≤TA≤+150°C
Maximum Junction Temperature (TJmax) 150°C
Lead Temperature (Soldering 10 seconds) 300°C
Thermal Resistance θJA Still Air 150°C
500LF/Min Air flow 45°C
θJC 45°C
ESD Rating to be determined
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) The Input voltage can exceed the supply voltages provided that the voltage from the input to any other terminal does not exceed the
maximum differential input voltage and excess dissipation is accounted for when VI< VS-.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower..
(4) Internal thermal limiting prevents excessive heating that could result in sudden failure, but the IC can be subjected to accelerated stress
with a shorted output and worst-case conditions.
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup Description Temp °C
1 Static tests at +25
2 Static tests at +125
3 Static tests at -55
4 Dynamic tests at +25
5 Dynamic tests at +125
6 Dynamic tests at -55
7 Functional tests at +25
8A Functional tests at +125
8B Functional tests at -55
9 Switching tests at +25
10 Switching tests at +125
11 Switching tests at -55
12 Settling time at +25
13 Settling time at +125
14 Settling time at -55
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LM10H Electrical Characteristics DC Parameters
The following conditions apply to all the following parameters, unless otherwise specified.
DC: At room temperature 1.2V ≤VS≤45V, VS-≤VCM ≤V± 0.85V.
DC: At temperature extremes 1.3V ≤VS≤45V, VS-≤VCM ≤V± 1.0V. Sub-
Symbol Parameter Conditions Notes Min Max Unit groups
-2.0 2.0 mV 1
IO= 0mA -3.0 3.0 mV 2, 3
VS= 1.2V, IO= ±2mA -3.0 3.0 mV 1
VIO Input Offset Voltage VS= 1.3V, IO= ±2mA -4.0 4.0 mV 2, 3
VS= 4V, IO= ±20mA -3.0 3.0 mV 1
VS= 4V, IO= ±15mA -4.0 4.0 mV 2, 3
-0.7 0.7 nA 1
IIO Input Offset Current -1.5 1.5 nA 2, 3
20 nA 1
IIB Input Bias Current 30 nA 2, 3
93 dB 1
CMRR Common Mode Rejection VS= 45V, -20V ≤VCM ≤24.2V 87 dB 2, 3
VS+= 0.85V, 90 dB 1
-0.35V ≥VS-≥-44.2V
VS+= 1V, 84 dB 2, 3
-0.3V ≥VS-≥-44.2V
PSRR Supply Voltage Rejection 0.85V ≤VS+≤44.6V, 96 dB 1
VS-= -0.35V
1V ≤VS+≤44.6V, 90 dB 2, 3
VS-= -0.3V
VRLine 91 dB 1
Line Regulation IRef = 1mA 85 dB 2, 3
VS= 1.2V, 0 ≤IO≤1mA 60 dB 1
VRLoad Load Regulation VS= 1.3V, 0 ≤IO≤1mA 57 dB 2, 3
400 µA 1
ISSupply Current 500 µA 2, 3
VS= ±20V, IO= 0A, 120 K 4
VO= ± 19.95V 80 K 5, 6
VS= ±2V, IO= ±20mA, 5.0 K 4
VO= ±1.4V
VS= ±2V, IO= ±15mA, 1.5 K 5, 6
VO= ±1.4V
AVLarge Signal Voltage Gain VS+= 0.85V, VCM = -0.25V 1.5 K 4
VS-= -0.35V, IO= ±2mA,
-0.15V ≤VO≤0.65V,
VS+= 1V, VCM = -0.35V 0.5 K 5, 6
VS-= -0.3V, IO= ±2mA,
+0.05V ≤VO≤0.65V,
1.1V ≤VOUT ≤6.1V, See (1) 14 K 4
-5mA ≤IOUT ≤-0.1mA
1.2V ≤VOUT ≤6.2V, See (1) 6.0 K 5, 6
-5mA ≤IOUT ≤-0.1mA
AVSH Shunt Gain 1.4V ≤VOUT ≤6.4V, See (1) 8.0 K 4
-5mA ≤IOUT ≤-0.1mA
1.4V ≤VOUT ≤6.4V, See (1) 4.0 K 5, 6
-20mA ≤IOUT ≤-0.1mA
(1) This defines operation in floating applications such as the bootstrapped regulator or two-wire transmitter. Output is connected to the VS+
terminal of the IC and input common mode is referred to VS-(see Typical Applications -). Effect of larger output-voltage swings with
higher load resistance can be accounted for by adding the positive-supply rejection error.
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LM10H Electrical Characteristics DC Parameters (continued)
The following conditions apply to all the following parameters, unless otherwise specified.
DC: At room temperature 1.2V ≤VS≤45V, VS-≤VCM ≤V± 0.85V.
DC: At temperature extremes 1.3V ≤VS≤45V, VS-≤VCM ≤V± 1.0V. Sub-
Symbol Parameter Conditions Notes Min Max Unit groups
0.2V ≤VRef ≤35V, IRef = 1mA 50 K
AVAmplifier Gain 23 K
0.2V ≤VRef ≤35V, 195 205 mV
VSense Feedback Sense Voltage 0≤IRef ≤1 mA 194 206 mV
50 nA
ISense Feedback Current 65 nA
0.5V ≤VO≤25V -75 75 µA
ΔISSupply Current Change VS= 5V, 4.5V ≤VO≤5V -60 60 µA
See (2) 250 KΩ
RIInput Resistance See (2) 150 KΩ
(2) Specified parameter, not tested,
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Definition of Terms
Input offset voltage:That voltage which must be applied between the input terminals to bias the unloaded
output in the linear region.
Input offset current:The difference in the currents at the input terminals when the unloaded output is in the
linear region.
Input bias current:The absolute value of the average of the two input currents.
Input resistance:The ratio of the change in input voltage to the change in input current on either input with the
other grounded.
Large signal voltage gain:The ratio of the specified output voltage swing to the change in differential input
voltage required to produce it.
Shunt gain:The ratio of the specified output voltage swing to the change in differential input voltage required to
produce it with the output tied to the VS+terminal of the IC. The load and power source are connected
between the VS+and VS-terminals, and input common-mode is referred to the VS-terminal.
Common-mode rejection:The ratio of the input voltage range to the change in offset voltage between the
extremes.
Supply-voltage rejection:The ratio of the specified supply-voltage change to the change in offset voltage
between the extremes.
Line regulation:The average change in reference output voltage over the specified supply voltage range.
Load regulation:The change in reference output voltage from no load to that load specified.
Feedback sense voltage:The voltage, referred to VS-, on the reference feedback terminal while operating in
regulation.
Reference amplifier gain:The ratio of the specified reference output change to the change in feedback sense
voltage required to produce it.
Feedback current:The absolute value of the current at the feedback terminal when operating in regulation.
Supply current:The current required from the power source to operate the amplifier and reference with their
outputs unloaded and operating in the linear range.
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Typical Performance Characteristics (Op Amp)
Input Current Common Mode Limits
Figure 4. Figure 5.
Output Voltage Drift Input Noise Voltage
Figure 6. Figure 7.
DC Voltage Gain Transconductance
Figure 8. Figure 9.
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Typical Performance Characteristics (Op Amp) (continued)
Output Saturation Output Saturation
Characteristics Characteristics
Figure 10. Figure 11.
Output Saturation
Characteristics Minimum Supply Voltage
Figure 12. Figure 13.
Minimum Supply Voltage Minimum Supply Voltage
Figure 14. Figure 15.
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Typical Performance Characteristics (Op Amp) (continued)
Frequency Response Output Impedance
Figure 16. Figure 17.
Typical Stability Range Large Signal Response
Figure 18. Figure 19.
Comparator Response Comparator Response
Time For Various Time For Various
Input Overdrives Input Overdrives
Figure 20. Figure 21.
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Typical Performance Characteristics (Op Amp) (continued)
Follower Pulse
Response Noise Rejection
Figure 22. Figure 23.
Rejection Slew Limiting Supply Current
Figure 24. Figure 25.
Thermal Gradient Thermal Gradient
Feedback Cross-coupling
Figure 26. Figure 27.
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Typical Performance Characteristics (Op Amp) (continued)
Shunt Gain Shunt Gain
Figure 28. Figure 29.
Shunt Gain Shunt Gain
Figure 30. Figure 31.
Shunt Gain Shunt Gain
Figure 32. Figure 33.
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Typical Performance Characteristics (Reference)
Line Regulation Load Regulation
Figure 34. Figure 35.
Reference Noise Voltage Minimum Supply Voltage
Figure 36. Figure 37.
Output Saturation Typical Stability Range
Figure 38. Figure 39.
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Typical Applications
Circuit descriptions available in application note AN-211 (SNOA638).
(Pin numbers are for devices in 8-pin packages)
Op Amp Offset Adjustment
Standard Limited Range
Limited Range With Boosted
Reference
Positive Regulators
Use only electrolytic output capacitors.
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Low Voltage Best Regulation
Zero Output
Use only electrolytic output capacitors.
Current Regulator Shunt Regulator
Required For Capacitive Loading
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Protected HV Regulator
Flame Detector
*800°C Threshold Is Established By Connecting Balance To VRef.
Light Level Sensor
*Provides Hysteresis
Remote Amplifier
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Remote Thermocouple Amplifier
Transmitter for Bridge Sensor
Precision Thermocouple Transmitter
10 mA ≤IOUT≤50 mA 500°C ≤TP≤1500°C *Gain Trim
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Thermocouple Transmitter
200°C≤Tp≤700°C
1 mA≤IOUT≤5 mA
†Gain Trim
Logarithmic Light Sensor
1 mA ≤IOUT≤5 mA
‡50 μA≤ID≤500 μA
††Center Scale Trim
†Scale Factor Trim
*Copper Wire Wound
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Battery-level Indicator Battery-threshold Indicator
Single-cell Voltage Monitor Double-ended Voltage Monitor
Flashes Above 1.2V Flash Rate Increases
Rate Increases With Above 6V and Below 15V
Voltage
Meter Amplifier
Input
10 mV, 100nA
Full-Scale
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Microphone Amplifier
ZOUT∼680Ω@ 5 kHz
AV≤1k
f1∼100 Hz
f2∼5 kHz
RL∼500
*Max Gain Trim
Isolated Voltage Sensor
†Controls “Loop Gain”
*Optional Frequency Shaping
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Light-level Controller
Circuit descriptions available in application note AN-211 (SNOA638).
APPLICATION HINTS
With heavy amplifier loading to VS-, resistance drops in the VS-lead can adversely affect reference regulation.
Lead resistance can approach 1Ω. Therefore, the common to the reference circuitry should be connected as
close as possible to the package.
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Table 1. Revision History
Date Released Revision Section Changes
10/26/2010 A New release to corporate format 1 MDS converted to standard corporate format.
MNLM10-X Rev 0AL will be archived
03/26/2013 A All sections Changed layout of National Data Sheet to TI format
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8760401GA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LM10H/883
5962-8760401GA Q A
CO
5962-8760401GA Q >
T
LM10H/883 ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LM10H/883
5962-8760401GA Q A
CO
5962-8760401GA Q >
T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
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