Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT73LC03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.4
GENERAL DESCRIPTION
The XRT73LC03A, 3-Channel, DS3/E3/STS-1 Line
Interface Unit is a low power CMOS version of the
XRT73L03A and consists of three independent line
transmitters and receivers integr ated on a single chip
designed for DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73LC0 3A can be configur ed
to support the E3 (34.368 Mbp s), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each
channel can be configur ed to opera te in a mod e/data
rate that is independent of the other channels.
In the transmit direction, each channel en code s input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) fo r-
mat and convert s the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73LC03A performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
FEATURES
•Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L03A
•Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
•Contains a 4-Wire Microprocessor Serial Interface
•Full Loop-Back Capability
•Transmit and Receive Power Down Modes
•Full Redundancy Support
•Uses Minimum External components
•Single +3.3V Power Supply
•Low power CMOS design
•5V tolerant I/O
•-40°C to +85°C Operating Temperature Range
•Available in a 120 pin LQFP packa ge
APPLICATIONS
•Digital Cross Connect Systems
•CSU/DSU Equipment
•Routers
•Fiber Optic Terminals
•Multiplexers
•ATM Switches
FIGURE 1. XRT73LC03A BLOCK DIAGRAM
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF_(n)
Channel 2 - (n) = 2
AGC/
Equalizer
Serial
Processor
Interface
Peak
Detector
LOS Detector
Slicer Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
Channel 0 - (n) = 0
Channel 1 - (n) = 1
Notes: 1. (n) = 0, 1, or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Device
Monitor
MTIP_(n)
MRing_(n)
DMO_(n)
Transmit
Logic Duty Cycle Adjust
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
E3_(n) STS-1/DS3_(n) Host/(HW) RLOL_(n) EXClk_(n) RxOFF RxClkINV
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
Tx
Control
XRT73LC03A
2
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
TYPICAL APPLICATIONS
TRANSMIT INTERFACE CHARACTERISTICS:
•Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a b ipolar signal
from the line
•Integrated Pulse Shaping Circuit
•Built-in B3ZS/HDB3 Encoder (which can be dis-
abled)
•Contains Transmit Clock Duty Cycle Correction
Circuit on-chip
•Generates pulses tha t comply with the ITU-T G.703
pulse template (E3 applications)
•Generates pulses that comply with the DSX-3 pulse
template as specified in Bellcore GR -4 99-CORE
and ANSI T1.102_1993
•Generates pulses that comply with the STSX-1
pulse template as specified in Bellcore GR-253-
CORE
•Transmitter can be turned off in order to support
redundancy designs
RECEIVE INTERFACE CHARACTERISTICS:
•Integrated Adaptive Receive Equalization (optional)
and Timing Recovery
•Declares and Clears the LOS defect per ITU-T
G.775 re qu ir em e nts (E3 and DS 3 ap p licat ion s)
•Meets Jitter Tolerance Requirements as specified
in ITU-T G.823_1993 (E3 Applications)
•Meets Jitter Tolerance Requirements as specified
in Bellcore GR-499-CORE (DS3 Applications)
•Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms
•Built-in B3ZS/HDB3 Decoder (which can be dis-
abled)
•Recovered Data can be muted while the LOS Con-
dition is declared
•Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
•Receiver can be powered down in order to con-
serve power in redundancy designs
FIGURE 2. MULTICHANNEL ATM APPLICATION
ATM
Switch/
SAR XRT74L73
RPOS
RNEG
RxLineClk
XRT71D03 XRT73LC03
RRPOS
RRNEG
RRClk
RPOS
RNEG
RxClk
RPOS
RNEG
RxClk
RTIP
RRing
TTIP
TRing
TPOS
TNEG
TxLineClk
MClk TPOS
TNEG
TxClk
3 Channel E3/DS3 ATM UNI 3 Channel E3/DS3 J/A 3 Channel E3/DS3 LIU
FIGURE 3. MULTISERVICE - FRAME RELAY APPLICATION
Frame
Relay XRT72L56
RPOS
RNEG
RxLineClk
XRT71D03 XRT73LC03
RRPOS
RRNEG
RRClk
RPOS
RNEG
RxClk
RPOS
RNEG
RxClk
RTIP
RRing
TTIP
TRing
TPOS
TNEG
TxLineClk
MClk
TPOS
TNEG
TxClk
6 Channel E3/DS3 Framer 2 x 3 Channel E3/DS3 J/A 2 x 3 Channel E3/DS3 LIU
XRT73LC03A
3
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
ORDERING INFORMATION
FIGURE 4. PIN OUT OF THE XRT73LC03A IN THE 120 PIN LQFP PACKAGE
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XRT73LC03A
RLOL_2
LCV_2
RLOS_2
RLOL_0
LCV_0
RLOS_0
RxDGND_0
NC
NC
RPOS_0
RNEG_0
RxClk_0
RxDVDD_0
EXClk_0
RxDGND_2
RPOS_2
RNEG_2
RxClk_2
HOST/(HW)
RxDVDD_2
AGND_0
TxAGND_0
DMO_0
TxAVDD_0
REGR/(RxClkINV)
STS-1/DS3_1
AGND_2
SR/(DR)
E3_1
NC
NC
LOSTHR_1
LLB_1
RLB_1
RxAVDD_1
RRing_1
RTIP_1
RxAGND_1
REQEN_1
RxAGND_2
RTIP_2
RRing_2
RxAVDD_2
RLB_2
LLB_2
LOSTHR_2
REQEN_0
RxAGND_0
RTIP_0
RRing_0
RxAVDD_0
RLB_0
LLB_0
LOSTHR_0
ICT
STS-1/DS3_0
SDO/(E3_0)
SDI/(RxOFF_0)
SClk/(RxOFF_1)
CS/(ENDECDIS)
TNData_1
TPData_1
TxClk_1
MRing_1
MTIP_1
TAOS_1
TAOS_2
TxLEV_1
TxLEV_2
TTIP_1
TxDVDD_1
TRing_1
TxAGND_1
TxAGND_2
MRing_2
MTIP_2
TxAGND_2
TRing_2
TxDVDD_2
TTIP_2
DMO_2
TxAVDD_2
TNData_2
TPData_2
TxClk_2
TxAGND_0
TRing_0
TxDVDD_0
TTIP_0
MTIP_0
MRing_0
TNData_0
TPData_0
TxClk_0
TxLEV_0
TAOS_0
EXDGND
EXDVDD
EXClk_1
REQEN_2
STS1/DS3_2
E3_2
EXClk_2
RxOFF_2
RLOL_1
LCV_1
RLOS_1
RxDGND_1
RPOS_1
RNEG_1
RxClk_1
LOSMUTEN
RxDVDD_1
AGND_1
TxOFF_2
TxOFF_1
TxOFF_0
TxAGND_1
TxAVDD_1
DMO_1
PART #PACKAGE OPERATING TEMPERATURE RANGE
XRT7 3L C 0 3AIV 120 Pin LQFP 14mm X 20m m -40oC to +85oC
XRT73LC03A
I
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
FEATURES .................................................................................................................................................... 1
APPLICATIONS ......................................................................................................................................... 1
TYPICAL APPLICATIONS ................................................................................................................................. 2
TRANSMIT INTERFACE CHARACTERISTICS: ..................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS: ....................................................................................................... 2
ORDERING INFORMATION ............................................................................................... 3
PIN DESCRIPTIONS (BY FUNCTION) .............................................................................. 4
TRANSMIT INTERFACE ................................................................................................................................... 4
RECEIVE INTERFACE ..................................................................................................................................... 6
CLOCK INTERFACE ...... ....................... ...................... ....................... ................... ....................... .................... 7
OPERATING MODE SELECT ........................................................................................................................... 7
CONTROL AND ALARM INTERFACE ................................................................................................................. 9
MICROPROCESSOR INTERFACE .................................................................................................................... 11
POWER AND GROUND PINS ......... .................... ................... ................ ................... .................... .................. 13
NO CONNECTION PINS .......................... ............................. .......................................................... ............... 14
ELECTRICAL CHARACTERISTICS ................................................................................ 15
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 15
SYSTEM DESCRIPTION .................................................................................................. 24
THE TRANSMIT SECTION - CHANNELS 0, 1 AND 2 ......................................................................................... 24
THE RECEIVE SECTION - CHANNELS 0, 1 AND 2 ........................................................................................... 24
THE MICROPROCESSOR SERIAL INTERFACE ........ ............. ............. ......... ............. ............. ............. ............. .. 24
1.0 Selecting the Data Rate .................................................................................................................... 25
1.1 CONFIGURING CHANNEL(N) ............................................................................................................................... 25
COMMAND REGISTER, CR4-(N) ...................................................................................................... 27
2.0 The Transmit Section ....................................................................................................................... 27
2.1 THE TRANSMIT LOGIC BLOCK ............................................................................................................................ 27
2.1.1 Accepting Dual-Rail Data from the Terminal Equipment ...................................................................... 27
2.1.2 Accepting Single-Rail Data from the Termi nal Equipment ................................................................... 28
COMMAND REGISTER CR1-(N) ....................................................................................................... 28
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY ................................................................................... 29
2.3 THE HDB3/B3ZS ENCODER BLOCK .................................................................................................................. 29
2.3.1 B3ZS Encoding .................................................................................................................................... 29
2.3.2 HDB3 Encoding .................................................................................................................................... 30
2.3.3 Disabling the HDB3/B3ZS Encoder ..................................................................................................... 30
COMMAND REGISTER CR2-(N) ....................................................................................................... 30
2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY ....................................................................................................... 31
2.4.1 Enabling the Transmit Line Build-Out Circuit ....................................................................................... 32
COMMAND REGISTER, CR1-(N) ...................................................................................................... 32
2.4.2 Disabling the Transmit Line Build-Out Circuit ....................................................................................... 32
COMMAND REGISTER, CR1-(N) ...................................................................................................... 33
2.4.3 Design Guideline for Setting the Transmit Line Build-Out Circuit ......................................................... 33
2.4.4 The Transmit Line Build-Out Circuit and E3 Applications .................................................................... 33
2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT73LC03A TO THE LINE ...................................................... 33
TRANSFORMER RECOMMENDATIONS ................... ......... .......... ....... ......... .......... .......... ......... .......... .. 34
3.0 The Receive Section ......................................................................................................................... 35
3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73LC03A TO THE LINE ........................................................ 35
3.2 THE RECEIVE EQUALIZER BLOCK ...................................................................................................................... 36
3.2.1 Guidelines for Setting the Receive Equalizer ...................................................................................... 36
COMMAND REGISTER CR2-(N) ....................................................................................................... 37
3.3 CLOCK RECOVERY PLL .................................................................................................................................... 38
3.3.1 The Training Mode ............................................................................................................................... 38
3.3.2 The Data/Clock Recovery Mode .......................................................................................................... 38
XRT73LC03A
II
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
3.4 THE HDB3/B3ZS DECODER ............................................................................................................................. 38
3.4.1 B3ZS Decoding (DS3/STS-1 Applications) .......................................................................................... 38
3.4.2 HDB3 Decoding (E3 Applications) ....................................................................................................... 38
3.4.3 Configuring the HDB3/B3ZS Decoder ................................................................................................. 39
COMMAND REGISTER CR2-(N) ...................................................................................................... 39
3.5 LOS DECLARATION/CLEARANCE ....................................................................................................................... 39
3.5.1 The LOS Declaration/Clearance Criteria for E3 Applications ............................................................... 40
3.5.2 The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications .......................................... 41
COMMAND REGISTER CR0-(N) ...................................................................................................... 42
COMMAND REGISTER CR2-(N) ...................................................................................................... 42
COMMAND REGISTER CR0-(N) ...................................................................................................... 42
COMMAND REGISTER CR2-(N) ...................................................................................................... 42
3.5.3 Muting the Recovered Data whil e the LOS is bein g Declared ............................................................. 42
COMMAND REGISTER CR3-(N) ...................................................................................................... 43
3.6 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT .............. 43
3.6.1 Routing Dual-Rail Format Data to the Receivin g Terminal Equipment ................................................ 43
COMMAND REGISTER CR3-(N) ...................................................................................................... 45
3.6.2 Routing Single-Rail Format (Binary Data Stream) data to the Receive Terminal Equipment .............. 45
COMMAND REGISTER CR3-(N) ...................................................................................................... 45
3.7 SHUTTING OFF THE RECEIVE SECTION ............................................................................................................. 46
COMMAND REGISTER CR3-(N) ...................................................................................................... 46
4.0 Diagnostic Features of the XRT73LC03A ...................................................................................... 47
4.1 THE ANALOG LOCAL LOOP-BACK MODE ............................................................................................................ 47
COMMAND REGISTER CR4-(N) ...................................................................................................... 48
4.2 THE DIGITAL LOCAL LOOP-BACK MODE. ........................................................................................................... 48
COMMAND REGISTER CR4-(N) ...................................................................................................... 48
4.3 THE REMOTE LOOP-BACK MODE ...................................................................................................................... 49
COMMAND REGISTER CR4-(n) ...................................................................................................... 49
4.4 TXOFF FEATURES ........................................................................................................................................... 50
COMMAND REGISTER CR1-(N) ...................................................................................................... 50
4.5 THE TRANSMIT DRIVE MONITOR FEATURES ....................................................................................................... 50
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE .................................................................................................... 51
COMMAND REGISTER CR1-(N) ...................................................................................................... 51
5.0 The Microprocessor Serial Interface .............................................................................................. 51
5.1 DESCRIPTION OF THE COMMAND REGISTERS .................................................................................................... 51
5.2 DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER ........................................................................... 53
5.2.1 Command Register - CR0-(n) .............................................................................................................. 53
COMMAND REGISTER CR0-(N) ....................................................................................................... 53
COMMAND REGISTER CR1-(N) ...................................................................................................... 53
5.2.3 Command Register CR2-(n) ................................................................................................................ 54
COMMAND REGISTER CR2-(N) ...................................................................................................... 54
COMMAND REGISTER CR3-(N) ...................................................................................................... 54
COMMAND REGISTER CR4-(N) ...................................................................................................... 55
5.3 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ................................................................................... 56
ORDERING INFORMATION ............................................................................................. 58
PACKAGE DIMENSIONS ................................................................................................. 58
REVISION HISTORY ............... ....... ...... ....... ...... ...... ....... ... ....... ...... ....... ...... ...... ....... ...... ....... ... ...... ....... ........ 59
XRT73LC03A
4
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
PIN DESCRIPTIONS (BY FUNCTION)
TRANSMIT INTERFACE
PIN #NAME TYPE DESCRIPTION
29
10
20
TTIP_0
TTIP_1
TTIP_2
OTransmit TTIP Output - Channel (n):
The XRT73LC03A uses this pin along with TRing_(n) to transmit a bipo-
lar line signal via a 1:1 transformer.
27
12
18
TRing_0
TRing_1
TRing_2
OTransmit Ring Output - Channel (n):
The XRT73LC03A uses this pin along with TTIP_(n) to transmit a bipolar
line signal via a 1:1 transformer.
34
3
25
TxClk_0
TxClk_1
TxClk_2
ITransmit Clock Input for TPData and TNData - Channel (n):
This input pin must be driven at 34.36 8 MHz for E3 applications, 44.736
MHz for DS3 applications, or 51.84 MHz for SONET STS-1 applications.
The XRT73LC03A uses this signal to sample the TPData_(n) and
TNData_(n) input pins. By default, the XRT73LC03A is configured to
sample these two pins on the falling edge of this signal.
NOTE: If the XRT73LC03A is operating in the HOST Mode, then the
device can be configured to sample the TPData_(n) and TNData_(n)
input pins on either the rising or falling edge of TxClk_(n).
33
2
24
TPData_0
TPData_1
TPData_2
ITransmit Positive Data Input - Channel (n):
The XRT73LC03A samples this pin on the falling edge of TxClk_(n). If
the device samples a "1", then it generates and transmits a positive
polarity pulse to the line.
The data should be applied to this input pin if the Transmit Section is
configured to accept Single-Rail data from the Terminal Equipment.
NOTE: If the XRT73LC03A is operating in the HOST Mode, then the
XRT73LC03A can be configured to sample the TPData_(n) pin on either
the rising or falling edge of TxClk_(n).
32
1
23
TNData_0
TNData_1
TNData_2
ITransmit Negative Data Input - Channel (n):
The XRT73LC03A samples this pin on the falling edge of TxClk_(n). If
the device samples a "1", then it generates and transmits a negative
polarity pulse to the line.
In Single-Rail Mode, this pin must be tied to GND to enable the HDB3/
B3ZS Encoder and Decoder, (internally pulled-down).
In Dual-Rail Mode this input is the N-Rail Data input.
NOTE: If the XRT73LC03A is operating in the HOST Mode, then the
XRT73LC03A can be configured to sample the TNData_(n) pin on either
the rising or falling edge of TxClk_(n).
XRT73LC03A
5
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
35
8
9
TxLEV_0
TxLEV_1
TxLEV_2
ITransmit Line Build-Out Enable/Disable Select - Channel (n):
This input pin permits the Tran smit Line Build-Out circu it within Channel
(n) to be enabled or disabled. In E3 mode, this pin has no effect on the
transmit pulse shape.
Setting this pin to "High" disables the Line Build-Out circuit. In this
mode, Channel (n) outputs partially-shaped pulses onto the line via the
TTIP_(n) and TRing_(n) output pins.
Setting this pin to "Low" enables the Line Build-Out ci rcuit within Chan-
nel (n). In this mode, Channel (n) ou tputs shaped pulses onto the line
via the TTIP_(n) and TRing_(n) output pins.
To compl y wi th the Isolated DSX-3/STSX-1 Pulse Te mplate Require-
ments per Bellcore GR-499-CORE or Bellcore GR-253-CORE:
a. Set this input pin to "1" if the cable length between the Cross-
Connect and the transmit output of Channel (n) is greater than
225 feet.
b. Set this input pin to "0" if the cable length between the Cross-
Connect and the transmit output of Channel (n ) is less than 225
feet.
This pin is active only if the following two conditions are true:
a. The XRT73LC03A is configured to operate in either the DS3 or
SONET STS-1 Modes.
b. The XRT73LC03A is configured to operate in the Hardware
Mode.
NOTE: This pin to should be tied to GND if the XRT73LC03A is going to
be operating in the HOST Mode, (internally pulled-down).
117
116
115
TxOFF_0
TxOFF_1
TxOFF_2
ITransmitter OFF Input - Channel (n):
Setting this input pin "High" turns off all of the Transmitte r Sections. In
this mode the TTIP and TRing outputs are tri-stated.
NOTES:
1. This input pin controls the TTIP and TRing outputs even when
the XRT73LC03A is operating in the HOST Mode.
2. For HOST Mode Operation, this pin is tied to GND if the Trans-
mitter is intended to be turned off via the Microprocessor Serial
Interface.
TRANSMIT INTERFACE
PIN #NAME TYPE DESCRIPTION
XRT73LC03A
6
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
RECEIVE INTERFACE
PIN #NAME TYPE DESCRIPTION
49
111
43
RxClk_0
RxClk_1
RxClk_2
OReceive Clock Output - Channel (n):
This output pin is the Recovered Clock signal from the incoming line sig-
nal for Channel (n). The Receive Section of Channel (n) outputs data via
the RPOS_(n) and RNEG_(n) output pins on the rising edge of this clock
signal.
Configure the Receive Section of Channel (n) to update the data on the
RPOS_(n) and RNEG_(n) output pins on the falling edge of RxClk_(n)
by doing one of the following:
a. Operating in the Hardware Mode
Pull the RxClkINV pin to "High".
b. Operating in the HOST Mode
Write a "1" into the RxClkINV bit-field within the Command Register.
50
110
44
RNEG_0
RNEG_1
RNEG_2
OReceive Negative Data Output - Channel (n):
This output pin pulses "High" whenever Channel (n) of the XRT73LC03A
has received a Negative Polarity pulse in the incoming line signal at the
RTIP_(n)/RRing_(n) inputs.
NOTE: If the Channel (n) B3ZS/HDB3 Decoder is enabled, then the zero
suppression patterns in the incoming line signal (such as: "00V", "000V",
"B0V", "B00V") is not reflected at this output.
51
109
45
RPOS_0
RPOS_1
RPOS_2
OReceive Positive Data Output - Channel (n):
This output pin pulses “High" whenever Channel (n) of the XRT73LC03A
has received a Positive Polarity pulse in the incoming line signal at the
RTIP_(n)/RRing_(n) inputs.
NOTE: If the Channel (n) B3ZS/HDB3 Decoder is enabled, then the zero
suppression patterns in the incoming line signal (such as: "00V", "000V",
"B0V", "B00V") is not reflected at this output.
71
85
79
RRing_0
RRing_1
RRing_2
IReceive Ring Input - Channel (n):
This input pin along with RTIP_(n) is used to receive the bip olar line sig-
nal from the Remote DS3/E3/STS-1 Terminal.
72
84
80
RTIP_0
RTIP_1
RTIP_2
IReceive TIP Input - Channe l (n):
This input pin along with RRing_(n) is used to receive the bipolar line sig-
nal from the Remote DS3/E3/STS-1 Terminal.
74
82
100
REQEN_0
REQEN_1
REQEN_2
IReceive Equalization Enable Input - Channel (n):
Setting this input pin "High" enables the Internal Receive Equalizer
within Channel (n). Setting this pin "Low" disables the Internal Receive
Equalizer. The guidelin es for enabling and disabling the Receive Equal-
izer are described in Section 3.2.
NOTE: This pin is ignored and should be tied to GND if the XRT73LC03A
is going to be operating in the HOST Mode, (inter nally pulled-down).
XRT73LC03A
7
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
96 REGR/
RxClkINV IRegister Reset Input (Invert RxClk(n)) Output - Select:
The function of this pin depends upon whether the XRT73LC03A is oper-
ating in the HOST Mode or in the Hardware Mode.
NOTE: This pin is internally pulled "High".
In the HOST-Mode - Register Reset Input:
Setting this input pin "Low" causes the XRT73LC03A to reset the con-
tents of the Command Registers to their default settings and default
operating configuration.
In the Hardware Mode - Invert RxClk Output Select:
Setting this input pin "High" configures the Receive Secti on of all Chan-
nels in the XRT73LC03A to invert their RxClk_(n) clock output signals
and configures Channel (n) to output the recovered data via the
RPOS_(n) and RNEG_(n) output pins on the falling edge of RxClk_(n).
Setting this pin "Low" configures Channel (n) to output the recovered
data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of
RxClk_(n).
RECEIVE INTERFACE
PIN #NAME TYPE DESCRIPTION
CLOCK INTERFACE
PIN #NAME TYPE DESCRIPTION
47
99
103
EXClk_0
EXClk_1
EXClk_2
IExternal Reference Clock Input - Channel (n):
Apply a 34.368 MHz clock signal for E3 applications, a 44.73 6 MHz
clock signal for DS3 applications or a 51.84 MHz clock signal for SONET
STS-1 applications.
The Channel (n) Clock Recovery PLL uses this signal as a Reference
Signal for Declaring and Clearing the Receive Loss of Lock Alarm. The
Clock recovery PLL also generates the exact clock for the LIU.
It is permissible to use the same clock that drives the TxClk_(n) input
pin.
It is permissible to operate the three Channels at different data rates.
OPERATING MODE SELECT
PIN #NAME TYPE DESCRIPTION
93 SR/(DR)I
Receive Output Single-Rail/Dual-Rail Select:
Setting this pin "High" configures the Receive Sections of all Channels to
output data in a Single-Rail Mode to the Terminal Equipment.
Setting this pin "Low" configures the Receive Sectio n of all Channels to
output data in a Dual-Rail Mode to the Terminal Equipment.
XRT73LC03A
8
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
64 SDO/(E3_0) I/O Serial Data Output from the Microprocessor Serial Interface/
E3_Mode Select - Channel 0:
The function of this pin depends on whether the XRT73LC03A is operat-
ing in the HOST Mode or in the Hardware Mode.
HOST Mode Operatio n - Serial Data Output for the Microprocessor
Serial Interface:
This pin serially outputs the contents of the specified Command Register
during Read Operations. The data is updated on the falling edge of the
SClk input signal and tri-stated upon completion of data transfer.
Hardware Mode Operation - E3 Mode Select - Channel 0:
This input pin is used to configure Channel 0 in the XRT73LC03A to
operate in the E3 or STS/DS3 Modes. Setting this input pin to "High"
configures Channel 0 to operate in the E3 Mode. Setting this input pin to
"Low" configures Channel 0 to operate in either the DS3 or STS-1
Modes, depending upon the state of the STS-1/DS3_0 input pin.
NOTE: This pin is internally pulled “Low” when XRT73LC03A is in the
Hardware Mode.
92
102 E3_1
E3_2 IE3 Select Input - Channel (n):
A "High" on this pin configures Channel (n) of the XRT73LC03A to oper-
ate in the E3 Mode.
A "Low" on this pin configures Channel (n) of the XRT73LC03A to check
the state of the STS-1/DS3_(n) input pin
NOTE: This input pin is ignored and should be connected to GND if the
XRT73LC03A is operating in the HOST Mode.
65
95
101
STS-1/DS3_0
STS-1/DS3_1
STS-1/DS3_2
ISTS-1/DS3 Sel e ct Input - Channel (n) :
“High” for STS-1 and “Low” for DS3 Operation.
The XRT73LC03A ignores this pin if the E3_(n) pin is set to "1".
This input pin is ignored if the XRT73LC03A is operating in the HOST
Mode.
NOTE: This pin should be tied to GND if the XRT73LC03A is going to be
operatin g in the HOST Mode, (internally pull ed-down).
42 HOST/(HW)I
HOST/Hardware Mode Select:
This input pin is used to enable or disable the Mi croprocessor Serial
Interface (e.g., consisting of the SDI, SDO, SClk, and CS pins).
Setting this input pin "High" enables the Microprocessor Serial Interface
(e.g. configures the XRT73LC03A to operate in the HOST Mode). In this
mode, configure the XRT73LC03A via the Microprocessor Serial Inter-
face. When the XRT73LC03A is operating in the HOST Mode, then it
ignores the states of many of the discrete input pins.
Setting this in pu t pi n "L ow " di sa bl e s the Microprocessor Serial Interface
(e.g., configures the XRT73LC03A to operate in the Hardware Mode). In
this mode, many of the external input control pins are functional.
OPERATING MODE SELECT
PIN #NAME TYPE DESCRIPTION
XRT73LC03A
9
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
CONTROL AND ALARM INTERFACE
PIN #NAME TYPE DESCRIPTION
31
4
15
MRing_0
MRing_1
MRing_2
IMonitor Ring Input - Channel (n):
The bipolar line output signa l from TRing_(n) can be connected to this
pin via a 270-ohm resistor in order to check for line driver failure. This
pin is internall y pu lled "High".
30
5
16
MTIP_0
MTIP_1
MTIP_2
IMonitor Ti p Input - Channel (n):
The bipolar line output signal from TTIP_(n) can be connected to this pin
via a 270-ohm resistor in order to check for line driver failure. This pin is
internally pulled "High".
38
120
21
DMO_0
DMO_1
DMO_2
ODrive Monitor Output - Channel (n):
If no transmitted AMI signal is present on MTIP_(n) and MRing_(n) input
pins for 128±32 TxClk periods, then DMO_ (n) toggles and remains
"High" until the next AMI signal is detected.
36
6
7
TAOS_0
TAOS_1
TAOS_2
ITransmit All Ones Select - Channel (n):
A "High" on this pin causes the Transmit Section, within Channel (n), to
generate and transmit a continuous AMI all “1’s " pattern onto the line .
The frequency of this "1’s" pattern is determined by TxClk_(n).
This input pin is ignored if the XRT73LC03A is operating in the HOST
Mode.
NOTE: This pin should be tied to GND if the XRT73LC03A is going to be
operating in the HOST Mode, (internally pulled-down).
55
107
58
RLOS_0
RLOS_1
RLOS_2
OReceive Loss of Signal Output Indicator - Channel (n):
This output pin toggles "High" if Channel (n ) has detecte d a Loss of Sig-
nal Condition in the incoming line signal.
The criteria that the XRT73LC03A uses to declare an LOS Condition
depends upon whether the device is operatin g in the E3 or STS-1/DS3
Mode.
57
105
60
RLOL_0
RLOL_1
RLOL_2
OReceive Loss of Lock Output Indicator - Channel (n):
This output pin toggles "High" if Channel (n) has detected a Loss of Lock
Condition. Channel (n) declares an LOL (Loss of Lock) Condition if the
recovered clock frequency deviates from the Reference Clock frequency
(available at the EXClk(n) input pin) by more than 0.5%.
56
106
59
LCV_0
LCV_1
LCV_2
OLine Code Violation Indicator - Channel 0:
Whenever the Receive Section of Channel (n) detects a Line Code Vio-
lation, it pulses this output pin "High". This output pin remain s "Low" at
all other times.
NOTE: The XRT73LC03A outputs an NRZ pulse via this output pin. It is
advisable to sample this output pin via the RxClk_(n) clock output signal.
66 ICT IIn-Circuit Test Input:
Setting this pin "Low" causes all digital and analog ou tputs to go into a
high-impedance state to allow for in-circuit testing. This pin should be
set to "High" for normal operation.
This pin is internally pulled "High".
67
89
75
LOSTHR_0
LOSTHR_1
LOSTHR_2
ILoss of Signal Threshold Control - Channel (n):
Forcing the LOSTHR_(n) pin to GND or VDD provides two settings. This
pin must be set to a “High” or “Low” level upon power up and should not
be changed during operation.
This pin is only applicable during DS3 or STS-1 operations.
XRT73LC03A
10
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
68
88
76
LLB_0
LLB_1
LLB_2
ILocal Loop-back - Channel (n):
This input pin along with RLB_(n) dictates which Loop-Back mode Chan-
nel (n) is operating in.
A "High" on this pin with RLB_(n) set to "Low" configures Channel (n) to
operate in the Analog Local Loop-Back Mode.
A "High" on this pin with RLB_(n) also being set to "High" configures
Channel (n) to operate in the Digital Local Loop-Back Mode.
NOTE: This pin is ignored and should be tied to GND if the XRT73LC03A
is going to be operating in the HOST Mode.
69
87
77
RLB_0
RLB_1
RLB_2
IRemote Loop-Back - Channel (n):
This input pin in conjunction with LLB_(n) dictates which Loop-Back
mode Channel (n) is operating in.
A "High" on this pin with LLB_(n) being set to "Low" configures Channel
(n) to operate in the Remote Loop-Back Mode.
A "High" on this pin with LLB_(n) also being set to "High" configures
Channel (n) to operate in the Digital Local Loop-Back Mode.
NOTE: This pin is ignored and should be tied to GND if the XRT73LC03A
is going to be operating in the HOST Mode.
112 LOSMUTEN I MUTE-upon-LOS Enable Input (Hardware Mode):
This input pin is use to configure the XRT73LC03A, while it is operating
in the Hardware Mode, to Mute the recovered data via the RPOS_(n),
RNEG_(n) output pins whenever one of the Channels declares an LOS
conditions.
Setting this input pin “High" configures all Channels to automatically pull
the RPOS_(n) and RNEG_(n) output pins “Low” whenever it is declaring
an LOS condition, thereby Muting the data being output to the Terminal
Equipment.
Setting this input pin "Low" configures all Channels to NOT automatically
Mute the recovered data whenever an LOS condition is declared.
NOTES: This pin is ignored and should be tied to GND if the
XRT73LC03A is going to be operating in the HOST Mode. This pin is
internally pulled "Low".
CONTROL AND ALARM INTERFACE
PIN #NAME TYPE DESCRIPTION
XRT73LC03A
11
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
MICROPROCESSOR INTERFACE
PIN # NAME TYPE DESCRIPTION
61 CS/
(ENDECDIS) IMicroprocessor Serial In terface - Chip Select In put/Encoder-
Decoder Disable Input:
This pin’s functionality depends on whether the XRT73LC03A is operat-
ing in the HOST or Hardware Mode.
HOST Mode - Chip Select Input
The Local Microprocessor must assert this pin (set it to "0") in order to
enable communication with th e XRT73LC03A via th e Microprocessor
Serial Interface.
NOTE: This pin is internally pulled “High".
Hardware Mode - Encoder/Decoder Disable Input
Setting this input pin "High" disa bles the B3ZS/HDB3 Encoder &
Decoder blocks in the XRT73LC03A and configures it to transmit and
receive the line signal in an AMI format.
Setting this input pin "Low" enables the B3ZS/HDB3 Encoder & Decoder
blocks and configures it to ransmit and receive the line signal in the
B3ZS format for STS-1/DS3 operation or in the HDB3 fo rmat for E3
operation.
NOTE: If the XRT73LC03A is operating in the Hardware Mode, this pin
setting configures the B3ZS/HDB3 Encoder and Decoder Blocks for all
Channels.
63 SDI/(RxOFF_0) I Serial Data Input for the Microprocessor Serial Interface/Receiver
Shut OFF Input - Channel 0:
The function of this input pin depends on whether the XRT73LC03A is
operating in the HOST Mode or in the Hardware Mode.
HOST Mode - Serial Data Input for the Microprocessor Serial Inter-
face:
To read or write data into the Command Registers over the Microproces-
sor Serial Interface, apply the Read/Write bit, the Address Values of the
Command Registers and Data Value to be written during Write Opera-
tions to this pin.
This input is sampled on the rising edge of the SClk pin.
Hardware Mode - Channel 0 Receiver Shut OFF Input:
Setting this input pin “High” shuts off the Channel 0 receiver . Setting this
input pin “Low” enables the Receive Section for full operation.
62 SClk/(RxOFF_1) I Microprocessor Serial Interface Clock Signal/Receiver Shut OFF
Input - Channel 1:
The function of this pin depends on whether the XRT73LC03A is operat-
ing in the HOST Mode or in the Hardware Mode.
HOST Mode - Microprocessor Serial Interface Clock Signal:
This signal is used to sample the data on the SDI pin on the rising edge
of this signal. Additionally, during Read operations the Microprocessor
Serial Interface updates the SDO output on the falling edge of this sig-
nal.
Hardware Mode - Receiver Shut OFF input - Channel 1:
Setting this input pin "High" shuts off the Channel 1 receiver . Setting this
input pin "Low" enables the Receive Section for full operation.
XRT73LC03A
12
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
104 RxOFF_2 I Receiver Shut OFF Input - Channel 2:
Hardware Mode - Receiver Shut OFF Input - Channel 2:
Setting this input pin "High" shuts off the Receive Section in Channel 2.
Setting this input pin "Low" enables the Recei v e Section for full opera-
tion.
96 REGR/
RxClkINV IRegister Reset Input pin (Invert RxClk(n)) Output - Select):
The function of this pin depends upon whether the XRT73LC03A is oper-
ating in the HOST Mode or in the Hardware Mode.
NOTE: This pin is internally pulled "High".
In the HOST-Mode - Register Reset Input:
Setting this input pin "Low" causes the XRT73LC03A to reset the con-
tents of the Command Registers to their default settings and default
operating configuration.
In the Hardware Mode - Invert RxClk Output Selec t:
Setting this input pin "High" configures the Receive Section of all Chan-
nels in the XRT73LC03A to invert their RxClk_(n) clock output signals
and configures Channel (n) to output the recovered data via the
RPOS_(n) and RNEG_(n) output pins on the falling edge of RxClk_(n).
Setting this pin "Low" configures Channel (n) to output the recovered
data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of
RxClk_(n).
MICROPROCESSOR INTERFACE
PIN # NAME TYPE DESCRIPTION
XRT73LC03A
13
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
POWER AND GROUND PINS
PIN # NAME TYPE DESCRIPTION
11 TxDVDD_1 **** Transmitter Digital Supply, 3.3V + 5% - Channel(n)
13 TxAGND_1 **** Transmi t ter Analog Ground - Channel( n)
14 TxAGND_2 **** Transmi t ter Analog Ground - Channel( n)
17 TxAGND_2 **** Transmi t ter Analog Ground - Channel( n)
19 TxDVDD_2 **** Transmitter Digital Supply, 3.3V + 5% - Channel(n)
22 TxAVDD_2 **** Transmitte r Analog Supply, 3.3V + 5% - Channel(n)
26 TxAGND_0 **** Transmi t ter Analog Ground - Channel( n)
28 TxDVDD_0 **** Transmitter Digital Supply, 3.3V + 5% - Channel(n)
37 TxAVDD_0 **** Transmitte r Analog Supply, 3.3V + 5% - Channel(n)
39 TxAGND_0 **** Transmitter Ana log Ground - Channel (n)
40 AGND_0 **** Analog Ground - Channel (n)
41 RxDVDD_2 **** Receiver Digital Supply 3.3V + 5% Channel (n)
46 RxDGND_2 **** Receiver Digital Ground - Channel(n)
48 RxDVDD_0 **** Receiver Digital Supply 3.3V + 5% Channel (n)
54 RxDGND_0 **** Receiver Digital Ground - Channel(n)
70 RxAVDD_0 **** Receiver Analog Sup ply 3.3V + 5% Channel (n)
73 RxAGND_0 **** Reciever Analog Ground Channel (n)
78 RxAVDD_2 **** Receiver Analog Sup ply 3.3V + 5% - Channe l (n)
81 RxAGND_2 **** Receiver Analog Ground - Channel (n)
83 RxAGND_1 **** Receiver Analog Ground - Channel (n)
86 RxAVDD_1 **** Receiver Analog Sup ply 3.3V + 5% - Channe l (n)
94 AGND_2 **** Analog Ground - Channel (n)
97 EXDGND **** External Reference Clock Ground
98 EXDVDD **** External Reference Clock Power Supply
108 RxDGND_1 **** Receiver Digital Ground - Channel(n)
113 RxDVDD_1 **** Receiver Digital Supply 3.3V + 5% Channel (n)
114 AGND_1 **** Analog Ground - Channel (n)
118 TxAGND_1 **** Transmitter Analog Ground - Ch annel(n)
119 TxAVDD_1 **** Transmitter Analog Supply, 3.3V + 5% - Channel(n)
XRT73LC03A
14
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
NO CONNECTION PINS
PIN # NAME TYPE DESCRIPTION
52 NC No connection
53 NC No connection
90 NC No connection
91 NC No connection
XRT73LC03A
15
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
ELECTRICAL CHARACTERISTICS E
NOTE: The XRT73LC03A is assembled in a thermally
enhanced package that uses an integral Aluminum Oxide
heat spreader.
NOTE: * Not applicable to pins with pull-up or pull-down
resistors.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature - 65°C to + 150°C
Operating Temperature - 40°C to + 85°C
Supply Voltage Range -0.5V to +3.465V
Theta-JA 22.2° C/W
Theta-JC 4.0° C/W
ELECTRICAL CHARACTERISTICS (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL PARAMETER MIN.TYP.MAX.UNITS
DC Electrical Characteristics
DVDD Digital DC Supply Voltage 3.135 3.3 3.465 V
AVDD Analog DC Supply Voltage 3.135 3.3 3.465 V
ICC Supply Current (Measured while Transmitting and Receiving all
"1’s")
NOTE: VDD = 3.465V
350 mA
VIL Input Low Voltage * 0.8 V
VIH Input High Voltage * 2.0 5.0 V
VOL Output Low Voltage, IOUT = -4.0mA * 0.4 V
VOH Output High Voltage, IOUT = 4.0mA * 2.8 V
ILInput Leakage Current * ±10 µA
XRT73LC03A
16
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
NOTES:
1. All XRT73LC03A digital inputs are designed to be
TTL 5V compliant.
2. All XRT73LC03A digital outputs are also TTL 5V
compliant. However , these outputs will not drive to
5V nor will they accept external 5V pull-ups.
ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
AC ELECTRICAL CHARACTERISTICS (SEE FIGURE 5)
TERMINAL SIDE TIMING PARAMETERS (SEE FIGURE 6 AND FIGURE 7) -- {(n) = 0, 1 OR 2 }
SYMBOL PARAMETER MIN.TYP.MAX.UNITS
TxClk_(n) Clock Duty Cycle (STS-1/DS3) 30 50 70 %
TxClk_(n) Clock Duty Cycle (E3) 30 50 70 %
TxClk_(n) Frequency (SONET STS-1) 51.84 MHz
TxClk_(n) Frequency (DS3) 44.736 MHz
TxClk_(n) Frequency (E3) 34.368 MHz
tRTX TxClk_(n) Clock Rise Time (10% to 90%) 3 5 ns
tFTX TxClk_(n) Clock Fall Time (90% to 10%) 3 5 ns
tTSU TPData_(n)/TNData_(n) to TxClk_(n) Falling Set up time 3 1.5 ns
tTHO TPData_(n)/TNData_(n) to TxClk_(n) Falling Hold time 3 1.5 ns
tLCVO RxClk_(n) to rising edge of LCV_(n) output delay 2.5 ns
tTDY TTIP_(n)/TRing_(n) to TxClk_(n) Rising Propagation Del ay time 8 ns
RxClk_(n) Clock Duty Cycle 50 %
RxClk_(n) Frequency (SONET STS-1) 51.84 MHz
RxClk_(n) Frequency (DS3) 44.736 MHz
RxClk_(n) Frequency (E3) 34.368 MHz
tCO RxClk_(n) to RPOS_(n)/RNEG_(n) Delay Time 0 2.5 ns
tRRX RxClk_(n) Clock Rise Time (10% to 90%) 1.5 ns
tFRX RxClk_(n) Clock Fall Time (10% to 90%) 1.5 ns
CIInput Capacit ance 10 pF
CLLoad Capacitance 10 pF
XRT73LC03A
17
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
FIGURE 5. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR E3, DS3 AND STS-1 RATES (TYPICAL CHANNEL)
FIGURE 6. TIMING DIAGRAM OF THE TRANSMIT TERMINAL INPUT INTERFACE
R1
31.6
R2
31.6
Channel (n)
Channel (n)
TxPOS_(n)
TxNEG_(n)
TxLineClk_(n)
TTIP_(n)
TRing_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
Only One Channel Shown
1:1
R3
75
TPDATA or
TNDATA
TTIP or
TRING
TClk
t
TSU
t
THO
t
RTX
t
FTX
t
TDY
FIGURE 7. TIMING DIAGRAM OF THE RECEIVE TERMINAL OUTPUT INTERFACE
RClk
t
RRX
t
FRX
RPOS or
RNEG
LCV
t
LCVO
t
CO
XRT73LC03A
18
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
LINE SIDE PARAMETERS E3 APPLICATION
TRANSMIT CHARACTERISTICS (SEE FIGURE 5)
SYMBOL PARAMETER MIN.TYP.MAX UNITS
Transmit Output Pulse Amplitude
(Measured at Secondary Output of Transformer) 0.90 1.00 1.10 Vpk
Transmit Output Pulse Amplitude Ratio 0.95 1.00 1.05
Transmit Output Pulse Width 12.5 14.55 16.5 ns
Transmit Output Pulse Wi dth Ratio 0.95 1.00 1. 05
Transmit Output Jitter with jitter-free input @ TxClk_(n) 0.02 0.05 UIpp
Receive Line Characteristics
Receive Sensitivity (Length of cable) 1200 1400 feet
Interference Margin -20 -15 dB
Signal Level to Decl are Loss of Signal -35 dB
Signal Level to Clear Loss of Signal -15 dB
Occurrence of LOS to LOS Declaration Time 10 255 UI
Termination of LOS to LOS Clearance Time 10 255 UI
Intrinsic Jitter (all “1’s” pattern) 0.02 UI
Jitter Tolerance @ Jitter Frequency = 100Hz 64 UI
Jitter Tolerance @ Jitter Frequency = 1kHz 30 UI
Jitter Tolerance @ Jitter Frequency = 10kHz 4 UI
Jitter Tolerance @ Jitter Frequency = 800kHz 0.15 0.2 0 UI
XRT73LC03A
19
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
LINE SIDE PARAMETERS SONET STS-1 APPLICATION
TRANSMIT CHARACTERISTICS (SEE FIGURE 5)
SYMBOL PARAMETER MIN.TYP.MAX UNITS
Transmit Output Pulse Amplitude (Measured with TxLEV=0) 0.65 0.75 0.90 Vpk
Transmit Output Pulse Amplitude (Measured with TxLEV=1) 0.90 1.00 1.10 Vpk
Transmit Output Pulse Width 8.6 9.65 10.6 ns
Transmit Output Pulse Amplitude Ratio 0.90 1.00 1.10
Transmit Output Jitter with jitter-free input @ TxClk_(n) 0.02 0.05 UI
Receive Line Characteristics
Receive Sensitivity (Le ngth of Cable) 900 1100 feet
Signal Level to Declare or Clear Loss of Signal (see Table 5 ) mV
Intrinsic Jitter (all “1’s” pattern) 0.02 UI
Jitter Tolerance @ Jitter Frequency = 100Hz 64 UI
Jitter Tolerance @ Jitter Frequency = 1kHz 64 UI
Jitter Tolerance @ Jitter Frequency = 10kHz 5 UI
Jitter Tolerance @ Jitter Frequency = 400kHz 0.15 0.35 UI
XRT73LC03A
20
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
LINE SIDE PARAMETERS DS3 APPLICATION
TRANSMIT CHARACTERISTICS (SEE FIGURE 5)
SYMBOL PARAMETER MIN.TYP.MAX UNITS
Transmit Output Pulse Amplitude (Measured at 0 feet, TxLEV=0) 0.65 0.75 0.85 Vpk
Transmit Output Pulse Amplitude (Measured at 0 feet, TxLEV=1) 0.90 1.00 1.10 Vpk
Transmit Output Pulse Width 10.10 11.18 12.28 ns
Transmit Output Pulse Amplitude Ratio 0.90 1.00 1.10
Transmit Output Jitter with jitter-free input @ TxClk_(n) 0.02 0.05 UI
Receive Line Characteristics
Receive Sensitivity (Length of cable) 900 1100 feet
Signal Level to Declare or Clear Loss of Signal (see Table 5 ) 70 mV
Intrinsic Jitter (all “1’s” pattern) 0.02 UI
Jitter Tolerance @ Jitter Frequency = 100Hz 64 UI
Jitter Tolerance @ Jitter Frequency = 1kHz 64 UI
Jitter Tolerance @ Jitter Frequency = 10kHz 5 UI
Jitter Tolerance @ Jitter Frequency = 300kHz (Cat II) 0.35 0.45 UI
XRT73LC03A
21
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
Figure 8, Figure 9 and Figure 10 present the Pulse
Template requirements for the E3, DS3 and STS-1
Rates.
FIGURE 8. ITU-T G.703 TRANSMIT OUTPUT PULSE TEMPLATE FOR E3 APPLICATIONS
0%
50%
V = 100%
14.55ns
Nominal Pulse
12.1ns
(14.55 - 2.45)
17 ns
(14.55 + 2.45)
8.65 ns
10%
10%
20%
FIGURE 9. BELLCORE GR-499-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS
XRT73LC03A
22
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
NOTES:
1. A5 is always "0".
2. R/W = "1" for "Read" Operations
3. R/W = "0" for "Write" Operations
4. A shaded pulse, denotes a “don’t care” value.
FIGURE 10. BELLCORE GR-2 53 -C OR E TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
STS-1 Pulse Templ ate
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
-1-0.9-0.8-0.7-0.6-0.5-0.4-0.3-0.2-0.1 00.10.20.30.40.50.60.70.80.911.11.21.31.4
Time, in UI
Normalized Amplitude
Lower Curve
Upper Curve
FIGURE 11. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
D0 D1 D2 000D4D3
High Z
SDO
A0 D0R/W D1A60A4A3A2A1 D7D6D5D4D3D2
SDI
12345678910111213141516
SClk
CS
High Z
XRT73LC03A
23
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
NOTE: The load is 10pF
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
MICROPROCESSOR SERIAL INTERFACE TIMING (SEE FIGURE 12)
SYMBOL PARAMETER MIN.TYP.MAX UNITS
t21 CS Low to Rising Edge of SClk Setup Time 5 ns
t22 SCLK Falling Edge to CS Low Assertion T ime 5 ns
t23 SDI to Rising Edge of SClk Setup Time 5 ns
t24 SDI to Rising Edge of SClk Hold Time 5 ns
t25 SClk "Low" Time 65 80 ns
t26 SClk "High" Time 65 80 ns
t27 SClk Period 160 ns
t28 CS Low to Rising Edge of SClk Hold Time 5 ns
t29 CS "Inactive" T ime 160 ns
t30 Falling Edge of SClk to SDO Valid Time 80 ns
t31 Falling Edge of SClk to SDO Invalid Time 65 ns
t32 Rising edge of CS to High Z 100 ns
t33 Rise/Fall time of SDO Output 20 ns
FIGURE 12. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
SDI R/W A1
A0
CS
SCLK
CS
SCLK
SDI
SDO D0 D1 D2 D7
t22
t21
t23 t24
t25 t26
t27 t28
t29
t30 t31 t32t33
Hi-Z
Hi-Z
XRT73LC03A
24
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
SYSTEM DESCRIPTION
A functional block diagram of the XRT73LC03A E3/
DS3/STS-1 T ransceiver IC is pr esented in Figure 13.
The XRT 73LC03A contains three separate channels
with three distinct sections:
•The Transmit Section - Channels 0, 1 and 2
•The Receive Section - Channels 0, 1 and 2
•The Microprocessor Serial Interface Section
THE T RANSMIT SECTION - CHANNELS 0, 1 AND 2
The Transmit Section, within each Channel, accepts
TTL/CMOS level signals from the Terminal Equip-
ment in either a Single-Rail or Dual-Rail fo rmat. The
Transmit Section then takes this data and does the
following:
•Encode this dat a into the B3ZS format if the DS3 or
SONET STS-1 Modes has been selected or into
the HDB3 format if the E3 Mode has been selected.
•Convert the CMOS level B3ZS or HDB3 encoded
data into pulses with shap es that are compliant with
the various industry standard pulse template
requirements.
•Drive these pulse s onto th e line via the TTIP_ (n )
and TRing_(n) output pins across a 1:1 Trans-
former.
NOTE: The Transmit Section drives a "1" (or a Mark) onto
the line by driving either a positive or negative polarity pulse
across the 1:1 Transformer within a given bit period. The
Transmit Section drives a "0" (or a Space) onto the line by
driving no pulse onto the line.
THE RECEIVE SECTION - CHANNELS 0, 1 AND 2
The Receive Section, within each Channel, receives
a bipolar signal from the line via the RTIP and RRing
signals through a 1:1 Transformer or 0.01µF Capaci-
tor.
The recovered clock and data outputs to the Local
Terminal Equipment in the form of CMOS level sig-
nals via the RPOS_(n) , RNEG _( n ) and R xClk _( n)
output pins.
THE MICROPROCESSOR SERIAL INTERFACE
The XR T73LC03A can be configured to operate in ei-
ther the Hardware Mode or the HOST Mode.
The XRT 73LC03A contains three identical channels.
The Microprocessor Interface In puts are common to
all channels. The descriptions that follow refer to
Channel(n) where (n) represents channel 0, 1 or 2.
a. Operating in the Hardware Mode
When the XR T73LC03A is o perating in the Hardware
Mode, then the following is true:
1. The Microprocessor Serial Interface blo ck is dis-
abled.
2. The XRT73LC03A is configured via input pin set-
tings.
The XRT73LC03A can be configured to operate in
the Hardware Mode by tying the HOST/(HW) input
pin to GND.
Each of the pins associated with the Microprocessor
Serial Interface takes on their alternative role as de-
fined inTable 1.
When the XR T73LC03A is oper ating in th e Hardware
Mode, all of the remaining input pins become active.
b. Operating in the HOST Mode
The XRT73LC03A can be configured to operate in
the HOST Mode by tying the HOST/(HW) input pin to
VDD.
When the XRT73LC03A is operating in the HOST
Mode, then the following is true.
1. The Microprocessor Serial Interface block is
enabled. Wr iting the appro priate data into the on-
chip Command Registe rs makes many co nfigura-
tion selections.
2. All of the following input pins are disabled and
should be connected to gro und:
•Pins 8, 9 & 35 - TxLEV_(n)
•Pins 6, 7 & 36 - TAOS_(n)
•Pin 74, 82 & 100 - REQEN_(n)
•Pin 69, 77 & 87 - RLB_(n)
•Pin 68, 76 & 88 - LLB_(n)
•Pin 92 & 102 - E3_(n)
•Pin 65, 95 & 101 - STS1/DS3_(n)
In HOST Mode Operation, the TxOFF_(n) input pins
can be used to turn on or turn off the T ransmit Output
Drivers within all Channels concurrently. The intent
behind this feature is to permit a system d esigned for
TABLE 1: ROLE OF MICROPROCESSOR SERIAL
INTERFACE PINS WHEN THE XRT73LC0 3A IS
OPERATING IN THE HARDWARE MODE
PIN #PIN NAME FUNCTION, WHILE IN
HARDWARE MODE
61 CS/(ENDECDIS) ENDECDIS
62 SClk/(RxOFF_1) RxOFF_1
63 SDI/(RxOFF_0) RxOFF_0
64 SDO/(E3_0) E3_0
96 REGR/(RxClkINV) RxClkINV
XRT73LC03A
25
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
redundancy to quickly switch out a defective line card
and switch-in the back-up line card.
1.0 SELECTING THE DATA RATE
Each channel within the XRT73LC03A can be config-
ured to support the E3 (34.368 Mbps), DS3 (44.736
Mbps) or the SONET STS-1 (51.84 Mbp s) rates. Fur-
ther, each channel can be configured to operate in a
mode/data rate that is independent of the other chan-
nels.
Two methods are available to select the data rate for
each channel of the XRT73LC03A.
1.1 CONFIGURING CHANNEL(n)
For the following disscussion the reader should refer
toTable 2 to determine the appropriate Address for
each command register of ea ch channel in the
XRT73LC03A. The command register descri ption re-
fers to CR(x)-(n), where (x) = 0 to 7 and (n) refers to a
particular channe l of the XRT73LC03A.
FIGURE 13. FUNCTIONAL BLOCK DIAGRAM OF THE XRT73LC03A
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF_(n)
Channel 2 - (n) = 2
AGC/
Equalizer
Serial
Processor
Interface
Peak
Detector
LOS Detector
Slicer Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
Channel 0 - (n) = 0
Channel 1 - (n) = 1
Notes: 1. (n) = 0, 1, or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Device
Monitor
MTIP_(n)
MRing_(n)
DMO_(n)
Transmit
Logic Duty Cycle Adjust
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
E3_(n) STS-1/DS3_(n) Host/(HW) RLOL_(n) EXClk_(n) RxOFF RxClkINV
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
Tx
Control
XRT73LC03A
26
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
Address:
The register add resse s are presente d in th e Hexa-
decimal format.
Type:
The Command Regis te rs ar e eit he r Re ad -O nly (R O)
type of registers or Read/Write (R/W) typ e of regis-
ters.
TABLE 2: HEXADECIMAL ADDRESSES AND BIT FORMATS OF XRT73LC03 A COMMAND REGISTERS
REGISTER BIT-FORMAT
ADDRESS COMMAND
REGISTER TYPE D4 D3 D2 D1 D0
CHANNEL0
0x00 CR0-0 RO RLOL_0 RLOS_0 ALOS_0 DLOS_0 DMO_0
0x01 CR1-0 R/W TxOFF_0 TAOS_0 TxClkINV_0 TxLEV_0 TxBIN_0
0x02 CR2-0 R/W Reserved ENDECDIS_0 ALOSDIS_0 DLOSDIS_0 REQEN_0
0x03 CR3-0 R/W SR/(DR)_0 LOSMUT_0 RxOFF_0 RxClk_0INV Reserved
0x04 CR4-0 R/W Reserved STS-1/DS3_0 E3_0 LLB_0 RLB_0
0x05 CR5-0 R/W Reserved Reserved Reserved Reserved Reserved
0x06 CR6-0 R/W Reserved Reserved Reserved Reserved Reserved
0x07 CR7-0 R/W Reserved Reserved Reserved Reserved Reserved
CHANNEL1
0x08 CR0-1 RO RLOL_1 RLOS_1 ALOS_1 DLOS_1 DMO_1
0x09 CR1-1 R/W TxOFF_1 TAOS_1 TxClkINV_1 TxLEV_1 TxBIN_1
0x0A CR2-1 R/W Reserved ENDECDIS_1 ALOSDIS_1 DLOSDIS_1 REQEN_1
0x0B CR3-1 R/W SR/(DR)_1 LOSMUT_1 RxOFF_1 RxClk_1INV Reserved
0x0C CR4-1 R/W Reserved STS-1/DS3_1 E3_1 LLB_1 RLB_1
0x0D CR5-1 R/W Reserved Reserved Reserved Reserved Reserved
0x0E CR6-1 R/W Reserved Reserved Reserved Reserved Reserved
0x0F CR7-1 R/W Reserved Reserved Reserved Reserved Reserved
CHANNEL2
0x10 CR0-2 RO RLOL_2 RLOS_2 ALOS_2 DLOS_2 DMO_2
0x11 CR1-2 R/W TxOFF_2 TAOS_2 TxClkINV_2 TxLEV_2 TxBIN_2
0x12 CR2-2 R/W Reserved ENDECDIS_2 ALOSDIS_2 DLOSDIS_2 REQEN_2
0x13 CR3-2 R/W SR/(DR)_2 LOSMUT_2 RxOFF_2 RxClk_2INV Reserved
0x14 CR4-2 R/W Reserved STS-1/DS3_2 E3_2 LLB_2 RLB_2
0x15 CR5-2 R/W Reserved Reserved Reserved Reserved Reserved
0x16 CR6-2 R/W Reserved Reserved Reserved Reserved Reserved
0x17 CR7-2 R/W Reserved Reserved Reserved Reserved Reserved
XRT73LC03A
27
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
The default value for each of the bit-fields within these reg-
isters is "0".
a. Operating in the Hardware Mode.
In order to configure individual Channels into the ap-
propriate mo de , se t the E3_( n ), an d th e ST S-1 /
DS3_(n) input pins (wher e n = 0, 1 or 2) to the appro-
priate logic states, as presente d be lo w inTable 3.
b. Operating in the HOST Mode.
To configure a Channel into the appropriate mode,
write the appropr iat e valu e s into the STS-1/DS3_(n)
and E3_(n) bit-fields within the Command Register
CR4-(n), as illustrated below (refer to Table 2 for the
correct address for each channel).
Table 4 relates the values of these two bit-fields to the
selected data rates.
2.0 THE TRANSMIT SECTION
Figure 13 indicates that the Transmit Section within
each Channel of the XR T73 LC03A consist s of the fo l-
lowing blocks:
•Transmit Logic Block
•TxClk_(n) Duty Cycle Adjust Block
•HDB3/(B3ZS) Encoder
•Pulse Shaping Block
The purpose of the Transmit Section is to take TTL/
CMOS level data from the terminal equipment an d
encode it into a format such that it can:
1. Be efficiently transmitted over coaxial cable at
E3, DS3, or STS-1 data rates.
2. Be reliably received by the Remote Terminal
Equipment at th e ot he r en d of the E3, DS3, or
STS-1 data link.
3. Comply with the applicable pulse template
requirements.
2.1 THE TRANSMIT LOGIC BLOCK
The purpose of the Transmit Logic Block is to accept
either Dual-Rail or Single-Rail (e.g., a binary data
stream) TTL/CMOS level data and timing information
from the Terminal Equipment.
2.1.1 Accepting Dual-Rail Data from the Termi-
nal Equipment
Whenever the XRT73LC03A accepts Dual-Rail data
from the Terminal Equipment, it does so via the fol-
lowing input signals:
•TPData_(n)
•TNData_(n)
•TxClk_(n)
Figure 14 illustrates the typical interface for the trans-
mission of data in a Dual-R ail Format between the
Terminal Equipment and the Transmit Section of the
XRT73LC03A.
TABLE 3: SELECTING THE DATA RATE FOR CHANNEL(n) VIA THE E3_(n) AND STS-1/DS3_(n) INPUT PINS
(HARDWARE MODE)
DATA RATE STATE OF E3_(n) PIN STATE OF STS-1/DS3_(n) PIN MODE OF B3ZS/HDB3 ENCODER/
DECODER BLOCKS
E3 (34.368 Mbps) 1 X (Don't Care) HDB3
DS3 (44.736 Mbps) 0 0 B3ZS
STS-1 (51.84 Mbps) 0 1 B3ZS
COMMAND REGISTER, CR4-(n)
D4 D3 D2 D1 D0
XSTS-1/(DS3)_(n)) E3_(n) LLB_(n) RLB_(n)
xxxxx
TABLE 4: SELECTING THE DATA RATE FOR CHANNEL(n)
VIA THE STS-1/DS3_(n) AND THE E3_(n) BIT-FIELDS
WITHIN THE APPROPRIATE COMMAND REGISTER (HOST
MODE)
SELECTED DATA
RATE STS-1/DS3_(n)
(D3) E3_(n)
(D2)
E3 X (Don't Care) 1
DS3 0 0
STS-1 1 0
XRT73LC03A
28
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
The manner that the LIU handles Dual-Rail data is
described below and illustrated in Figure 15. The
T ransmit Section (of a Channel) typically samples the
data on the TPData_(n) and TNDat a_(n) input pins on
the falling edge of TxClk_(n).
TxClk_(n) is the clock signal that is of the selected
data ra te frequency, E3 = 34.368 MHz, DS3 = 44.736
MHz and STS-1 = 51.84 MHz. If the Transmit Sec-
tion samples a "1" on the TPData_(n) input pin, then
the Tr an sm it Sec tio n of th e de vice ultima te ly gen e r-
ates a positive polarity pulse via the TTIP_(n) and
TRing_(n) output pins across a 1:1 transformer . If the
T ransmit Section samples a "1" on the TNDat a_(n) in -
put pin, then the Transmit Section of the device ulti-
mately generates a negative polarity pulse via the
TTIP_(n) and TRing_(n) output pins across a 1:1
transformer.
2.1.2 Accepting Single-Rail Data from the Ter-
minal Equipment
To transmit da ta in a Single-Rail data from the Termi-
nal Equipment, configure the XRT73LC03A in the
HOST Mode.
Write a "1" into the TxBin_(n) (TRANSMIT BINary)
bit-field of Command Register CR1-(n) shown below.
NOTE: Please refer to Table 2 for the Address of the indi -
vidual Channel(n).
The Transmit Section of each channel samples this
input pin on the falling edge of the TxClk_(n) clock
signal and encodes this dat a into the appropriate bi-
polar line signal across the TTIP_(n) and TRing_(n)
output pins.
NOTES:
FIGURE 14. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FOR-
MAT FROM THE TRANSMITTING TERMINAL EQUIPMENT TO THE TRANSMIT SECTION OF A CHANNEL
Exar E3/DS3/STS-1 LIU
Transmit
Logic
Block
TxPOS
TxNEG
TxLineClk
TPData
TNData
TxClk
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
FIGURE 15. THE XRT73LC03A SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT PINS
TxClk
TPData
TNData
Data 1 1 0
COMMAND REGISTER CR1-(n)
D4 D3 D2 D1 D0
TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBin_(n)
XX X X1
XRT73LC03A
29
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
1. In this mode, the Transmit Logic Block ignores the
TNData_(n) input pin.
2. If the Transmit Section of a given channel is config-
ured to accept Single-Rail data from the Terminal
Equipment, the B3ZS/HDB3 Encoder must be
enabled.
Figure 16 illustrates the behavior of the TPData_(n)
and TxClk_(n) signals when the Transmit Logic Block
has been configured to accept Single-Rail data from
the Terminal Equipment.
2.2 THE T RANSMIT CLOCK DUTY CYCLE ADJUST CIR-
CUITRY
The on-chip Pulse-Shaping cir cuitry within the Trans-
mit Section of each Channel in the XRT 73LC03A
generates pulses of the appropriate shapes and width
to meet the applic able pu lse tem p late req u ire m en ts.
The widths of these output pulses are defined by the
width of the half-period pulses within the TxClk_(n)
signal.
However, if the widths of the pulses within the
TxClk_(n) clock signal are allowed to vary significant-
ly, this could jeopardize the chip's ability to generate
Transmit Output pulses of the appropriate width and
thereby not meet the Pulse Template requirement
specification. Consequently, the chip's ability to gen-
erate compliant pulses could depend up on the duty
cycle of the clock signal applied to the TxClk_(n) input
pin.
The Transmit Clock Duty Cycle Adjust Circuitry ac-
cepts clock pulses via the TxClk_(n) input pin at duty
cycles ranging from 30% to 70% and converts them
to a 50% duty cycle.
2.3 THE HDB3/B3ZS ENCODER BLOCK
The purpose of the HDB3/B3ZS Encoder Block is to
aid in the Clock Recovery process at the Remo te Ter-
minal Equipment by ensuring an upper limit on the
number of consecutive zeros that can exist within the
line signal.
2.3.1 B3ZS Encoding
If the XRT73LC03A has been con fig ur ed to op e ra te
in the DS3 or SONET STS-1 Modes, then the HDB3/
B3ZS Encoder blocks operate in the B3ZS Mode.
When the Encoder is operating in this mode, it parses
through and searches the Transmit Binary Data
Stream from the Transmit Logic Block for the occur-
rence of three (3) consecutive zeros (e.g., "000"). If
the B3ZS Encoder finds an occurrence of three con-
secutive zeros, then it substit utes these three "0’s",
with either a "00V" or a "B0V" pattern.
Where:
"B" represents a Bipolar pulse th at is comp lian t with
the Alternating Polarity requirements of the AMI (Al-
ternate Mark Inversion) line code; and
"V" represents a Bipolar Violation (e.g., a bipolar
pulse that violates the Alternating Polarity require-
ments of the AMI line code).
The B3ZS Encoder decides whether to substitute
with either the “00V" or the "B0V" pattern in order to
insure that an odd number of bipolar pulses exist be-
tween any two consecutive violation pulses.
Figure 17 illustrates the B3ZS Encoder at work with
two separate strings of th re e (o r mo re ) consecutive
zeros
FIGURE 16. THE BEHAVIOR OF THE TPDATA AND TXCLK INPUT SGNALS, WHILE THE TRANSMIT LOGIC BLOCK IS
ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT
TxClk
TPData
Data 1 1 0
XRT73LC03A
30
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
2.3.2 HDB3 Encoding
If the XRT73LC03A is configured to operate in the E3
Mode, then the HDB3/B3ZS Encoder blocks operate
in the HDB3 Mode. When the Encoder is operating in
this mode, it parses through and searches the Trans-
mit Data S tre am from the Tr ansmit Logic Block for the
occurrence of four (4) consecutive zeros (e.g.,
"0000"). If the HDB3 Encoder finds an occurrence of
four consecutive zeros, then it substitutes these four
"0’s", with either a "000V" or a "B00V" pattern. The
HDB3 Encoder decides whether to substitute with ei-
ther the "000V" or the "B00V" pattern in order to in-
sure that an odd number of bipolar pulses exist be-
tween any two consecutive violation pulses.
Figure 18 illustrates the HDB3 Encoder at work with
two separate strings of four (or more) co nsecutive ze-
ros.
2.3.3 Disabling the HDB3/B3ZS Encoder
The XRT73LC03A HDB3/B3ZS Encoder can be dis-
abled by two method s.
a. Operating in the Hardware Mode.
The HBD3/B3ZS Encoder blocks of all channels
are disabled by setting the ENDECDIS (Encoder/
Decoder Disable) input pin to “1".
NOTE: By executing this step the HDB3/B3ZS Encoder and
Decoder blocks in all channels of the XRT73LC03A are glo-
bally disabled.
a. Operating in the HOST Mode.
When the XRT73LC03A is operating in the HOST
Mode the HDB3/B3ZS Encoders in e ach channel can
be individually enabled or disabled. Disable the
HDB3/B3ZS Encoder block in Channel(n) by setting
the ENDECDIS(n) bit-field in Command Register
(CR2-(n)), to "1"
FIGURE 17. AN EXAMPLE OF B3ZS ENCODING
TClk
TPOS
SR data
Encoded
PDATA
Encoded
NDATA
100 101
01 0000000000000000110 10 111 0
001100 01010000000 0001 111 10 0 00 00000
01 00000101010101010101110101010101
Line signal BV
0
V00
0
FIGURE 18. AN EXAMPLE OF HDB3 ENCODING
TClk
TPOS
SR data
Encoded
PDATA
Encoded
NDATA
100 101
001 0000000000000000110 10 111 0
001100 01010000000 0001 11 11000000000
01 00000101010101010101110101010101
Line signal BV0
V
000
0
COMMAND REGISTER CR2-(n)
D4 D3 D2 D1 D0
Reserved ENDECDIS_(n) ALOSDIS_(n) DLOSDIS_(n) REQEN_(n)
XRT73LC03A
31
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
NOTE: This method can only be used if the XRT73LC03A is
operating in the HOST Mode.
If either of these me th o ds are used to disab le th e
HDB3/B3ZS Encoder, then the LIU transmits the data
as received via the TPDat a_(n) and TNData_ (n) input
pins.
2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY
The Transmit Pulse Shaper Circuitry consists of a
Transmit Line Build-Out circuit which can be enabled
or disabled by setting the TxLEV_(n) input pin or
TxLEV_(n) bit-field to “High”or "Low". The purpose of
the Tr an sm it Lin e Bu ild - Out circuit is to permit config-
uration of each channel to transmit an output pulse
which is compliant to either of the following pulse
template requirements when measured at the Digital
Cross Connect System. Each of these Bellcore spec-
ifications state that the cable length between the
Transmit Output and the Digital Cross Connect sys-
tem can range anywhere from 0 to 450 feet.
The Isolated DSX-3 Pulse Template Requirement per
Bellcore GR-499-CORE is illustrated in Figure 19 and
the Isolated STSX-1 Pulse Template Requirement
per Bellcore GR-253-CORE is illustrated in Figure 20.
X 1 XX X
COMMAND REGISTER CR2-(n)
D4 D3 D2 D1 D0
FIGURE 19. THE BELLCORE GR-499-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS
DS3 Pulse Template
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
Tim e , in UI
Norm aliz e d Am plitude
Lower Curve
Upper Curve
XRT73LC03A
32
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
.
2.4.1 Enabling the Transmit Line Build-Out Cir-
cuit
If the Transmit Line Build-Out Circuit is en abled, th en
the Tr an sm it Section of the Channe l out puts shaped
pulses onto the line via the TTIP_(n) and TRing_(n)
output pins.
Enable the Transmit Line Build-Out circuit for each
channel by doing th e follo wing:
a. Operating in the Hardware Mode
Set the TxLEV_(n) input pin to “Low".
b. Operating in the HOST Mode
Set the TxLEV_(n) bit-field to "0", as illustrated below.
2.4.2 Disabling the Transmit Line Build-Out Cir-
cuit
If the Transmit Line Build-Out circuit is disabled, then
the XRT73LC03A outputs partially shaped pulses on-
to the line via the TTIP_(n) and TRing_(n) output
pins.
Disable the Tr ansmit Line Build-Ou t circu i t by doin g
the following:
a. Operating in the Hardware Mode
Set the TxLEV_(n) input pin to “High".
b. Operating in the HOST Mode
FIGURE 20. THE BELLCORE GR-253-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLI-
CATIONS
STS-1 Pulse Template
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
-1-0.9
-0.8-0.7
-0.6-0.5
-0.4-0.3
-0.2-0.1 00.1
0.20.30.4
0.50.6
0.70.8
0.9 1
1.11.2
1.31.4
Time , i n UI
Normalized Amplitude
Lower Curve
Upper Curve
COMMAND REGISTER, CR1-(n)
D4 D3 D2 D1 D0
TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n)
0X X 0X
XRT73LC03A
33
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
Set the TxLEV_(n) bit-field to "1" as illustrated below.
2.4.3 Design Guideline for Set ting the Transmit
Line Build-Out Circuit
The TxLEV_(n) input pins or bit-fields should be set
based upon the overall cable length between the
Transmitting Terminal and the Digital Cross Connect
system where the pulse template measurements are
made.
If the cable length bet ween the Transmitting Ter-
minal and the DSX-3 or STSX-1 is less than 225
feet, enable the T ransmit Line Build-Out circ uit by
setting the TxLEV_(n) input pin or bit-field to "0".
NOTE: In this case, the configured channel outputs shaped
(e.g., not square-wave) pulses onto the line via its TTIP_(n)
and TRing_(n) output pins. The shape of this output pulse
is such that it complies with the pulse te mplate require-
ments even when subjected to cable loss ranging from 0 to
225 feet.
If the cable length bet ween the Transmitting Ter-
minal and the DSX-3 or STSX-1 is greater than 225
feet, disable the Transmit Line Build-Out circuit
by setting the TxLEV_(n) input pin or bit-field to
"1".
NOTE: In this case, the configured channel outputs partially
shaped pulses onto the line via the TTIP_(n) and TRing_(n)
output pins. The cable loss that these pulses experience
over long cable lengths (e.g., greater than 225 feet) cause
these pulses to be properly shaped and comply with the
appropriate pulse template requirement.
2.4.4 The Transmit Line Build-Out Circuit and
E3 Applications
The ITU-T G.703 Pulse Template Requirements for
E3 states that the E3 transmit output pulse should be
measured at the Second ary Side of the Transmit Out-
put Transformer for Pulse Template compliance. In
other words, there is no Digital Cross Connect Sys-
tem pulse template requirement for E3. Consequent-
ly, the Transmit Line Build-Out circuit within a given
Channel is disabled whenever that chann el has been
configured to operate in the E3 Mode.
2.5 INTERFACING THE TRANSMIT SECTIONS OF THE
XRT73LC03A TO THE LINE
The E3, DS3 and SONET STS-1 specification docu-
ments all st ate th at line signals tran smitted over coax-
ial cable are to be terminated with 75 Ohm resistor.
Interface the Transmit Section of the XRT73LC03A
in the manner illustrated in Figure 21.
COMMAND REGISTER, CR1-(n)
D4 D3 D2 D1 D0
TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n)
0X X 1X
FIGURE 21. RECOMMENDED SCHEMATIC FOR INTERFACING THE TRANSMIT SECTION OF THE XRT73LC03A
TO THE LINE
R1
31.6
R2
31.6
Channel (n)
TxPOS_(n)
TxNEG_(n)
TxLineClk_(n)
TTIP_(n)
TRing_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
Only One Channel Shown
1:1
J1
BNC
XRT73LC03A
34
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
TRANSFORMER VENDOR INFORMATION
Pulse
Corporate Office
12220 World Trade Drive
San Diego, CA 92128
Tel: (858)-674-8100
FAX: (858)-674-8 262
Europe
1 & 2 Huxley Road
The Surrey Research Park
Guildford, Surrey GU2 5RE
United Kingdom
Tel: 44-1483-401700
FAX: 44-1483-401701
Asia
150 Kampong Ampat
#07-01/02
KA Centre
Singapore 368324
Tel: 65-287-8998
FAX: 65-280-0080
Website: http://www.pulseeng.com
Halo Electronics
Corporate Office
P.O. Box 5826
Redwood City, CA 94063
Tel: (650)568-5800
FAX: (650)568-6165
Email: info@haloelectronics.com
Website: http://www.haloelectronics.com
Transpower Technologies, In c.
Corporate Office
Park Center West Building
9805 Double R Blvd, Suite # 100
Reno, NV 89511
(800)500-5930 or (775)852-0140
Email: info@trans-power.com
Website: http://www.trans-power.com
TRANSFORMER RECOMMENDATIONS
PARAMETER VALUE
Turns Ratio 1:1
Primary Inductance 40H
Isolation Voltage 1500Vrms
Leakage Inductance 0.6H
PART NUMBER VENDOR INSULATION PACKAGE TYPE
PE-68629 Pulse 3000V Large Thru-Hole
PE-65966 Pulse 1500V Small Thru-Hole
PE-65967 Pulse 1500V Small SMT
T3001 Pulse 1500V Small SMT
TG01-0406NS Halo 1500V Small SMT
TTI 7601-SM Trans-Power 1500V Small SMT
XRT73LC03A
35
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
3.0 THE RECEIVE SECTION
Figure 13 indicates the Receive Section consists of
the following blocks:
•AGC/Equalizer
•Peak Detector
•Slicer
•Clock Recovery PLL
•Data Recovery
•HDB3/B3ZS Decoder
The purpose of the Receive Section is to take an in-
coming attenuated/disto rted bipolar signal from the
line and encode it back into the TTL/CMOS format
where it can b e receive d and pro cesse d by th e Termi-
nal Equipment.
3.1 INTERFACING THE RECEIVE SECTIONS OF THE
XRT73LC03A TO THE LINE
The design of the Receive Circuitry should be trans-
former-coupled to the Receive Section to the line.
The specification documents for E3, DS3, and STS-1
all specify 75 Ohm termination loads when transmit-
ting over coaxial cable. The r ecommended method to
interface the Receive Section to the line in a manner
is shown in Figure 22.
FIGURE 22. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73LC03A
TO THE LINE (TRANSFORMER-COUPLING)
J1
BNC
T1
1:1
R1
37.4
R2
37.4
Channel (n)
RxPOS_(n)
RxNEG_(n)
RxClk_(n)
RTIP_(n)
RRing_(n)
RPOS_(n)
RNEG_(n)
RxClk_(n)
C1
0.01uf
Only One Channel Shown
XRT73LC03A
36
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
3.2 THE RECEIVE EQUALIZER BLOCK
The purpose of this block is to equalize the incoming
distorted signal due to cable loss. The Receive
Equalizer attempts to restore the shape of the line
signal so that the transmitted data and clock can be
recovered reliably.
.
3.2.1 Guidelines for Setting the Receive Equal-
izer
This data sheet presents guidelin es fo r set tin g the
Receive Equalizer, for the following conditions.
1. If the overall cable length, from the local Receiv-
ing Terminal to the Remote Transmitting Terminal
is NOT known.
2. If the overall cable leng th , from the Local Receiv-
ing Terminal to the remote Transmitting Terminal
is known.
3.2.1.1 If the Overall Cable Length is NOT
Known
This section presents recommendations on what
state to set the Receive Equalizer when the overall
cable-length, from the local Receiving Terminal to the
remote Transmitting Terminal is NOT known. For
DS3, STS-1 and E3 applicat ions, enable the Receive
Equalizer by setting either the REQEN_(n) input pin
“high” or the REQEN_(n) bit-field to “1”. The remain-
der of this section provides an explanation why we
recommend enabling the Receive Equ alizer for these
applications.
3.2.1.1.1 The Use of the Receive Equalizer in a
Typical DS3 or STS-1 Application
Most System Manufacturers of equipment supporting
DS3 and STS-1 lines, interface their equipment to ei-
ther a DSX-3 or STSX-1 Cross-Co nnect. While in-
stalling their equipment the Tr ansmit Line Build-Out
circuit is set to the proper setting that makes the
transmit output pulse compliant with the Isolated
DSX-3 or STSX-1 Pulse Template requirements. For
the XRT73LC03A device, this is achieved by setting
the TXLEV_(n) input pin o r bit-field to the approp riate
level.
FIGURE 23. THE TYPICAL APPLICATION FOR THE SYSTEM INSTALLER
Digital Cross-Connect
System
Transmitting
Terminal
Receiving
Terminal
0 to 450 feet of Cable
Pulses that are
comp liant t o the
Isolated DSX-3 or
STSX-1 Pulse Template
Requirement
0 to 450 feet of
Cable
DSX-3
or
STSX-1
XRT73LC03A
37
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
When the System Manufacturer is interfacing the Re-
ceive Section of the XRT73LC03A to the Cross-Con-
nect, they should be aware of the following facts:
1. All DS3 or STS-1 line signals that ar e pr es en t at
either the DSX-3 or the STSX-1 Cross Connect
are required to meet the Isolated Pulse Template
Requiremen ts per Bellcor e GR- 4 99 -C ORE for
DS3 applications, or Bellcore GR-253-C OR E for
STS-1 applications.
2. Bellcore documen ts state that the amplitu de of
these pulses at the DSX-3 or STSX-1 location
can range in amplitude from 360mVpk to
850mVpk.
3. Bellcore documents stipulate that the Receiving
Terminal must be able to receive the pulse tem-
plate compliant line signal over a cable length of
0 to 450 feet from the DSX-3 or the STSX-1
Cross-Connect location.
These facts are reflected in Figure 23.
Design Considerations for DS3 and STS-1 Appli-
cations
When installing equipment into environments depict-
ed in Figure 23, the system installa tion personnel
may be able to dete rm in e th e cab le leng th bet wee n
the local terminal equipment and the DSX-3/STSX-1
Cross-Connect Patch-Panel. The cable length be-
tween the local terminal equipment and the DSX-3/
STSX-1 Cross-Connect Pa tch Panel ranges betwee n
0 and 450 feet.
It is extremely unlikely that the system installation
personnel will know the cable length between the
DSX-3/STSX-1 Cross-Connect Patch-Panel and the
remote terminal equipment. Therefore, we recom-
mend that the Receive Equalizer be enabled by set-
ting the REQEN_(n) input pin or bit-field to “1”.
The only time that the Receive Equalizer should be
disabled is when there is an off-chip equalizer in the
Receive path between the DSX-3/STSX-1 Cross-
Connect and the RTIP_(n)/RRING_(n) input pins, or
in applications where the Receiver is directly monitor-
ing the transmit output signal directly.
3.2.1.2 Design Considerations for E3 Applica-
tions
In E3 System installation, it is recommended that the
Receive Equalizer of the XRT73LC03A device be en-
abled by pulling the REQEN_(n) input pins “High” or
by setting the REQEN_(n) bit-fields to “1”.
NOTE: The results of extensive testing indicates that when
the Receive Equalizer is enabled, the XRT73LC03A device
is capable of receiving an E3 line signal with anywhere from
0 to 12dB of cable loss over the Industrial Temperature
range.
• Design Considerations for E3 Applications or if
the Overall Cable Len gth is known
If during System Installation the overall cable length
is known, then in order to optimize the performance
of the XRT73LC03 A in terms of receive intrinsic jitter,
etc., enable or disable the Receive Equalizer based
upon the following recommendations:
The Receive Equalizer should be turne d ON if the
Receive Section of a given channel is going to re-
ceive a line signal with an overall cable length of 300
feet or greater. Conversely, turn OFF the Receive
Equalizer if the Receive Section of a given channel is
going to receive a line signal over a cable length of
less than 300 feet.
NOTES:
1. If the Receive Equalizer block is turned ON when it
is receiving a line signal over short cable length,
the received line signal may be over-equalized
which could degrade performance by increasing
the amount of jitter that exists in the recovered data
and clock signals or by creating bit-errors
2. The Receive Equalizer has been designed to
counter the frequency-dependent cable loss that a
line signal experiences as it travels from the trans-
mitting terminal to the receiving terminal. However ,
the Receive Equalizer was not designed to counter
flat loss where all of the Fourier frequency compo-
nents within the line signal are subject to the same
amount of attenuation. Flat loss is handled by the
AGC block.
Disable the Receive Equalizer block by doing either
of the following.
a. Operating in the Hardware Mode
Set the REQEN_(n) input pin “Low".
b. Operating in the HOST Mode
Write a "0" to the REQEN_(n) bit-field within Com-
mand Register CR2, as illustrated below.
COMMAND REGISTER CR2-(n)
D4 D3 D2 D1 D0
Reserved ENDECDIS_(n) ALOSDIS_(n) DLOSDIS_(n) REQEN_(n)
XXXX
0
XRT73LC03A
38
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
3.3 CLOCK RECOVERY PLL
The purpose of the Clock Recovery PLL is to track
the incoming Dual-Ra il data strea m and to derive and
generate a re co ver e d clock signal.
It is important to note that the Clock Recovery PLL re-
quires a line rate clock signal at the EXClk_(n) input
pin.
The Clock Recovery PLL operates in one of two
modes:
•The Training Mode.
•The Data/Clock Recovery Mode
3.3.1 The Training Mode
If a given channel is not re ceiving a line signal via the
RTIP and RRing input pins, or if the frequency differ-
ence between the line signal an d that applied via the
EXClk_(n) input pin exceeds 0.5%, then the channel
operates in the Training Mode. When the channel is
operating in the Training Mode, it does the following:
a. Declare a Loss of Lock indication by toggling its
respective RLOL_(n) output pin “High".
b. Output a clock signal via the RxClk_(n) output
pins which is derived from the signal applied to
the EXClk_(n) input pin.
3.3.2 The Data/Clock Recovery Mode
If the frequency difference between the line signal
and that applied via the EXClk_(n) input pin is less
than 0.5%, then the channel operates in the Data/
Clock Recovery mode. In this mode, the Clock Re-
covery PLL locks onto the line signal via the RTIP
and RRing input pins.
3.4 THE HDB3/B3ZS DECODER
The Remote Transmitting Terminal typically encodes
the line signal into some sort of Zero Suppression
Line Code (e.g., HDB3 for E3 , and B3ZS for DS3 and
STS-1). The purpose of this encoding activity was to
aid in the Clock Recovery process of this data within
the Near-End Receiving Terminal. However , once the
data h as made it a cross the E3 , DS3 or STS-1 Trans-
port Medium and has be en recovered by the Clock
Recovery PLL, it is now necessary to restore the orig-
inal content of the data. Hence, the purpose of the
HDB3/B3ZS Decoding block is to restore the data
transmitted over the E3, DS3 or STS-1 line to its orig-
inal content prior to Zero Suppression Coding.
3.4.1 B3ZS Decoding (DS3/STS-1 Applications)
If the XRT73LC03A is configured to op er a te in the
DS3 or STS-1 Modes, then the HDB3/B3ZS Decod-
ing Blocks performs B3ZS Decoding. When the De-
coders are operating in this mode, each of the De-
coders parses through its respective incoming Dual-
Rail data and checks for the occurrence of either a
“00V" or a "B0V" pattern. If the B3ZS Decoder de-
tects this particular pattern, then it substitutes these
bits with a "000" pattern.
NOTE: If the B3ZS Decoder detects any bipolar violations
that is not in accordance with the B3ZS Line Code format,
or if the B3ZS Decoder detects a string of 3 (or more) con-
secutive "0’s” in the incoming line signal, then the B3ZS
Decoder flags this event as a Line Code Violation by puls-
ing the LCV output pin “High" .
Figure 24 illustrates the B3ZS Decoder at work with
two sepa rate Zero Supp ression patterns in th e incom-
ing Dual-Rail Data Stream.
3.4.2 HDB3 Decoding (E3 Applications)
If the XRT73LC03A is configured to operate in the E3
Mode, then each of the HDB3/B3ZS Decoding Blocks
performs HDB3 Decoding. When the Decoders are
operating in this mo de , the y ea ch parse thro ug h th e
incoming Dual-Rail dat a and check for the occurrence
of either a "000V" or a "B00V" pattern. If the HDB3
FIGURE 24. AN EXAMPLE OF B3ZS DECODING
Data 0 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1
RPOS
RNEG
0 0 V
Line Signal
B 0 V
RCLK
XRT73LC03A
39
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
Decoder detects this pa rticular pattern, then it substi-
tutes these bits with a “0000" pattern. Figure 25 illustrates the HDB3 Decoder at work with
two separate Zero Suppression pa tterns, in the in-
coming Dual-Rail Data Stream.
NOTE: If the HDB3 Decoder detects any bipolar violation
(e.g., "V") pulses that is not in accordance with the HDB3
Line Code format, or if the HDB3 Decoder detects a string
of 4 (or more) "0's" in the incoming line signal, then the
HDB3 Decoder flags this event as a Line Code Violation by
pulsing the LCV output pin “High".
3.4.3 Configuring the HDB3/B3ZS Decoder
The XRT73LC03A can enable or disable the HDB3/
B3ZS Decoder blocks by either of the following
means.
a. Operating in the HOST Mode
Enable the HDB3/B3ZS Decoder block of Channel(n)
by writing a "0" into the (SR/DR)_(n) bit-field within
Command Register CR3-(n), as illustrated below.
b. Operating in the Hardware Mode
To globally enable all HDB3/B3ZS Decoder blocks in
the XRT73LC03A, pull the ENDECDIS input pin
“Low". To globally disable all HDB3/B3ZS Decoder
blocks in the XR T73LC03A and configure the
XRT73LC03A to transmit and receive in an AMI for-
mat, pull the ENDECDIS input pin "High".
3.5 LOS DECLARATION/CLEARANCE
Each channel of the XRT73LC03A contains circuitry
that monitors the following two parameters associat-
ed with the incoming line signals.
1. The amplitude of the incoming line signal via the
RTIP and RRing inputs.
2. The number of pulses detected in the incoming
line signal within a certain amount of time.
If a given channel of the XRT73LC03A determines
that the incoming line signal is missing due to either
insufficient am plitude or a lack of pulses in the incom-
ing line signal, it declares a Loss of Signal (LOS) con-
dition. The channel declares the LOS condition by
toggling its respective RLOS_(n) output pin “High”
and by setting its corresponding RLOS_(n) bit field in
Command Register 0 or Command Register 8 to "1".
Conversely, if the channel determines that the incom-
ing line signal has been restored (e.g., there is suffi-
cient amplitude and pulses in the incoming line sig-
nal), it clears the LOS condition by toggling its re-
spective RLOS_(n) output pin "Low" and setting its
corresponding RLOS_(n) bit-field to "0".
In general, the LOS Declaration/Clearance scheme
that is employed in the XRT73LC03A is based upon
FIGURE 25. AN EXAMPLE OF HDB3 DECODING
Data 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1
0 0 0 V
Line Signal
B 0 0 V
RPOS
RNEG
RCLK
COMMAND REGISTER CR2-(n)
D4 D3 D2 D1 D0
Reserved ENDECDIS_(n) ALOSDIS_(n) DLOSDIS_(n) REQEN_(n)
X0X X 1
XRT73LC03A
40
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
ITU-T Recommendation G.775 for both E3 and DS3
applications.
3.5.1 The LOS Declaration/Clearance Criteria
for E3 Applications
When the XRT73LC03A is operating in the E3 Mode,
a given channel declares an LOS Condition if its re-
ceive line signal amplitude drops to -35dB or below.
Further, the channel clea rs the LOS Condition if it s re-
ceive line signal amplitude rises back to -15dB or
above. Figure 26 illustrates the signal levels at which
each channel of the XRT73LC03A declares and
clears LOS.
Timing Require ments associated with Declaring
and Clearing the LOS Indicator
The XRT73LC03A was designed to meet the ITU-T
G.775 specification timing requirements for declaring
and clearing the LOS indicator. In particular, a chan-
nel declares an LOS between 10 and 255 UI (or E3
bit-periods) after the actual time the LOS condition
occurred. Further, the channel clears the LOS indica-
tor within 10 to 255 UI after rest or at ion of the incom -
ing line signal. Figure 27 illustrates the LOS Declara-
tion and Clearance behavior in response to the Loss
of Signal event and then the restoration of the signal.
FIGURE 26. THE SIGNAL LEVELS THAT THE XRT73LC03A DECLARES AND CLEARS LOS
0 dB
-12 dB
-15dB
-35dB
Maximum Cable Loss for E3
LOS Signal Must be Declared
LOS Signal Must be Cleared
LOS Signal may be Cleared or Declared
XRT73LC03A
41
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
3.5.2 The LOS Declaration/Clearance Criteria
for DS3 and STS-1 Applic ations
When the XRT73LC03A is operating in the DS3 or
STS-1 Mode, then each channel declares and clears
LOS based upon the following two criteria.
•Analog LOS (ALOS) Decl aration/Clearance Crite-
ria
•Digital LOS (DLOS) Declaration/Clearance Crite-
ria
In the DS3 Mode, the LOS output (RLOS) is simply
the logical "OR" of the ALO S an d DLO S states .
1. The Analog LOS (ALOS) Declaration/Clearance
Criteria
A channel declares an Analog LOS (ALOS_(n)) Con-
dition if the amplitude of the incoming line signal
drops below a specific amplitude as defined by the
voltage at the LOSTHR input pin, and whether the
Receive Equalizer is enabled or not.
Table 5 presents the various voltage levels at the
LOSTHR input pin, the state of the Receive Equalizer
and the correspo nding ALOS (Analog LOS) threshold
amplitudes.
Declaring ALOS
A channel(n) d eclares ALOS_(n) whenever th e ampli-
tude of the receive line signal falls below the Signal
Level to Declare ALOS levels, as specified inTable 5.
Clearing ALOS_(n)
A channel(n) clear s ALOS_(n) whenever the ampli-
tude of the receiv e line sign al in cr ea se s above the
Signal Level to Clear ALOS levels, as specified in
Table 5.
There is approximately a 2dB hysteresis in the re-
ceived signal level that exists between d eclaring and
clearing ALOS_(n) in order to prevent chattering in
the RLOS_(n) output signal.
Monitoring the State of ALOS_(n)
FIGURE 27. THE BEHAVIOR OF THE LOS OUTPUT INDICATOR IN RESPONSE TO THE LOSS OF SIGNAL AND THE RES-
TORATION OF SIGNAL
Actual Occurrence
of LOS Condition Line Signal
is Restored
Time Range for
LOS Declaration
Time Range for
LOS Clearance
G.775
Compliance G.775
Compliance
0 UI
10 UI
0 UI
10 UI 255 UI255 UI
RTIP/
RRing
RLOS Output Pin
TABLE 5: THE ALOS (ANALOG LOS) DECLARE AND CLEAR THRESHOLDS FOR A GIVEN SETTING OF LOSTHR &
REQEN (DS3 AND STS-1 APPLICATIONS)
APPLICATION REQEN SETTING LOSTHR SETTING SIGNAL LEVEL TO
DECLARE ALOS SGNAL LEVEL TO CLEAR
ALOS
DS3 11<
22mV >90mV
01<
17mV >70mV
STS-1 11<
25mV >115mV
01<
20mV >90mV
XRT73LC03A
42
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
If the XRT73LC03A is operating in the HOST Mode,
the state of ALOS_(n) of Channel(n) can be polled or monitored by reading in the contents of Command
Register CR0. .
If the ALOS_(n) bit-field contains a "1", then the cor-
responding Channel(n) is currently declaring an
ALOS condition. Conversely, if the ALOS_(n) bit- field
contains a "0", then the channel is not currently de-
claring an ALOS condition.
Disabling the ALOS Detector
For debugging purposes, it may be useful to disable
the ALOS Detector. If the XRT73LC03A is operating
in the HOST Mode, disable the Channel(n) ALOS De-
tector by writing a "1" into the ALOSDIS_(n) bit-field
in Command Register CR2.
2. The Digital LOS (DLOS) Declaration/Clearance
Criteria
A given channel(n) declares a Digital LOS
(DLOS_(n)) condition if the XRT73LC03A detects
160±32 or more consecutive "0’s" in the incoming da-
ta.
The channel clears DLOS if it detects four consecu-
tive sets of 32 bit-periods, each of which contains at
least 10 "1’s" (e.g., average pulse density of greater
than 33%).
Monitoring the State of DLOS
If the XRT73LC03A is operating in the HOST Mode
the state of DLOS_(n) of Channel(n) can be polled or
monitored by reading in the contents of Command
Register CR0.
If the DLOS_(n) bit-field contains a “1”, then the cor-
responding channel(n) is currently declaring a DLOS
condition. Conversely, if the DLOS_(n) bit-field con-
tains a “0”, then the channel(n) is currently declaring
the DLOS condition.
Disabling the DLOS Detector
For debugging purposes, it is useful to disable the
DLOS_(n) detector. If the XRT73LC03A is operating
in the HOST Mode, the DLOS Detector can be dis-
abled by writing a “1” into the DLOSDIS_(n) bit-field in
Command Register CR2.
NOTE: Setting both the ALOSDIS_(n) and DLOSDIS_(n)
bit-fields to "1" disables LOS Declaration by Channel(n).
3.5.3 Muting the Recovered Da t a while the LOS
is being Declared
In some applications it is not desirable for a channel
within the E3/DS3/STS-1 LIU to recover data and
route it to the Receiving Terminal while the channel is
declaring an LOS condition. Consequently, the
XRT73LC03A includes an LOS Muting feature. This
feature, if enabled, causes a given channel to halt
transmission of the recovered data to the Receiving
Terminal while the LOS condition is "true". In this
case, the RPOS_(n) and RNEG_(n) output pins are
COMMAND REGISTER CR0-(n)
D4 D3 D2 D1 D0
RLOL_(n) RLOS_(n) ALOS_(n) DLOS_(n) DMO_(n)
Read Only Read Only Read Only Read Only Read Only
COMMAND REGISTER CR2-(n)
D4 D3 D2 D1 D0
Reserved ENDECDIS_(n) ALOSDIS_(n) DLOSDIS_(n) REQEN_(n)
XX1XX
COMMAND REGISTER CR0-(n)
D4 D3 D2 D1 D0
RLOL_(n) RLOS_(n) ALOS_(n) DLOS_(n) DMO_(n)
Read Only Read Only Read Only Read Only Read Only
COMMAND REGISTER CR2-(n)
D4 D3 D2 D1 D0
Reserved ENDECDIS_(n) ALOSDIS(n) DLOSDIS(n) REQEN(n)
XXX1X
XRT73LC03A
43
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
forced to "0". Once the LOS condition has been
cleared, then the channel(n) resumes normal trans-
mission of the recovered data to the Receiving Termi-
nal.
This feature is available whenever XRT73LC03A is
operating in the HOST Mode or Hardwar e Mode.
a. Operating in the Hardware Mode.
The Muting upon LOS feature is enabled by pulling
the LOSMUTEN outp ut pin “Hig h ". This en ab le s the
Muting upon LOS feature glob ally for all channels.
b. Operating in the HOST Mode.
The Muting upon LOS feature for each Channe l can
be enabled by writing a "1" into the LOSMUT_(n) bit-
field within Command Register 3.
NOTE: This step only enables the Muting upon LOS feature
within Channel(n).
3.6 ROUTING THE RECOVERED TIMING AND DATA
INFORMATION TO THE RECEIVING TERMINAL
EQUIPMENT
Each channel takes the Recovered Timing and Data
information, converts it into CMOS levels and routes
it to the Receiving Terminal Equipment via the
RPOS_(n), RNEG_(n) and RxClk_(n) output pins.
Each channel can deliver the recovered data and
clock information to the Receiving Terminal in either a
Single-Rail or Dual-Rail format.
3.6.1 Routing Dual-Rail Format Data to the
Receiving Terminal Equipment
Whenever a channel delivers Dual-Rail format to the
Terminal Equipment, it does so via the following sig-
nals.
•RPOS_(n)
•RNEG_(n)
•RxClk_(n)
Figure 28 illustrates the typical interface for the trans-
mission of data in a Dual-Rail Format from the Re-
ceive Section of a channel to the Rece iving Terminal
Equipment.
.
The manner that a given channel transmits Dual-Rail
data to the Receiving Terminal Equipment is de- scribed below and illustrated in Figure 29. Each
COMMAND REGISTER CR3-(n)
D4 D3 D2 D1 D0
(SR/DR)_(n) LOSMUT_(n) RxOFF_(n) RxClk_(n)INV Reserved
X1xxx
FIGURE 28. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT,
FROM THE RECEIVE SECTION OF THE XRT73LC03A TO THE RECEIVING TERMINAL EQUIPMENT
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
Exar E3/DS3/STS-1 LIU
Receive
Logic
Block
RxPOS
RxNEG
RxClk
RPOS
RNEG
RxClk
XRT73LC03A
44
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
channel(n) typically updates the da ta on the
RPOS_(n) and RNEG_(n) output pins on the rising
edge of RxClk_(n ).
RxClk_(n) is the Recovered Clock signal from the in-
coming Received line signal. As a result, these clock
signals are typically 34.368 MHz for E3 applications,
44.736 MHz for DS3 applications and 51.8 4 MHz for
SONET STS-1 applications.
In general, if a given channel received a positive -po-
larity pulse in the incoming line signal via the
RTIP_( n) and RRing_(n) input pins, then the channel
pulses its corresponding RPOS_(n) output pin “High".
Conversely, if the channel received a negative-polari-
ty pulse in the incoming line signal via the RTIP_(n)
and RRing_(n) in put pins, the n th e ch annel( n) pu lses
its corresponding RNEG_(n) output pin “High".
Inverting the Rx Clk _( n ) ou t puts
Each channel can invert the RxClk_(n) signals with
respect to the delivery of the RPOS_(n) and
RNEG_(n) output data to the Receiving Terminal
Equipment. This feature may be useful for those cus-
tomers whose Receiving Terminal Equipment logic
design is such that the RPOS_(n) and RNEG_(n) da-
ta must be sampled on the rising edge of RxClk_(n).
Figure 30 illustrates the behavior of the RPOS_(n),
RNEG_(n) and RxClk_(n) signals when the
RxClk_(n) signal has been inverted.
In the Hardware Mode:
Setting the RxClkINV pin “High” results in all chan-
nels of the XRT73LC03A to output the recovered dat a
on RPOS_(n) and RNEG_(n) on the falling edge of
RxClk_(n). Setting this pin “Low” results in the recov-
ered data on RPOS_(n) and RNEG_(n) to output on
the rising edge of RxClk_(n).
a. Operating in the HOST Mode In order to configure a channel(n) to invert the
RxClk_(n) output signal, the XRT73LC03A must be
operating in the HOST Mode.
FIGURE 29. HOW THE XRT73LC03A OUTPUTS DATA ON THE RPOS AND RNEG OUTPUT PINS
RxClk
RPOS
RNEG
FIGURE 30. THE BEHAVIOR OF THE RPOS, RNEG, AND RXCLK SIGNALS WHEN RXCLK IS INVERTED
RxClk
RPOS
RNEG
XRT73LC03A
45
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
To invert RxClk _( n) , ass oc iat ed with Cha n ne l(n ) ,
write a "1" into the RxClk_(n)INV bit-field within Com-
mand Register CR-3 .
b. Operating in the Hardware Mode
Setting the RxClkINV input pin “High" inverts all the
RxClk_(n) output signals.
3.6.2 Routing Single-Rail Format (Binary Data
Stream) data to the Receive Terminal Equipment
To route Single-Rail format data (e.g., a binary data
stream) from the Receive Section of a channel to the
Receiving Terminal Equipment, do the following.
a. Operating in the HOST Mode
To configure Channel(n) to output Single-Rail data to
the Terminal Equipment, write a "1" into the (SR/
DR)_(n) bit-field within Command Register CR3-(n).
The configured channel outputs Single-Rail data to
the Receiving Terminal Equipment via its correspond-
ing RPOS_(n) and RxClk_(n) output pins, as illustrat-
ed in Figure 31 and Figure 32.
b. Operating in the Hardware Mode
The XRT73LC03A is configure to output Dual-Rail
data from the Receive Sections of all channels by
pulling the (SR/DR) pin to GND.
The XRT73LC03A is configure to output Single-Rail
data from the Receive Sections of all channels by
pulling the (SR/DR) pin to VDD.
NOTE: When the XRT73LC03A is operating in the Hard-
ware Mode, the setting of the (SR/DR) input pin applies glo-
bally to all channels.
.
COMMAND REGISTER CR3-(n)
D4 D3 D2 D1 D0
(SR/DR)_(n) LOSMUT_(n) RxOFF_(n) RxClk_(n)INV Reserved
XXX 1 X
COMMAND REGISTER CR3-(n)
D4 D3 D2 D1 D0
(SR/DR)_(n) LOSMUT_(n) RxOFF_(n) RxClk_(n)INV Reserved
1XXX X
FIGURE 31. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A SINGLE-RAIL FORMAT
FROM THE RECEIVE SECTION OF THE XRT73LC03A TO THE RECEIVING TERMINAL EQUIPMENT
Terminal Equipment
(E3/DS3 or STS-1
Framer)
Exar E3/DS3/STS-1 LIU
Receive
Logic
Block
RxPOS
RxClk
RPOS
RxClk
XRT73LC03A
46
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
NOTE: The RNEG_(n) output pin is internally tied to Ground
whenever this feature is implemented.
3.7 SHUTTING OFF THE RECEIVE SECTION
The Receive Section of each channel in the
XRT73LC03A can be shut off. This feature may
come in handy in some redundant system designs.
Particularly, in those designs wher e th e Re ceiv e Ter-
mination within the Secondary LIU Line Card has
been switched-out and is not receiving any traffic in
parallel with the Primary Line Ca rd. I n th is cas e, ha v -
ing the LIU on the Secon dary Line Card co nsume the
normal amount of current is a waste of power. This
feature can perm it po we rin g do wn the Rece ive Sec-
tion of the LIU’s on the Secondary Line Card which
reduces their powe r cons um p tio n by ap p rox im at ely
80%
a. Operating in the Hardware Mode
Shut off the Receive Sections by pulling the RxOFF
input pin “High". Turn on the Receiver Sections by
pulling the RxOFF input pin to “Low".
b. Operating in the HOST Mode
Shut off the Receive Sections by writing a "1" into the
RxOFF bit-field within Co mmand Register CR3-(n).
T u rn on th e Receive Se ction of Channe l(n) by writing
a "0" into the RxOFF bit-field within Command Regis-
ter CR3-(n).
FIGURE 32. THE BEHAVIOR OF THE RPOS AND RXCLK OUTPUT SIGNALS WHILE THE XRT73LC03A IS TRANS-
MITTING SINGLE-RAIL DATA TO THE RECEIVING TERMINAL EQUIPMENT
RxClk
RPOS
COMMAND REGISTER CR3-(n)
D4 D3 D2 D1 D0
(SR/
DR)_(n) LOSMUT_(n) RxOFF_(n) RxClk_(n)INV Reserved
XX 1XX
XRT73LC03A
47
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
4.0 DIAGNOSTIC FEATURES OF THE
XRT73LC03A
The XRT73LC03A suppo rts equipment diagnostic ac-
tivities by supporting the following Loop-Back modes
within each channel.
•Analog Local Loop-Back.
•Digital Local Loop-Back
•Remote Loop-Back
NOTE: In this data sheet we use the convention that Chan-
nel(n) refers to either channel 0, 1 or 2. Similarly, specific
input and output pins uses this convention to denote which
channel it is associated with.
4.1 THE ANALOG LOCAL LOOP-BACK MODE
When a given channel is configured to operate in the
Analog Local Loop-Back Mode, the channel ignores
any signals that are input to its RTIP_(n) and
RRing_(n) input pins. The Transmitting Terminal
Equipment transmits clock and data into this channel
via the TPData_(n ), TNData_(n) and TxClk_(n) input
pins. This data is processed through the Transmit
Clock Duty Cycle Adjust PLL and the HDB3/B3ZS
Encoder. Finally, this data is output to the line via the
TTIP_(n) and TRing_(n) output pins. Additionally , this
data which is being output via the TTIP_(n) and
TRing_(n) outp u t pins is also looped back into the At-
tenuator/Receive Equalizer Block. Consequently , this
data is processe d through the entir e Receive Section
of the channel. After this post-Loop-Back data has
been proces se d thr o ug h th e Rec eive Section it out-
puts to the Near-End Receiving Terminal Equipment
via the RPOS_(n), RNEG_(n) and RxClk_(n) output
pins.
Figure 33 illustrates the path that the data t akes when
the channel is configured to operate in the Analog Lo-
cal Loop-Back Mode.
Configure a give n ch an ne l to op er at e in th e Ana l og
Local Loop-Back Mode by employin g either one of
the following two steps
a. Operating in the HOST Mode
NOTE: See for a description of Command Registers and
Addresses for the different channels.
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, write a “1" into the LL B_(n) bit-
field and a "0" into the RLB_(n) bit-field within Com-
mand Register CR4.
FIGURE 33. A CHANNEL OPERATING IN THE ANALOG LOCAL LOOP-BACK MODE
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
Notes: 1. (n) = 0, 1 or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in
Hardware Mode.
RLOL_(n) EXClk_(n)
Device
Monitor
MTIP_(n)
MRing_(n)
Transmit
Logic Duty Cycle Adjust
TxLEV_(n)
TxOFF_(n)
DMO_(n)
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface Analog Local
Loop-Back Path
XRT73LC03A
48
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
b. Operating in the Hardware Mode
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, set the LLB_(n) input pin “High"
and the RLB_(n) input pin "Low".
4.2 THE DIGITAL LOCAL LOOP-BACK MODE.
When a given channel is configured to operate in the
Digital Local Loop-Back Mode, the channel ignores
any signals that are input to the RTIP and RRing in-
put pins. The Transmitting Terminal Equipment trans-
mits clock and data into the XRT73LC03A via the TP-
Data, TNData and TxClk input pins. This data is pro-
cessed through the T ransmit Clock Duty Cycle Adjust
PLL and the HDB3/B3Z S Encode r block . At this
point, this data is looped back to the HDB3/B3ZS De-
coder block. After this post-Loop-Back dat a has been
processed through the HDB3/B3ZS Decoder block, it
outputs to the Near-End Receiving Terminal Equip-
ment via the RPOS, RNEG and RxClk output pins.
Figure 34 illustrates the path that the data t akes when
the chip is configured to operate in the Digital Local
Loop-Back Mode.
Configure a channel to operate in the Digital Local
Loop-Back Mode by employing either one of the fol-
lowing two-steps:
a. Operating in the Host Mode
To configure Channel (n) to operate in the Digital Lo-
cal Loop-Back Mode, write a "1" into both the LLB
and RLB bit-fiel ds within Command Reg ister CR4-(n).
b. Operating in the Hardware Mode.
COMMAND REGISTER CR4-(n)
D4 D3 D2 D1 D0
XSTS-1/DS3
_(n) E3_(n) LLB_(n) RLB_(n)
XX X
1 0
FIGURE 34. THE DIGITAL LOCAL LOOP-BACK PATH WITHIN A GIVEN CHANNEL
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV(_n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData(_n)
TNData_(n)
TxClk_(n)
Notes: 1. (n) = 0, 1 or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in
Hardware Mode.
RLOL_(n) EXClk_(n)
Device
Monitor
MTIP_(n)
MRing(_n)
Transmit
Logic Duty Cycle Adjust
TxLEV_(n)
TxOFF_(n)
DMO_(n)
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Digital Local
Loop-Back Path
COMMAND REGISTER CR4-(n)
D4 D3 D2 D1 D0
XSTS-1/DS3
_(n) E3_(n) LLB_(n) RLB_(n)
XX X
1 1
XRT73LC03A
49
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
To configure Channel (n) to operate in the Digital Lo-
cal Loop-Back Mode, pull both the LLB input pin and
the RLB input pin "High".
4.3 THE REMOTE LOOP-BACK MODE
When a given channel is configured to operate in the
Remote Loop-Back Mode, the channel ignores any
signals that are input to the TPData and TNDat a input
pins. The channel receives the incoming line signal
via the RTIP and RRing input pins. This data is pro-
cessed through the entire Receive Section and is ou t-
put to the Receive Terminal Equipment via the RPOS,
RNEG and RxClk outpu t pins. Addit ion ally, this data
is also internally looped back into the Pulse-Shaping
block within the Transmit Section. At this point, this
data is routed through the remainder of the Transmit
Section of the channel and transmitted out onto the
line via the TTIP_(n) and TRing_(n) output pins.
Figure 35 illustrates the path that the data t akes when
the chip is configur ed t o oper ate in the Remote Loo p-
Back Mode.
Configure a channel to operate in the Remote Loop-
Back Mode by employing either one of the following
two steps
a. Operating in the HOST Mode
To configure Channel (n) to operate in the Remote
Loop-Back Mo de , writ e a "1" int o the RLB bit -fiel d ,
and a "0" into the LLB bit-field, within Command Reg-
ister CR4. b. Operating in the Hardware Mode
To configure Channel(n) to operate in the Remote
Loop-Back Mode, pull both the RLB_(n) input pin to
“High" and the LLB_(n) input pin to "Low".
FIGURE 35. THE REMOTE LOOP-BACK PATH, WITHIN A GIVEN CHANNEL
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
Notes: 1. (n) = 0, 1 or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in
Hardware Mode.
RLOL_(n) EXClk_(n)
Device
Monitor
MTIP_(n)
MRing_(n)
Transmit
Logic Duty Cycle Adjust
TxLEV_(n)
TxOFF_(n)
DMO_(n)
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Remote
Loop-Back Path
COMMAND REGISTER CR4-(n)
D4 D3 D2 D1 D0
XSTS-1/DS3
_(n) E3_(n) LLB_(n) RLB_(n)
XX X
0 1
XRT73LC03A
50
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
4.4 TXOFF FEATURES
The Transmit Section of each Channel in the
XRT73LC03A can be shut off. When this feature is
invoked, the Transmit Section of the configu red ch an -
nel is shut-off and the Transmit Output signals (e.g.,
TTIP_(n) and TRing_(n)) is tri-stated. This feature is
useful for system redundancy conditions or during di-
agnostic testing.
a. Operating in the Hardware Mode
Shut off the Transmit Driver concurrently within all
Channels by toggling the TxOFF input pin “High".
Turn on the Tr ansmit Driver by toggl ing the TxOFF in-
put pin “Low".
b. Operating in the HOST Mode
Turn off the Transmit Driver within Channel(n) by set-
ting the TxOFF_(n) b it-field within Command Regi ster
CR1-(n) to "1".
Writing a "0" into this bit-field enables the Chan-
nel(n)Transmit Driv er.
NOTE: In order to permit a system designed for redundancy
to quickly shut-off a defective line card and turn-on the
back-up line card, the XRT73LC03A was designed such
that either Tran smitter can quickly be turned-on or turned-
off by toggling the TxOFF input pins. This approach is
much quicker then setting the TxOFF_(n) bit-fields via the
Microprocess or Serial Interface.
Table 6 presents a Truth Table which relates the set-
ting of the TxOFF external pin a nd bit- field for a chan-
nel to the state of the Transmitter. This table applies
to all Channels of the XRT73LC03A.
To control the state of all transm itters via the Micro-
processor Serial interface, connect the TxOFF input
pin to GND.
4.5 THE TRANSMIT DRIVE MONITOR FEATURES
The T ransmit Drive Mon itor is used to monitor the line
in the Tr an sm it Dire ctio n for th e occ ur re n ce of fau lt
conditions such as a short circuit on the line, a defec-
tive Transmit Drive in the XRT73LC03A or another
LIU.
Activate the Chan ne l(n ) Transmit Drive Monitor by
connecting the MTIP_(n) pin to the TTIP_(n) line
through a 270 Ohm resistor con nected in series, and
connecting the MRing_(n) pin to the TRing_(n) line
through a 270 Ohm resistor connected in series.
Such an approach is illustrated in Figure 36.
COMMAND REGISTER CR1-(n)
D4 D3 D2 D1 D0
TxOFF_(n) TAOS_(n
)TxClkINV_(n) TxLEV_(n) TxBIN_(n)
1X X XX
TABLE 6: THE RELATIONSHIP BETWEEN THE TXOFF INPUT PIN, THE TXOFF BIT FIELD AND THE STATE OF THE
TRANSMITTER
STATE OF THE TXOFF
INPUT PIN STATE OF THE TXOFF
BIT FIELD STATE OF THE TRANSMITTER
LOW 0 ON (Transmitter is Active)
LOW 1 OFF (Transmitter is Tri-Stated)
HIGH 0 OFF (Transmitter is Tri-Stated)
HIGH 1 OFF (Transmitter is Tri-Stated)
XRT73LC03A
51
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
When the Transmit Drive Monitor circuitry within a
given line is connected to the line, as illustrated in
Figure 36, then it monitors the line for transitions. As
long as the Transmit Drive Monitor circuitry detects
transitions on the line via the MTIP_(n) and
MRing_(n) pins, then it keeps the DMO (Drive Moni-
tor Output) signal "Low". However, if the Transmit
Drive Monitor circuit detects no transitions on the line
for 128+32 TxClk periods, then the DMO (Drive Mon i-
tor Output) signal toggles "High".
NOTE: The Transmit Drive Monitor circuit does not have to
be used to operate the Transmit Section of the
XRT73LC03A. This is purely a diagnostic feature.
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE
The XRT73LC03A can command any channel to
transmit an all “1’ s " p atter n onto the line b y toggling a
single input pin or by setting a single bit-field within
one of the Command Registe rs to "1".
NOTE: When this feature is activated, the Transmit Section
of the configured channel overwrites the Terminal Equip-
ment data with this all “1’s" pattern.
a. Operating in the Hardware Mode
Configure Channel(n) to transmit an all “1’s " pattern
by toggling the TAOS_(n) input pin “High". Terminate
the all “1’s" pattern by toggling the T AOS_(n) input pin
“Low".
b. Operating in the HOST Mode
Configure Channel(n) to transmit an all “1’s" pattern
by writing to Command Register CR 1- (n ) an d se ttin g
the TAOS_(n) bit-field (bit D3) to "1".
Terminate the all “1’s" pattern by writing to Command
Register CR1-(n) and setting the TAOS_(n) bit-field
(D3) to "0".
5.0 THE MICROPROCESSOR SERIAL INTER-
FACE
The on-chip Command Re gisters of XRT7 3LC03A
DS3/E3/STS-1 Line Interface Unit IC are used to con-
figure the XRT73LC03A into a wide-variety of modes.
This section discusses the following:
1. The description of the Command Registers.
2. A description on how to use the Microprocessor
Serial Interface.
5.1 DESCRIPTION OF THE COMMAND REGISTERS
(repeated as Table 7), lists the Command Registers,
their Addresses and their bit-formats.
FIGURE 36. THE XRT73LC03A EMPLOYING THE TRANSMIT DRIVE MONITOR FEATURES
R1 = 31.6
R2 = 31.6
Channel (n)
TxPOS_(n)
TxNEG_(n)
TxLineClk_(n)
TTIP_(n)
TRing_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
Only One Channel Shown
1:1
J1
BNC
MTIP_(n)
MRing_(n)
R3 = 270
R4 = 270
COMMAND REGISTER CR1-(n)
D4 D3 D2 D1 D0
TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n)
01XXX
XRT73LC03A
52
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
Address
The register add resse s are presente d in th e Hexa-
decimal format.
Type:
The Command Regis te rs ar e eit he r Re ad -O nly (R O)
type of registers or Read/Write (R/W) typ e of regis-
ters. Each channel of the XRT73LC03A has eight
command registers, CR0-(n) through CR7-(n) where
TABLE 7: HEXADECIMAL ADDRESSES AND BIT FORMATS OF XRT73LC03A COMMAND REGISTERS
REGISTER BIT-FORMAT
ADDRESS COMMAND
REGISTER TYPE D4 D3 D2 D1 D0
CHANNEL0
0x00 CR0-0 RO RLOL_0 RLOS_0 ALOS_0 DLOS_0 DMO_0
0x01 CR1-0 R/W TxOFF_0 TAOS_0 TxClkINV_0 TxLEV_0 TxBIN_0
0x02 CR2-0 R/W Reserved ENDECDIS_0 ALOSDIS_0 DLOSDIS_0 REQEN_0
0x03 CR3-0 R/W SR/(DR)_0 LOSMUT_0 RxOFF_0 RxClk_0INV Reserved
0x04 CR4-0 R/W Reserved STS-1/DS3_0 E3_0 LLB_0 RLB_0
0x05 CR5-0 R/W Reserved Reserved Reserved Reserved Reserved
0x06 CR6-0 R/W Reserved Reserved Reserved Reserved Reserved
0x07 CR7-0 R/W Reserved Reserved Reserved Reserved Reserved
CHANNEL1
0x08 CR0-1 RO RLOL_1 RLOS_1 ALOS_1 DLOS_1 DMO_1
0x09 CR1-1 R/W TxOFF_1 TAOS_1 TxClkINV_1 TxLEV_1 TxBIN_1
0x0A CR2-1 R/W Reserved ENDECDIS_1 ALOSDIS_1 DLOSDIS_1 REQEN_1
0x0B CR3-1 R/W SR/(DR)_1 LOSMUT_1 RxOFF_1 RxClk_1INV Reserved
0x0C CR4-1 R/W Reserved STS-1/DS3_1 E3_1 LLB_1 RLB_1
0x0D CR5-1 R/W Reserved Reserved Reserved Reserved Reserved
0x0E CR6-1 R/W Reserved Reserved Reserved Reserved Reserved
0x0F CR7-1 R/W Reserved Reserved Reserved Reserved Reserved
CHANNEL2
0x10 CR0-2 RO RLOL_2 RLOS_2 ALOS_2 DLOS_2 DMO_2
0x11 CR1-2 R/W TxOFF_2 TAOS_2 TxClkINV_2 TxLEV_2 TxBIN_2
0x12 CR2-2 R/W Reserved ENDECDIS_2 ALOSDIS_2 DLOSDIS_2 REQEN_2
0x13 CR3-2 R/W SR/(DR)_2 LOSMUT_2 RxOFF_2 RxClk_2INV Reserved
0x14 CR4-2 R/W Reserved STS-1/DS3_2 E3_2 LLB_2 RLB_2
0x15 CR5-2 R/W Reserved Reserved Reserved Reserved Reserved
0x16 CR6-2 R/W Reserved Reserved Reserved Reserved Reserved
0x17 CR7-2 R/W Reserved Reserved Reserved Reserved Reserved
XRT73LC03A
53
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
(n) = 0, 1 or 2. The associated addresses for each
channel are presented in , (repeated as Table 7).
NOTE: The default value for each of the bit-fields within
these register is "0".
5.2 DESCRIPTION OF BIT-FIELDS FOR EACH COM-
MAND REGISTER
5.2.1 Command Register - CR0-(n)
The bit-format and default values for Command Reg-
ister CR0-(n) are listed below followed by the function
of eah of these bit-fields.
Bit D4 - RLOL_(n) (Receive Loss of Lock Status -
Channel(n))
This Read-Only bit-field reflect s the lock status of the
Channel(n) Clock Recovery Phase-Locked-Loop
This bit-field is set to “0” if the Channel(n) Clock Re-
covery PLL is in lock with the incoming line signal.
This bit-field is se t to "1" if the Clock Recovery PLL is
out of lock with the incoming line signal.
Bit D3 - RLOS_(n) (Receiv e Loss of Signal St atus -
Channel(n))
This Read-Only bit-field indicates whether or not the
Channel(n) of the Receiver is currently declaring an
LOS (Loss of Signal) Condition.
This bit-field is set to "0" if Channel(n) is not currently
declaring the LOS Condition.
This bit-field is set to "1" if Channel(n) is declaring an
LOS Condition.
Bit D2 - ALOS_(n) (Analog L oss of Sign al Status -
Channel(n))
This Read-Only bit-field indicates whether or not the
Channel(n) Analog LOS Detector is currently declar-
ing an LOS condition.
This bit-field is set to "0" if the Analog LOS Detector
within Channel(n) is NOT curren tly decla rin g an LO S
condition. This bit-field is set to "1" if the Analog LOS
Detector is currently declaring an LOS condition.
NOTE: The purpose is to isolate the Detector (e.g., either
the Analog LOS or the Digital LOS detector) that is declar-
ing the LOS condition. This feature may be useful for trou-
bleshooting/debugging purpo ses
Bit D1 - DLOS_(n) (Digital Loss of Signal Status -
Channel(n))
This Read-Only bit-field indicates whether or not the
Channel(n) Digital LOS Detector is currently declar-
ing an LOS condition.
This bit-fiel d is set to "0" if the Channel(n) Digital LOS
Detector is NOT currently declaring an LOS condi-
tion. This bit-field is set to "1" if the Channel(n) Digit al
LOS Detector is currently d eclaring an LOS conditio n.
NOTE: The purpos e is to isolate the Detector (e.g., either
the Analog LOS or the Digital LOS detector) that is declar-
ing the LOS condition. This feature may be useful for trou-
bleshooting/debugging purposes.
Bit D0 - DMO_(n) (Drive Monitor Output Status -
Channel(n))
This Read-Only bit-field reflects the status of the
DMO output pin.
5.2.2 Command Register CR1
The bit-format and default values for Command Reg-
ister CR1-(n) are listed below followed by the function
of each of these bit-fields..
Bit D4 - TxOFF_(n) (Transmitter OFF - Channel(n))
This Read/Write bit-field is used to turn off the Chan-
nel(n) Transmitter.
Writing a "1" to this bit field turns off the Transmitter
and tri-state the Transmit Output. W riting a "0" to this
bit-field turns on the Transmitter.
Bit D3 - TAOS_(n) (Transmit All OneS - Chan-
nel(n))
This Read/Write bit-field is used to command the
Channel(n) Transmitter to generate and transmit an
all “1’s” pattern onto the line.
Writing a "1" to this bit-field commands the Transmit-
ter to transmit an all “1’s” pattern onto the line. Writ-
ing a "0" to this bit-field commands normal operation.
Bit D2 - TxClkINV_(n) (Transmit Clock Invert -
Channel(n))
This Read/Write bit-field is used to configure the
Transmitter to sample the signal at the TPData a nd
TNData pins on the rising edge or falling edge of Tx-
Clk (the Transmit Line Clock signal).
Writing a "1" to this bit-field configures the T ransmitter
to sample the TPDat a and TNData input pins on the
rising edge of TxClk. Writing a “0" to this bit-fie ld con-
COMMAND REGISTER CR0-(n)
D4 D3 D2 D1 D0
RLOL_(n) RLOS_(n) ALOS_(n) DLOS_(n) DMO_(n)
11111
COMMAND REGISTER CR1-(n)
D4 D3 D2 D1 D0
TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n)
00 0 00
XRT73LC03A
54
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
figures the Transmitter to sample the TPDa ta and
TNData input pins on the falling edge of TxClk.
Bit D1 - TxLEV_(n) (Transmit Line Build-Out En-
able/Disable Select - Channel(n))
This Read/Write bit-field is used to enable or disable
the Channel(n) Transmit Line Build-Out circuit.
Setting this bit-field "High" disables the Channel(n)
Line Build-Out circuit. In this mode, Channel(n) out-
puts partially-shaped pulses onto the line via the
TTIP_(n) and TRing_(n) output pins.
Setting this bit-field "Low" enables the Channel(n)
Line Build-Out circuit. In this mode, Channel(n) out-
puts shaped pulses onto the line via the TTIP_(n) and
TRing_(n) output pins.
In order to comply with the Isolated DSX-3/STSX-1
Pulse Template Requiremnts per Bellcore GR-499-
CORE or GR-253-CORE:
a. Set this bit-field to "1" if the cable length between
the Cross-Connect and the transmit output of Chan-
nel(n) is greater than 225 feet.
b. Set this bit-field to "0" if the cable length between
the Cross-Connect and the transmit output of Chan-
nel(n) is less than 225 fe et .
This bit-field is active only if the XRT73LC03A is con-
figured to operate in the DS3 or SONET STS- 1
Modes.
If the cable length is greater than 225 feet, set this bit-
field to "1" in order to increase the amplitude of the
Transmit Output Signal. If the cable length is less
than 225 feet, set this bit-field to "0".
NOTE: This option is only available when the XRT73LC03A
is operating in the DS3 or STS-1 Mode.
5.2.3 Command Register CR2-(n)
The bit-format and default values for Command Reg-
ister CR2-(n) are listed below followed by the function
of each of these bit fields.
Bit D4 - Reserved
Bit D3 - Reserved
Bit D2 - ALOSDIS (Analog LOS Disable - Chan-
nel(n))
This Read/Write bit-field is used to enable or disable
the Channel(n) Analo g LO S Det ec tor.
Writing a "0" to this bit-field enables the Analog LOS
Detector. Writing a "1" to this bit-field disables the
Analog LOS Detector.
NOTE: If the Analog LOS Detector is disabled, then the
RLOS input pin is only asserted by the DLOS (Digital LOS
Detector).
Bit D1 - DLOSDIS_(n) (Digital LOS Disable - Chan-
nel(n))
This Read/Write bit-field to used to enable or disable
the Channel(n) Digital LOS Detector .
Writing a "0" to this bit-field enables the Digital LOS
Detector. Writing a "1" to this bit-field disables the
Digital LOS Detector.
NOTE: If the Digital LOS Detector is disabled, then the
RLOS input pin is only asserted by the ALOS (Analog LOS
Detector).
Bit D0 - REQEN_(n) (Receive Equalization Enable
- Channel(n))
This Read/Write bit-field is used to enable or disable
the internal Channel(n) Receive Equalizer.
Writing a "1" to this bit-field enables the Internal
Equalizer. Writing a "0" to this bit-field disables the
Internal Equalizer.
5.2.4 Command Register CR3-(n)
The bit-format and default values for Command Reg-
ister CR3-(n) are listed below followed by the function
of each of these bit fields.
COMMAND REGISTER CR2-(n)
D4 D3 D2 D1 D0
Reserved ENDECDIS_(n) ALOSDIS_(n) DLOSDIS_(n) REQEN_(n)
X0000
COMMAND REGISTER CR3-(n)
D4 D3 D2 D1 D0
SR/DR_(n) LOSMUT_(n) RxOFF_(n) RxClk_(n)INV Reserved
0 000 0
XRT73LC03A
55
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
Bit D4 - SR/DR_(n) (Single-Rail/Dual-Rail Data
Output - Channel(n))/(B3ZS/HDB3 Encoder/De-
coder-Disable - Channel(n))
This Read/Write bit-fiel d is used to configure Chan-
nel(n) to output the received data from the Remote
Terminal in a binary or Dua l-Rail format and Enable or
Disable the B3ZS/HDB3 Encoder and Decoder
blocks.
Writing a "1" to this bit-field enables the B3ZS/HDB3
Encoder and Decoder blocks. Writing a "0" to this bit-
field disables the B3ZS/HDB3 Encoder and Decoder
blocks.
NOTE: This Encoder/Decoder performs HDB3 Encoding/
Decoding if the XRT73LC03A is operating in the E3 Mode.
Otherwise, it performs B3ZS Encoding/Decoding.
.Writing a "1" to this bit-field also configures Chan-
nel(n) to output data to the Terminal Equipment in a
binary (Single-Rail) format via the RPOS_(n) output
pin, RNEG_(n) is grounded. Writing a "0" to this bit-
field configures Channel(n) to output data to the Ter-
minal Equipment in a Dual-Rail format via both the
RPOS_(n) and RNEG_(n) output pins.
Bit D3 - LOSMUT_(n) (Recovered Data Muting,
during LOS Condition - Channel(n))
This Read/Write bit-fiel d is used to configure Chan-
nel(n) to not output any recovered data from the line
while it is declaring an LOS condition.
Writing a "0 " to th is bit-fie ld co nfigur es th e ch ip to ou t-
put recovered da ta even while the XRT73LC03A is
declaring an LOS condition. Writing a "1" to this bit-
field configures the ch ip to NOT outpu t the r ecovered
data while an LOS condition is being declared.
NOTE: In this mode, RPOS_(n) and RNEG_(n) is set to "0",
asynchronously.
Bit D2 - RxOFF (Receive Section - Shut OFF Se-
lect)
This Read/Write bit-field is used to shut-off the Re-
ceive Sections. The purpose is to conserve power
consumption when this device is the back-up device
in a Redundancy Syste m .
Writing a "1" into this bit-field shuts off the Receive
Sections. Writing a "0" into this bit-field turns on the
Receive Sections.
Bit D1 - RxClk_(n)INV (Invert RxClk_(n))
This Read/Write bit-fiel d is used to configure the
Channel(n) Receiver to output the recovered data on
either the rising edge or the falling edge of the
RxClk_(n) clock signal.
Writing a "0 " to this bit-field configures the Receiver to
output the recovered data on the rising edge of the
RxClk_(n) output signal. Writing a "1" to this bit-field
configures th e Rec eiv er to ou tpu t th e re co ver e d da ta
on the falling edge of the RxClk_(n) output signal.
Bit D0 - Reserved
This bit-field has no defined functionality
Command Register CR4-(n)
The bit-format and default values for Command Reg-
ister CR4 are listed below followed by the function of
each of these bit-fields.
Bit D4 - Reserved
This bit-field has no defined functionality
Bit D3 - STS-1/(DS3_(n)) - Channel(n) - Mode Se-
lect
This Read/Write bit field is used to configure Chan-
nel(n) to operate in either the SONET STS-1 Mode or
the DS3 Mode.
Writing a "0" into this bit-field configures Channel(n)
to operate in the DS3 Mode. Writing a "1" into this bit-
field configures Channel(n) to operate in the SONET
STS-1 Mode.
NOTE: This bit-field is ignored if the E3_(n) bit-field (e.g.,
D2 within this Command Register) is set to "1".
Bit D2 - E3 Mode Select - Channel(n)
This Read/Write bit-field is used to configure Chan-
nel(n) to operate in the E3 Mode.
Writing a "0" into this bit-field configures Channel(n)
to operate in either the DS3 or SONET STS-1 Mode
as specified by the setting of the DS3 bit-field within
this Command Register. Writing a "1" into this bit-
field configures Channel(n) to operate in the E3
Mode.
Bit D1 - LLB_(n) (Local Loop-Back - Channel(n))
This Read/Write bit-field along with RLB_(n) is used
to configure Channel(n ) to operate in any o ne of a va-
riety of Loop-Back modes.
Table 8 relates the contents of LLB_(n) and RLB_(n)
and the corresponding Loop-Back mode for Chan-
nel(n).
Bit D0 - RLB_(n) (Remote Loop-Back - Chan-
nel(n))
COMMAND REGISTER CR4-(n)
D4 D3 D2 D1 D0
Reserved STS-1/DS3_(n) E3_(n) LLB_(n) RLB_(n)
00000
XRT73LC03A
56
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
This Read/Write bit-field, along with LLB_(n), is used
to configure Channel(n ) to opera te in a ny one of a va-
riety of Loop-Back modes.
Table 8 relates the contents of LLB_(n) and RLB_(n)
and the corresponding Loop-Back mode for Chan-
nel(n).
5.3 OPERATING THE MICROPROCESSOR SERIAL
INTERFACE.
The XRT73LC03A Serial Interface is a simple four
wire interface th at is com patible with many of the mi-
crocontrollers available in the market. This interface
consists of the following signals:
•CS - Chip Select (Active Low)
•SClk - Serial Clock
•SDI - Serial Data Input
•SDO - Serial Data Output
Using the Microprocessor Serial Interfa ce
The following instructions for using the Microproces-
sor Serial Interface are best understood by referring
to the diagram in Figure 37 and the timi ng diagr am in
Figure 38.
In order to use the Microprocessor Serial Interface, a
clock signal must be first applied to the SClk input
pin. Then, initiate a Read or Write operation by as-
serting the active-low Chip Select input pin CS. It is
important to assert the CS pin (e.g., toggle it “Low") at
least 5ns prior to the ver y first rising edge of the clock
signal.
Once the CS input pin has been asserted, the type of
operation an d th e target re gis ter add r ess must now
be specified. Provide this information to the Micro-
processor Serial Interface by writing eight serial bits
of data into the SDI input.
NOTE: Each of these bits is clocked into the SDI input on
the rising edge of SClk.
Bit 1 - R/W (Read/Write) Bit
This bit is clocked into the SDI input, on the first rising
edge of SClk after CS has been asserted. This bit in-
dicates whether the current operation is a Read or
Write operation. A "1" in this bit specifies a Read op-
eration, a "0" in this bit spe cif ies a Write opera tion .
Bits 2 through 6: The five (5) bit Address Values
(labeled A0, A1, A2 , A3 and A4)
The next five rising edges of the SClk signal clocks in
the 5-bit address value for this particular Read or
Write operation. The address selects the Command
Register in the XRT73LC03A that the user is either
reading dat a from or writing data to. The addre ss bits
must be supplied to the SDI input p in in asce nding o r-
der with the LSB (least significant bit) first.
Bit 7:
A5 must be set to "0", as shown in Figure 37.
Bit 8 - A6
The value of A6 is a don't care.
Once these first 8 bits have been written into the Mi-
croprocessor Serial Interface, the subsequent action
depends upon whether the curre nt operation is a
Read or Write operation.
Read Operation
Once the last address bit (A4) has been clocked into
the SDI input, the Read operation proceeds through
an idle period lasting two SClk periods. On the falling
edge of SClk Cycle #8 (see Figure 37) the serial dat a
output signal (SDO) becomes active. At this point,
reading the data conten ts of the addr e sse d Co m-
mand Register at Address [A4, A3, A2, A1, A0] via
the SDO output pin can begin. The Micr oprocessor
Serial Interface outputs this five bit data word (D0
through D4) in ascending order with the LSB first on
the falling edges of the SClk pin. Consequently, the
data on the SDO output pin is sufficiently stable for
reading by the Micro processor on the very next rising
edge of the SClk pin.
Write Operation
Once the last address bit (A4) has been clocked into
the SDI input, the Write operation proceeds through
an idle period lasting two SClk periods. Prior to the
rising edge of SClk Cycle # 9 (see Figure 37). Apply
TABLE 8: CONTENTS OF LLB_(n) AND RLB_(n) AND THE CORRESPONDING LOOP-BACK MODE FOR CHANNEL(n)
LLB_(n) RLB_(n) LOOP-BACK MODE (FOR CHANNEL(n))
00 None
1 0 Analog Loop-Back Mode (See Section 4.1 for details)
1 1 Digital Loop-Back Mode (See Section 4.2 for details)
0 1 Remote Loop-Back Mode (See Section 4.3 for details)
XRT73LC03A
57
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
the desired eight b it data wor d to the SDI input pin via
the Microprocessor Serial Interface. The Micropro-
cessor Serial Interface latches the value on the SDI
input pin on the rising edge of SClk. Apply this word
(D0 through D7) serially, in ascending order with the
LSB first.
Simplified Interface Option
The design of the circuitry connecting to the Micro -
processor Serial Interface can be simplified by tying
both the SDO and SDI pins together and reading dat a
from and/or writing dat a to this combined signal. This
simplification is possib le be ca us e on ly on e of th es e
signals are active at any given time. The inactive sig-
nal is tri-stated.
NOTES:
1. A5 is always "0"
2. R/W = "1" for Read Operations
3. R/W = "0" for Write Operations
4. Shaded box denotes a “don't care” value
FIGURE 37. MICROPROCESSOR SERIAL INTERFACE DATA S TRUCTURE
FIGURE 38. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
D0 D1 D2 000D4D3
High Z
SDO
A0 D0R/W D1A60A4A3A2A1 D7D6D5D4D3D2
SDI
12345678910111213141516
SClk
CS
High Z
SDI R/W A1
A0
CS
SCLK
CS
SCLK
SDI
SDO D0 D1 D2 D7
t22
t21
t23 t24
t25 t26
t27 t28
t29
t30 t31 t32t33
Hi-Z
Hi-Z
XRT73LC03A
58
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4
ORDERING INFORMATION
PACKAGE DIMENSIONS
PART #PACKAGE OPERATING TEMPERATURE RANGE
XRT73LC03AIV 120 Pin LQFP 14mm X 20mm -40oC to +85oC
THERMAL INFORMATION Theta-JA = 22.2°C/W Theta-JC =4.0°C/W
Note: The con tr ol di mensi on is t he mill imete r c olumn
120 LEAD QUAD FLAT PACK
14mm X 20 mm, LQFP
Rev. 1.00
eB
136
37
60
6196
97
120
A2
A
A1
L
C
E1 E
D
D1
MIN MAX MIN MAX
A 0.055 0.063 1.40 1.60
A1 0.002 0.006 0.05 0.15
A2 0.053 0.057 1.35 1.45
B 0.007 0.011 0.17 0.27
C 0.004 0.008 0.09 0.20
D 0.858 0.874 21.80 22.20
D1 0.783 0.791 19.90 20.10
E 0.622 0.638 15.80 16.20
E1 0.547 0.555 13.90 14.10
e
L 0.018 0.030 0.45 0.75
0o7o0o7o
SYMBOL INCHES MILLIMETERS
0.020BSC 0.50BSC
0.370 0.390 9.909.40
XRT73LC03A
59
NOTICE
EXAR Corporation reserves the right to make changes to the products cont ained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no represen-
tatio n that the circuits are free of patent infringement. Charts and schedules contained here in ar e only for
illustration purposes and may vary depending upon a user’s specific application. While the information in
this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys-
tem or to significantly affect its safety or effectiveness. Products are not a utho rized fo r use in such applica-
tions unless EXAR Corporation receive s, in writing, assurances to its satisfaction that: (a) the risk of injury
or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-
ration is adequately protected under the circumstances.
Copyright 2003 EXAR Corporation
Datasheet October 2012.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REV. 1.0.4 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REVISION HISTORY
REV #DATE CHANGES MADE
1.0.0 July 2003 Final Release. Changed Theta-JA and Theta-JC. Icc reduced from 370mA to 350mA
in electrical Characteristics. Changed TQFP to LQFP.
1.0.1 Octobe r 2003 Changed the default register setting for LOSMUT_(n) in CR3.
1.0.2 September 2008 Updated datasheet Headers. Corrected Figure 12 block diagram typo. Redefined t22
Serial Processor Interface timing.
1.0.3 July 2012 Updated the Pinout and pin description to redefine pins 11, 19 and 28 as transmiter dig-
ital supply pins. Removed reference to exposed heat slug in the note on thermally
enhanced package found in the electrical specifications, page 15.
1.0.4 October 2012 Change package description on page 15. Updated Theta-JA/JC values. Update with
new Exar logo.