EN
IN OUT
GND
VIN
VEN
GND
VOUT
LP3990 COUT
1 µF
CIN
1 µF
OFF ON
GND
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LP3990
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LP3990 150-mA Linear Voltage Regulator for Digital Applications
1 Features 3 Description
The LP3990 regulator is designed to meet the
1• 1% Voltage Accuracy at Room Temperature requirements of portable, battery-powered systems
• Stable with Ceramic Capacitor providing an accurate output voltage, low-noise, and
• Logic Controlled Enable low-quiescent current. The LP3990 will provide a 0.8-
V output from the low input voltage of 2 V at up to a
• No Noise Bypass Capacitor Required 150-mA load current. When switched into shutdown
• Thermal-Overload and Short-Circuit Protection mode via a logic signal at the enable pin (EN), the
• Input Voltage Range, 2 V to 6 V power consumption is reduced to virtually zero.
• Output Voltage Range, 0.8 V to 3.3 V The LP3990 is designed to be stable with space-
• Output Current, 150 mA saving ceramic capacitors with values as low as 1 µF.
• Output Stable - Capacitors, 1 µF Performance is specified for a –40°C to 125°C
• Virtually Zero IQ(Disabled), < 10 nA junction temperature range.
• Very Low IQ(Enabled), 43 µA For output voltages other than 0.8 V, 1.2 V, 1.35 V,
• Low Output Noise, 150 µVRMS 1.5 V, 1.8 V, 2.5 V, 2.8 V, or 3.3 V, please contact
the Texas Instruments sales office.
• PSRR, 55 dB at 1 kHz
• Fast Start-Up, 105 µs Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications DSBGA (4) 1.324 mm x 1.045 mm (MAX)
• Cellular Handsets LP3990 WSON (6) 2.90 mm x 1.60 mm
• Hand-Held Information Appliances SOT-23 (5) 3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP3990
SNVS251J –MAY 2004–REVISED SEPTEMBER 2014
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Table of Contents
7.3 Feature Description................................................... 9
1 Features.................................................................. 17.4 Device Functional Modes........................................ 10
2 Applications ........................................................... 18 Application and Implementation ........................ 11
3 Description............................................................. 18.1 Application Information............................................ 11
4 Revision History..................................................... 28.2 Typical Application ................................................. 11
5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 14
6 Specifications......................................................... 410 Layout................................................................... 14
6.1 Absolute Maximum Ratings ...................................... 410.1 Layout Guidelines ................................................. 14
6.2 Handling Ratings ...................................................... 410.2 Layout Examples................................................... 15
6.3 Recommended Operating Conditions....................... 410.3 DSBGA Mounting.................................................. 16
6.4 Thermal Information.................................................. 410.4 DSBGA Light Sensitivity ....................................... 16
6.5 Electrical Characteristics........................................... 511 Device and Documentation Support................. 17
6.6 Output Capacitor, Recommended Specifications..... 611.1 Trademarks........................................................... 17
6.7 Timing Requirements................................................ 611.2 Electrostatic Discharge Caution............................ 17
6.8 Typical Performance Characteristics ........................ 711.3 Glossary................................................................ 17
7 Detailed Description.............................................. 912 Mechanical, Packaging, and Orderable
7.1 Overview................................................................... 9Information........................................................... 17
7.2 Functional Block Diagram......................................... 9
4 Revision History
Changes from Revision I (May 2013) to Revision J Page
• Added Device Information and Handling Rating tables, Feature Description,Device Functional Modes,Application
and Implementation,Power Supply Recommendations,Layout,Device and Documentation Support, and
Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section.............. 1
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IN
6EN
5N/C
4
1
OUT 2
GND 3
N/C
TOP VIEW BOTTOM VIEW
3
N/C 2
GND 1
OUT
IN
6
EN
5
N/C
4
(Thermal DAP) Thermal DAP
4
N/C 5
OUT
EN
3GND
2IN
1
EN
A2 IN
B2 EN
A2
IN
B2
A1
GND B1
OUT A1
GND
B1
OUT
TOP VIEW BOTTOM VIEW
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SNVS251J –MAY 2004–REVISED SEPTEMBER 2014
5 Pin Configuration and Functions
4 Pins 5 Pins
DSBGA (YZR) SOT-23 (DBV)
WSON (NGG)
6 Pins
Pin Functions
PIN
DSBGA SOT-23 WSON I/O DESCRIPTION
NAME YZR DBV NGG
GND A1 2 2 — Common Ground.
EN A2 3 5 Enable Input; Enables the Regulator when ≥0.95 V.
I Disables the Regulator when ≤0.4 V.
Enable Input has 1-MΩ(typical) pull-down resistor to GND.
OUT B1 5 1 Voltage output. A 1-µF Low ESR Capacitor should be connected to this Pin.
OConnect this output to the load circuit.
IN B2 1 6 I Voltage supply Input. A 1-µF capacitor should be connected at this input.
4 3 I No internal connection.
N/C N/A 4 I No internal connection.
N/A
N/C Pad — Thermal pad. Connect to Pin 2.
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6 Specifications
6.1 Absolute Maximum Ratings(1)(2)(3)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
Input voltage –0.3 6.5
Output voltage –0.3 Note(4) V
ENABLE input voltage –0.3 6.5
Continuous power dissipation internally limited Note(5)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) All voltages are with respect to the potential at the GND pin.
(4) The lower of VIN + 0.3 V or 6.5 V.
(5) Internal thermal shutdown circuitry protects the device from permanent damage.
6.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –2000 2000
pins(1)
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22- V
250 1500
C101, all pins
Machine model –200 200
(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
Input voltage, VIN 2 6 V
Enable input voltage, VEN 0.0 VIN
Junction temperature, TJ(1) –40 125 °C
(1) TJ(max) = (TA(max) + (RθJA × PD(max)) )
6.4 Thermal Information LP3990
THERMAL METRIC(1) YZR (DSBGA) DBV (SOT-23) NGG (WSON) UNIT
4 PINS 5 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 188.9 165.2 53.9
RθJC(top) Junction-to-case (top) thermal resistance 1.0 69.9 51.2
RθJB Junction-to-board thermal resistance 105.3 27.3 28.2 °C/W
ψJT Junction-to-top characterization parameter 0.7 1.8 0.6
ψJB Junction-to-board characterization parameter 105.2 26.8 28.3
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 8.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics(1)(2)
Unless otherwise noted, VEN = 950 mV, VIN = VOUT + 1 V or VIN = 2 V, whichever is higher. CIN = 1 µF, IOUT = 1 mA, COUT =
0.47 µF. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage Note (3), TJ= 25°C 2 6 V
DSBGA –1 1%
ILOAD = 1 mA WQFN –1.5% 1.5%
TJ= 25°C SOT-23 –1.5% 1.5%
Output voltage tolerance DSBGA –2.5% 2.5%
Over full line and load WQFN –3% 3%
regulation SOT-23 –4% 4%
Line regulation error VIN = (VOUT(NOM) + 1 V) to 6 V 0.1 0.02 0.1 %/V
VOUT = 0.8 V to 1.95
ΔVOUT V –0.005 0.002 0.005
DSBGA
VOUT = 0.8 V to 1.95
V –0.008 0.003 0.008
IOUT = 1 mA
Load regulation error %/mA
WQFN, SOT-23
to 150 mA VOUT = 2 V to 3.3 V –0.002 0.0005 0.002
DSBGA
VOUT = 2 V to 3.3 V –0.005 0.002 0.005
WQFN, SOT-23
VDO Dropout voltage IOUT = 150 mA(4) (5) 120 200 mV
ILOAD Load current Note (5)(6), TJ= 25°C 0 µA
VEN = 950 mV, IOUT = 0 mA 43 80
IQQuiescent current VEN = 950 mV, IOUT = 150 mA 65 120 µA
VEN = 0.4 V (output disabled), TJ= 25°C 0.002 0.2
ISC Short circuit current limit Note (7) 550 1000 mA
IOUT Maximum output current 150
ƒ = 1 kHz, IOUT = 1 mA to 150 mA 55
Power Supply Rejection
PSRR dB
Ratio ƒ = 10 kHz, IOUT = 150 mA 35
VOUT = 0.8 V 60
BW = 10 Hz to 100
eηOutput noise voltage(5) VOUT = 1.5 V 125 µVRMS
kHz VOUT = 3.3 V 180
Junction temperature (TJ) rising until the 155
Thermal shutdown output is disabled
TSHUTDOWN °C
junction temperature Hysteresis 15
(1) All voltages are with respect to the device GND terminal, unless otherwise stated.
(2) Minimum and Maximum limits are ensured through test, design, or statistical correlation over the operating junction temperature range
(TJ) of –40°C to 125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TJ= 25°C, and are
provided for reference purposes only.
(3) VIN(MIN) = VOUT(NOM) + 0.5 V, or 2 V, whichever is higher.
(4) Dropout voltage is voltage difference between input and output at which the output voltage drops to 100 mV below its nominal value.
This parameter applies only for output voltages above 2 V.
(5) This electrical specification is verified by design.
(6) The device maintains the regulated output voltage without the load.
(7) Short-circuit current is measured with VOUT pulled to 0 V and VIN worst case = 6 V.
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Electrical Characteristics(1)(2) (continued)
Unless otherwise noted, VEN = 950 mV, VIN = VOUT + 1 V or VIN = 2 V, whichever is higher. CIN = 1 µF, IOUT = 1 mA, COUT =
0.47 µF. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENABLE CONTROL CHARACTERISTICS
VEN = 0 V (Output is disabled) 0.001 0.1
Maximum input current TJ= 25°C
IEN(8) µA
at EN pin VEN = 6 V 2.5 6 10
VIN = 2 V to 6 V
VIL Low input threshold VEN falling from ≥VIH until the output is 0.4
disabled V
VIN = 2 V to 6 V
VIH High input threshold VEN rising from ≤VIL until the output is 0.95
enabled
(8) ENABLE Pin has 1-MΩ(typical) resistor connected to GND.
6.6 Output Capacitor, Recommended Specifications(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Capacitance(2) 0.7(3) 1 500 µF
COUT Output capacitance ESR 5 mΩ
(1) Unless otherwise specified, values and limits apply for TJ= 25°C.
(2) The full operating conditions for the application should be considered when selecting a suitable capacitor to ensure that the minimum
value of capacitance is always met. Recommended capacitor type is X7R. However, dependent on application, X5R, Y5V, and Z5U can
also be used. (See Detailed Design Procedure.)
(3) Limit applies over the full operating junction temperature range (TJ) of −40°C to 125°C.
6.7 Timing Requirements MIN NOM(1) MAX(2) UNIT
VOUT = 0.8 V 80 150
From VEN ↑VIH to
TON Turnon time (3) VOUT 95% level VOUT = 1.5 V 105 200 µs
(VIN(MIN) to 6 V) VOUT = 3.3 V 175 250
Line transient response Trise = Tfall = 30 µs(3), mV (pk-
8 16
(ΔVOUT)ΔVIN = 600 mV pk)
Transient Trise = Tfall = 1 µs(3),
response Load transient response IOUT = 1 mA to 150 mA 55 100 mV
(ΔVOUT)COUT = 1 µF
(1) Nom values apply for TJ= 25°C.
(2) Maximum limits apply over the full operating junction temperature (TJ) range of −40°C to 125°C.
(3) This electrical specification is verified by design.
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2 2.5 3 3.5 4 4.5 5 5.5 6
VIN
GND I (µA)
TJ = 125°C
TJ = 25°C
TJ = -40°C
20
30
40
50
60
70
80
90
100
TIME (100 Ps/DIV)
800 VIN = 2.5V
CURRENT
(mA)
VOUT
(1V/Div)
600
400
200
0
2 2.5 3 3.5 4 4.5 5 5.5 6
VIN
GND I (PA)
20
30
40
50
60
70
80
90
100
TJ = 125°C
TJ = 25°C
TJ = -40°C
2 2.5 3 3.5 4 4.5 5 5.5 6
VIN
GND I (PA)
TJ = 125°C
TJ = 25°C
20
30
40
50
60
70
80
90
100
TJ = -40°C
0 50 75 100 125 150
LOAD CURRENT (mA)
GROUND CURRENT (PA)
0
10
20
30
40
50
80
TJ = 125°C
TJ = 25°C
TJ = -40°C
25
60
70
-40 -25 0 25 50 75 100 125
TEMPERATURE (°C)
VOUT CHANGE (%)
-2.00
-1.50
-1.00
-0.50
0.00
0.50
1.00
1.50
2.00
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6.8 Typical Performance Characteristics
Unless otherwise specified, CIN = 1 µF ceramic, COUT = 0.47 µF ceramic, VIN = VOUT(NOM) + 1 V, TA= 25°C, VOUT(NOM) = 1.5 V;
VEN = VIN.
Figure 1. Output Voltage Change vs Temperature Figure 2. Ground Current vs Load Current
ILOAD = 0 mA ILOAD = 1 mA
Figure 3. Ground Current vs VIN Figure 4. Ground Current vs VIN
ILOAD = 150 mA
Figure 6. Short Circuit Current
Figure 5. Ground Current vs VIN
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1
0.1 10 100
FREQUENCY (kHz)
NOISE (PV/ Hz)
0.01
0.1
1
10
VOUT = 1.5V
VOUT = 3.3V
TIME (50 Ps/DIV)
IL = 1 mA
VEN
(1V/Div) VOUT
(500 mV/Div)
100 1k 10k 100k 1M
FREQUENCY (Hz)
RIPPLE REJECTION (dB)
IL = 1 mA
COUT = 0.47 PF
COUT = 1 PF
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
100 1k 10k 100k 1M
FREQUENCY (Hz)
RIPPLE REJECTION (dB)
ILOAD = 150 mA
COUT = 1 PF
COUT = 0.47 PF
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
TIME (100 Ps/DIV)
800 VIN = 6V
CURRENT
(mA)
VOUT
(1V/Div)
600
400
200
0
TIME (100 Ps/DIV)
3.1
2.5
CIN = 1 PF
COUT = 0.47 PF
IL = 1 to 150 mA
VIN (V)
'VOUT
(10 mV/Div)
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Typical Performance Characteristics (continued)
Unless otherwise specified, CIN = 1 µF ceramic, COUT = 0.47 µF ceramic, VIN = VOUT(NOM) + 1 V, TA= 25°C, VOUT(NOM) = 1.5 V;
VEN = VIN.
Figure 7. Short Circuit Current Figure 8. Line Transient
Figure 10. Power Supply Rejection Ratio
Figure 9. Power Supply Rejection Ratio
Figure 11. Enable Start-Up Time Figure 12. Noise Density
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+
Current
Limit Thermal
Shutdown
IN OUT
GND
VREF
800 mV
EN
OFF ON
1 M
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7 Detailed Description
7.1 Overview
Designed meet the requirements of portable, battery-powered digital systems providing an accurate output
voltage with fast start-up. When disabled via a low logic signal at the enable pin (EN), the power consumption is
reduced to virtually zero
The LP3990 is designed to perform with a single 1-μF input capacitor and a single 1-μF ceramic output
capacitor.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Enable (EN)
The LP3990 Enable (EN) pin is internally held low by a 1-MΩresistor to GND. The EN pin voltage must be
higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin
voltage must be lower than the VIL threshold to ensure that the device is fully disabled. If the EN pin is left open
the LP3990 output will be disabled.
7.3.2 Thermal Overload Protection (TSD)
Thermal Shutdown disables the output when the junction temperature rises to approximately 155°C which allows
the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry enables.
Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a
result of overheating.
The Thermal Shutdown circuitry of the LP3990 has been designed to protect against temporary thermal overload
conditions. The Thermal Shutdown circuitry was not intended to replace proper heat-sinking. Continuously
running the LP3990 device into thermal shutdown may degrade device reliability.
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7.4 Device Functional Modes
7.4.1 Enable (EN)
The LP3990 EN pin is internally held low by a 1-MΩresistor to GND. The EN pin voltage must be higher than the
VIH threshold to ensure that the device is fully enabled under all operating conditions.
7.4.2 Minimum Operating Input Voltage (VIN)
The LP3990 does not include any dedicated UVLO circuitry. The LP3990 internal circuitry is not fully functional
until VIN is at least 2 V. The output voltage is not regulated until VIN ≥(VOUT + VDO), or 2 V, whichever is higher.
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EN
IN OUT
GND
VIN
VEN
GND
VOUT
LP3990 COUT
1 µF
CIN
1 µF
OFF ON
GND
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP3990 is a linear voltage regulator for digital applications designed to be stable with space-saving ceramic
capacitors as small as 1 µF.
8.2 Typical Application
Figure 13 shows the typical application circuit for the LP3990. The input and output capacitances may need to be
increased above the 1 μF shown for some applications.
Figure 13. LP3990 Typical Application
8.2.1 Design Requirements
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 2 V to 6 V
Output voltage 1.8 V
Output current 100 mA
Output capacitor range 1 µF
Input/output capacitor ESR range 5 mΩto 500 mΩ
8.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Available input voltage range
• Output voltage needed
• Output current needed
• Input and output capacitors
8.2.2.1 Power Dissipation and Device Operation
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from
the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power
dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces
between the die junction and ambient air.
The maximum allowable power dissipation for the device in a given package can be calculated using Equation 1:
PD-MAX = ((TJ-MAX - TA) / RθJA) (1)
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The actual power being dissipated in the device can be represented by Equation 2:
PD= (VIN - VOUT) x IOUT (2)
These two equations establish the relationship between the maximum power dissipation allowed due to thermal
consideration, the voltage drop across the device, and the continuous current capability of the device. These two
equations should be used to determine the optimum operating conditions for the device in the application.
In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is present,
the maximum ambient temperature (TA-MAX) may be increased.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum
ambient temperature (TA-MAX) may have to be derated. TA-MAX is dependent on the maximum operating junction
temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the
application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA),
as given by Equation 3:
TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX)) (3)
Alternately, if TA-MAX can not be derated, the PDvalue must be reduced. This can be accomplished by reducing
VIN in the 'VIN–VOUT' term as long as the minimum VIN is met, or by reducing the IOUT term, or by some
combination of the two.
8.2.2.2 External Capacitors
In common with most regulators, the LP3990 requires external capacitors for regulator stability. The LP3990 is
specifically designed for portable applications requiring minimum board space and smallest components. These
capacitors must be correctly selected for good performance.
8.2.2.3 Input Capacitor
An input capacitor is required for stability. It is recommended that a 1-µF capacitor be connected between the
LP3990 IN pin and GND pin (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean
analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: To ensure stable operation it is essential that good PCB design practices are employed to minimize
ground impedance and keep input inductance low. If these conditions cannot be met, or if long leads are used to
connect the battery or other power source to the LP3990, then it is recommended that the input capacitor is
increased. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a
low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the
input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain
approximately 1 µF over the entire operating temperature range.
8.2.2.4 Output Capacitor
The LP3990 is designed specifically to work with very small ceramic output capacitors. A 1-µF ceramic capacitor
(temperature types Z5U, Y5V or X7R/X5R) with ESR between 5 mΩto 500 mΩ, is suitable in the LP3990
application circuit.
For this device the output capacitor should be connected between the OUT pin and GND pin.
It is also possible to use tantalum or film capacitors at the device output, but these are not as attractive for
reasons of size and cost (see Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR
value that is within the range 5 mΩto 500 mΩfor stability.
8.2.2.5 No-Load Stability
The LP3990 will remain stable and in regulation with no external load. This is an important consideration in some
circuits, for example CMOS RAM keep-alive applications.
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0402, 6.3V, X5R
0603, 10V, X5R
0 1.0 2.0 3.0 4.0 5.0
DC BIAS (V)
20%
40%
60%
80%
100%
CAP VALUE (% of NOMINAL 1 PF)
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8.2.2.6 Capacitor Characteristics
The LP3990 is designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The
ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩto 40 mΩ, which easily meets the ESR
requirement for stability for the LP3990.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly, depending on the operating conditions and
capacitor type.
In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance can vary with DC bias conditions as well as
temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.
The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer
performance figures in general. As an example, Figure 14 shows a typical graph comparing different capacitor
case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result
in the capacitance value falling below the minimum value given in the recommended capacitor specifications
table (0.7 µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size
capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for
the nominal value capacitor are consulted for all conditions, as some capacitor sizes (for example, 0402) may not
be suitable in the actual application.
Figure 14. Graph Showing A Typical Variation In Capacitance vs DC Bias
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of –55°C to 125°C, will only vary the capacitance to within ±15%. The capacitor type X5R has
a similar tolerance over a reduced temperature range of –55°C to 85°C. Many large value ceramic capacitors,
larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by
more than 50% as the temperature varies from 25°C to 85°C. Therefore, X7R and X5R types are recommended
over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47-µF to 4.7-µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to -40°C, so some guard band must be allowed.
8.2.2.7 Enable Control
The LP3990 features an active high Enable pin, EN, which turns the device on when pulled high. When not
enabled the regulator output is off and the device typically consumes 2 nA.
If the application does not require the Enable switching feature, the EN pin should be tied to VIN to keep the
regulator output permanently on.
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LP3990
TIME (50 Ps/DIV)
IL = 150 mA
VEN
(1V/Div) VOUT
(500 mV/Div)
TIME (20 Ps/DIV)
150
1
CIN = 1 PF
COUT = 0.47 PF
LOAD CURRENT
(mA)
'VOUT
(50 mV/Div)
LP3990
SNVS251J –MAY 2004–REVISED SEPTEMBER 2014
www.ti.com
To ensure proper operation, the signal source used to drive the EN input must be able to swing above and below
the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH.
An internal 1-MΩpull-down resistor ties the EN input to ground, ensuring that the device remains off if the EN pin
is left open circuit.
8.2.3 Application Curves
Figure 16. Load Transient
Figure 15. Enable Start-Up Time
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 2 V to 6 V. The input supply should be
well regulated and free of spurious noise. To ensure that the LP3990 output voltage is well regulated, the input
supply should be at least VOUT + 0.5 V, or 2 V, whichever is higher. A minimum capacitor value of 1-μF is
required to be within 1 cm of the IN pin.
10 Layout
10.1 Layout Guidelines
The dynamic performance of the LP3990 is dependant on the layout of the PCB. PCB layout practices that are
adequate for typical LDO's may degrade the load regulation, PSRR, noise, or transient performance of the
LP3990.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP3990, and as
close as is practical to the package. The ground connections for CIN and COUT should be back to the LP3990
ground pin using as wide, and as short, of a copper trace as is practical.
Connections using long trace lengths, narrow trace widths, and/or connections through vias should be avoided.
These will add parasitic inductances and resistance that results in inferior performance especially during transient
conditions.
A Ground Plane, either on the opposite side of a two-layer PCB, or embedded in a multi-layer PCB, is strongly
recommended. This Ground Plane serves two purposes : 1) Provide a circuit reference plane to assure accuracy,
and 2) provides a thermal plane to remove heat from the LP3990 WSON package through thermal vias under the
package DAP.
14 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LP3990
COUT
VIN
VEN
VOUT CIN
LP3990SD
Power Ground
1
2
3 4
5
6
Thermal
Pad
IN
GND
EN
OUT
N/C
COUT
1
2
34
5
VIN
VEN
VOUT
CIN
LP3990MF
Power Ground
B2 B1
A1
VIN VOUT
Power Ground
VEN
CIN COUT
LP3990TL
A2
LP3990
www.ti.com
SNVS251J –MAY 2004–REVISED SEPTEMBER 2014
10.2 Layout Examples
Figure 17. LP3990 DSBGA Layout
Figure 18. LP3990 SOT-23 Layout
Figure 19. LP3990 WSON Layout
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LP3990
LP3990
SNVS251J –MAY 2004–REVISED SEPTEMBER 2014
www.ti.com
10.3 DSBGA Mounting
The DSBGA package requires specific mounting techniques, which are detailed in TI Application Note DSBGA
Wafer Level Chip Scale PackageSNVA009.
For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the
DSBGA device.
10.4 DSBGA Light Sensitivity
Exposing the DSBGA device to direct light may affect the operation of the device. Light sources, such as halogen
lamps, can affect electrical performance, if placed in close proximity to the device.
Light with wavelengths in the infra-red portion of the spectrum is the most detrimental, and so, fluorescent
lighting used inside most buildings, has little or no effect on performance.
16 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: LP3990
LP3990
www.ti.com
SNVS251J –MAY 2004–REVISED SEPTEMBER 2014
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LP3990
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP3990MF-1.2/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SCDB
LP3990MF-1.8/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SCFB
LP3990MF-2.5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SCJB
LP3990MF-2.8/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SCKB
LP3990MF-3.3/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SCLB
LP3990MFX-1.2/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SCDB
LP3990MFX-1.8/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SCFB
LP3990MFX-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SCLB
LP3990SD-1.2/NOPB ACTIVE WSON NGG 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L086B
LP3990SD-1.5/NOPB ACTIVE WSON NGG 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L087B
LP3990SD-1.8/NOPB ACTIVE WSON NGG 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L088B
LP3990TL-0.8/NOPB ACTIVE DSBGA YZR 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125
LP3990TL-1.2/NOPB ACTIVE DSBGA YZR 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125
LP3990TL-1.35/NOPB ACTIVE DSBGA YZR 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125
LP3990TL-1.5/NOPB ACTIVE DSBGA YZR 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125
LP3990TL-1.8/NOPB ACTIVE DSBGA YZR 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125
LP3990TL-2.5/NOPB ACTIVE DSBGA YZR 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125
LP3990TL-2.8/NOPB ACTIVE DSBGA YZR 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125
LP3990TLX-0.8/NOPB ACTIVE DSBGA YZR 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125
LP3990TLX-1.2/NOPB ACTIVE DSBGA YZR 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP3990TLX-1.5/NOPB ACTIVE DSBGA YZR 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125
LP3990TLX-1.8/NOPB ACTIVE DSBGA YZR 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125
LP3990TLX-2.5/NOPB ACTIVE DSBGA YZR 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125
LP3990TLX-2.8/NOPB ACTIVE DSBGA YZR 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 3
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LP3990 :
•Automotive: LP3990-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP3990MF-1.2/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3990MF-1.8/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3990MF-2.5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3990MF-2.8/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3990MF-3.3/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3990MFX-1.2/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3990MFX-1.8/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3990MFX-3.3/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3990SD-1.2/NOPB WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LP3990SD-1.5/NOPB WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LP3990SD-1.8/NOPB WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LP3990TL-0.8/NOPB DSBGA YZR 4 250 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1
LP3990TL-1.2/NOPB DSBGA YZR 4 250 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1
LP3990TL-1.35/NOPB DSBGA YZR 4 250 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1
LP3990TL-1.5/NOPB DSBGA YZR 4 250 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1
LP3990TL-1.8/NOPB DSBGA YZR 4 250 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1
LP3990TL-2.5/NOPB DSBGA YZR 4 250 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1
LP3990TL-2.8/NOPB DSBGA YZR 4 250 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Sep-2018
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP3990TLX-0.8/NOPB DSBGA YZR 4 3000 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1
LP3990TLX-1.2/NOPB DSBGA YZR 4 3000 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1
LP3990TLX-1.5/NOPB DSBGA YZR 4 3000 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1
LP3990TLX-1.8/NOPB DSBGA YZR 4 3000 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1
LP3990TLX-2.5/NOPB DSBGA YZR 4 3000 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1
LP3990TLX-2.8/NOPB DSBGA YZR 4 3000 178.0 8.4 1.09 1.35 0.76 4.0 8.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP3990MF-1.2/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LP3990MF-1.8/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LP3990MF-2.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LP3990MF-2.8/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LP3990MF-3.3/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LP3990MFX-1.2/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP3990MFX-1.8/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP3990MFX-3.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LP3990SD-1.2/NOPB WSON NGG 6 1000 210.0 185.0 35.0
LP3990SD-1.5/NOPB WSON NGG 6 1000 210.0 185.0 35.0
LP3990SD-1.8/NOPB WSON NGG 6 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Sep-2018
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP3990TL-0.8/NOPB DSBGA YZR 4 250 210.0 185.0 35.0
LP3990TL-1.2/NOPB DSBGA YZR 4 250 210.0 185.0 35.0
LP3990TL-1.35/NOPB DSBGA YZR 4 250 210.0 185.0 35.0
LP3990TL-1.5/NOPB DSBGA YZR 4 250 210.0 185.0 35.0
LP3990TL-1.8/NOPB DSBGA YZR 4 250 210.0 185.0 35.0
LP3990TL-2.5/NOPB DSBGA YZR 4 250 210.0 185.0 35.0
LP3990TL-2.8/NOPB DSBGA YZR 4 250 210.0 185.0 35.0
LP3990TLX-0.8/NOPB DSBGA YZR 4 3000 210.0 185.0 35.0
LP3990TLX-1.2/NOPB DSBGA YZR 4 3000 210.0 185.0 35.0
LP3990TLX-1.5/NOPB DSBGA YZR 4 3000 210.0 185.0 35.0
LP3990TLX-1.8/NOPB DSBGA YZR 4 3000 210.0 185.0 35.0
LP3990TLX-2.5/NOPB DSBGA YZR 4 3000 210.0 185.0 35.0
LP3990TLX-2.8/NOPB DSBGA YZR 4 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Sep-2018
Pack Materials-Page 3
MECHANICAL DATA
NGG0006A
www.ti.com
SDE06A (Rev A)
MECHANICAL DATA
YZR0004xxx
www.ti.com
TLA04XXX (Rev D)
0.600±0.075 D
E
4215042/A 12/12
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
D: Max =
E: Max =
1.324 mm, Min =
1.045 mm, Min =
1.263 mm
0.984 mm
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/E 09/2019
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
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