1/2May 2000
1 - DESCRIPTION
This Errata Sheet describes the functional and
electr ical problems known.
The revision num ber BB can b e found in the sec-
ond line printed on the ST10F168 package. It
looks like: XBB-XXXXXXX where "BB" identifies
the revi sion numbe r.
2 - FUNCTIONAL PROBLE MS
The following malfunctions are known in this
device:
2.1 - ST_PWRDN.1 - Exec ution of PWRDN
Instruction
When instruction PWRDN is executed while pin
NMI is at a high level (if PWRDCFG bit is clear in
SYSCON register) or while at least one P2 pin
used to exit from power-down mode (if PWRD-
CFG bit is set in SYSCON register) is at the activ e
level, power down mode should not be entered,
and the PWRDN instruction should be ignored.
However, under the conditions described below,
the PWRDN instruction may not be ignored, and
no further instructions are fetched from external
mem or y, i.e. the CPU is in a quasi-idle state. This
p ro blem w ill on l y oc c ur in the followi ng si tuat io ns:
a) the instructions following the PWRDN instruc-
tion are located in an external memory, and a
multiplexed bus configuration with memory
tristate waitstate (bi t MT-TCx=0) is used.
b) the instr uction preceeding the PW RDN instruc-
tion wr ites to exter nal memor y or an XPeripheral
(XRAM, CAN), and the instructions following the
PWRDN instruction are located in external mem-
ory. In this ca se, th e problem will occur f or any bu s
configuration.
Note The on-chip peripherals are still working
correctly, in particular t he Watchdog Timer,
if not disabled, will reset the device upon
an overflow. Interrupts and PEC transfers,
however, can not be processed. In case
NMI is asserted low while the device is in
this quasi-idle state, power-down mode is
entered.
No problem will occur if the NMI pin is low (if
PW RDCFG = 0 ) or if a ll P2 pins used to exit from
power-down mode are at inactive l eve l (if PWRD-
CFG = 1): the chip will normally enter powerdown
mode.
Workaround:
Ensure that no instructi on which writes t o ext ernal
mem ory or an XPer ipheral preceeds the PW RDN
instruct ion, otherwise insert e.g. a NOP instruct ion
in front of PW RDN. When a multiplexed bus with
memory tristate waitstate is used, the PWRDN
instr uction s ho uld be executed f rom inter nal RA M
or XRAM.
Summary of Remaining Functional Problems
Known on the ST10F168-BB
3 - DEVIATI ONS FROM DC/AC PREL IM INARY
SPECIFICATION
DC parameters
After characterization, the DC parameter of ALE
active current has been changed: IALEH change
from 500µA to 600 µA.
No t e on on-chi p osci ll at or
The XTAL2 output is not designed to provide a
valid signal when XTAL1 is supplied by an
external clock signal. It may happen, if the
external clock signal is not perfectly symetrical
and centered on VDD / 2, that XTAL2 signal is not
equal to XTAL1. This is due to the design of the
oscillator, which has a auto-adaptation gain
cont rol dedicat ed to external crystal.
If an external clock signal is directly provided on
XTAL1 pin, then le ave XTA L2 pin disconnected to
achieve the lowest consumption of the on-chip
oscillator.
4 - ER RA TA SHEET VERSION IN F OR MAT I O N
This document was released on the 23rd of
May 2000. It reflects the current silicon status of
the ST10F168B B re vision and i s only v alid f or t his.
Name Short Description
ST_PWRDN.1 Powerdown mode not ignored
ST10F168
16-Bit MCU Wit h 256K Byte Flash and 8K Byte RAM Memories
This is advance information on a new product now in dev elopment or undergoing evaluation. Details are subject to change without notice.
ERRATA SHEET - REVISION BB
ST10F168
2/2
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
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