TOSHIBA TMP88C060 CMOS 8-Bit Microcomputer TMP88CO60F The 88C060 is the high-speed and high-performance 8-bit microcomputer, including eight multiple timer / counters, a 10-bit A/D converter, serial interfaces (UART, IC bus, and SIO). It can externally expand large program memory /data memory (up to 1 Mbytes linear address space). Part No. ROM RAM Package TMP88CO60F ROM less 512 x 8bit_| P-LQFP80-1212-0.50A Features @8-bit microcomputer TLCS-870 / X Series. P-LOFP80-1212-0.50A @ Minimum instruction execution time : 0.32 s (at 12.5 MHz) @ Instruction execution time can be changed to reduce power consumption. min. 0.32 us, 0.64 4S,1.28 us, 2.56 us, 5.12 us, 122 us at 12.5 MHz / 32.768 kHz @ External memory expansion Expanded up to 1M bytes (for both programs and data) @ Non-multiplexed bus (20 bits of address and 8 bits of data) Wait control @ Bus arbitration control @ 18 interrupt sources (External : 6, Internal : 12) @ Input / Output ports (42 pins) @ High current output : 8 pins (typ. 20 mA), LED direct drive @ Two 16-bit Timer / Counters @ 7C1:Timer, Event counter, Programmable pulse generator TMP88CO60F output, Pulse width measurement, External trigger timer, and Window modes. @ TC2 : Timer, Event counter, and Window modes. @ Four 8-bit Timer / Counters TC3: Timer, Event counter, and Capture for Remote control signal decoding (Pulse width /duty measurement) modes. @ TC4: Timer, Event counter, PWM outputs, and programmable divider output modes. @ TC5 : Timer, PWM output, and programmable divider output modes @ TC6 : Timer and Baud-rate generation for UART modes 980910EBP1 @ For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to the foreign exchange and foreign trade laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. Purchase of TOSHIBA ?C components conveys a license under the Philips ?C Patent Rights to use these components in an IC system, provided that the system conforms to the IC Standard Specification as defined by Philips. 3-60-1 1999-10-07TOSHIBA TMP88C060 @ Time Base Timer (Interrupt frequency : 1 kHz to 16384 kHz) @ Watchdog Timer @ Divider output (frequency : 1 kHz to 8 kHz) @ Two 8-bit Serial Interfaces @ 8-bit UART (Parity. framing. overrun error detection) @ 8-bit Serial Bus (I?C-Bus for multi-master system and SIO) @ 10-bit successive approximate type A/D converter 8 analog inputs Conversion time : 59 s at 12.5 MHz, 44 ws at 4.2 MHz @ Dual clock operation @ Five Power saving operating modes @ STOP mode : @ SLOW mode: @ IDLE1 mode: @ IDLE2 mode : @ SLEEP mede: Oscillation stops. Battery / Capacitor back-up. Release by stop pin input. Low power consumption operation using low-frequency clock (32.768 kHz) CPU stops, and Peripherals operate using high-frequency clock. Release by interrupts. (CPU restarts) CPU stops, and Peripherals operate using high and low frequency clock. Release by interrupts. CPU stops, and Peripherals operate using low-frequency clock. Release by interrupts. @ Wide operating voltage : 2.7 to 5.5 V at 4.2 MHz/ 32.768 kHz, 4.5 to 5.5 V at 12.5 MHz/ 32.768 kHz @ Emulation Pod : BM88CO60FOA 3-60-2 1999-10-07TOSHIBA TMP88C060 Pin Assignments (Top View) P-LQFP80-1212-0.50A 65 7 ~ v B NAR ARR RRR apap NH fOnNwntmn- oO WIORFEIF 22222222 Vla|>2zZzjz2---- sc ct Eblarckedaddddid BRON TMN- ON, eer reo ee ~~ [TT 1< P76 50 PDI~~ p75 [IT 1~< P74 PIT I< P73 [TT > p72 [TT 1~ P71 45 (<> P70 [IT I* vs $ [TT 1- VASS [TT I~* VAREF [IT 1-* vDD O 40 35 30 25 <> <>oOm P06 WAIT) CI po <~C11)10 FAC D1 <~COo XOUT _ C1420 POO (A16) C1 P01 (A17) CO PO2 (A18) <LI PO3 (A19) C1 P07 (CLK) C10 P04 (BUSRO PO5 (BUSAK) P45 (SDA/SO) P44 (SCL/SI) P43 (SCK) P42 (TxD) P41 (RxD) P40 P37 P36 P35 (INT4/TC4) P34 (INT3 /TC3) P33 (PWM5 /PDOS5) P32 (PWM4/PDO4) P31 P30 RESET P23 P22 (KTOUT) P21 (XTIN) P20 (INTS /STOP) VSS 3-60-3 1999-10-07TOSHIBA Block Diagram External Memory EA Access pin Power J VDD Supply | VSS Reset I/O RESET Test Pin TEST: Xtal . XIN Connecting {x Pins Analog VAREF Reference VASS Voltage Read Signal RD Data Bus Write D7 Signal to WR BO External Memory interface Data Memory RAM Standby Controller System Controller Timing Generator Clock Gear High fregu Clock Low fregu TLCS-870/X CPU CORE Time Base Timer Watchdog Timer 10-bit A/D Converter Address Bus Al5 to AO P07 (CLK) P06 (WAIT) P05 (BUSAK) P04 (BUSRQ) P03 (A19) to POO (A16) it/ Bus Arbitration Controller 16-bit mer /Counters TC1 TC2 Interrupt Controller 8-bit Timer / Counters Tc4 TCS Receiver TMP88C060 8-bit Serial Interfaces UART | I?C Bus} SIO P23 P77 (AIN7) P17 P37 P45 to to to to to to P20 P70 (AINO) P10 P30 P40 (analog inputs) 3-60-4 1999-10-07TOSHIBA TMP88C060 Pin Function Pin name Input / Output Function P07 (CLK) VO (Output) 8-bit programmable input / output ports Divided-by-4 clock output to P70 (AINO) these ports must be set to the analog input mode by P7CR and select the channel in ADCCR. PO6 (WAIT) VO (Input) _ | (tri-state). Wait request input P05 (BUSAR) V0 (Output) Each bit of these ports can be individually tbe ecrneeetes configured as an input or an output. _ WO (Input) |When used as a wait request input, a bus | VQ (Output) [release request input, an external vO interrupt input, or a timer counter input, wetreterteeeeseeseess corresponding bit must be configured as HO (Input) input. When used as a divided-by-4 clock output, a bus acknowledge output, PPG VO (Output) output, or a divider output, the output Tiree latch must be set to 1 and corresponding bit must be configured as]. 1/0 (Input) output. After reset, PO3 to POO are address buses. When used as a port, these ports must be set to the ports by EXPCR. weeeeeees VO. 4-bit input / output port with latch. vee ee eee eee eee e eee ene e eee tenons seat ann aeeeaeeeeanneeaned V0 (Output) lWhen used as an input port, a resonator Xtal connecting pins (32.768 kHz). For weetenerercrreeeenenes connecting pin, an external interrupt inputting external clock, XTIN is used and . . XTOUT is opened. vO (Input) input, or a STOP mode release input, the Tecra interrupt, seaeeeeeeeeaees STOP weees 4 weeaee weeeeeeed output latch must be set to "1". . pt input 5 or mode release signal input sos VO. soussisstussusntistisesississsnastusstusiassissisee External interrupt input 4 or Timer / Counter 4 /0 (Input) 8-bit input / output port (large current) input i eeeneeeeeereeeeee output) with latch. External interrupt input 3 or Timer / Counter 3 cee ceteetttteeeseneees When used as an input port, PWM output) impute esses an external interrupt input, or a timer] 8-bit PWM output 5 or, 8-bit programmable counter input, the output latch must be] divider output 5 VO (Output) setto "1". 8-bit PWM output 4 or, 8-bit programmable cecteeteteeceee divider OUt~UT issues! VO $10 data output FC bus data Oc cecceeseessstteeeessneeee 6-bit input / output port with latch. $IO data input 70 (I/O) When used as an input port or a serial] @C bus clock MO eeeeead interface pin, the output latch must be set} SIO clock input/output aeeeeeed to"1". ART data Output oc ccccccceseseeeneeeeee UART data input ceed 8-bit programmable input / output port (tri-state). Each bit of these ports can be P77 (AIN7) individually configured as an input or an V/O (Input) Joutput. When used as an analog input,| A/D converter analog input (ch 7 to ch 0) 3-60-5 1999-10-07TOSHIBA TMP88C060 Pinname Input / Output Function A15 to AO EA Lower address bus (external memory connect) Input External memory access input. Be tied to low. XIN, XOUT Input, Xtal connecting pins for high-frequency clock. Output For inputting external clock, XIN is used and XOUT is opened. RESET v0 Reset signal input or watchdog timer output / address-trap-reset output / system-clock- reset output. TEST Input Test pin for out-going test. Be tied to low. VDD, VSS Power +5V,0V (GND) IVAREF, VASS Supply Analog reference voltage for A/D converter (High, Low) 3-60-6 1999-10-07TOSHIBA TMP88C060 Operational Description 1. CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, the external memory interface, and the reset circuit. 1.1 Memory Address Map The TLCS-870 / X Series is capable of addressing 1M bytes of memory. Figure 1-1 shows the memory address map of the 88C060. The memory of the 88C060 is organized with 3 address spaces such as ROM, RAM SFR (Special Function Register). It uses a memory mapped I/O system, and all I/O registers are mapped in the SFR address space. There are 16 banks of the general-purpose register. The register banks are also assigned to the first 128 bytes of the RAM address space. SFR ogare 64 bytes Note : ROM; Read Only Memory includes 00040 General-purpose Program memory : 128 bytes register banks Vector tables Internal OOOBF beceececceesceeeesceeeee (8 registers x 16 banks) RAM, Random Access Memory includes RAM 00QCco : 384 bytes Data memory 0023F Stack 00240 General-purpose register banks reserved SFR ; Special Function Register includes HO ports go 0 5 Peripheral control registers : Peripheral status registers System control registers External ~ a interrupt control registers ROM RAM Program Status Word FFF3F eee eee ree Vector table for vector call Frese |... 6abytes |) instruction (16 vectors) FFF80 : 128 bytes Vector table for interrupts FFFFF and reset (32 vectors) Figure 1-1. Memory address map 1.2. Program Memory (ROM) The 88C060 can address up to 1M bytes of external program memory space except the first 4K bytes space (00000, to OOFFFy). The 88C060 does not have internal ROM. An external program memory must be connected. 1.3 DataMemory (ROM) The 88C060 can address up to 1M bytes of data memory space. Data memory consists of internal data memory (on-chip RAM) and external data memory (RAM and / or ROM). The 88C060 has 512 bytes of static RAM. The first 128 bytes (00040, to OOOBFy) of the internal RAM are also used as general- purpose register banks. The data memory contents become unstable when the power supply is turned on ; therefore, the data memory should be initialized by an initialization routine. 3-60-7 1999-10-07TOSHIBA TMP88C060 Electrical Characteristics Absolute Maximum Rating (Veg = 0 V) Parameter Symbol Conditions Rating Su Vv Vv -0.31t06.5 In Vv Vv - 0.3 to Vpp + 0.3 Vv P21, P22, RESET, Tri-st - 0.3 to Vpp +: 0.3 Vv Output Voltage ; 7 P20, P23, Sink Drain Port -0.3105.5 PO, P1, P2, P4, P7 3.2 Output Current (Per 1 pin) A19-0, D7-0, RD, WR 12 P3 30 80 120 Power Dissi =70 PD 330 Soldering Tem re me 260 (10 S Tem re T -55to 125 Tem re T - 40 to 85 Output Current (Total) Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must nat be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. Recommended Operating Conditions (Vsg =0 V, Topr = 40 to 85 C) Parameter Symbol Pins Conditions Min Max Unit fco= NORMAL1, 2 mode 4.5 Supply Voltage 12.5MHz_ | IDLE1, 2 mode fc= NORMAL1, 2 made Vop 4.2MHz__ | IDLE1, 2mode 2.7 5.5 Vv fs= SLOW mode 32.768 kHz| SLEEP mode STOP mode 2.0 E h i TTL Input High Voltage Vind input ysteresis and Vpp24.5V Vpp x 0.70 Vin2 | Hysteresis input Vpp x 0.75 Ving | Except TLLinput Vop<4.5V Vpp x 0.90 Vop V TTL input Vpp=5V 2.2 Vina | (Data bus) Vop=3V Vpp - 0.2 Input Low Voltage Vii input, hysteresis and TTL Vpp2=4.5V Vpp x 0.30 Vit2 Hysteresis input Vpp x 0.25 Vig | Except TTL input Vpp<4.5V 0 Vpp x 0.10 V TTL input Vpp=5V 0.8 Vita | (Data bus) Vop=3V 0.2 Vpp =4.5 Vto5.5V Clock Frequency fc | XIN, XOUT (Normal 1, 2 modes) 10 12.5 | MHz Vpp=2.7Vto5.5V 4.2 fs XTIN, XTOUT 30.0 34.0 kHz Note1: The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. Note2 : fc (Min.) are calculated at using clock Gear as follow : (Minimum value of fc) = (pre-scaled ration) x 1 [MHz] 3-60-128 1999-10-07TOSHIBA TMP88C060 DC Characteristics (Vsg = OV, Topr= 40 to 85 C) Parameter Symbol Pins Conditions Min | Typ. | Max | Unit Hysteresis Voltage Vus Hysteresis input - 0.9 - Vv lind TEST, EA : : - Vpp = 5.5 V Input Current lin2 Sink Open Drain, Tir-state Port - - +2] pA Vin=5.5V/0V lin3 RESET, STOP . Rinz RESET 100 220 450 Input Resistance kQ Ring | TEST - 70 - Oscillator Feed-back Rey XIN-XTOUT - 1.2 - Ma Resistance Rest XTIN-XTOUT - 6 - Output Leakage lLoi Sink Open Drain Port Vpp = 5-5 V, Vout =5-5 V - - A Current ILo2 Tir-st port Vpp =5.5V, Vout = 5.5 V/0V - - +2 e Vv Tir-st port Vpp = 4.5 V, lon = - 0.7 MA 4.1 - - Output High Voltage Ore p == pp oF Vv Vou3 _|A19-0, D7-0, RD, WR Vpp = 4.5 V, low = 400 ys 24] - - Output Low Voltage Voir3 |A19-0, D7-0, RD, WR Vpp =4.5V, lol = 1.6mA - - 0.45 /) V | Except XOUT, P3, Vpp = 4.5 V, VoL =0.4V 1.6 Output Low Voltage Ott 119-0, D7-0, RD, WR pose ee Os , mA loc3[P3 Vpp =4.5V, VoL=1.0V - 20 - Supply Currentin Vpp =5.5V 15 20 NORMAL1, 2 mode Vin=5.3V/0.2V A m Supply Currentin fc = 12.5 MHz 6 8 IDLE1, 2 mode fs = 32.768 kHz Supply Currentin Vpp = 3.0V Pply lbp DD _ 30 60 SLOW mode Vin=2.8V/0.2V A Supply Currentin fs = 32.768 kHz 15 30 e SLEEP mode Supply Currentin Vpp =5.5V Pply DD _ 0.5 10 | pA STOP mode Vin=5.3V/0.2V Note1: Typical values show those at Top, = 25 C, Vop =5 V. Note2: Input current ty, ling : The current through pull-up or pull-down resistor is not included. Note3: IDD: Except for IREF. 3-60-129 1999-10-07TOSHIBA TMP88C060 A.C. Characteristics (1) (Vsg =O V, Vpp = 4.5 to 5.5 V, Topr= 40 to 85 C) (1)-@ Clock Parameter Symbol Conditions Min Typ. Max Unit In NORMAL1, 2 mode 0.32 - 4 . . In IDLE1, 2 mode Machine Cycle Time tcy es In SLOW mode 117.6 - 133.3 In SLEEP mode High Level Clock Pulse Width tweu For external clock operation (XIN input) 33.75 - - ns Low Level Clock Pulse Width twee fe = 12.5 MHz High Level Clock Pulse Width twsy | For external clock operation (XIN input) 14.7 - - ws Low Level Clack Pulse Width twsL fs = 32.768 kHz (1)-@ External Memory Interface Variable 12.5 MHz . Parameter Symbol - - Unit Min Max Min Max Address Setup to RD tarp 0.5t 30 - 10 - ns Address Setup to WR tawr 1.5t-30 - 90 - ns . troa Address Hold Time After RD / WR 0.5t- 35 - 5 - ns twra Address to Valid Data In tapi - 3.5t-95 - 185 ns RD to Valid Data In trops - 3.0t- 100 - 140 ns RD Low Pulse Width twrp 0.3t-40 - 200 - ns Input Data Hold After RD tRDDH 0 - 0 - ns WR Low Pulse Width twwr 2.0t 40 - 120 - ns Data Setup to WR tower 2.0t- 40 - 120 - ns Data Hold After WR twrbH 0.5t-35 - 5 - ns XIN to Address Delay txXINA - 140 - 140 ns XTIN to Address Delay txTinNa - 340 - 340 ns Note : t=tcy/4(t=80 ns @ fc = 12.5 MHz) 3-60-130 1999-10-07TOSHIBA TMP88C060 (1)-@ Wait Variable 12.5 MHz . Parameter Symbol - - Unit Min Max Min Max Address Setup to WAIT tawtr - 1.5t- 100 - 20 ns Address Setup to WAIT tawtTrR 1.5t+20 - 140 - ns RD Setup to WAIT trowTF - 1.0t- 100 - -20 ns RD Setup to WAIT trowTR 1.0t +20 - 100 - ns WR Setup to WAIT twrwtTR 20 - 20 - ns Address Valid to CLK tacik - 4.0t+35 - 355 ns t CLK Pulse Width Wok 2.0t-50 - 110 - ns tweLkH CLK Set up to WAIT teLKwT - 1.5t-70 - 50 ns Note: t=tcy/4(t =80 ns @ fe = 12.5 MHz) (1)-@ Bus Arbitration Variable 12.5 MHz \ Parameter Symbol - - Unit Min Max Min Max Bus Floating to BUSAK terak 0.5t- 30 - 10 - ns Period from BUSRQ to BUSAK tpack - 5.5t +30 - 470 ns Note 1: t=tcy/4(t=80ns @ fc = 12.5 MHz) Note 2: When the BUSRQ is set to "0" during Wait Cycle", the Bus will be released after the completion of "Wait Cycle. Note 3: When the BUSRQ is set to "0" just before interrupt request, the Bus will be released after the completion of current instruction execution and interrupt sequence. A.C. Meaurement Condition Output Level : High 2.2 V/ Low 0.8 V, CL= 100pF Input level : High 2.4 V / Low 0.4 V (D7 to DO) High 0.7 Vpp / Low 0.3 Vpp (WAIT) High 0.8 Vpp / Low 0.2 Vpp (Except D7 to DO and WAIT) 3-60-131 1999-10-07TOSHIBA TMP88C060 A.C. Charactiristics (Vsg = OV, Vpp = 2.7 to5.5V, Topr= 40 to 85 C) (2)-@ Clock Parameter Symbol Conditions Min Typ. Max Unit In NORMAL1, 2 mode 0.95 - 4 . . In IDLE1, 2 mode Machine Cycle Time tcy es In SLOW mode 117.6 - 133.3 In SLEEP mode High Level Clock Pulse Width tweu For external clock operation (XIN input) 110 - - ns Low Level Clock Pulse Width twee fc = 4.2 MHz High Level Clock Pulse Width twsy | For external clock operation (XTIN input) 14.7 - - ws Low Level Clack Pulse Width twsL fs = 32.768 kHz (2)-@ External Memory Interface Variable 4.2 MHz . Parameter Symbol ; ; Unit Min Max Min Max Address Setup to RD tarp 0.5t- 110 - 9 - ns Address Setup to WD tawr 1.5t- 120 - 237 - ns . aS trpa Address Hold Time After RD / WR 0.5t- 110 - 9 - ns twra Address to Valid Data In tapi - 3.5t- 270 - 563 ns RD to Valid Data In trops - 3.0t- 205 - 509 ns RD Low Pulse Width twrp 3.0t- 40 - 674 - ns Input Data Hold After RD tropH 0 - 0 - ns WR Low Pulse Width twwre 2.0t- 85 - 391 - ns Data Setup to WR tower 2.0t-50 - 426 - ns Data Hold After WR twrou | 0.5t- 110 - 9 - ns Note : t=tcy/4 (t =238 ns @ fc = 4.2 MHz) 3-60-132 1999-10-07TOSHIBA TMP88C060 (2)-@ Wait Variable 4.2 MHz . Parameter Symbol - - Unit Min Max Min Max Address Setup to WAIT tawtF - 1.5t-257 - 100 ns Address Setup to WAIT tawtTR 1.5t+ 125 - 482 - ns RD Setup to WAIT trowTr - 1.0t- 165 - 73 ns RD Setup to WAIT trowtr | 1.0t+125 - 363 - ns WR Setup to WAIT twrwtrR 50 - 50 - ns Address Valid to CLK tacik - 4.0t+70 - 1022 ns t CLK Pulse Width Wek 1 2 0t- 118 - 358 - ns tweLkH CLK Set up to WAIT tekwt = 1.5t- 170 - 187 ns Note: t=tcy/4(t =238 ns @ fc = 4.2 MHz) (2)-@ Bus Arbitration Variable 4.2 MHz . Parameter Symbol ; ; Unit Min Max Min Max Bus Floating to BUSAK tBrak 0.5t- 109 - 10 - ns Period from BUSRQ to BUSAK tpack - 5.5t+ 109 - 1200 ns Note 1: t=tcy/4 (t=238 ns @ fc = 4.2 MHz) Note 2: When the BUSRQ is set to "0" during Wait Cycle, the Bus will be released after the completion of "Wait Cycle. Note 3: When the BUSRQ is set to "0" just before interrupt request, the Bus will be released after the completion of current instruction execution and interrupt sequence. A.C. Meaurement Condition Output Level : High0.7 Vpp/ Low 0.3 Vpp, CL = 100 pF Input level : High 0.9 Vpp/ Low 0.1 Vpp 3-60-133 1999-10-07TOSHIBA TMP88C060 A/D Conversion Characteristics (Topr = - 40 to 85 C) Parameter Symbol Conditions Min Typ. Max Unit VAREF Vpp- 1.5 - Vpp Analog Reference Voltage V Vass Vss - Vss Analog Reference Voltage AVaree 25 _ _ v Range Analog Input Voltage VaIN Vass - VAREF Vv Vpp = AVDD = VAREF=5.5V Analog Supply Current I - 0.5 1.0 mA nateg -upPly REF | vss = AVSS = VASS = 0.0V Non-Linearity Error Vop = 5.0 to 5.5 V, Vsg = 0.0V - - #2 Zero Point Error AVDD = VAREF = 5.000 V - - +2 AVSS = VASS = 0.000 V LSB Full Scale Error low Speed Conversion (58.9 15, - ~ +2 Total Error @ 12.5 MHz) - - +4 Non-Linearity Error Vpp = 2.7 to 5.5 V, Vss = 0.0V - - +2 Zero Point Error AVDD = VAREF = 2.700V - - +2 AVSS = VASS = 0.000 V LSB Full Scale Error Hihg speed conversion (43.7 1s, ~ ~ +2 Total Error @4.2 Mhz) - - +4 Note. AVarer = Varer Vass 3-60-134 1999-10-07TOSHIBA TMP88C060 Timing Chart (1) Read Cycle XIN XTIN A19to0 D7 ta DO (2) Write Cycle XIN XTIN A19to0 D7 to DO i) rr A tite | twsL tweL | tweH twsH tXINA tXTINA ~S YPN NS VS x. TN tarp twep troa. tapi trpops > ltRDDH Input data VS NS NS NS NS x tawre twwr twra ' \ TowR twrDH Data output 4 TWCLKL tweLKH \ 3-60-135 1999-10-07TOSHIBA TMP88C060 (3) Wait Timing ae c ir 7 7 AI9t00 x CC c x a} d?} tawtTR ae ae WAIT \ A rd A 7 tawtr SS tRowTE. __ errr t RD RDWTR J N. 3 we wa ~<a} twRWTR teLKWwT teLkwT | A 0 aA J - (4) Bus Arbitation teack A19to0 _xX Pp ---___----~~-- D7 to 0 ----< y Po rr ry A [| -----_-------- 3-60-136 1999-10-07