Intel(R) Cyclone(R) 10 GX Device Datasheet Subscribe Send Feedback C10GX51002 | 2018.06.15 Latest document on the web: PDF | HTML Contents Contents Intel(R) Cyclone(R) 10 GX Device Datasheet....................................................................................................................................3 Electrical Characteristics...................................................................................................................................................... 3 Operating Conditions.................................................................................................................................................. 3 Switching Characteristics....................................................................................................................................................21 Transceiver Performance Specifications....................................................................................................................... 21 Core Performance Specifications.................................................................................................................................29 Periphery Performance Specifications.......................................................................................................................... 36 Configuration Specifications................................................................................................................................................ 44 POR Specifications....................................................................................................................................................44 JTAG Configuration Timing.........................................................................................................................................45 FPP Configuration Timing.......................................................................................................................................... 45 AS Configuration Timing............................................................................................................................................49 DCLK Frequency Specification in the AS Configuration Scheme....................................................................................... 50 PS Configuration Timing............................................................................................................................................50 Initialization............................................................................................................................................................ 52 Configuration Files....................................................................................................................................................52 Minimum Configuration Time Estimation......................................................................................................................54 Remote System Upgrades......................................................................................................................................... 55 User Watchdog Internal Circuitry Timing Specifications..................................................................................................55 I/O Timing....................................................................................................................................................................... 55 Programmable IOE Delay................................................................................................................................................... 56 Glossary.......................................................................................................................................................................... 56 Document Revision History for the Intel Cyclone 10 GX Device Datasheet................................................................................. 60 Intel(R) Cyclone(R) 10 GX Device Datasheet 2 C10GX51002 | 2018.06.15 Intel(R) Cyclone(R) 10 GX Device Datasheet This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Intel(R) Cyclone(R) 10 GX devices. Intel Cyclone 10 GX devices are offered in extended and industrial grades. Extended devices are offered in -E5 (fastest) and - E6 speed grades. Industrial grade devices are offered in the -I5 and -I6 speed grades. Related Information Intel Cyclone 10 GX Device Overview Provides more information about the densities and packages in the Intel Cyclone 10 GX devices. Electrical Characteristics The following sections describe the operating conditions and power consumption of Intel Cyclone 10 GX devices. Operating Conditions Intel Cyclone 10 GX devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Intel Cyclone 10 GX devices, you must consider the operating requirements described in this section. Absolute Maximum Ratings This section defines the maximum operating conditions for Intel Cyclone 10 GX devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions. Caution: Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Table 1. Absolute Maximum Ratings for Intel Cyclone 10 GX Devices Symbol Description Condition Minimum Maximum Unit VCC Core voltage power supply -- -0.50 1.21 V VCCP Periphery circuitry and transceiver fabric interface power supply -- -0.50 1.21 V VCCERAM Embedded memory power supply -- -0.50 1.36 V VCCPT Power supply for programmable power technology and I/O pre-driver -- -0.50 2.46 V VCCBAT Battery back-up power supply for design security volatile key register -- -0.50 2.46 V VCCPGM Configuration pins power supply (1) -0.50 2.46 V VCCIO I/O buffers power supply 3 V I/O -0.50 4.10 V LVDS I/O -0.50 2.46 V VCCA_PLL Phase-locked loop (PLL) analog power supply -- -0.50 2.46 V VCCT_GXB Transmitter power supply -- -0.50 1.34 V VCCR_GXB Receiver power supply -- -0.50 1.34 V VCCH_GXB Transceiver output buffer power supply -- -0.50 2.46 V continued... (1) The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os. Intel(R) Cyclone(R) 10 GX Device Datasheet 4 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol Description Condition Minimum -25 Maximum Unit 25 mA (2)(3)(4)(5) IOUT DC output current per pin -- TJ Operating junction temperature -- -55 125 C TSTG Storage temperature (no bias) -- -65 150 C (6) Related Information * AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 Devices Provides the power sequencing requirements for Intel Cyclone 10 GX devices. * Power-Up and Power-Down Sequences, Power Management in Intel Cyclone 10 GX Devices chapter Provides the power sequencing requirements for Intel Cyclone 10 GX devices. Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns. The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 2.70 V for LVDS I/O can only be at 2.70 V for ~4% over the lifetime of the device. (2) The maximum current allowed through any LVDS I/O bank pin when the device is not turned on or during power-up/power-down conditions is 10 mA. (3) Total current per LVDS I/O bank must not exceed 100 mA. (4) Voltage level must not exceed 1.89 V. (5) Applies to all I/O standards and settings supported by LVDS I/O banks, including single-ended and differential I/Os. (6) Applies only to LVDS I/O banks. 3 V I/O banks are not covered under this specification and must be implemented as per the power sequencing requirement. For more details, refer to AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria(R) 10, and Intel Stratix(R) 10 Devices and Power Management in Intel Cyclone 10 GX Devices chapter. Intel(R) Cyclone(R) 10 GX Device Datasheet 5 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Table 2. Maximum Allowed Overshoot During Transitions for Intel Cyclone 10 GX Devices This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. The LVDS I/O values are applicable to the VREFP_ADC and VREFN_ADC I/O pins. Symbol Description Condition (V) LVDS I/O Vi (AC) AC input voltage (7) Overshoot Duration as % at TJ = 100C Unit 3 V I/O 2.50 3.80 100 % 2.55 3.85 42 % 2.60 3.90 18 % 2.65 3.95 9 % 2.70 4.00 4 % > 2.70 > 4.00 No overshoot allowed % For an overshoot of 2.5 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) x 100. This 10-year period assumes that the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. (7) The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os. Intel(R) Cyclone(R) 10 GX Device Datasheet 6 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Figure 1. Intel Cyclone 10 GX Devices Overshoot Duration 2.71 V 2.7V 1.8 V DT T Recommended Operating Conditions This section lists the functional operation limits for the AC and DC parameters for Intel Cyclone 10 GX devices. Recommended Operating Conditions Table 3. Recommended Operating Conditions for Intel Cyclone 10 GX Devices This table lists the steady-state voltage values expected from Intel Cyclone 10 GX devices. Power supply ramps must all be strictly monotonic, without plateaus. Symbol Description Condition Minimum (8) Typical Maximum (8) Unit VCC Core voltage power supply -- 0.87 0.9 0.93 V VCCP Periphery circuitry and transceiver fabric interface power supply -- 0.87 0.9 0.93 V VCCPGM Configuration pins power supply 1.8 V 1.71 1.8 1.89 V 1.5 V 1.425 1.5 1.575 V continued... (8) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. Intel(R) Cyclone(R) 10 GX Device Datasheet 7 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol Description Condition Minimum (8) Typical Maximum (8) Unit 1.2 V 1.14 1.2 1.26 V Embedded memory power supply 0.9 V 0.87 0.9 0.93 V Battery back-up power supply (For design security volatile key register) 1.8 V 1.71 1.8 1.89 V 1.2 V 1.14 1.2 1.26 V VCCPT Power supply for programmable power technology and I/O pre-driver 1.8 V 1.71 1.8 1.89 V VCCIO I/O buffers power supply 3.0 V (for 3 V I/O only) 2.85 3.0 3.15 V 2.5 V (for 3 V I/O only) 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V 1.5 V 1.425 1.5 1.575 V 1.35 V (10) 1.35 (10) V 1.25 V 1.19 1.25 1.31 V 1.2 V (10) 1.2 (10) V VCCERAM VCCBAT (9) VCCA_PLL PLL analog voltage regulator power supply -- 1.71 1.8 1.89 V VREFP_ADC Precision voltage reference for voltage sensor -- 1.2475 1.25 1.2525 V continued... (8) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (9) If you do not use the design security feature in Intel Cyclone 10 GX devices, connect VCCBAT to a 1.5-V to 1.8-V power supply. Intel Cyclone 10 GX power-on reset (POR) circuitry monitors VCCBAT. Intel Cyclone 10 GX devices do not exit POR if VCCBAT is not powered up. (10) For minimum and maximum voltage values, refer to the I/O Standard Specifications section. Intel(R) Cyclone(R) 10 GX Device Datasheet 8 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol VI (11)(12) Description DC input voltage VO Output voltage TJ Operating junction temperature tRAMP (13) Power supply ramp time Condition Minimum (8) Typical Maximum (8) Unit 3 V I/O -0.3 -- 3.3 V LVDS I/O -0.3 -- 2.19 V -- 0 -- VCCIO V Extended 0 -- 100 C Industrial -40 -- 100 C Standard POR 200 s -- 100 ms -- Fast POR 200 s -- 4 ms -- Related Information I/O Standard Specifications on page 15 Transceiver Power Supply Operating Conditions Table 4. Transceiver Power Supply Operating Conditions for Intel Cyclone 10 GX Devices Symbol VCCT_GXB[L1][C,D] Description Transmitter power supply Condition Chip-to-chip 12.5 Gbps Or Minimum (14) 1.0 Typical Maximum 1.03 (14) Unit 1.06 V continued... (8) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (11) The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os. (12) This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value. (13) tramp is the ramp time of each individual power supply, not the ramp time of all combined power supplies. (14) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. Intel(R) Cyclone(R) 10 GX Device Datasheet 9 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol Description Condition Minimum (14) Typical Maximum (14) Unit Backplane 6.6 Gbps VCCR_GXB[L1][C,D] Receiver power supply VCCH_GXBL Transceiver output buffer power supply Chip-to-chip 11.3 Gbps 0.92 0.95 0.98 V Chip-to-chip 12.5 Gbps Or Backplane 6.6 Gbps 1.0 1.03 1.06 V Chip-to-chip 11.3 Gbps 0.92 0.95 0.98 V 1.710 1.8 1.890 V -- Related Information * Transceiver Performance for Intel Cyclone 10 GX Devices on page 21 * Intel Cyclone 10 GX Pin Connection Guidelines DC Characteristics Supply Current and Power Consumption Intel offers two ways to estimate power for your design--the Excel-based Early Power Estimator (EPE) and the Intel Quartus(R) Prime Power Analyzer feature. Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources. The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates. (14) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. Intel(R) Cyclone(R) 10 GX Device Datasheet 10 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Related Information * Early Power Estimator User Guide Provides more information about power estimation tools. * Power Analysis and Optimization User Guide: Intel Quartus Prime Pro Edition Provides more information about power estimation tools. I/O Pin Leakage Current Table 5. I/O Pin Leakage Current for Intel Cyclone 10 GX Devices If VO = VCCIO to VCCIOMAX, 300 A of leakage current per I/O is expected. Symbol Description Condition Min Max Unit II Input pin VI = 0 V to VCCIOMAX -80 80 A IOZ Tri-stated I/O pin VO = 0 V to VCCIOMAX -80 80 A Bus Hold Specifications The bus-hold trip points are based on calculated input voltages from the JEDEC standard. Table 6. Bus Hold Parameters for Intel Cyclone 10 GX Devices Parameter Symbol Condition VCCIO (V) 1.2 Min Bus-hold, low, sustaining current ISUSL VIN > VIL (max) Bus-hold, high, sustaining current ISUSH VIN < VIH (min) 1.5 Max (15), 8 26 (16) -8 (15), -26 (16) -- -- Min 12 32 (15), (16) -12 (15), -32 (16) Unit 1.8 Max -- -- Min 30 55 (15), (16) -30 (15), -55 (16) 2.5 3.0 Max Min Max Min Max -- 60 -- 70 -- A -- -60 -- -70 -- A continued... (15) This value is only applicable for LVDS I/O bank. (16) This value is only applicable for 3 V I/O bank. Intel(R) Cyclone(R) 10 GX Device Datasheet 11 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Parameter Symbol Condition VCCIO (V) 1.2 1.5 Unit 1.8 2.5 3.0 Min Max Min Max Min Max Min Max Min Max Bus-hold, low, overdrive current IODL 0 V < VIN < VCCIO -- 125 -- 175 -- 200 -- 300 -- 500 A Bus-hold, high, overdrive current IODH 0 V < VIN < VCCIO -- -125 -- -175 -- -200 -- -300 -- -500 A Bus-hold trip point VTRIP -- 0.3 0.9 0.38 1.13 0.68 1.07 0.70 1.7 0.8 2 V OCT Calibration Accuracy Specifications If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block. Table 7. OCT Calibration Accuracy Specifications for Intel Cyclone 10 GX Devices Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change. Symbol Description Condition (V) Resistance Tolerance -E5, -I5 -E6, -I6 Unit 25- and 50- RS Internal series termination with calibration (25 and 50- setting) VCCIO = 1.8, 1.5, 1.2 15 15 % 34- and 40- RS Internal series termination with calibration (34 and 40- setting) VCCIO = 1.5, 1.25, 1.2 15 15 % VCCIO = 1.35 20 20 % 48-, 60-, 80-, and 120- RS Internal series termination with calibration (48, 60-, 80-, and 120- setting) VCCIO = 1.2 15 15 % 240- RS Internal series termination with calibration (240- setting) VCCIO = 1.2 20 20 % 30- RT Internal parallel termination with calibration (30- setting) VCCIO = 1.5, 1.35, 1.25 -10 to +40 -10 to +40 % 34-, 48-, 80-, and 240- RT Internal parallel termination with calibration (34-, 48-, 80-, and 240- setting) VCCIO = 1.2 15 15 % continued... Intel(R) Cyclone(R) 10 GX Device Datasheet 12 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol 40-, 60-, and 120- RT 80- RT Description Condition (V) Resistance Tolerance -E5, -I5 -E6, -I6 Unit Internal parallel termination with calibration (40-, 60-, and 120- setting) VCCIO = 1.5, 1.35, 1.25, 1.2 -10 to +40 -10 to +40 % (17) 15 15 % Internal parallel termination with calibration (80- setting) VCCIO = 1.2 15 15 % VCCIO = 1.2 Related Information I/O Standards Support in Intel Cyclone 10 GX Devices OCT Without Calibration Resistance Tolerance Specifications Table 8. OCT Without Calibration Resistance Tolerance Specifications for Intel Cyclone 10 GX Devices This table lists the Intel Cyclone 10 GX OCT without calibration resistance tolerance to PVT changes. Symbol 25- and 50- RS (17) Description Internal series termination without calibration (25- and 50- setting) Condition (V) Resistance Tolerance Unit -E5, -I5 -E6, -I6 VCCIO = 3.0, 2.5 40 40 % VCCIO = 1.8, 1.5, 1.2 50 50 % 34- and 40- RS Internal series termination without calibration (34- and 40- setting) VCCIO = 1.5, 1.35, 1.25, 1.2 50 50 % 48- and 60- RS Internal series termination without calibration (48- and 60- setting) VCCIO = 1.2 50 50 % 120- Rs Internal series termination without calibration (120- setting) VCCIO = 1.2 50 50 % 100- RD Internal differential termination (100- setting) VCCIO = 1.8 35 40 % Only applicable to POD12 I/O standard. Intel(R) Cyclone(R) 10 GX Device Datasheet 13 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Pin Capacitance Table 9. Pin Capacitance for Intel Cyclone 10 GX Devices Maximum Unit CIO_COLUMN Symbol Input capacitance on column I/O pins Description 2.5 pF COUTFB Input capacitance on dual-purpose clock output/feedback pins 2.5 pF Internal Weak Pull-Up and Weak Pull-Down Resistor All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. The weak pull-down feature is only available for the pins as described in the Internal Weak Pull-Down Resistor Values for Intel Cyclone 10 GX Devices table. Table 10. Internal Weak Pull-Up Resistor Values for Intel Cyclone 10 GX Devices Symbol RPU Description Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. Condition (V) (18) (19) Unit VCCIO = 3.0 5% 25 k VCCIO = 2.5 5% 25 k VCCIO = 1.8 5% 25 k VCCIO = 1.5 5% 25 k VCCIO = 1.35 5% 25 k VCCIO = 1.25 5% 25 k VCCIO = 1.2 5% 25 k (18) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. (19) Valid with 25% tolerances to cover changes over PVT. Intel(R) Cyclone(R) 10 GX Device Datasheet 14 Value Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Table 11. Internal Weak Pull-Down Resistor Values for Intel Cyclone 10 GX Devices Pin Name Description Condition (V) Value (19) Unit nIO_PULLUP Dedicated input pin that determines the internal pull-ups on user I/O pins and dual-purpose I/O pins. VCC = 0.9 3.33% 25 k TCK Dedicated JTAG test clock input pin. VCCPGM = 1.8 5 % 25 k VCCPGM = 1.5 5% 25 k VCCPGM = 1.2 5% 25 k VCCPGM = 1.8 5% 25 k VCCPGM = 1.5 5% 25 k VCCPGM = 1.2 5% 25 k MSEL[0:2] Configuration input pins that set the configuration scheme for the FPGA device. Related Information Intel Cyclone 10 GX Device Family Pin Connection Guidelines Provides more information about the pins that support internal weak pull-up and internal weak pull-down features. I/O Standard Specifications Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Intel Cyclone 10 GX devices. For minimum voltage values, use the minimum VCCIO values. For maximum voltage values, use the maximum VCCIO values. You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. Related Information Recommended Operating Conditions on page 7 Intel(R) Cyclone(R) 10 GX Device Datasheet 15 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Single-Ended I/O Standards Specifications Table 12. Single-Ended I/O Standards Specifications for Intel Cyclone 10 GX Devices I/O Standard VCCIO (V) VIL (V) VIH (V) VOL (V) VOH (V) IOL (20) (mA) IOH (20) (mA) Min Typ Max Min Max Min Max Max Min 3.0-V LVTTL 2.85 3 3.15 -0.3 0.8 1.7 3.3 0.4 2.4 2 -2 3.0-V LVCMOS 2.85 3 3.15 -0.3 0.8 1.7 3.3 0.2 VCCIO - 0.2 0.1 -0.1 2.5 V 2.375 2.5 2.625 -0.3 0.7 1.7 3.3 0.4 2 1 -1 1.8 V 1.71 1.8 1.89 -0.3 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.45 VCCIO - 0.45 2 -2 1.5 V 1.425 1.5 1.575 -0.3 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO 2 -2 1.2 V 1.14 1.2 1.26 -0.3 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO 2 -2 Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Table 13. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel Cyclone 10 GX Devices I/O Standard VCCIO (V) VREF (V) VTT (V) Min Typ Max Min Typ Max Min Typ Max SSTL-18 Class I, II 1.71 1.8 1.89 0.833 0.9 0.969 VREF - 0.04 VREF VREF + 0.04 SSTL-15 Class I, II 1.425 1.5 1.575 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO SSTL-135/ SSTL-135 Class I, II 1.283 1.35 1.418 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO SSTL-125/ SSTL-125 Class I, II 1.19 1.25 1.31 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO SSTL-12/ SSTL-12 Class I, II 1.14 1.2 1.26 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO continued... (20) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 3.0-V LVTTL specification (2 mA), you should set the current strength settings to 2 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the datasheet. Intel(R) Cyclone(R) 10 GX Device Datasheet 16 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 I/O Standard VCCIO (V) VREF (V) VTT (V) Min Typ Max Min Typ Max Min Typ Max HSTL-18 Class I, II 1.71 1.8 1.89 0.85 0.9 0.95 -- VCCIO/2 -- HSTL-15 Class I, II 1.425 1.5 1.575 0.68 0.75 0.9 -- VCCIO/2 -- HSTL-12 Class I, II 1.14 1.2 1.26 0.47 x VCCIO 0.5 x VCCIO 0.53 x VCCIO -- VCCIO/2 -- HSUL-12 1.14 1.2 1.3 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO -- -- -- POD12 1.16 1.2 1.24 0.69 x VCCIO 0.7 x VCCIO 0.71 x VCCIO -- VCCIO -- Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Table 14. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel Cyclone 10 GX Devices I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL (21) IOH (21) (mA) (mA) Min Max Min Max Max Min Max Min SSTL-18 Class I -0.3 VREF -0.125 VREF + 0.125 VCCIO + 0.3 VREF - 0.25 VREF + 0.25 VTT - 0.603 VTT + 0.603 6.7 -6.7 SSTL-18 Class II -0.3 VREF -0.125 VREF + 0.125 VCCIO + 0.3 VREF - 0.25 VREF + 0.25 0.28 VCCIO -0.28 13.4 -13.4 SSTL-15 Class I -- VREF - 0.1 VREF + 0.1 -- VREF - 0.175 VREF + 0.175 0.2 x VCCIO 0.8 x VCCIO 8 -8 SSTL-15 Class II -- VREF - 0.1 VREF + 0.1 -- VREF - 0.175 VREF + 0.175 0.2 x VCCIO 0.8 x VCCIO 16 -16 SSTL-135/ SSTL-135 Class I, II -- VREF - 0.09 VREF + 0.09 -- VREF - 0.16 VREF + 0.16 0.2 x VCCIO 0.8 x VCCIO -- -- SSTL-125/ SSTL-125 Class I, II -- VREF - 0.09 VREF + 0.09 -- VREF - 0.15 VREF + 0.15 0.2 x VCCIO 0.8 x VCCIO -- -- continued... (21) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the datasheet. Intel(R) Cyclone(R) 10 GX Device Datasheet 17 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL (21) IOH (21) (mA) (mA) Min Max Min Max Max Min Max Min SSTL-12/ SSTL-12 Class I, II -- VREF - 0.10 VREF + 0.10 -- VREF - 0.15 VREF + 0.15 0.2 x VCCIO 0.8 x VCCIO -- -- HSTL-18 Class I -- VREF -0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 8 -8 HSTL-18 Class II -- VREF - 0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 16 -16 HSTL-15 Class I -- VREF - 0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO - 0.4 8 -8 HSTL-15 Class II -- VREF - 0.1 VREF + 0.1 -- VREF - 0.2 VREF + 0.2 0.4 VCCIO -0.4 16 -16 HSTL-12 Class I -0.15 VREF - 0.08 VREF + 0.08 VCCIO + 0.15 VREF - 0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO 8 -8 HSTL-12 Class II -0.15 VREF - 0.08 VREF + 0.08 VCCIO + 0.15 VREF - 0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO 16 -16 -- VREF - 0.13 VREF + 0.13 -- VREF - 0.22 VREF + 0.22 0.1 x VCCIO 0.9 x VCCIO -- -- -0.15 VREF - 0.08 VREF + 0.08 VCCIO + 0.15 VREF - 0.15 VREF + 0.15 (0.7 - 0.15) x VCCIO (0.7 + 0.15) x VCCIO -- -- HSUL-12 POD12 Differential SSTL I/O Standards Specifications Table 15. Differential SSTL I/O Standards Specifications for Intel Cyclone 10 GX Devices I/O Standard VCCIO (V) VSWING(DC) (V) VSWING(AC) (V) VIX(AC) (V) Min Typ Max Min Max Min Max Min Typ Max SSTL-18 Class I, II 1.71 1.8 1.89 0.25 VCCIO + 0.6 0.5 VCCIO + 0.6 VCCIO/2 - 0.175 -- VCCIO/2 + 0.175 SSTL-15 Class I, II 1.425 1.5 1.575 0.2 (22) 2(VIH(AC) - VREF) 2(VREF - VIL(AC)) VCCIO/2 - 0.15 -- VCCIO/2 + 0.15 continued... (21) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the datasheet. Intel(R) Cyclone(R) 10 GX Device Datasheet 18 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 I/O Standard VCCIO (V) Min Typ VSWING(DC) (V) Max VSWING(AC) (V) VIX(AC) (V) Min Max Min Max Min Typ Max 2(VIH(AC) - VREF) 2(VIL(AC) - VREF) VCCIO/2 - 0.15 VCCIO/2 VCCIO/2 + 0.15 SSTL-135/ SSTL-135 Class I, II 1.283 1.35 1.45 0.18 (22) SSTL-125/ SSTL-125 Class I, II 1.19 1.25 1.31 0.18 (22) 2(VIH(AC) - VREF) 2(VIL(AC) - VREF) VCCIO/2 - 0.15 VCCIO/2 VCCIO/2 + 0.15 SSTL-12/ SSTL-12 Class I, II 1.14 1.2 1.26 0.16 (22) 2(VIH(AC) - VREF) 2(VIL(AC) - VREF) VREF - 0.15 VCCIO/2 VREF + 0.15 POD12 1.16 1.2 1.24 0.16 -- 0.3 -- VREF - 0.08 -- VREF + 0.08 Differential HSTL and HSUL I/O Standards Specifications Table 16. Differential HSTL and HSUL I/O Standards Specifications for Intel Cyclone 10 GX Devices I/O Standard (22) VCCIO (V) VDIF(DC) (V) VDIF(AC) (V) VIX(AC) (V) VCM(DC) (V) Min Typ Max Min Max Min Max Min Typ Max Min Typ Max HSTL-18 Class I, II 1.71 1.8 1.89 0.2 -- 0.4 -- 0.78 -- 1.12 0.78 -- 1.12 HSTL-15 Class I, II 1.425 1.5 1.575 0.2 -- 0.4 -- 0.68 -- 0.9 0.68 -- 0.9 HSTL-12 Class I, II 1.14 1.2 1.26 0.16 VCCIO + 0.3 0.3 VCCIO + 0.48 -- 0.5 x VCCIO -- 0.4 x VCCIO 0.5 x VCCIO 0.6 x VCCIO HSUL-12 1.14 1.2 1.3 2(VIH(DC) - VREF) 2(VREF - VIH(DC)) 2(VIH(AC) - VREF) 2(VREF - VIH(AC)) 0.5 x VCCIO - 0.12 0.5 x VCCIO 0.5 x VCCIO +0.12 0.4 x VCCIO 0.5 x VCCIO 0.6 x VCCIO The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC) and VIL(DC)). Intel(R) Cyclone(R) 10 GX Device Datasheet 19 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Differential I/O Standards Specifications Table 17. Differential I/O Standards Specifications for Intel Cyclone 10 GX Devices Differential inputs are powered by VCCPT which requires 1.8 V. I/O Standard LVDS (25) RSDS (HIO) Mini-LVDS (HIO) (27) LVPECL (28) (26) VCCIO (V) VID (mV) (23) VICM(DC) (V) VOD (V) (24) VOCM (V) (24) Min Typ Max Min Condition Max Min Condition Max Min Typ Max Min Typ Max 1.71 1.8 1.89 100 VCM = 1.25 V -- 0 DMAX 700 Mbps 1.85 0.247 -- 0.6 1.125 1.25 1.375 1 DMAX >700 Mbps 1.6 1.71 1.8 1.89 100 VCM = 1.25 V -- 0.3 -- 1.4 0.1 0.2 0.6 0.5 1.2 1.4 1.71 1.8 1.89 200 -- 600 0.4 -- 1.325 0.25 -- 0.6 1 1.2 1.4 1.71 1.8 1.89 300 -- -- 0.6 DMAX 700 Mbps 1.7 -- -- -- -- -- -- 1 DMAX >700 Mbps 1.6 Related Information Transceiver Specifications for Intel Cyclone 10 GX Devices on page 22 Provides the specifications for transmitter, receiver, and reference clock I/O pin. (23) The minimum VID value is applicable over the entire common mode range, VCM. (24) RL range: 90 RL 110 . (25) For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 700 Mbps and 0 V to 1.85 V for data rates below 700 Mbps. (26) For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V. (27) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.425 V. (28) For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and 0.45 V to 1.95 V for data rates below 700 Mbps. Intel(R) Cyclone(R) 10 GX Device Datasheet 20 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Switching Characteristics This section provides the performance characteristics of Intel Cyclone 10 GX core and periphery blocks for extended grade devices. Transceiver Performance Specifications Transceiver Performance for Intel Cyclone 10 GX Devices Table 18. Transmitter and Receiver Data Rate Performance Symbol/Description Chip-to-Chip (29) Condition Datarate Unit Maximum data rate VCCR_GXB = VCCT_GXB = 1.03 V 12.5 Gbps Maximum data rate VCCR_GXB = VCCT_GXB = 0.95 V 11.3 Gbps Minimum Data Rate 1.0 Maximum data rate VCCR_GXB = VCCT_GXB = 1.03 V Backplane 6.6 Minimum Data Rate Table 19. (30) 1.0 (30) Gbps Gbps Gbps ATX PLL and Fractional PLL (fPLL) Performance Symbol/Description Supported Output Frequency Condition Frequency Unit Maximum Frequency 6.25 GHz Minimum Frequency 500 MHz (29) Chip-to-chip links are applications with short reach channels. (30) Intel Cyclone 10 GX transceivers can support data rates down to 125 Mbps with over sampling. You must create your own over sampling logic. Intel(R) Cyclone(R) 10 GX Device Datasheet 21 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Table 20. CMU PLL Performance Symbol/Description Supported Output Frequency Condition Frequency Unit Maximum Frequency 5.15625 GHz Minimum Frequency 2450 MHz Related Information Transceiver Power Supply Operating Conditions on page 9 High-Speed Serial Transceiver-Fabric Interface Performance for Intel Cyclone 10 GX Devices Table 21. High-Speed Serial Transceiver-Fabric Interface Performance for Intel Cyclone 10 GX Devices The frequencies listed are the maximum frequencies. Symbol/Description Condition (V) Core Speed Grade Unit -5 -6 20-bit interface - FIFO VCC = 0.9 400 400 MHz 20-bit interface - Registered VCC = 0.9 400 400 MHz 32-bit interface - FIFO VCC = 0.9 404 335 MHz 32-bit interface - Registered VCC = 0.9 404 335 MHz 64-bit interface - FIFO VCC = 0.9 234 222 MHz 64-bit interface - Registered VCC = 0.9 234 222 MHz Transceiver Specifications for Intel Cyclone 10 GX Devices Table 22. Reference Clock Specifications Symbol/Description Supported I/O Standards Condition Dedicated reference clock pin RX pin as a reference clock Min Typ Max CML, Differential LVPECL, LVDS, and HCSL Unit (31) CML, Differential LVPECL, and LVDS continued... (31) HCSL is only supported for PCIe. Intel(R) Cyclone(R) 10 GX Device Datasheet 22 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol/Description Condition Min Typ Max Unit Input Reference Clock Frequency (CMU PLL) 61 -- 800 MHz Input Reference Clock Frequency (ATX PLL) 100 -- 800 MHz -- 800 MHz Input Reference Clock Frequency (fPLL PLL) 25 (32) / 50 Rise time 20% to 80% -- -- 400 ps Fall time 80% to 20% -- -- 400 ps Duty cycle -- 45 -- 55 % Spread-spectrum modulating clock frequency PCIe 30 -- 33 kHz Spread-spectrum downspread PCIe -- 0 to -0.5 -- % On-chip termination resistors -- -- 100 -- Absolute VMAX Dedicated reference clock pin -- -- 1.6 V RX pin as a reference clock -- -- 1.2 V Absolute VMIN -- -0.4 -- -- V Peak-to-peak differential input voltage -- 200 -- 1600 mV VICM (AC coupled) VCCR_GXB = 0.95 V -- 0.95 -- V VCCR_GXB = 1.03 V -- 1.03 -- V 250 -- 550 mV 100 Hz -- -- -70 dBc/Hz 1 kHz -- -- -90 VICM (DC coupled) Transmitter REFCLK Phase Noise (622 MHz) HCSL I/O standard for PCIe reference clock (33) dBc/Hz continued... (32) 25 MHz is for HDMI applications only. (33) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 622 MHz + 20*log(f/622). Intel(R) Cyclone(R) 10 GX Device Datasheet 23 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol/Description Min Typ Max Unit 10 kHz -- -- -100 dBc/Hz 100 kHz -- -- -110 dBc/Hz 1 MHz -- -- -120 dBc/Hz Transmitter REFCLK Phase Jitter (100 MHz) 1.5 MHz to 100 MHz (PCIe) -- -- 4.2 ps (rms) RREF -- -- 2.0 k 1% -- Maximum rate of change of the reference clock frequency TSSC-MAX-PERIOD-SLEW (34) 0.75 ps/UI Max SSC df/dt Table 23. Transceiver Clocks Specifications Symbol/Description CLKUSR pin for transceiver calibration reconfig_clk Table 24. Condition Condition Min Typ Max Unit Transceiver Calibration 100 -- 125 MHz Reconfiguration interface 100 -- 125 MHz Channel Span Unit Transceiver Clock Network Maximum Data Rate Specifications Clock Network (34) Maximum Performance ATX fPLL CMU x1 12.5 12.5 10.3125 6 channels in a single bank Gbps x6 12.5 12.5 N/A 6 channels in a single bank Gbps PLL feedback compensation mode 12.5 12.5 N/A Side-wide Gbps xN at 1.03 V VCCR_GXB/ VCCT_GXB 12.5 12.5 N/A Side-wide Gbps xN at 0.95 V VCCR_GXB/ VCCT_GXB 10.5 10.5 N/A Side-wide Gbps Defined for worst case spread spectrum clock (SSC) modulation profile, such as Lexmark. Intel(R) Cyclone(R) 10 GX Device Datasheet 24 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Table 25. Receiver Specifications Symbol/Description Condition Min Typ Max Unit High Speed Differential I/O, CML , Differential LVPECL , and LVDS(35) Supported I/O Standards -- Absolute VMAX for a receiver pin (36) -- -- -- 1.2 V Absolute VMIN for a receiver pin (37) -- -0.4 -- -- V Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration -- -- -- 1.6 V VCCR_GXB = 0.95 V -- -- 2.4 V VCCR_GXB = 1.03 V -- -- 2.0 V -- 50 -- -- mV 85- setting -- 85 30% -- 100- setting -- 100 30% -- VCCR_GXB = 0.95 V -- 600 -- mV VCCR_GXB = 1.03 V -- 700 -- mV Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration Minimum differential eye opening at receiver serial input pins (38) Differential on-chip termination resistors VICM (AC and DC coupled) (39) continued... (35) CML, Differential LVPECL, and LVDS are only used on AC coupled links. (36) The device cannot tolerate prolonged operation at this absolute maximum. (37) The device cannot tolerate prolonged operation at this absolute minimum. (38) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. (39) Intel Cyclone 10 GX devices support DC coupling to other Intel Cyclone 10 GX devices and other devices with a transmitter that has matching common mode voltage. Intel(R) Cyclone(R) 10 GX Device Datasheet 25 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol/Description tLTR (40) tLTD(41) tLTD_manual(42) tLTR_LTD_manual(43) Run Length CDR PPM tolerance Programmable DC Gain Programmable AC Gain at High Gain mode and Data Rate 6 Gbps Table 26. Condition Min Typ Max Unit -- -- -- 10 s -- 4 -- -- s -- 4 -- -- s -- 15 -- -- s -- -- -- 200 UI -300 -- 300 PPM -1000 -- 1000 PPM Setting = 0-4 0 -- 10 dB Setting = 0-28 VCCR_GXB = 0.95 V 0 -- 19 dB Setting = 0-28 VCCR_GXB = 1.03 V 0 -- 21 dB Min Typ Max Unit PCIe-only All other protocols Transmitter Specifications Symbol/Description Condition Supported I/O Standards -- Differential on-chip termination resistors 85- setting High Speed Differential I/O -- 85 20% (44) -- -- continued... (40) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset. (41) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high. (42) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode. (43) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode. (44) High Speed Differential I/O is the dedicated I/O standard for the transmitter in Intel Cyclone 10 GX transceivers. Intel(R) Cyclone(R) 10 GX Device Datasheet 26 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol/Description VOCM (AC coupled) VOCM (DC coupled) Rise time Fall time (45) (45) Intra-differential pair skew Table 27. Condition Min Typ Max Unit 100- setting -- 100 20% -- VCCT_GXB = 0.95 V -- 450 -- mV VCCT_GXB = 1.03 V -- 500 -- mV VCCT_GXB = 0.95 V -- 450 -- mV VCCT_GXB = 1.03 V -- 500 -- mV 20% to 80% 20 -- 130 ps 80% to 20% 20 -- 130 ps TX VCM = 0.5 V and slew rate setting of SLEW_R5 (46) -- -- 15 ps Typical Transmitter VOD Settings Symbol VOD differential value = VOD-to-VCCT_GXB ratio x VCCT_GXB VOD Setting VOD-to-VCCT_GXB Ratio 31 1.00 30 0.97 29 0.93 28 0.90 27 0.87 26 0.83 25 0.80 24 0.77 23 0.73 22 0.70 continued... (45) The Intel Quartus Prime software automatically selects the appropriate slew rate depending on the design configurations. (46) SLEW_R1 is the slowest and SLEW_R5 is the fastest. SLEW_R6 and SLEW_R7 are not used. Intel(R) Cyclone(R) 10 GX Device Datasheet 27 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol Table 28. VOD Setting VOD-to-VCCT_GXB Ratio 21 0.67 20 0.63 19 0.60 18 0.57 17 0.53 16 0.50 15 0.47 14 0.43 13 0.40 12 0.37 Transmitter Channel-to-channel Skew Specifications Mode Channel Span x6 Clock Up to 6 channels in one bank xN Clock Within 2 banks PLL Feedback Compensation (47), (48) Side-wide Maximum Skew Unit 61 ps 230 ps 1600 ps Related Information PLLs and Clock Networks (47) refclk is set to 125 MHz during the test. (48) You can reduce the lane-to-lane skew by increasing the reference clock frequency. Intel(R) Cyclone(R) 10 GX Device Datasheet 28 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Core Performance Specifications Clock Tree Specifications Table 29. Clock Tree Performance for Intel Cyclone 10 GX Devices Parameter Performance (All Speed Grades) Unit Global clock, regional clock, and small periphery clock 644 MHz Large periphery clock 525 MHz PLL Specifications Fractional PLL Specifications Table 30. Fractional PLL Specifications for Intel Cyclone 10 GX Devices Symbol Parameter Condition Min Typ Max 800 (49) Unit fIN Input clock frequency -- 30 -- MHz fINPFD Input clock frequency to the phase frequency detector (PFD) -- 30 -- 700 MHz fCASC_INPFD Input clock frequency to the PFD of destination cascade PLL -- 30 -- 60 MHz fVCO PLL voltage-controlled oscillator (VCO) operating range -- 6 -- 12.5 GHz tEINDUTY Input clock duty cycle -- 45 -- 55 % fOUT Output frequency for internal global or regional clock -- -- -- 644 MHz fDYCONFIGCLK Dynamic configuration clock for -- -- -- 100 MHz reconfig_clk continued... (49) This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. Intel(R) Cyclone(R) 10 GX Device Datasheet 29 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol tLOCK Parameter Time required to lock from end-of-device configuration or deassertion of Condition Min Typ Max Unit -- -- -- 1 ms pll_powerdown tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-postscale counters/delays) -- -- -- 1 ms fCLBW PLL closed-loop bandwidth -- 0.3 -- 4 MHz tPLL_PSERR Accuracy of PLL phase shift -- -- -- 50 ps tARESET Minimum pulse width on the pll_powerdown signal -- 10 -- -- ns FREF 100 MHz -- -- 0.13 UI (p-p) FREF < 100 MHz -- -- 650 ps (p-p) FOUT 100 MHz -- -- 600 ps (p-p) FOUT < 100 MHz -- -- 60 mUI (p-p) FOUT 100 MHz -- -- 600 ps (p-p) FOUT < 100 MHz -- -- 60 mUI (p-p) -- -- 32 -- bit tINCCJ tOUTPJ (50)(51) (52) tOUTCCJ dKBIT (52) Input clock cycle-to-cycle jitter Period jitter for clock output Cycle-to-cycle jitter for clock output Bit number of Delta Sigma Modulator (DSM) Related Information Memory Output Clock Jitter Specifications on page 43 Provides more information about the external memory interface clock output jitter specifications. (50) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps. (51) FREF is fIN/N, specification applies when N = 1. (52) External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Intel Cyclone 10 GX Devices table. Intel(R) Cyclone(R) 10 GX Device Datasheet 30 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 I/O PLL Specifications Table 31. I/O PLL Specifications for Intel Cyclone 10 GX Devices Symbol fIN Parameter Input clock frequency Condition Min Typ -5 speed grade 10 -- 700 Max (53) Unit MHz -6 speed grade 10 -- 650 (53) MHz fINPFD Input clock frequency to the PFD -- 10 -- 325 MHz fCASC_INPFD Input clock frequency to the PFD of destination cascade PLL -- 10 -- 60 MHz fVCO PLL VCO operating range -5 speed grade 600 -- 1434 MHz -6 speed grade 600 -- 1250 MHz fCLBW PLL closed-loop bandwidth -- 0.1 -- 8 MHz tEINDUTY Input clock or external feedback clock input duty cycle -- 40 -- 60 % fOUT Output frequency for internal global or regional clock (C counter) -5, -6 speed grade -- -- 644 MHz fOUT_EXT Output frequency for external clock output -5 speed grade -- -- 720 MHz -6 speed grade -- -- 650 MHz tOUTDUTY Duty cycle for dedicated external clock output (when set to 50%) -- 45 50 55 % tFCOMP External feedback clock compensation time -- -- -- 10 ns Dynamic configuration clock for mgmt_clk and -- -- -- 100 MHz -- -- -- 1 ms fDYCONFIGCLK scanclk tLOCK Time required to lock from end-of-device configuration or deassertion of areset continued... (53) This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. Intel(R) Cyclone(R) 10 GX Device Datasheet 31 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol Parameter Condition Min Typ Max Unit tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) -- -- -- 1 ms tPLL_PSERR Accuracy of PLL phase shift -- -- -- 50 ps tARESET Minimum pulse width on the areset signal -- 10 -- -- ns FREF 100 MHz -- -- 0.15 UI (p-p) FREF < 100 MHz -- -- 750 ps (p-p) FOUT 100 MHz -- -- 175 ps (p-p) FOUT < 100 MHz -- -- 17.5 mUI (p-p) FOUT 100 MHz -- -- 175 ps (p-p) FOUT < 100 MHz -- -- 17.5 mUI (p-p) FOUT 100 MHz -- -- 600 ps (p-p) FOUT < 100 MHz -- -- 60 mUI (p-p) Cycle-to-cycle jitter for clock output on the regular I/O FOUT 100 MHz -- -- 600 ps (p-p) FOUT < 100 MHz -- -- 60 mUI (p-p) Period jitter for dedicated clock output in cascaded PLLs FOUT 100 MHz -- -- 175 ps (p-p) FOUT < 100 MHz -- -- 17.5 mUI (p-p) tINCCJ (54)(55) Input clock cycle-to-cycle jitter tOUTPJ_DC Period jitter for dedicated clock output tOUTCCJ_DC tOUTPJ_IO Cycle-to-cycle jitter for dedicated clock output (56) tOUTCCJ_IO Period jitter for clock output on the regular I/O (56) tCASC_OUTPJ_DC Related Information Memory Output Clock Jitter Specifications on page 43 Provides more information about the external memory interface clock output jitter specifications. (54) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps. (55) FREF is fIN/N, specification applies when N = 1. (56) External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Intel Cyclone 10 GX Devices table. Intel(R) Cyclone(R) 10 GX Device Datasheet 32 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 DSP Block Specifications Table 32. DSP Block Performance Specifications for Intel Cyclone 10 GX Devices Mode Performance Unit -E5 -I5 -E6 -I6 Fixed-point 18 x 19 multiplication mode 456 438 364 346 MHz Fixed-point 27 x 27 multiplication mode 450 434 358 344 MHz Fixed-point 18 x 18 multiplier adder mode 459 440 370 351 MHz Fixed-point 18 x 18 multiplier adder summed with 36-bit input mode 444 422 349 326 MHz Fixed-point 18 x 19 systolic mode 459 440 370 351 MHz Complex 18 x 19 multiplication mode 456 438 364 346 MHz Floating point multiplication mode 447 427 347 326 MHz Floating point adder or subtract mode 388 369 288 266 MHz Floating point multiplier adder or subtract mode 386 368 290 270 MHz Floating point multiplier accumulate mode 418 393 326 294 MHz Floating point vector one mode 404 382 306 282 MHz Floating point vector two mode 383 367 293 278 MHz Memory Block Specifications To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus Prime software to report timing for the memory block clocking schemes. When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX. Intel(R) Cyclone(R) 10 GX Device Datasheet 33 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Table 33. Memory Block Performance Specifications for Intel Cyclone 10 GX Devices Memory MLAB M20K Block Mode Performance -E5, -I5 -E6 -I6 Unit Single port, all supported widths (x16/x32) 570 490 490 MHz Simple dual-port, all supported widths (x16/x32) 570 490 490 MHz Simple dual-port with the read-during-write option set to Old Data, all supported widths 400 330 330 MHz ROM, all supported width (x16/x32) 570 490 490 MHz Single-port, all supported widths 625 530 510 MHz Simple dual-port, all supported widths 625 530 510 MHz Simple dual-port with the read-during-write option set to Old Data, all supported widths 470 410 410 MHz Simple dual-port with ECC enabled, 512 x 32 410 360 360 MHz Simple dual-port with ECC and optional pipeline registers enabled, 512 x 32 520 470 470 MHz True dual port, all supported widths 600 480 480 MHz ROM, all supported widths 625 530 510 MHz Temperature Sensing Diode Specifications Internal Temperature Sensing Diode Specifications Table 34. Internal Temperature Sensing Diode Specifications for Intel Cyclone 10 GX Devices Temperature Range Accuracy Offset Calibrated Option Sampling Rate Conversion Time Resolution -40 to 100C 5C No 1 MHz < 5 ms 10 bits Related Information Transfer Function for Internal TSD Provides the transfer function for the internal TSD. Intel(R) Cyclone(R) 10 GX Device Datasheet 34 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 External Temperature Sensing Diode Specifications Table 35. External Temperature Sensing Diode Specifications for Intel Cyclone 10 GX Devices * The typical value is at 25C. * Diode accuracy improves with lower injection current. * Absolute accuracy is dependent on third party external diode ADC and integration specifics. Description Min Typ Max Unit Ibias, diode source current 10 -- 100 A Vbias, voltage across diode 0.3 -- 0.9 V Series resistance -- -- <1 Diode ideality factor -- 1.03 -- -- Internal Voltage Sensor Specifications Table 36. Internal Voltage Sensor Specifications for Intel Cyclone 10 GX Devices Parameter Minimum Typical Maximum Unit Resolution -- -- 6 Bit Sampling rate -- -- 500 Ksps Differential non-linearity (DNL) -- -- 1 LSB Integral non-linearity (INL) -- -- 1 LSB Gain error -- -- 1 % Offset error -- -- 1 LSB Input capacitance -- 20 -- pF 0.1 -- 11 MHz Input signal range for Vsigp 0 -- 1.5 V Common mode voltage on Vsign 0 -- 0.25 V Input signal range for Vsigp - Vsign 0 -- 1.25 V Clock frequency Unipolar Input Mode Intel(R) Cyclone(R) 10 GX Device Datasheet 35 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Periphery Performance Specifications This section describes the periphery performance, high-speed I/O, and external memory interface. Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. High-Speed I/O Specifications Table 37. High-Speed I/O Specifications for Intel Cyclone 10 GX Devices When serializer/deserializer (SERDES) factor J = 3 to 10, use the SERDES block. For LVDS applications, you must use the PLLs in integer PLL mode. You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin. The Intel Cyclone 10 GX devices support the following output standards using true LVDS output buffer types on all I/O banks: * True RSDS output standard with data rates of up to 360 Mbps * True mini-LVDS output standard with data rates of up to 400 Mbps Symbol Condition -E5, -I5 -E6, -I6 Unit Min Typ Max Min Typ Max fHSCLK_in (input clock frequency) True Differential I/O Standards Clock boost factor W = 1 to 40 (57) 10 -- 700 10 -- 625 MHz fHSCLK_in (input clock frequency) Single Ended I/O Standards Clock boost factor W = 1 to 40 (57) 10 -- 625 10 -- 525 MHz -- -- -- -- -- fHSCLK_OUT (output clock frequency) 700 (58) 625 (58) MHz continued... (57) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate. (58) This is achieved by using the PHY clock network. Intel(R) Cyclone(R) 10 GX Device Datasheet 36 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol Condition -E5, -I5 Min Transmitter Unit Max Min Typ Max -- 1434 (62) -- 1250 Mbps (62) -- 1076 (62) -- 938 Mbps SERDES factor J = 2, uses DDR registers (62) -- 275 (63) (62) -- 250 (63) Mbps SERDES factor J = 1, uses DDR registers (62) -- 275 (63) (62) -- 250 (63) Mbps tx Jitter - True Differential I/O Standards Total jitter for data rate, 600 Mbps - 1.6 Gbps -- -- 200 -- -- 250 ps Total jitter for data rate, < 600 Mbps -- -- 0.12 -- -- 0.15 UI (64) TX output clock duty cycle for Differential I/O Standards 45 50 55 45 50 55 % True Differential I/O Standards -- -- 180 -- -- 200 ps True Differential I/O Standards fHSDR (data rate) (59) tDUTY tRISE & & tFALL (65) (61) SERDES factor J = 4 to 10 (62) SERDES factor J = 3 (60)(61)(62) (60)(61)(62) Typ -E6, -I6 continued... (59) Requires package skew compensation with PCB trace length. (60) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis. (61) The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface. (62) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and serializer do not have a minimum toggle rate. (63) The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal integrity meets the interface requirements. (64) Not applicable for DIVCLK = 1. Intel(R) Cyclone(R) 10 GX Device Datasheet 37 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol Condition -E6, -I6 Unit Min Typ Max Min Typ Max True Differential I/O Standards -- -- 150 -- -- 150 ps True Differential I/O Standards fHSDRDPA (data rate) SERDES factor J = 4 to 10 (60)(61)(62) 150 -- 1434 150 -- 1250 Mbps SERDES factor J = 3 (60)(61)(62) 150 -- 1076 150 -- 938 Mbps fHSDR (data rate) (without DPA) (59) SERDES factor J = 3 to 10 (62) -- (66) (62) -- (66) Mbps SERDES factor J = 2, uses DDR registers (62) -- (63) (62) -- (63) Mbps SERDES factor J = 1, uses DDR registers (62) -- (63) (62) -- (63) Mbps TCCS Receiver -E5, -I5 (64)(59) DPA (FIFO mode) DPA run length -- -- -- 10000 -- -- 10000 UI DPA (soft CDR mode) DPA run length SGMII/GbE protocol -- -- 5 -- -- 5 UI All other protocols -- -- 50 data transition per 208 UI -- -- 50 data transition per 208 UI -- Soft CDR mode Soft-CDR ppm tolerance -- -- -- 300 -- -- 300 ppm Non DPA mode Sampling Window -- -- -- 300 -- -- 300 ps (65) This applies to default pre-emphasis and VOD settings only. (66) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported. Intel(R) Cyclone(R) 10 GX Device Datasheet 38 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 DPA Lock Time Specifications Figure 2. DPA Lock Time Specifications with DPA PLL Calibration Enabled rx_reset DPA Lock Time rx_dpa_locked 256 data transitions Table 38. 96 core clock cycles 256 data transitions 96 core clock cycles 256 data transitions DPA Lock Time Specifications for Intel Cyclone 10 GX Devices The specifications are applicable to both extended and industrial grades. The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1-to-0 transition. Standard SPI-4 Parallel Rapid I/O Miscellaneous (67) Training Pattern Number of Data Transitions in One Repetition of the Training Pattern Number of Repetitions per 256 Data Transitions (67) Maximum Data Transition 00000000001111111111 2 128 640 00001111 2 128 640 10010000 4 64 640 10101010 8 32 640 01010101 8 32 640 This is the number of repetitions for the stated training pattern to achieve the 256 data transitions. Intel(R) Cyclone(R) 10 GX Device Datasheet 39 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Figure 3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.4 Gbps LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification Jitter Amphlitude (UI) 25 8.5 0.28 0.1 F1 F3 F2 F4 Jitter Frequency (Hz) Table 39. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.4 Gbps Jitter Frequency (Hz) Sinusoidal Jitter (UI) F1 10,000 25.00 F2 17,565 25.00 F3 1,493,000 0.28 F4 50,000,000 0.28 Intel(R) Cyclone(R) 10 GX Device Datasheet 40 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Figure 4. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.4 Gbps Sinusoidal Jitter Amplitude 20db/dec 0.1 UI P-P baud/1667 Frequency 20 MHz Memory Standards Supported by the Hard Memory Controller Table 40. Memory Standards Supported by the Hard Memory Controller for Intel Cyclone 10 GX Devices This table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator. Memory Standard DDR3 SDRAM Rate Support Half rate Speed Grade -5 -6 Quarter rate -5 -6 Ping Pong PHY Support Maximum Frequency (MHz) I/O Bank 3 V I/O Bank Yes 533 225 -- 533 225 Yes 466 166 -- 466 166 Yes 933 450 -- 933 450 Yes 933 333 continued... Intel(R) Cyclone(R) 10 GX Device Datasheet 41 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Memory Standard DDR3L SDRAM Rate Support Half rate Quarter rate Speed Grade Ping Pong PHY Support I/O Bank 3 V I/O Bank -- 933 333 -5 Yes 533 225 -- 533 225 -6 Yes 466 166 -- 466 166 Yes 933 450 -- 933 450 Yes 933 333 -- 933 333 -5 -- 400 225 -6 -- 333 166 -5 -- 800 450 -6 -- 666 333 -5 -6 LPDDR3 SDRAM Half rate Quarter rate Maximum Frequency (MHz) Related Information External Memory Interface Spec Estimator Provides the specific details of the memory standards supported. DLL Range Specifications Table 41. DLL Frequency Range Specifications for Intel Cyclone 10 GX Devices Intel Cyclone 10 GX devices support memory interface frequencies lower than 600 MHz, although the reference clock that feeds the DLL must be at least 600 MHz. To support interfaces below 600 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported range. Parameter DLL operating frequency range Intel(R) Cyclone(R) 10 GX Device Datasheet 42 Performance (for All Speed Grades) Unit 600 - 1333 MHz Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 DQS Logic Block Specifications Table 42. DQS Phase Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) for Intel Cyclone 10 GX Devices This error specification is the absolute maximum and minimum error. Symbol Performance (for All Speed Grades) Unit 5 ps tDQS_PSERR Memory Output Clock Jitter Specifications Table 43. Memory Output Clock Jitter Specifications for Intel Cyclone 10 GX Devices The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential signal-splitter and double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel recommends using PHY clock networks for better jitter performance. The memory output clock jitter is applicable when an input jitter of 10 ps peak-to-peak is applied with bit error rate (BER) 10-12, equivalent to 14 sigma. Protocol DDR3 Parameter Symbol Data Rate (Mbps) Min Max Unit Clock period jitter tJIT(per) 1,866 -40 40 ps Cycle-to-cycle period jitter tJIT(cc) 1,866 -40 40 ps tJIT(duty) 1,866 -40 40 ps Duty cycle jitter OCT Calibration Block Specifications Table 44. OCT Calibration Block Specifications for Intel Cyclone 10 GX Devices Symbol Description Min Typ Max Unit -- -- 20 MHz > 2000 -- -- Cycles OCTUSRCLK Clock required by OCT calibration blocks TOCTCAL Number of OCTUSRCLK clock cycles required for RS OCT /RT OCT calibration TOCTSHIFT Number of OCTUSRCLK clock cycles required for OCT code to shift out -- 32 -- Cycles TRS_RT Time required between the dyn_term_ctrl and oe signal transitions in a bidirectional I/O buffer to dynamically switch between RS OCT and RT OCT -- 2.5 -- ns Intel(R) Cyclone(R) 10 GX Device Datasheet 43 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Figure 5. Timing Diagram for on oe and dyn_term_ctrl Signals RX Tristate Tristate TX RX oe dyn_term_ctrl TRS_RT TRS_RT Configuration Specifications This section provides configuration specifications and timing for Intel Cyclone 10 GX devices. POR Specifications Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration. Table 45. Fast and Standard POR Delay Specification for Intel Cyclone 10 GX Devices POR Delay Fast Minimum 4 Standard 100 Maximum 12 (68) 300 Unit ms ms Related Information MSEL Pin Settings Provides more information about POR delay based on MSEL pin settings for each configuration scheme. (68) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip. Intel(R) Cyclone(R) 10 GX Device Datasheet 44 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 JTAG Configuration Timing Table 46. JTAG Timing Parameters and Values for Intel Cyclone 10 GX Devices Symbol Description Min 30, 167 (69) Max Unit -- ns tJCP TCK clock period tJCH TCK clock high time 14 -- ns tJCL TCK clock low time 14 -- ns tJPSU (TDI) TDI JTAG port setup time 2 -- ns tJPSU (TMS) TMS JTAG port setup time 3 -- ns tJPH JTAG port hold time 5 -- ns tJPCO JTAG port clock to output -- 11 ns tJPZX JTAG port high impedance to valid output -- 14 ns tJPXZ JTAG port valid output to high impedance -- 14 ns FPP Configuration Timing DCLK-to-DATA[] Ratio (r) for FPP Configuration Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature. Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per second (Wps). For example, in FPP x16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps. (69) The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V - 1.5 V when you perform the volatile key programming. Intel(R) Cyclone(R) 10 GX Device Datasheet 45 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Table 47. DCLK-to-DATA[] Ratio for Intel Cyclone 10 GX Devices You cannot turn on encryption and compression at the same time for Intel Cyclone 10 GX devices. Configuration Scheme FPP (8-bit wide) FPP (16-bit wide) FPP (32-bit wide) Encryption Compression DCLK-to-DATA[] Ratio (r) Off Off 1 On Off 1 Off On 2 Off Off 1 On Off 2 Off On 4 Off Off 1 On Off 4 Off On 8 FPP Configuration Timing when DCLK-to-DATA[] = 1 Note: When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP x8, FPP x16, and FPP x32. For the respective DCLK-to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Intel Cyclone 10 GX Devices table. Table 48. FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Intel Cyclone 10 GX Devices Use these timing parameters when the decompression and design security features are disabled. Parameter Symbol Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low 480 1,440 ns tCF2ST0 nCONFIG low to nSTATUS low 320 960 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS tCF2ST1 nSTATUS low pulse width nCONFIG high to nSTATUS high 268 -- 3,000 (70) 3,000 (71) s s continued... (70) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. Intel(R) Cyclone(R) 10 GX Device Datasheet 46 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol Minimum Maximum Unit nCONFIG high to first rising edge on DCLK 3,010 -- s nSTATUS high to first rising edge of DCLK 10 -- s tDSU DATA[] setup time before rising edge on DCLK 5.5 -- ns tDH DATA[] hold time after rising edge on DCLK 0 -- ns tCH DCLK high time 0.45 x 1/fMAX -- s tCL DCLK low time 0.45 x 1/fMAX -- s tCLK DCLK period 1/fMAX -- s fMAX DCLK frequency (FPP x8/x16/x32) -- 100 MHz 175 830 s 4 x maximum DCLK period -- -- tCD2CU + (600 x CLKUSR period) -- -- tCF2CK (72) tST2CK (72) Parameter (73) tCD2UM CONF_DONE high to user mode tCD2CU CONF_DONE high to CLKUSR enabled tCD2UMC CONF_DONE high to user mode with CLKUSR option on Related Information FPP Configuration Timing Provides the FPP configuration timing waveforms. (71) This value is applicable if you do not delay configuration by externally holding the nSTATUS low. (72) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (73) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. Intel(R) Cyclone(R) 10 GX Device Datasheet 47 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 FPP Configuration Timing when DCLK-to-DATA[] >1 Table 49. FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel Cyclone 10 GX Devices Use these timing parameters when you use the decompression and design security features. Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low 480 1,440 ns tCF2ST0 nCONFIG low to nSTATUS low 320 960 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width 268 3,000 (74) s tCF2ST1 nCONFIG high to nSTATUS high -- 3,000 (74) s tCF2CK (75) nCONFIG high to first rising edge on DCLK 3,010 -- s tST2CK (75) nSTATUS high to first rising edge of DCLK 10 -- s tDSU DATA[] setup time before rising edge on DCLK 5.5 -- ns tDH DATA[] hold time after rising edge on DCLK N-1/fDCLK (76) -- s tCH DCLK high time 0.45 x 1/fMAX -- s tCL DCLK low time 0.45 x 1/fMAX -- s tCLK DCLK period 1/fMAX -- s fMAX DCLK frequency (FPP x8/x16/x32) -- 100 MHz tR Input rise time -- 40 ns tF Input fall time -- 40 ns continued... (74) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (75) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (76) N is the DCLK-to-DATA ratio and fDCLK is the DCLK frequency the system is operating. Intel(R) Cyclone(R) 10 GX Device Datasheet 48 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol Parameter Minimum Maximum Unit (77) 175 830 s 4 x maximum DCLK period -- -- tCD2CU + (600 x CLKUSR period) -- -- tCD2UM CONF_DONE high to user mode tCD2CU CONF_DONE high to CLKUSR enabled tCD2UMC CONF_DONE high to user mode with CLKUSR option on Related Information FPP Configuration Timing Provides the FPP configuration timing waveforms. AS Configuration Timing Table 50. AS Timing Parameters for AS x1 and AS x4 Configurations in Intel Cyclone 10 GX Devices The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device. The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing Parameters for Intel Cyclone 10 GX Devices table. Symbol (77) Parameter Minimum Maximum Unit tCO DCLK falling edge to AS_DATA0/ASDO output -- 2 ns tSU Data setup time before falling edge on DCLK 1 -- ns tDH Data hold time after falling edge on DCLK 1.5 -- ns tCD2UM CONF_DONE high to user mode 175 830 s tCD2CU CONF_DONE high to CLKUSR enabled 4 x maximum DCLK period -- -- tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (600 x CLKUSR period) -- -- The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device. Intel(R) Cyclone(R) 10 GX Device Datasheet 49 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Related Information * PS Configuration Timing on page 50 * AS Configuration Timing Provides the AS configuration timing waveform. DCLK Frequency Specification in the AS Configuration Scheme Table 51. DCLK Frequency Specification in the AS Configuration Scheme This table lists the internal clock frequency specification for the AS configuration scheme. The DCLK frequency specification applies when you use the internal oscillator as the configuration clock source. The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz. You can only set 12.5, 25, 50, and 100 MHz in the Intel Quartus Prime software. Parameter Minimum Typical Maximum Intel Quartus Prime Software Settings Unit 5.3 7.5 9.7 12.5 MHz 10.5 15.0 19.3 25.0 MHz 21.0 30.0 38.5 50.0 MHz 42.0 60.0 77.0 100.0 MHz DCLK frequency in AS configuration scheme PS Configuration Timing Table 52. PS Timing Parameters for Intel Cyclone 10 GX Devices Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low 480 1,440 ns tCF2ST0 nCONFIG low to nSTATUS low 320 960 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width 268 tCF2ST1 nCONFIG high to nSTATUS high -- 3,000 (78) 3,000 (79) s s continued... Intel(R) Cyclone(R) 10 GX Device Datasheet 50 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Symbol Minimum Maximum Unit nCONFIG high to first rising edge on DCLK 3,010 -- s nSTATUS high to first rising edge of DCLK 10 -- s tDSU DATA[] setup time before rising edge on DCLK 5.5 -- ns tDH DATA[] hold time after rising edge on DCLK 0 -- ns tCH DCLK high time 0.45 x 1/fMAX -- s tCL DCLK low time 0.45 x 1/fMAX -- s tCLK DCLK period 1/fMAX -- s fMAX DCLK frequency -- 125 MHz 175 830 s 4 x maximum DCLK period -- -- tCD2CU + (600 x CLKUSR period) -- -- tCF2CK (80) tST2CK (80) Parameter (81) tCD2UM CONF_DONE high to user mode tCD2CU CONF_DONE high to CLKUSR enabled tCD2UMC CONF_DONE high to user mode with CLKUSR option on Related Information PS Configuration Timing Provides the PS configuration timing waveform. (78) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (79) This value is applicable if you do not delay configuration by externally holding the nSTATUS low. (80) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (81) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device. Intel(R) Cyclone(R) 10 GX Device Datasheet 51 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Initialization Table 53. Initialization Clock Source Option and the Maximum Frequency for Intel Cyclone 10 GX Devices Initialization Clock Source Internal Oscillator CLKUSR (82)(83) Configuration Scheme Maximum Frequency (MHz) Minimum Number of Clock Cycles AS, PS, and FPP 12.5 600 AS, PS, and FPP 100 Configuration Files There are two types of configuration bit stream formats for different configuration schemes: * PS and FPP--Raw Binary File (.rbf) * AS--Raw Programming Data File (.rpd) The .rpd file size follows the Intel configuration devices capacity. However, the actual configuration bit stream size for .rpd file is the same as .rbf file. (82) To enable CLKUSR as the initialization clock source, in the Intel Quartus Prime software, select Device and Pin Options General Device initialization clock source CLKUSR pin. (83) If you use the CLKUSR pin for AS and transceiver calibration simultaneously, the only allowed frequency is 100 MHz. Intel(R) Cyclone(R) 10 GX Device Datasheet 52 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Table 54. Configuration Bit Stream Sizes for Intel Cyclone 10 GX Devices Use this table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf) format, have different file sizes. For the different types of configuration file and file sizes, refer to the Intel Quartus Prime software. However, for a specific version of the Intel Quartus Prime software, any design targeted for the same device has the same uncompressed configuration file size. I/O configuration shift register (IOCSR) is a long shift register that facilitates the device I/O peripheral settings. The IOCSR bit stream is part of the uncompressed configuration bit stream, and it is specifically for the Configuration via Protocol (CvP) feature. Uncompressed configuration bit stream sizes are subject to change for improvements and optimizations in the configuration algorithm. Variant Product Line Uncompressed Configuration Bit Stream Size (bits) IOCSR Bit Stream Size (bits) Recommended EPCQ-L Serial Configuration Device Intel Cyclone 10 GX GX 085 81,923,582 2,507,264 EPCQ-L256 or higher density GX 105 81,923,582 2,507,264 EPCQ-L256 or higher density GX 150 81,923,582 2,507,264 EPCQ-L256 or higher density GX 220 81,923,582 2,507,264 EPCQ-L256 or higher density Intel(R) Cyclone(R) 10 GX Device Datasheet 53 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Minimum Configuration Time Estimation Table 55. Minimum Configuration Time Estimation for Intel Cyclone 10 GX Devices The estimated values are based on the uncompressed configuration bit stream sizes in the Configuration Bit Stream Sizes for Intel Cyclone 10 GX Devices table. Variant Product Line Intel Cyclone 10 GX Active Serial (84) Fast Passive Parallel (85) Width DCLK (MHz) Minimum Configuration Time (ms) Width DCLK (MHz) Minimum Configuration Time (ms) GX 085 4 100 204.81 32 100 25.60 GX 105 4 100 204.81 32 100 25.60 GX 150 4 100 204.81 32 100 25.60 GX 220 4 100 204.81 32 100 25.60 Related Information * Configuration Files on page 52 * DCLK Frequency Specification in the AS Configuration Scheme on page 50 Provides the DCLK frequency using internal oscillator. (84) The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external CLKUSR may guarantee the frequency accuracy of 100 MHz. If you use internal oscillator of 100 MHz, you may not get the actual frequency of 100 MHz. For the DCLK frequency using internal oscillator, refer to the DCLK Frequency Specification in the AS Configuration Scheme table. (85) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic. Intel(R) Cyclone(R) 10 GX Device Datasheet 54 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Remote System Upgrades Table 56. Remote System Upgrade Circuitry Timing Specifications for Intel Cyclone 10 GX Devices Parameter Minimum Maximum Unit fMAX_RU_CLK (86) -- 40 MHz tRU_nCONFIG (87) 250 -- ns 250 -- ns tRU_nRSTIMER (88) Related Information * Remote System Upgrade State Machine Provides more information about configuration reset (RU_CONFIG) signal. * User Watchdog Timer Provides more information about reset_timer (RU_nRSTIMER) signal. User Watchdog Internal Circuitry Timing Specifications Table 57. User Watchdog Internal Oscillator Frequency Specifications for Intel Cyclone 10 GX Devices Parameter User watchdog internal oscillator frequency Minimum Typical Maximum Unit 5.3 7.9 12.5 MHz I/O Timing I/O timing data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the timing analysis. You may generate the I/O timing report manually using the Timing Analyzer or using the automated script. (86) This clock is user-supplied to the remote system upgrade circuitry. If you are using the Remote Update Intel FPGA IP core, the clock user-supplied to the Remote Update Intel FPGA IP core must meet this specification. (87) This is equivalent to strobing the reconfiguration input of the Remote Update Intel FPGA IP core high for the minimum timing specification. (88) This is equivalent to strobing the reset_timer input of the Remote Update Intel FPGA IP core high for the minimum timing specification. Intel(R) Cyclone(R) 10 GX Device Datasheet 55 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 The Intel Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route. Related Information AN775: I/O Timing Information Generation Guidelines Provides the techniques to generate I/O timing information using the Intel Quartus Prime software. Programmable IOE Delay Table 58. IOE Programmable Delay for Intel Cyclone 10 GX Devices For the exact values for each setting, use the latest version of the Intel Quartus Prime software. The values in the table show the delay of programmable IOE delay chain with maximum offset settings after excluding the intrinsic delay (delay at minimum offset settings). Programmable IOE delay settings are only applicable for I/O buffers and do not apply for any other delay elements in the PHYLite for Parallel Interfaces Intel Cyclone 10 FPGA IP core. Parameter (89) Maximum Offset Minimum Offset (90) Fast Model Slow Model Unit Extended Industrial -E5, -I5 -E6, -I6 Input Delay Chain Setting (IO_IN_DLY_CHN) 63 0 2.012 2.003 5.241 6.035 ns Output Delay Chain Setting (IO_OUT_DLY_CHN) 15 0 0.478 0.475 1.263 1.462 ns Glossary Table 59. Glossary Term Differential I/O Standards Definition Receiver Input Waveforms continued... (89) You can set this value in the Intel Quartus Prime software by selecting Input Delay Chain Setting or Output Delay Chain Setting in the Assignment Name column. (90) Minimum offset does not include the intrinsic delay. Intel(R) Cyclone(R) 10 GX Device Datasheet 56 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Term Definition Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground Differential Waveform VID p-n=0V VID Transmitter Output Waveforms Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground Differential Waveform VOD p-n=0V VOD fHSCLK I/O PLL input clock frequency. fHSDR High-speed I/O block--Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. fHSDRDPA High-speed I/O block--Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. J High-speed I/O block--Deserialization factor (width of parallel data bus). JTAG Timing Specifications JTAG Timing Specifications: continued... Intel(R) Cyclone(R) 10 GX Device Datasheet 57 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Term Definition TMS TDI t JCH t JCP t JCL tJPH t JPSU TCK tJPZX t JPXZ tJPCO TDO RL Receiver differential input discrete resistor (external to the Intel Cyclone 10 GX device). Sampling window (SW) Timing Diagram--the period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window, as shown: Bit Time 0.5 x TCCS Single-ended voltage referenced I/O standard RSKM Sampling Window (SW) RSKM 0.5 x TCCS The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. Single-Ended Voltage Referenced I/O Standard continued... Intel(R) Cyclone(R) 10 GX Device Datasheet 58 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Term Definition V CCIO V OH V IH(AC) V REF V IH(DC) V IL(DC) V IL(AC) V OL V SS tC High-speed receiver/transmitter input and output clock period. TCCS (channel-to-channel-skew) The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). tDUTY High-speed I/O block--Duty cycle on high-speed transmitter output clock. tFALL Signal high-to-low transition time (80-20%) tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input tOUTPJ_IO Period jitter on the GPIO driven by a PLL tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL tRISE Signal low-to-high transition time (20-80%) Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w). VCM(DC) DC Common mode input voltage. VICM Input Common mode voltage--The common mode of the differential signal at the receiver. VID Input differential voltage swing--The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. VDIF(AC) AC differential input voltage--Minimum AC input differential voltage required for switching. VDIF(DC) DC differential input voltage-- Minimum DC input differential voltage required for switching. VIH Voltage input high--The minimum positive voltage applied to the input which is accepted by the device as a logic high. continued... Intel(R) Cyclone(R) 10 GX Device Datasheet 59 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Term Definition VIH(AC) High-level AC input voltage VIH(DC) High-level DC input voltage VIL Voltage input low--The maximum positive voltage applied to the input which is accepted by the device as a logic low. VIL(AC) Low-level AC input voltage VIL(DC) Low-level DC input voltage VOCM Output Common mode voltage--The common mode of the differential signal at the transmitter. VOD Output differential voltage swing--The difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter. VSWING Differential input voltage VIX Input differential cross point voltage VOX Output differential cross point voltage W High-speed I/O block--Clock Boost Factor Document Revision History for the Intel Cyclone 10 GX Device Datasheet Document Version 2018.06.15 2018.04.06 Changes * * * * Added Intel Cyclone 10 GX Devices Overshoot Duration figure and description. Added a link in the OCT Calibration Accuracy Specifications section. Removed Equation for OCT Variation Without Recalibration. * * Updated the I/O Timing section on the I/O timing information generation guidelines. Updated the description and maximum offset values in the IOE Programmable Delay for Intel Cyclone 10 GX Devices table. Updated the note to CLKUSR in the Initialization Clock Source Option and the Maximum Frequency for Intel Cyclone 10 GX Devices table. Added notes to IOUT specification in the Absolute Maximum Ratings for Intel Cyclone 10 GX Devices table. Intel(R) Cyclone(R) 10 GX Device Datasheet 60 Intel(R) Cyclone(R) 10 GX Device Datasheet C10GX51002 | 2018.06.15 Date November 2017 Version 2017.11.10 Changes * * * * * * * * * * * * * * * * May 2017 2017.05.08 Changed the full symbol names for VCCR_GXB and VCCT_GXB, and changed the description for VCCH_GXB in the Transceiver Power Supply Operating Conditions for Intel Cyclone 10 GX Devices table. Removed note from the Transceiver Power Supply Operating Conditions section. Added a footnote in the Reference Clock Specifications table. Removed the "Programmable AC Gain at High Gain mode and Data Rate 12.5 Gbps" parameter from the Receiver Specifications table. Changed the channel span descriptions for the x1 and x6 clock networks in the Transceiver Clock Network Maximum Data Rate Specifications table. Changed the description of the VOD ratio in the Typical Transmitter VOD Settings table. Changed the specifications for CDR PPM deviation limit in the Receiver Specifications table. Updated the description for VCCT_GXB, VCCR_GXB, and VCCH_GXB. Added note to VI in the Recommended Operating Conditions for Intel Cyclone 10 GX Devices table. Updated notes to RSDS and Mini-LVDS in the Differential I/O Standards Specifications for Intel Cyclone 10 GX Devices table. Updated fVCO specifications in the Fractional PLL Specifications for Intel Cyclone 10 GX Devices table. Updated temperature range from "-40 to 125C" to "-40 to 100C" in the Internal Temperature Sensing Diode Specifications for Intel Cyclone 10 GX Devices table. Updated the description for the Memory Output Clock Jitter Specifications for Intel Cyclone 10 GX Devices table. Updated the following IP cores name: -- Remote Update Intel FPGA -- PHYLite for Parallel Interfaces Intel Cyclone 10 FPGA Removed automotive-grade information. Removed Preliminary tags. Initial release. Intel(R) Cyclone(R) 10 GX Device Datasheet 61