1
®
FN8104.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
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X24C45
256 Bit, 16 x 16 Bit
Serial AUTOSTORE™ NOVRAM
FEATURES
• AUTOSTORE NOVRAM
—Automatically performs a store operation
upon loss of VCC
• Single 5V supply
• Ideal for use with single chip microcomputers
—Minimum I/O interface
—Serial port compatible (COPS™, 8051)
—Easily interfaced to microcontroller ports
• Software and hardware control of nonvolatile
functions
• Auto recall on power-up
• TTL and CMOS compatible
• Low power dissipation
—Active current: 10mA
—Standby current: 50µA
• 8-lead PDIP and 8-lead SOIC packages
• High reliability
—Store cycles: 1,000,000
—data retention: 100 years
DESCRIPTION
The Intersil X24C45 is a serial 256-bit NOVRAM featur-
ing a static RAM configured 16 x 16, overlaid bit-by-bit
with a nonvolatile EEPROM array. The X24C45 is fabri-
cated with Intersil’s Advanced CMOS Floating Gate
technology.
The Intersil NOVRAM design allows data to be trans-
ferred between the two memory arrays by means of
software commands or external hardware inputs. A
store operation (RAM data to EEPROM) is completed
in 5ms or less and a r ecall operation (E EP ROM data to
RAM) is completed in 2µs or less.
The X24C45 also includes the AUTOSTORE feature, a
user selectable feature that automatically performs a
store operation when VCC falls below a preset threshold.
Intersil NOVRAMs are designed for unlimited write
operations to RAM, either from the host or reca lls fro m
EEPROM and a minimum 1,000,000 store operations.
Inherent data retention is specified to be greater than
100 years.
IBLOCK DIAGRAM
Nonvolatile
Control
Logic
Column
Decode
Row
Decode
4-Bit
Counter
Decode
Instruction
Register
CE (1)
DI (3)
SK (2) DO (4)
RECALL (6)
AS (7)
Static
RAM
256-Bit
STORE
EEPROM
RECALL
Instruction
Data Sheet June 1, 2005
2FN8104.0
June 1, 2005
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be HIGH to enable all
read/write operations. CE must remain HIGH following
a Read or Write command until the data transfer is
complete. CE LOW places the X24C45 in the low
power standby mode and resets the instruction register.
Therefore, CE must be brought LOW after the comple-
tion of an operation in order to reset the instruction reg-
ister in preparation for the next command.
Serial Clock (SK)
The Serial Clock input is used to clock all data into and
out of the device.
Data In (DI)
Data In is the serial data input.
Data Out (DO)
Data Out is the serial data output. It is in the high
impedance state except during data output cycles in
response to a READ instruction.
AUTOSTORE Output (AS)
AS is an open drain output which, when asserted indi-
cates VCC has fallen below the AUTOSTORE thresh-
old (VASTH). AS may be wire-ORed with multiple open
drain outputs and used as an interr upt input to a micro-
controller or as a n input to a low powe r reset cir cuit.
RECALL
RECALL LOW will initiate an internal transfer of data
from EEPROM to the RAM array.
PIN CONFIGURATION
PIN NAMES
Symbol Description
CE Chip Enable
SK Serial Clock
DI Serial Data In
DO Serial Data Out
RECALL Recall Input
AS AUTOSTORE Oput
VCC +5V
VSS Ground
CE
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
AS
RECALL
VSS
X24C45
DIP/SOIC
X24C45
3FN8104.0
June 1, 2005
DEVICE OPERATION
The X24C45 contains an 8-bit instruction register. It is
accessed via the DI input, with data being clocked in
on the rising edge of SK. CE must be HIGH during the
entire data transfer operation.
Table 1. contains a list of the instructions and their opera-
tion codes. The most significant bit (MSB) of all instruc-
tions is a logic one (HIGH), bits 6 through 3 are either
RAM address bits (A) or don’t cares (X) and bits 2
through 0 are the operation codes. The X24C45 requires
the instruction to be shifted in with the MSB first.
After CE is HIGH, the X24C45 will not begin to inter-
pret the data stream until a logic "1" has been shifted
in on DI. Therefore, CE may be brought HIGH with SK
running and DI LOW. DI must then go HIGH to indi-
cate the start condition of an instruction before the
X24C45 will begin any action.
In addition, the SK clock is totally static. The user can
completely stop the clock and data shifting will be
stopped. Restarting the clock will resume shifting of data.
RCL and RECALL
Either a software RCL instruction or a LOW on the
RECALL input will initiate a transfer of EEPROM data
into RAM. This software or hardware recall operation
sets an internal "previous recall" latch. This latch is
reset upon power-up and must be intentionally set by
the user to enable any write or store operations.
Although a recall operation is performed upon power-
up, the previous recall latch is not set by this operation.
WRDS and WREN
Internally the X24C45 contains a "write enable" latch.
This latch must be set for either writes to the RAM or
store ope rations to the EEPROM. The WREN in struc-
tion sets the latch and the WRDS instruction resets the
latch, disabling both RAM writes and EEPROM stores,
effectively protecting the nonvolatile data from corrup-
tion. The write enable latch is automatically reset on
power-up.
STO
The software STO instruction will initiate a transfer of
data from RAM to EEPROM. In order to safeguard
against unwanted store operations, the following con-
ditions must be true:
– STO instruction issued.
– The internal "write enable" latch must be set (WREN
instruction issued).
– The "p revious recall" latch must be set (eithe r a soft-
ware or hardware recall operation).
Once the store cycle is initiated, all othe r device func-
tions are inhibited. Upon completion of the store cycle,
the write enable latch is reset. Refer to Figure 4 for a
state diagram description of enabling/disabling condi-
tions for store o perations.
Table 1. Instruction Set
Instructio n Format, I2 I1 I0Operation
WRDS (Figure 3) 1XXXX000 Reset Write Enable Latch (Disables Writes and Stores)
STO (Figure 3) 1XXXX001 STORE RAM Data in EEPROM
ENAS 1XXXX010 Enable AUTOSTORE Feature
WRITE (Figure 2) 1AAAA011 Write Data into RAM Address AAAA
WREN (Figure 3) 1XXXX100 Set Write Enable Latch (Enables Writes and Stores)
RCL (Figure 3) 1XXXX101 Recall EEPROM Data into RAM
READ (Figure 1) 1AAAA11X Read Data from RAM Address AAAA
X24C45
4FN8104.0
June 1, 2005
WRITE
The WRITE instruction co ntains the 4-bit address of the
word to be written. The write instruction is immediately
followed by the 16-bit word to be written. CE must remain
HIGH during the entire operation. CE must go LOW
before the next rising edge of SK. If CE is brought LOW
prematurely (after the instruction but before 16 bits of
data are transferred), the instruction register will be reset
and the data that was shifted-in will be written to RAM.
If CE is kept HIGH for more than 24 SK clock cycles
(8-bit instruction plus 16-bit data), the data already
shifted-in will be over written.
READ
The READ instruction conta ins the 4-bi t addr ess of the
word to be accessed. Unlike the other six instructions,
I0 of the instruction word is a "don’t care". This pro-
vides two advantages. In a design that ties both DI
and DO together, the absence of an eighth bit in the
instruction allows the host time to convert an I/O line
from an output to an input. Secondly, it allows for v alid
data output during the ninth SK clock cycle.
D0, the firs t bit output durin g a read oper ation, is trun-
cated. That is, it is internally clocked by the falling
edge of the eighth SK clock; whereas, all succeeding
bits are clocked by the rising edge of SK (refer to Read
Cycle Diagram).
LOW POWER MODE
When CE is LOW, non-critical internal devices are
powered-down, placing the device in the standby
power mode, thereby min imizing power consumption.
AUTOSTORE Feature
The AUTOSTORE instruction (ENAS) sets the
"AUTOSTORE enable" latch, allowing the X24C45 to
automatically perform a stor e operatio n when VCC falls
below the AUTOSTORE threshold (VASTH).
Notes: X = Don't Care
A = Address
WRITE PROTECTION
The X24C45 provides two software write protection
mechanism s to pr even t inad vert ent st ores of unkn own
data.
Power-Up Condition
Upon power-up the "write enable" and "AUTOSTORE
enable" latches are in the reset state, disabling any
store operation.
Unknown Data Store
The "previou s reca ll" latch must be set aft er po we r- up .
It may be set only by performing a software or hard-
ware recall operation, which assures that data in all
RAM locations is valid.
SYSTEM CONSIDERATIONS
Power-Up Recall
The X24C45 performs a power-up recall that transfers
the EEPROM contents to the RAM array. Although the
data may be read from the RAM array, this recall does
not set the "previous recall" latch. During this power-
up recall operation, all commands are ignored. There-
fore, the host should delay any operations with the
X24C45 a minimum of tPUR after VCC is stable.
X24C45
5FN8104.0
June 1, 2005
Figure 1. RAM Read
Figure 2. RAM Write
Figure 3. Non-Data Operations
1
CE
3 4 5 6 7 8
1 A 1 A A A 1 X*
SK
DI
9 10 11 12 22 23
D1D2D3D14 D15
D13
DO HIGH Z
*Bit 8 of Read Instructions is Don’t Care
D0
224
D0
1
CE
3 4 5 6 7 8
1 A 1 A A A 1
SK
DI
9 10 11 22 23
224
D1D2D14 D15
D12
D0
0
21
D13
1
CE
2 3 4 5 6 7 8
1 X I2
X X X
SK
DI I1I0
X24C45
6FN8104.0
June 1, 2005
Figure 4. FX24C45 State Diagram
Power
On
Store
Enabled
RAM Read
Or Write
RAM
Read
Enabled
RAM
Read
Enabled
RAM
Read &
Write Enabled
WREN
Command
RAM Read
RAM Read
Power-Up
Recall
RCL Command
Or Recall
STO Or
Wrds Cmd
Power
OFF
Read & Write
RAM
Enabled
Store Enabled
AUTOSTORE
Enabled
RAM Read
Or Write
WREN
Command
AUTOSTORE
Power-down
STO Or
Wrds Cmd
ENAS Command
X24C45
7FN8104.0
June 1, 2005
ABSOLUTE MAXIMUM RATINGS
Temperature under bias....................-65°C to +135°C
Storage temperature .........................-65°C to +150°C
Voltage on any pin
with respect to VSS.................................. -1V to +7V
D.C. output current...............................................5mA
Lead temperature ( soldering, 10 seconds)........300°C
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any other conditions above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
Symbol Parameter
Limits
Unit Test ConditionsMin. Max.
lCC1 VCC supply current (TTL inputs) 10 mA SK = 0.4V/2.4V Levels @ 1MHz, DO
= open, All other inputs = VIH
lCC2 VCC supply current (during
AUTOSTORE) 2 mA All inputs = VIH, CE = VIL
DO = open, VCC = 4.3V
ISB1 VCC standby current (TTL inputs) 1 mA DO = Open, CE = VIL,
All other inputs = VIH
ISB2 V
CC standby current (CMOS inputs) 50 µA DO = Open, CE = VSS,
All other inputs = VCC – 0.3V
ILI Input load current 10 µA VIN = VSS to VCC
ILO Output leakage current 10 µA VOUT = VSS to VCC
VlL(1) Input LOW voltage -1 0.8 V
VIH(1) Input HIGH voltage 2 VCC + 1 V
VOL Output LOW voltage 0.4 V IOL = 4.2mA
VOH Output HIGH voltage 2.4 V IOH = –2mA
VOL(AS) Output LOW voltage (AS) 0.4 V IOL(AS) = 1mA
Parameter Min. Unit
Endurance 100,000 Data changes per bit
Store cycles 1,000,000 Store cycles
Data retention 100 Years
Symbol Parameter Max. Unit Test Conditions
COUT(2) Output capacitance 8 pF VOUT = 0V
CIN(2) Input capacitance 6 pF VIN = 0V
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial -40°C +85°C
Military -55°C +125°C
Supply Voltage Limits
X24C45 5V ±10%
X24C45
8FN8104.0
June 1, 2005
EQUIVALENT A. C. LOAD CIRCUIT A.C. CONDITIONS OF TEST
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Read and Write Cycle Limits
POWER-UP TIMING
Notes: (3) SK rise and fall times must be less than 50ns.
(4) tPUR and tPUW are the delays required from the time VCC is stable until the specified opera tion can be initiated. These paramet ers are
periodically sampled and not 100% tested.
5V
919Ω
497Ω
Output
100pF
Input pulse levels 0V to 3V
Input rise and fall times 10ns
Input and output timing levels 1.5V
Symbol Parameter Min. Max. Unit
FSK(3) SK frequency 1 MHz
tSKH SK positive pulse width 400 ns
tSKL SK negative pulse width 400 ns
tDS Data setup time 400 ns
tDH Data hold time 80 ns
tPD1 SK to data bit 0 valid 375 ns
tPD SK to data valid 375 ns
tZChip enable to output high Z 1 µs
tCES Chip enable setup 800 ns
tCEH Chip enable hold 350 ns
tCDS Chip deselect 800 ns
Symbol Parameter Max. Unit
tPUR(4) Power-up to read operation 200 µs
tPUW(4) Power-up to write or store operation 5 ms
X24C45
9FN8104.0
June 1, 2005
Write Cycle
Read Cycle
SK
1/FSK
tCES tCEH tCDS
x 1 2 n
tSKH tSKL
tDS tDH
CE
DI
SK CYCLE #
SK
6 7 8 9 10 n
D0 D1 Dn
High Z High Z
CE
DI
DO
DON’T CARE
SK CYCLE #
I2 I1
tPD1
tPD
tZ
VIH
X24C45
10 FN8104.0
June 1, 2005
NONVOLATILE OPERATIONS
ARRAY RECALL LIMITS
Recall Timing
SOFTWARE STORE CYCLE LIMITS
Notes: (5) NOP designates when the X24C45 is not currently executing an instruction.
(6) RECALL rise time must be <10µs.
(7) Typical values are for TA = 25°C and nominal supply voltage.
Operation RECALL Software Instruction Write Enable Latch State Previous Recall
Latch State
Hardware recall 0 NOP(5) XX
Software recall 1 RCL X X
Software store 1 STO SET SET
Symbol Parameter Min. Max. Unit
tRCC Recall cycle time 2 µs
tRCP Recall pulse width(6) 500 ns
tRCZ Recall to output in high Z 500 ns
Symbol Parameter Min. Typ.(7) Max. Unit
tST Store time after clock 8 of STO command 2 5 ms
tRCC
tRCZ High Z
RECALL
DO
tRCP
X24C45
11 FN8104.0
June 1, 2005
AUTOSTORE CYCLE LIMITS
AUTOSTORE Cycle Timing Diagrams
SYMBOL TABLE
Symbol Parameter Min. Max. Unit
tASTO AUTOSTORE cycle time 5 ms
VASTH AUTOSTORE threshold voltage 4.0 4.3 V
VASEND AUTOSTORE cycle end voltage 3.5 V
AS
tPUR tASTO tPUR
0V
VASTH
VCC
VCC
Time (ms)
VASTH
VASEND
AUTOSTORE Cycle in Progress
tASTO
Store Time
Volts (V)
5
4
3
2
1
WAVEFORM INPUTS OUTPUTS
Must be
steady Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X24C45
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8104.0
June 1, 2005
Ordering Information
X24C45 P T -V
Device
VCC Limits
Blank = 5V ± 10%
Temperature Rang e
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
M = Military = -55°C to +125°C
Package
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
X24C45
