DM9374N - National Semiconductor

TL/F/10210

DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs

June 1989

DM9374 7-Segment Decoder/Driver/Latch

with Constant Current Sink Outputs

General Description

The ’74 is a 7-segment decoder driver incorporating input

latches and output circuits to directly drive common anode

LED displays.

Connection Diagram

Dual-In-Line Package

TL/F/10210–1

Order Number DM9374N

See NS Package Number N16E

Logic Symbol

TL/F/10210–2

VCC ePin 16

GND ePin 8

Pin Description

Names

A0– A3 Address (Data Inputs)

LE Latch Enable Input (Active LOW)

RBI Ripple Blanking Input (Active LOW)

RBO Ripple Blanking as Output (Active LOW)

as Input (Active LOW)

a–g Constant Current Outputs (Active LOW)

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage 5.5V

Operating Free Air Temperature Range 0§Ctoa

70§C

Storage Temperature Range b65§Ctoa

150§C

Note:

The ‘‘Absolute Maximum Ratings’’ are those values

beyond which the safety of the device cannot be guaran-

teed. The device should not be operated at these limits. The

parametric values defined in the ‘‘Electrical Characteristics’’

table are not guaranteed at the absolute maximum ratings.

The ‘‘Recommended Operating Conditions’’ table will define

the conditions for actual device operation.

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VOUT Output Voltage Applied OFF 10 V

(Figure A)

VIH High Level Input Voltage 2 V

VIL Low Level Input Voltage 0.8 V

IOH High Level Output Current, a–g,V

OUT e5.5V 250 mA

IOL Low Level Output Current, a–g,V

OL e3.0V 12 18 mA

TAFree Air Operating Temperature 0 70 §C

ts(H) Setup Time HIGH or LOW 75 ns

ts(L) An to LE 30

th(H) Hold Time HIGH or LOW 0 ns

th(L) An to LE 0

tw(L) LE Pulse Width LOW 85 ns

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

(Note 1)

VIInput Clamp Voltage VCC eMin, IIeb

12 mA b1.5 V

VOH High Level Output Voltage VCC eMin, IOH eMax, VIL eMax 2.4 3.4 V

VOL Low Level Output Voltage VCC eMin, IOL eMax, VIH eMin 0.2 0.4 V

IIInput Current @Max Input Voltage VCC eMax, VIe5.5V 1 mA

IIH High Level Input Current VCC eMax, VIe2.4V 40 mA

IIL Low Level Input Current VCC eMax, VIe0.4V b1.6 mA

IOS Short Circuit Output Current VCC eMax (Note 2) b18 b57 mA

ICCH Supply Current VCC eMax, VIN e0V, 50 mA

VOUT e3.0V

Note 1: All typicals are at VCC e5V, TAe25§C.

Note 2: Not more than one output should be shorted at a time.

Switching Characteristics

VCC ea

5.0V, TAea

25§C (See Section 1 for test waveforms and output load)

CLe15 pF

Symbol Parameter RLe1kXUnits

Min Max

tPLH Propagation Delay 140 ns

tPHL An to a–g 140

tPLH Propagation Delay 140 ns

tPHL LE to a–g 140

TL/F/10210–9

FIGURE A. Output Voltage Safe Operating Area

TL/F/10210–10

FIGURE B. Typical Constant Segment Current

Versus Output Voltage

Functional Description

The ’9374 is a 7-segment decoder/driver with latches on

the address inputs and active LOW constant current outputs

to drive LEDs directly. This device accepts a 4-bit binary

code and produces output drive to the appropriate seg-

ments of the 7-segment display. It has a decode format

which produces numeric codes ‘‘0’’ through ‘‘9’’ and other

codes.

Latches on the four data inputs are controlled by an active

LOW Latch Enable, LE. When LE is LOW, the state of the

outputs is determined by the input data. When LE goes

HIGH, the last data present at the inputs is stored in the

latches and the outputs remain stable. The LE pulse width

necessary to accept and store data is typically 50 ns, which

allows data to be strobed into the ’74 at normal TTL speeds.

This feature means that data can be routed directly from

high speed counters and frequency dividers into the display

without slowing down the system clock or providing interme-

diate data storage.

The latch/decoder combination is a simple system which

drives LED displays with multiplexed data inputs from MOS

time clocks, DVMs, calculator chips, etc. Data inputs are

multiplexed while the displays are in static mode. This low-

ers component and insertion costs, since several circuitsÐ

seven resistors per display, strobe drivers, a separate dis-

play voltage source, and clock failure detect circuitsÐtradi-

tionally found in multiplexed display systems are eliminated.

It also allows low strobing rates to be used without display

flicker.

Another ’74 feature is the reduced loading on the data in-

puts when the Latch Enable is HIGH (only 10 mA typ). This

allows many ’74s to be driven from a MOS device in multi-

plex mode without the need for drivers on the data lines.

The ’74 also provides automatic blanking of the leading

and/or trailing-edge zeroes in a multidigit decimal number,

resulting in an easily readable decimal display conforming to

normal writing practice. In an 8-digit mixed integer fraction

decimal representation, using the automatic blanking capa-

bility 0060.0300 would be displayed as 60.03. Leading-edge

zero suppression is obtained by connecting the Ripple

Blanking Output (RBO) of a decoder to the Ripple Blanking

Input (RBI) of the next lower stage device. The most signifi-

cant decoder stage should have the RIB input grounded;

and since suppression of the least significant integer zero in

a number is not usually desired, the RBI input of this decod-

er stage should be left open. A similar procedure for the

fractional part of a display will provide automatic suppres-

sion of trailing-edge zeroes. The RBO terminal of the decod-

er can be OR-tied with a modulating signal via an isolating

buffer to achieve duration intensity modulation. A suitable

signal can be generated for this purpose by forming a vari-

able frequency multivibrator with a cross coupled pair of

TTL or DTL gates.

Logic Diagram

TL/F/10210–3

Truth Table

Binary Inputs Outputs Display

State LE RBI A3 A2 A1 A0 a b c d e f g RBO

ÐH*XXXX

STABLE H Stable

0 L L LLLLHHHHHHH L Blank

0 L H LLLLLLLLLLH H 0

1 L X L L L H HL LHHHH H 1

2 L X L L H L LLHLLHL H 2

3 L X L L H H LLLLHHL H 3

4 L X L H L L HLLHHLL H 4

5 L X LHLHLHLLHLL H 5

TL/F/10210–4

6 L X L H H L LHLLLLL H 6

7 L X L H H H L L LHHHH H 7

8 L X H L L L LLLLLLL H 8

9 L X H L L H LLLLHLL H 9

10 L X HLHLHHHHHHL H Ð

11 L X H L H H LHHLLLL H E

12 L X H H L L HLLHLLL H H

13 L X HHLHHHHLLLHH L

14 L X HHHLLLHHLLL H P

15 L X HHHHHHHHHHH H BLANK

X X X XXXXHHHHHHH L** BLANK

*The RBI will blank the display only if a binary zero is stored in the latches.

**RBO used as an input overrides all other input conditions.

HeHIGH Voltage Level

LeLOW Voltage Level

XeImmaterial

Numerical Designations

TL/F/10210–5

Applications

It is possible with common anode 7-segment LED displays

and constant current sink decoder drivers to save substan-

tial amounts of power by carefully choosing operating points

on display supply voltage. First, examine the power used in

the normal display driving method where the display and

decoder driver are both operated from a a5.0V regulated

supply (VCC eVS).

The power dissipated by the LED and the driver outputs is

(VCC xI

seg x n Segments). The total power dissipated with a

15 mA LED displaying an eight (8) would be:

PTOT e5.0Vx15mAx7

e525 mW

Of this 525 mW, the power actually required to drive the

LED is dependent on the VFdrop of each segment. Most

GaAsP LEDs exhibit either a 1.7V or a 3.4V forward voltage

drop. Therefore, the required total power for seven seg-

ments would be:

P(1.7) e1.7Vx15mAx7

e178.5 mW

P(3.4) e3.4Vx15mAx7

e357 mW

The remaining power is dissipated by the driver outputs

which are maintaining the 15 mA constant current required

by the LEDs. Most of this power is wasted, since the driver

can maintain approximately 15 mA with as little as 0.5V

across the output device. By using a separate power source

(VS,

Figure C

) for the LEDs, which is set to the LED VFplus

the offset voltage of the driver, as much as 280 mW can be

saved per digit. i.e.,

VSeVF(Max) aVoffset

e2.0V a0.5V

e2.5V

PTe2.5V x 14 mA (from

Figure B

)x7

e245 mW

These figures show that using a separate supply to drive the

LEDs can offer significant display power savings. In battery

powered equipment, two rechargeable nickle-cadmium cells

in series would be sufficient to drive the display, while four

such cells would be needed to operate the logic units.

Another method to save power is to apply intensity modula-

tion to the displays

(Figure D)

. It is well known that LED

displays are more efficient when operated in pulse mode.

There are two reasons: one, the quantum efficiency of the

LED material is better; secondly the eye tends to peak de-

tect. Typically a 20% off duty cycle to displays (GaAsP) will

produce the same brightness as operating under dc condi-

tions.

TL/F/10210–11

FIGURE C. Separate Supply for LED Displays

Applications (Continued)

TL/F/10210–6

All Inverters are DTL 9936 or Open Collector TTL 7405

FIGURE D. Intensity Control by RBO Pulse Duty Cycle

Low Power, Low Cost Display Power SourcesÐIn small

line operated systems using TTL/MSI and LED or incandes-

cent displays, a significant portion of the total dc power is

consumed to drive the displays. Since it is irrelevant wheth-

er displays are driven from unfiltered dc or pulsed dc (at fast

rates), a dual power system can be used that makes better

utilization of transformer rms ratings. The system utilizes a

full wave rectified but unsmoothed dc voltage to provide the

displays with 120 Hz pulsed power while the reset of the

system is driven by a conventional dc power circuit. The

frequency of 120 Hz is high enough to avoid display flicker

problems. The main advantages of this system are:

#Reduced transformer rating

#Much smaller smoothing capacitor

#Increased LED light output due to pulsed operation

With the standard capacitor filter circuit, the rms current (full

wave) loading of the transformer is approximately twice the

dc output. Most commercial transformer manufacturers rate

transformers with capacitive input filters as follows:

Full Wave Bridge Rectifier Circuit

Transformer rms current e1.8 x dc current required

Full Wave Center Tapped Rectifier Circuit

Transformer rms current e1.2 x dc current required

Therefore, the removal of a large portion of the filtered dc

current requirement (display power) substantially reduces

the transformer loading.

There are two basic approaches. First

(Figure E)

is the di-

rect full wave rectified unregulated supply to power the dis-

plays. The ’74 decoder driver constant current feature main-

tains the specified segment current after the LED diode

drop and 0.5V saturation voltage has been reached

(j2.2V). Care must be exercised not to exceed the ’74

power ratings and the maximum voltage that the decoder

driver sees in both the ‘‘on’’ and ‘‘off’’ modes.

The second approach

(Figure F)

uses a 3-terminal voltage

regulator such as the 7805 to provide dc pulsed power to

the display with the peak dc voltage limited to a5.0V. This

approach allows easier system thermal management by

heat sinking the regulator rather than the display or display

drivers. When this power source is used with an intensity

modulation scheme or with a multiplexed display system,

the frequencies must be chosen such that they do not beat

with the 120 Hz full wave rectified power frequency.

Applications (Continued)

TL/F/10210–7

FIGURE E. Direct Unregulated Display Supply

TL/F/10210–8

FIGURE F. Pulsed Regulated Display Supply

DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs

Physical Dimensions inches (millimeters)

16-Lead Molded Dual-In-Line Package (N)

Order Number DM9374N

NS Package Number N16E

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