1
Ultra Low Dropout 1A, 2A, 3A Low Input Voltage NMOS
LDOs
ISL80111, ISL80112, ISL80113
The ISL80111, ISL80112, and ISL80113 are ultra low dropout
LDOs providing the optimum balance between performance, size
and power consumption in size constrained designs for data
communication, computing, storage and medical applications.
These LDOs are specified for 1A, 2A and 3A of output current and
are optimized for low voltage conversions.Operating with a VIN of
1V to 3.6V and with a legacy 3.3V to 5V on the BIAS, the VOUT is
adjustable from 0.8V to 3.3V. With a VIN PSRR greater than 40dB
at 100kHz makes these LDOs an ideal choice in noise sensitive
applications. The guaranteed ±1.6% VOUT accuracy overall
conditions lends these parts to suppling an accurate voltage to
the latest low voltage digital ICs.
An enable input allows the part to be placed into a low quiescent
current shutdown mode. A submicron CMOS process is utilized for
this product family to deliver best-in-class analog performance
and overall value for applications in need of input voltage
conversions typically below 2.5V. It also has the superior load
transient regulation unique to a NMOS power stage. These LDOs
consume significantly lower quiescent current as a function of
load compared to bipolar LDOs.
Features
• Ultra low dropout: 75mV at 3A, (typ)
• Excellent VIN PSRR: 70dB at 1kHz (typ)
• ±1.6% guaranteed VOUT accuracy for -40ºC < TJ < +125ºC
• Very fast load transient response
• Extensive protection and reporting features
•V
IN range: 1V to 3.6V, VOUT range: 0.8V to 3.3V
• Small 10 Ld 3x3 DFN package
Applications
• Noise-sensitive instrumentation and medical systems
• Data acquisition and data communication systems
• Storage, telecommunications and server equipment
• Low voltage DSP, FPGA and ASIC core power supplies
• Post-regulation of switched mode power supplies
FIGURE 1. TYPICAL APPLICATION SCHEMATIC FIGURE 2. DROPOUT VOLTAGE OVER-TEMP AND IOUT
FIGURE 3. VIN PSRR vs LOAD CURRENT (ISL80113) FIGURE 4. ΔVADJ vs TEMPERATURE
VIN
9
VIN
10
ENABLE
7
VBIAS
4
GND
1.2V ±5%
CIN
10µF
VIN
CBIAS
5
PG 6
VOUT 1
VOUT 2
VOUT
1.0V
COUT
10µF
ADJ 3
PGOOD
R4
1.0kΩ
R3
1.0kΩ
EN
OPEN DRAIN COMPATIBLE
3.3V ±10%
VBIAS
1µF
ISL80111, ISL80112, ISL80113
TEMPERATURE (°C)
0
10
20
30
40
50
60
70
80
90
100
-40 25 85 125
DROPOUT VOLTAGE, BIAS = 5V (mV)
3A
2A
1A
0
20
40
60
80
100
100 1k 10k 100k 1M
PSRR (dB)
FREQUENCY (Hz)
IOUT = 2A
IOUT = 3A
IOUT = 0A
IOUT = 1A
BIAS = 5V
VOUT = 2.5V
VIN = 3.3V
COUT = 10µF
0.985
0.990
0.995
1.000
1.005
1.010
1.015
-40 0 25 85 125
TEMPERATURE (°C)
ΔVADJ +25°C NORMALIZED (%)
November 1, 2013
FN7841.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL80111, ISL80112, ISL80113
2FN7841.2
November 1, 2013
Block Diagram
Pin Configuration
ISL80111, ISL80112, ISL80113
(10 LD 3X3 DFN)
TOP VIEW
R7
EN
EN
ENEN
ENABLE M7
500mV
425mV
M3 POWER NMOS
M1
VIN
VOUT
*R3
GND
PG
ADJ
M2
+
-
+
-
+
-
+
-
+
-
IL/10,000 IL
VBIAS CURRENT
LIMIT
DRIVER
BIAS
EN
THERMAL
SHUTDOWN
UVLO
VIN
UVLO
VIN
2
3
4
1
5
9
8
7
10
6
VOUT
VOUT
ADJ
VBIAS
GND
VIN
VIN
NC
ENABLE
PG
EPAD
(GND)
Pin Descriptions
PIN
NUMBER PIN NAME DESCRIPTION
1, 2 VOUT Output voltage pin. Range 0.8V to 3.3V
3 ADJ ADJ pin for externally setting VOUT. Range
0.5V to VOUT
4 VBIAS Bias voltage pin for internal control circuits.
Range 2.9V to 5.5V
5GNDGround pin
6PGV
OUT in regulation signal. Logic low defines
when VOUT is not in regulation. Range 0V to
BIAS
7ENABLE V
IN independent chip enable. TTL and CMOS
compatible. Range 0V to VBIAS
8NCNo Connect
9, 10 VIN Input supply pins. Range 1.0V to 3.6V
EPAD EPAD at ground potential. It is recommended
to solder the EPAD to the ground plane.
ISL80111, ISL80112, ISL80113
3FN7841.2
November 1, 2013
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
VOUT
(V)
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG
DWG. #
ISL80111IRAJZ 1ADJ ADJ -40 to +85 10 Ld 3x3 DFN L10.3x3
ISL80112IRAJZ 2ADJ ADJ -40 to +85 10 Ld 3x3 DFN L10.3x3
ISL80113IRAJZ 3ADJ ADJ -40 to +85 10 Ld 3x3 DFN L10.3x3
ISL80111EVAL1Z ISL80111 Evaluation Board
ISL80112EVAL1Z ISL80112 Evaluation Board
ISL80113EVAL1Z ISL80113 Evaluation Board
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information pages for ISL80111, ISL80112, and ISL80113. For more information on MSL
please see Tech Brief TB363.
ISL80111, ISL80112, ISL80113
4FN7841.2
November 1, 2013
Absolute Maximum Ratings (Note4) Thermal Information
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 to +6V
VOUT Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +4V
PG, ENABLE, SENSE/ADJ, Relative to GND (Note 5) . . . . . . . . . -0.3 to +6V
VBIAS Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
PG Rated Current (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . 4000V
Machine Model (Tested per JESD22-115-A) . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V
Latch Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
10 Ld 3x3 DFN Package (Notes 7, 8). . . . . 48 4
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions (Notes 4, 6)
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VIN Relative to GND (ISL80113) (Note 9) . . . . . . . . . . . . VOUT + 0.4V to 5V
VIN Relative to GND (ISL80112) (Note 9) . . . . . . . . . . . . VOUT + 0.3V to 5V
VIN Relative to GND (ISL80111) (Note 9) . . . . . . . . . . . . VOUT + 0.2V to 5V
Nominal VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 3.3V
PG, ENABLE, SENSE/ADJ, SS Relative to GND . . . . . . . . . . . . . . .0V to 5.5V
VBIAS Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 5.5V
VBIAS Relative to VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8V minimum
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. Absolute maximum ratings define limits of safe operation. Extended operation at these conditions may compromise reliability. Exceeding these limits
will result in damage. Recommended operating conditions define limits where specifications are guaranteed.
5. Absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
6. Electromigration specification defined as lifetime average junction temperature of +110°C where maximum rated DC current = lifetime average
current.
7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
9. Minimum operating voltage applied to VIN is 1V if VIN - VDO < 1V
Electrical Specifications Unless otherwise specified, VIN = VOUT + 0.4V, VBIAS = 2.9V, VOUT = 1.2V, CBIAS = 1µF, CIN = 10µF,
COUT = 2.2µF, TJ = +25°C, IL = 0mA. Applications must follow thermal guidelines of the package to determine worst-case junction temperature. Please
refer to “Power Dissipation” on page 13 and Tech Brief TB379.
Boldface limits apply over junction temperature (TJ) range, -40°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA where datasheet limits
are defined.
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10) UNITS
DC CHARACTERISTICS
VBIAS UVLO UVLO_BIAS_r VBIAS Rising 2.3 2.9 V
UVLO_BIAS_f VBIAS Falling 1.55 2.1 2.8 V
VBIAS UVLO Hysteresis UVLOB_HYS 0.2 V
DC ADJ Pin Voltage Accuracy VADJ 1.0V ≤ VIN ≤ 3.6V, ILOAD = 0A, 2.9V ≤ VBIAS ≤ 5.5V,
VOUT = VADJ
494 502 510 mV
DC Input Line Regulation ΔVOUT VOUT + 0.4V ≤ VIN ≤ 3.6V 0.01 0.9 mV
DC Bias Line Regulation ΔVOUT 2.9V<VBIAS<5.5V with respect to ADJ pin 0.3 1.4 mV
DC Output Load Regulation ΔVOUT 0A ≤ ILOAD ≤ 3A -2 -0.2 2mV
Feedback Input Current VADJ = 0.5V 10 80 nA
VIN Quiescent Current IQ (VIN) VOUT = 2.5V 8 10 mA
VIN Quiescent Current IQ (VIN) VOUT = 3.3, 10.6 mA
ISL80111, ISL80112, ISL80113
5FN7841.2
November 1, 2013
VIN Quiescent Current IQ (VIN) VOUT = 1.0V 3.5 mA
VBIAS Quiescent Current IQ (VBIAS) 0 ≤ IL ≤ 3A, VBIAS = 5.5V 2.9 4.6 mA
Ground Pin Current in
Shutdown
ISHDN ENABLE Pin = 0.2V, TJ = +125°C 3 20 µA
VIN Dropout Voltage
(Note 11)
VDO(VIN) ILOAD = 1A, VOUT = 1.2V, 2.9V ≤ VBIAS ≤ 5V 27 90 mV
ILOAD = 2A, VOUT = 1.2V, 2.9V ≤ VBIAS ≤ 5V 53 115 mV
ILOAD = 3A, VOUT = 1.2V, 2.9V ≤ VBIAS ≤ 5V 75 140 mV
VBIAS Dropout Voltage
(Note 11)
VDO(BIAS) ILOAD = 1A, VOUT = 1.2V 1.1 1.3 V
ILOAD = 2A, VOUT = 1.2V 1.2 1.4 V
ILOAD = 3A, VOUT = 1.2V 1.3 1.5 V
OVERCURRENT PROTECTION
Output Short Circuit Current
(3A Version)
ISC VOUT = 0.2V 5.2 A
Output Short Circuit Current
(2A Version)
VOUT = 0.2V 3.2 A
Output Short Circuit Current
(1A Version)
VOUT = 0.2V 2.2 A
OVER-TEMPERATURE PROTECTION
Thermal Shutdown
Temperature
TSD 160 °C
Thermal Shutdown
Hysteresis
TSDn 20 °C
AC CHARACTERISTICS
Input Supply Ripple Rejection PSRR(VIN) f = 120Hz, ILOAD = 1A 80 dB
PSRR(VBIAS) f = 120Hz, ILOAD = 1A 60 dB
Output Noise Voltage eN(RMS) ILOAD = 10mA, BW = 100Hz ≤ f ≤ 100kHz 100 µVRMS
Spectral Noise Density eNILOAD = 3A, f = 10Hz 7 µV/√Hz
ILOAD = 3A, f = 100Hz 3 µV/√Hz
DEVICE START-UP CHARACTERISTICS
EN Start-up Time tEN COUT = 10µF, ILOAD = 1A 50 µs
BIAS Start-up Time tBIAS COUT = 10µF, EN = BIAS 100 µs
ENABLE PIN CHARACTERISTICS
Turn-on Threshold (Rising) VOUT + 0.4V ≤ VIN ≤ 3.6V, 2.9V ≤ VBIAS ≤ 5.5V 400 680 850 mV
Hysteresis (Rising Threshold) 1.2V ≤ VIN ≤ 3.6V, 2.9V ≤ VBIAS ≤ 5.5V 60 260 330 mV
PG PIN CHARACTERISTICS
PG Flag Falling Threshold PGTH 2.9V ≤ VBIAS ≤ 5.5V 71 82 93 %VOUT
PG Flag Hysteresis PGHYS 2.9V ≤ VBIAS ≤ 5.5V 9.3 %VOUT
Electrical Specifications Unless otherwise specified, VIN = VOUT + 0.4V, VBIAS = 2.9V, VOUT = 1.2V, CBIAS = 1µF, CIN = 10µF,
COUT = 2.2µF, TJ = +25°C, IL = 0mA. Applications must follow thermal guidelines of the package to determine worst-case junction temperature. Please
refer to “Power Dissipation” on page 13 and Tech Brief TB379.
Boldface limits apply over junction temperature (TJ) range, -40°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA where datasheet limits
are defined. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10) UNITS
ISL80111, ISL80112, ISL80113
6FN7841.2
November 1, 2013
PG Flag Low Voltage ISINK = 500µA 90 130 mV
PG Flag Leakage Current PG = VBIAS = 5.5V 11 300 nA
PG Flag Sink Current 710 mA
NOTES:
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
11. Dropout is defined by the difference in supply (VIN, VBIAS) and VOUT when the supply produces a 2% drop in VOUT from its nominal value, output
voltage set to 2.5V.
12. For normal operation, VIN must always be less than or equal to the voltage applied to VBIAS. Part is protected against fault conditions where VIN can
be greater than VBIAS.
Electrical Specifications Unless otherwise specified, VIN = VOUT + 0.4V, VBIAS = 2.9V, VOUT = 1.2V, CBIAS = 1µF, CIN = 10µF,
COUT = 2.2µF, TJ = +25°C, IL = 0mA. Applications must follow thermal guidelines of the package to determine worst-case junction temperature. Please
refer to “Power Dissipation” on page 13 and Tech Brief TB379.
Boldface limits apply over junction temperature (TJ) range, -40°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA where datasheet limits
are defined. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10) UNITS
ISL80111, ISL80112, ISL80113
7FN7841.2
November 1, 2013
Typical Operating Performance Unless otherwise noted, VIN = 1.8V, VBIAS = 3.3V, VOUT = 1.2V, CIN = COUT = 10µF,
TJ = +25°C, ILOAD = 0A.
FIGURE 5. DROPOUT vs VBIAS FIGURE 6. VADJ DISTRIBUTION
FIGURE 7. ΔVADJ vs TEMPERATURE FIGURE 8. LOAD REGULATION vs TEMPERATURE
FIGURE 9. LOAD REGULATION, VOUT vs IOUT FIGURE 10. VIN LINE REGULATION
0
10
20
30
40
50
60
70
80
90
100
-40 25 125
TEMPERATURE (°C)
3A VBIAS = 3.3V
3A VBIAS = 5V
2A VBIAS = 3.3V
2A VBIAS = 5V
1A VBIAS = 3.3V
1A VBIAS = 5V
VIN DROPOUT VOLTAGE (mV)
0
2
4
6
8
10
12
14
16
18
500.0 500.5 501.0 501.5 502.0 502.5 503.0 503.5 504.0
PERCENTAGE OF POPULATION
VADJ @ +25°C (mV)
0.985
0.990
0.995
1.000
1.005
1.010
1.015
-40 0 25 85 125
TEMPERATURE (°C)
ΔVADJ +25°C NORMALIZED (%)
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
-40 0 25 85 125
TEMPERATURE (°C)
Δ VOUT (mV)
IOUT = 0A - 3A
LOAD CURRENT (A)
0 0.5 1.0 1.5 2.0 2.5 3.0
1.2200
1.2175
1.2150
1.2125
1.2100
1.2075
1.2050
1.2025
1.2000
1.1975
1.1950
1.1925
1.1900
OUTPUT VOLTGE (V)
VIN = 1.6V, VBIAS = 2.9V
VBIAS=3.7V
VBIAS = 3.7V
1.205
1.204
1.203
1.202
1.201
1.200
1.199
1.198
1.197
1.196
1.195
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.61.82.02.22.42.62.83.03.23.43.63.84.0
ISL80111, ISL80112, ISL80113
8FN7841.2
November 1, 2013
FIGURE 11. VBIAS LINE REGULATION FIGURE 12. BIAS GROUND CURRENT vs LOAD CURRENT
FIGURE 13. INPUT GROUND CURRENT vs VIN and VOUT FIGURE 14. INPUT GROUND CURRENT vs VBIAS
FIGURE 15. BIAS GROUND CURRENT vs VIN and VOUT FIGURE 16. BIAS GROUND CURRENT vs VBIAS
Typical Operating Performance Unless otherwise noted, VIN = 1.8V, VBIAS = 3.3V, VOUT = 1.2V, CIN = COUT = 10µF,
TJ = +25°C, ILOAD = 0A. (Continued)
VIN=1.6V
VIN = 1.6V
1.205
1.204
1.203
1.202
1.201
1.200
1.199
1.198
1.197
1.196
1.195
BIAS VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0123
BIAS GROUND CURRENT (mA)
OUTPUT CURRENT(A)
BIAS = 5V
BIAS = 2.9V
VIN INPUT VOLTAGE (V)
1.0 1.4 1.8 2.2 2.6 3.0 3.8
11
VIN INPUT GROUND CURRENT (mA)
3.4
10
9
8
7
6
5
4
3
2
1
VBIAS = 5V
VOUT = 0.8V
VBIAS = 5V
VOUT = 1.0V
VBIAS = 5V
VOUT = 3.3V
VBIAS = 5V
VOUT = 1.8V
VBIAS = 3.3V
VOUT = 1.8V
VBIAS = 3.3V
VOUT = 1.0V
VBIAS = 3.3V
VOUT = 0.8V
BIAS VOLTAGE (V)
2.9 3.2 3.5 3.8 4.1 4.4 5.0
3.2
BIAS INPUT GROUND CURRENT (mA)
4.7
2.8
2.6
2.4
2.2
2.0
3.0
VIN=1.6V
VOUT = 0.8V
INPUT VOLTAGE (V)
1.0 1.4 1.8 2.2 2.6 3.0 3.8
3.2
BIAS GROUND CURRENT (mA)
3.4
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
VBIAS = 3.3V
VOUT = 2.5V
VBIAS = 5V
VOUT = 2.5V
VBIAS = 5V
VOUT = 1.2V
VBIAS = 5V
VOUT = 0.8V
VBIAS = 3.3V
VOUT = 0.8V
VBIAS = 3.3V
VOUT = 1.2V
BIAS VOLTAGE (V)
2.9 3.2 3.5 3.8 4.1 4.4 5.0
3.45
BIAS GROUND CURRENT (mA)
VIN = 1.6V
4.7
2.85
2.65
2.45
2.25
1.85
3.25
3.05
2.05
ISL80111, ISL80112, ISL80113
9FN7841.2
November 1, 2013
FIGURE 17. VIN IQ vs VOUT VOLTAGE FIGURE 18. ENABLE START-UP WITH PGOOD
FIGURE 19. ISL8011X INTO AND OUT OF THERMAL SHUTDOWN FIGURE 20. ISL80111 ENABLED INTO OVERCURRENT
FIGURE 21. ISL80112 ENABLED INTO OVERCURRENT FIGURE 22. ISL80113 ENABLED INTO OVERCURRENT
Typical Operating Performance Unless otherwise noted, VIN = 1.8V, VBIAS = 3.3V, VOUT = 1.2V, CIN = COUT = 10µF,
TJ = +25°C, ILOAD = 0A. (Continued)
0
2
4
6
8
10
12
1.0 1.5 1.8 2.5 3.3
VIN INPUT CURRENT (mA)
OUTPUT VOLTAGE(V)
VBIAS = 5.0V
VOUT = 3.6V
EN
VOUT
IIN
PGOOD
VOUT
PGOOD
IOUT
EN
VOUT
IIN
CLOAD = 1000µF
PGOOD
ISL80111 CURRENT LIMITING @ 2.1A
DURING TURN-ON OC EVENT
EN
VOUT
IIN
CLOAD = 1000µF
PGOOD
ISL80112 CURRENT LIMITING @ 3.4A
DURING TURN-ON OC EVENT
EN
VOUT
IIN
CLOAD = 1000µF
PGOOD
ISL80113 CURRENT LIMITING @ 5A
DURING TURN-ON OC EVENT
ISL80111, ISL80112, ISL80113
10 FN7841.2
November 1, 2013
FIGURE 23. 100mA LOAD TRANSIENT RESPONSE FIGURE 24. 1A LOAD TRANSIENT RESPONSE
FIGURE 25. 2A LOAD TRANSIENT RESPONSE FIGURE 26. 3A LOAD TRANSIENT RESPONSE
FIGURE 27. VIN PSRR vs LOAD CURRENT FIGURE 28. BIAS PSRR vs LOAD CURRENT
Typical Operating Performance Unless otherwise noted, VIN = 1.8V, VBIAS = 3.3V, VOUT = 1.2V, CIN = COUT = 10µF,
TJ = +25°C, ILOAD = 0A. (Continued)
TIME (20µs/DIV)
VOUT (5mV/DIV)
IOUT = 200mA
IOUT =100mA
VOUT (20mV/DIV)
IOUT = 1.1A
IOUT = 0.1A
TIME (20µs/DIV)
VOUT (20mV/DIV)
IOUT = 2.1A
IOUT = 0.1A
TIME (20µs/DIV)
VOUT (50mV/DIV)
IOUT = 3.1A
IOUT = 0.1A
TIME (20µs/DIV)
0
20
40
60
80
100
100 1k 10k 100k 1M
PSRR (dB)
FREQUENCY (Hz)
IOUT = 2A
IOUT = 3A
IOUT = 0A
IOUT = 1A
BIAS = 5V
VOUT = 2.5V
VIN = 3.3V
COUT = 10µF
0
20
40
60
80
100
100 1k 10k 100k 1M
PSRR (dB)
FREQUENCY (Hz)
BIAS = 5V
VOUT = 2.5V
VIN = 3.3V
COUT = 10µF
IOUT = 3A
IOUT = 0A
IOUT = 1A
IOUT = 2A
ISL80111, ISL80112, ISL80113
11 FN7841.2
November 1, 2013
FIGURE 29. VVIN PSRR vs LOAD CURRENT FIGURE 30. VBIAS PSRR vs LOAD CURRENT
FIGURE 31. VIN PSRR vs COUT FIGURE 32. VIN PSRR vs COUT
FIGURE 33. VIN PSRR vs LOAD CURRENT FIGURE 34. VBIAS PSRR vs LOAD CURRENT
Typical Operating Performance Unless otherwise noted, VIN = 1.8V, VBIAS = 3.3V, VOUT = 1.2V, CIN = COUT = 10µF,
TJ = +25°C, ILOAD = 0A. (Continued)
0
20
40
60
80
100
100 1k 10k 100k 1M
PSRR (dB)
FREQUENCY (Hz)
IOUT = 0A
IOUT = 2A
BIAS = 3.3V
VOUT = 1.0V
VIN = 1.5V
COUT = 10µF
IOUT = 3A
IOUT = 1A
0
20
40
60
80
100
PSRR (dB)
100 1k 10k 100k 1M
FREQUENCY (Hz)
IOUT = 0A
IOUT = 2A
BIAS = 3.3V
VOUT = 1.0V
VIN = 1.5V
COUT = 10µF
IOUT = 3A
IOUT = 1A
0
20
40
60
80
100
PSRR (dB)
100 1k 10k 100k 1M
FREQUENCY (Hz)
BIAS = 5V
VOUT = 2.5V
VIN = 3.3V
IOUT = 3A
COUT = 10µF
COUT = 20µF
COUT = 2.2µF
0
20
40
60
80
100
PSRR (dB)
100 1k 10k 100k 1M
FREQUENCY (Hz)
BIAS = 5V
VOUT = 2.5V
VIN = 3.3V
IOUT = 1A
COUT = 2.2µF
COUT = 20µF
COUT = 10µF
0
20
40
60
80
100
PSRR (dB)
100 1k 10k 100k 1M
FREQUENCY (Hz)
IOUT = 0A
IOUT = 2A
BIAS = 5V
VOUT = 2.5V
VIN = 3.3V
COUT = 5x2.2µF
IOUT = 3A
IOUT = 1A
0
20
40
60
80
100
PSRR (dB)
100 1k 10k 100k 1M
FREQUENCY (Hz)
IOUT = 0A
IOUT = 2A
BIAS = 5V
VOUT = 2.5V
VIN = 3.3V
COUT = 5x2.2µF
IOUT = 3A
IOUT = 1A
ISL80111, ISL80112, ISL80113
12 FN7841.2
November 1, 2013
Functional Description
The ISL80111, ISL80112 and ISL80113 are high-performance,
low-dropout regulators featuring an NMOS pass device. Benefits
of using an NMOS as a pass device include low input voltage,
stability over a wide range of output capacitors, and ultra low
dropout voltage. The ISL80111, ISL80112 and ISL80113 are
ideal for post regulation of switch mode power supplies.
The ISL80111, ISL80112 and ISL80113 also integrate enable,
power-good indicator, current limit protection, and thermal
shutdown functions into a space-saving 3x3 DFN package.
Input Voltage Requirements
The VIN pin provides the high current to the drain of the NMOS
pass transistor. The specified minimum input voltage is 1V and
dropout voltage for this family of LDOs has been conservatively
specified.
Bias Voltage Requirements
The VBIAS input powers the internal control circuits, reference
voltage, and LDO gate driver. The difference between the VBIAS
voltage and the output voltage must be greater than the VBIAS
dropout voltage specified in the “Electrical Specifications” table
beginning on Page 4. The minimum VBIAS input is 2.9V.
Enable Operation
The ENABLE turn-on threshold is typically 600mV with a
hysteresis of 100mV. This pin must not be left floating. When this
pin is not used, it must be tied to VBIAS. A 1k to 10k pull-up
resistor is required for applications that use open collector or
open drain outputs to control the ENABLE pin.
Soft-start Operation
The ISL8011x has an internal 100µs typical soft-start function to
prevent excessive in-rush current during start-up.
Power-good Operation
The PGOOD flag is an open-drain NMOS that can sink up to 10mA
during a fault condition. Applications not using this feature must
connect this pin to ground. The PGOOD pin requires an external
pull-up resistor, which is typically connected to the VOUT pin. The
PGOOD pin should not be pulled up to a voltage source greater
than VBIAS. A PGOOD fault can be caused by the output voltage
going below 84% of the nominal output voltage. PGOOD does not
function during thermal shutdown as the VOUT is less than the
minimum regulation voltage during that time.
Output Voltage Selection
An external resistor divider is used to scale the output voltage
relative to the internal reference voltage. This voltage is then fed
back to the error amplifier. The output voltage can be
programmed to any level between 0.8V and 4V. Referring to
Figure 1 the external resistor divider, R3 and R4, is used to set
the output voltage as shown in Equation 1. The recommended
value for R4 is 500 to 1k. R3 is then chosen according to
Equation 2.
Current Limit Protection
The ISL80111, ISL80112, and ISL80113 incorporate protection
against overcurrent due to a short, overload condition applied to
the output and the in-rush current that occurs at start-up. The
LDO performs as a constant current source when the output
current exceeds the current limit threshold noted in “Electrical
Specifications” on page 4. If the short or overload condition is
removed from VOUT, then the output returns to normal voltage
mode regulation. In the event of an overload condition, the LDO
might begin to cycle on and off due to the die temperature
exceeding the thermal fault condition.
Thermal Fault Protection
If the die temperature exceeds (typically) +160°C, the LDO
output shuts down until the die temperature cools to (typically)
+140°C. The level of power, combined with the thermal
impedance of the package (+48°C/W), determines whether the
junction temperature exceeds the thermal shutdown
temperature.
FIGURE 35. CONTINUOUS POWER LIMIT vs AIR TEMP AND FLOW FIGURE 36. INPUT VOLTAGE NOISE vs BIAS VOLTAGE
Typical Operating Performance Unless otherwise noted, VIN = 1.8V, VBIAS = 3.3V, VOUT = 1.2V, CIN = COUT = 10µF,
TJ = +25°C, ILOAD = 0A. (Continued)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
25 30 35 40 45 50 55 60 65 70 75 80 85 105 125
TEMPERATURE (°C)
0 lfm
300 lfm
MAX POWER (VIN-VOUT) x IOUT (W)
0.1
1
10
100
1000
0.1 1 10 100 1k 10k 100k
FREQUENCY (Hz)
INPUT VOLTAGE NOISE (µV/√Hz)
VBIAS = 3.8V
VOUT = 1V
VIN = 1.28V
IOUT = 3A
VBIAS = 5V
VOUT = 3.3V
VIN = 3.8V
IOUT = 3A
VOUT 0.5V R3
R4
-------1+
⎝⎠
⎜⎟
⎛⎞
×=(EQ. 1)
R3R4VOUT
0.5V
----------------1–
⎝⎠
⎛⎞
×=(EQ. 2)
ISL80111, ISL80112, ISL80113
13 FN7841.2
November 1, 2013
See Figure 35 for maximum continuous power dissipation
guidance for ambient temperature and linear air flow rate. This
graph ignores the insignificant power dissipation contribution of
the BIAS pin.
External Capacitor
Requirements
External capacitors are required for proper operation. To ensure
optimal performance, careful attention must be paid to the
layout guidelines and selection of capacitor type and value.
Input Capacitor
The minimum input capacitor required for proper operation is
10µF with a ceramic dielectric. This minimum capacitor must be
connected to the VIN and ground pins of the LDO no further than
0.5cm away.
Output Capacitor
The ISL8011x applies state-of-the-art internal compensation to
simplify selection of the output capacitor. Stable operation over
the full temperature range, VIN range, VOUT range, and load
extremes is guaranteed for all capacitor types and values,
assuming a 1µF X5R/X7R is used for local bypass on VOUT. This
minimum capacitor must be connected to the VOUT and ground
pins of the LDO no further than 0.5cm away.
Lower-cost Y5V and Z5U type ceramic capacitors are acceptable,
if the size of the capacitor is larger, to compensate for the
significantly lower tolerance over X5R/X7R types. Additional
capacitors of any value, in ceramic, POSCAP, or alum/tantalum
electrolytic types, can be placed in parallel to improve PSRR at
higher frequencies or load-transient AC output voltage
tolerances.
Bias Capacitor
The minimum input capacitor required for proper operation is
1µF with a ceramic dielectric. This minimum capacitor must be
connected to the VBIAS and ground pins of the LDO no further
than 0.5cm away. When the VBIAS pin is connected to the VIN
pin, a total of 10µF of X5R/X7R connected to the VIN pin and
ground is sufficient.
Power Dissipation and Thermals
Power Dissipation
Junction temperature must not exceed the range specified in the
“Recommended Operating Conditions” section on Page 4. Power
dissipation can be calculated with Equation 3.
The maximum allowable junction temperature, TJ(MAX), and the
maximum expected ambient temperature, TA(MAX), determine
the maximum allowable power dissipation, as shown in
Equation 4, where θJA is the junction-to-ambient thermal
resistance.
For safe operation, ensure that power dissipation calculated in
Equation 3 (PD) is less than the maximum allowable power
dissipation, PD(MAX).
The DFN package uses the copper area on the PCB as a heat
sink. For heat sinking, the EPAD of this package must be
soldered to the copper plane (GND plane). Figure 37 shows a
curve for the θJA of the DFN package for different copper area
sizes.
General PowerPAD Design Considerations
The following is an example of how to use vias to remove heat
from the IC.
Filling the thermal pad area with vias is recommended. A typical
via array is to fill the thermal pad footprint with vias spaced such
that they are center on center 3x the radius apart from each
other. Keep the vias small but not so small that their inside
diameter prevents solder from wicking through the holes during
reflow.
Connect all vias to the round plane. For efficient heat transfer, it
is important that the vias have low thermal resistance. Do not
use “thermal relief” patterns to connect the vias. It is important
to have a complete connection of the plated through-hole to each
plane.
PDVIN VOUT
–()IOUT VBIAS IQ BIAS()VIN IQ VIN
()×+×+×=
(EQ. 3)
PDMAX()
TJMAX()
TA
–()θ
JA
⁄=(EQ. 4)
FIGURE 37. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
THERMAL VIAS θJA vs EPAD-MOUNT COPPER LAND
AREA ON PCB
46
44
42
40
38
36
34
θJA (°C/W)
2 4 6 8 10 12 14 16 18 20 22 24
EPAD-MOUNT COPPER LAND AREA ON PCB (mm2)
FIGURE 38. PCB VIA PATTERN
ISL80111, ISL80112, ISL80113
14 FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
Split Supply LDO Evaluation
Board User Guide
Description
The ISL8011XEVAL1Z provides a simple platform to evaluate
performance of the ISL8011X family of split supply LDOs.
Jumpers are provided to easily set popular output voltages.
The ISL80111, ISL80112, and ISL80113 are single-output LDOs
specified for 1A, 2A, 3A of output current and are optimized for
less than 2.5V and less output voltage conversions. The
ISL8011X supports VIN voltages down to 1V, provided a standard
legacy 3.3V or 5V is applied on the VBIAS pin. The output voltage
is adjustable from 0.8V to 3.3V.
An enable input, having a threshold < 1V, allows the part to be
placed into a low quiescent current shutdown mode. A submicron
CMOS process is utilized for this product family to deliver
best-in-class analog performance and overall value for
applications in need of input voltage conversions to typically
below 2.5V. It also has the superior load transient regulation
unique to a NMOS power stage.
These LDOs consume significantly lower quiescent current as a
function of load compared to bipolar LDOs. This lower
consumption translates into higher efficiency and the ability to
consider packages with smaller footprints. The quiescent current
has been modestly compromised in design to enable leading
class fast load transient response and load regulation.
What’s Inside
• The evaluation kit contains the following:
• The ISL80113EVAL1Z with the appropriate parts installed
• The ISL80111, ISL80112, ISL80113 data sheet
Test Steps
1. Select the desired output voltage by shorting one of the
jumpers from JP2 through JP5.
2. Connect both the BIAS and VIN supplies and the load. Enable
the IC using jumper JP6 (bottom position) or via a signal on
the center post, observe the output.
3. The shipped configuration is enabled and VOUT = 3.3V.
4. Scope shots taken from ISL8011XEVAL1Z boards.
FIGURE 39. ISL80113EVAL1Z (TOP PCB LEFT, PHOTOGRAPH RIGHT)
ISL80111, ISL80112, ISL80113
15 FN7841.2
November 1, 2013
Schematic
Bill of Materials
REFERENCE
DESIGNATOR VALUE DESCRIPTION MANUFACTURER
PART
NUMBER
U1 ISL80111, ISL80112 or ISL80113 as noted on
the evaluation board
Intersil ISL80111IRAJZ,
ISL80112IRAJZ,
ISL80113IRAJZ
C1, C3 10µF CAP, SMD, 0805, 50V, 10% Generic
C2 1µF CAP, SMD, 0603 Generic
R1 1kRES, SMD, 0603, 1% Generic
R2 2.05kRES, SMD, 0603, 1% Generic
R3 2.61kRES, SMD, 0603, 1% Generic
R4 4.02kRES, SMD, 0603, 1% Generic
R5 5.62kRES, SMD, 0603, 1% Generic
R6 1kRES, SMD, 0603, 1% Generic
R7 100kRES, SMD, 0603, 1% Generic
JP1, JP2, JP3,
JP4, JP5, JP6
Jumper Generic
TP1, TP2, TP3
TP4, TP5, TP6
Terminal Connector Generic
ISL80111, ISL80112, ISL80113
16
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7841.2
November 1, 2013
For additional products, see www.intersil.com/product_tree
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE REVISION CHANGE
November 1, 2013 FN7841.2 Electrical Spec table: Bold the Min and Max values.
Page 4- Electrical Spec table title area: Removed “Unless otherwise noted, all parameters are guaranteed
over the conditions specified as follows” and replaced by “Unless otherwise specified”.
Updated POD to latest revision from rev 7 to rev 8. The changes as follow: Corrected L-shaped leads in
Bottom view and land pattern so that they align with the rest of the leads (L shaped leads were shorter)
June 5, 2012 FN7841.1 Ordering Information table on Page 3: Changed evaluation board names from: ISL80111IRAJEVALZ,
ISL80112IRAJEVALZ and ISL80113IRAJEVALZ to ISL80111EVAL1Z, ISL80112EVAL1Z and
ISL80113VAL1Z.
Changed POD L10.3x3 on Page 17 to latest revision from Rev 6 to Rev 7. Change to POD is as follows:
Removed package outline and included center to center distance between lands on recommended land
pattern.
Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm and
0.30mm from the terminal tip." since it is not applicable to this package. Renumbered notes accordingly.
Figure 6 VADJ Distribution , corrected "Y" scale units from (0.18, 0.16, 0.14, 0.12, 0.10, 0.08, 0.06, 0.04,
0.02, and 0.00) to (18, 16,14,12,10, 8, 6, 4, 2, and 0).
Electrical Specifications table on Page 4 "Added UVLO rising spec to show max of 2.9V so implementation
at 3.3V is not a math problem".
March 30 2012 FN7841.0 Initial Release and Added “UVLO _BIAS _r” spec on pg 4. Modified Figures 13 - 17.
ISL80111, ISL80112, ISL80113
17 FN7841.2
November 1, 2013
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 8, 7/12
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
5.
either a mold or mark feature.
3.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
(4X) 0.10
INDEX AREA
PIN 1
PIN #1 INDEX AREA
C
SEATING PLANE
BASE PLANE
0.08
SEE DETAIL "X"
C
C4
5
5
A
B
0.10 C
1
1.00
0.20
8x 0.50
2.00
3.00
(10x 0.23)
(8x 0.50)
2.00
1.60
(10 x 0.55)
3.00
0.05
0.20 REF
10 x 0.23
10x 0.35
1.60
MAX
(4X) 0.10 AB
C
M
0.415
0.23
0.35
0.200
2
2.85 TYP
