REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) A Updated document. Added three device types 04, 05, and 06. Added S package. Added two vendors. Editorial changes throughout. 91-08-23 M. A. Frye B Update boilerplate. Add device type 07 for vendor 66675. Editorial changes throughout. 94-07-12 M. A. Frye C Add device types 08 through 10. Update boilerplate. Editorial changes throughout. 95-05-12 M. A. Frye D Add device types 11 through 14. Update boilerplate. 98-12-04 Raymond Monnin E Lower tPD and tCO minimum value by 1 ns for devices 01, 02, and 03. ksr 99-08-04 Raymond Monnin F Boilerplate update, part of 5 year review. ksr 07-04-24 Robert M. Heber ksr APPROVED THE ORIGINAL FIRST PAGE HAS BEEN REPLACED REV SHEET REV SHEET REV STATUS REV F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Kenneth S. Rice STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 CHECKED BY http://www.dscc.dla.mil Wm J. Johnson APPROVED BY THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE Michael A. Frye DRAWING APPROVAL DATE MICROCIRCUIT, MEMORY, DIGITAL, EE PROGRAMMABLE ARRAY LOGIC, MONOLITHIC SILICON 89-12-18 AMSC N/A REVISION LEVEL F SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 . 1 OF 5962-89839 13 5962-E314-07 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89839 01 R A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time current 01 16V8 16-input, 8-output, EECMOS, architecturally generic, programmable AND-OR array 30 130 02 16V8 16-input, 8-output, EECMOS, architecturally generic, programmable AND-OR array 20 130 03 16V8 16-input, 8-output, EECMOS, architecturally generic, programmable AND-OR array 15 130 04, 11 16V8 16-input, 8-output, EECMOS, architecturally generic, programmable AND-OR array 10 130 05 16V8 16-input, 8-output, EECMOS, architecturally generic, programmable AND-OR array 25 65 06 16V8 16-input, 8-output, EECMOS, architecturally generic, programmable AND-OR array 20 65 07 16V8 16-input, 8-output, EECMOS, architecturally generic, programmable AND-OR array 7.5 130 08, 12 16V8 16-input, 8-output, EECMOS, architecturally generic, programmable AND-OR array 25 65 09, 13 16V8 16-input, 8-output, EECMOS, architecturally generic, programmable AND-OR array 15 130 10, 14 16V8 16-input, 8-output, EECMOS, architecturally generic, programmable AND-OR array 15 65 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter R S 2 Descriptive designator GDIP1-T20 or CDIP2-T20 GDFP2-F20 or CDFP3-F20 CQCC1-N20 Terminals Package style 20 20 20 Dual-in-line Flat package Square chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89839 A REVISION LEVEL F SHEET 2 1.3 Absolute maximum ratings. Supply voltage range ................................................................................... Input voltage range applied.......................................................................... Off-state output voltage range applied ......................................................... Storage temperature range .......................................................................... Maximum power dissipation (PD) 2/............................................................. Lead temperature (soldering, 10 seconds)................................................... Thermal resistance, junction-to-case (JC).................................................. Junction temperature (TJ)............................................................................. Data retention .............................................................................................. Endurance.................................................................................................... -0.5 V dc to +7.0 V dc -2.5 V dc to VCC + 1.0 V dc 1/ -2.5 V dc to VCC + 1.0 V dc 1/ -65C to +150C 1.5 W +260C See MIL-STD-1835 +175C 10 years (minimum) 100 erase/write cycles (minimum) 1.4 Recommended operating conditions. Supply voltage range (VCC)......................................................................... High level input voltage range (VIH)............................................................. Low level input voltage range (VIL) .............................................................. High level output current (IOH) .................................................................... Low level output current (IOL) ...................................................................... Case operating temperature range (TC) ...................................................... 4.5 V dc to 5.5 V dc 2.0 V dc to VCC + 1.0 V dc VSS -0.5 V dc to +0.8 V dc -2.0 mA maximum 12 mA maximum -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 1 Minimum input voltage is -0.5 V dc which may undershoot to -2.5 V dc for pulses less than 20 ns. 2/ Must withstand the added PD due to short circuit test (e.g., ISC). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89839 A REVISION LEVEL F SHEET 3 TABLE I. Electrical performance characteristics. Test Input leakage current Bidirectional pin leakage current Output low voltage Output high voltage Input low voltage 1/ Input high voltage 1/ Operating power supply current 2/ Output short circuit current 3/ Input capacitance Bidirectional pin capacitance Functional tests Symbol ILX II/O/Q VOL VOH VIL VIH ICC IOS CIN CI/O/Q Conditions -55C TC +125C VSS = 0 V, 4.5 V VCC 5.5 V unless otherwise specified 0.0 V VIN VCC 0.0 V VI/O/Q VCC VCC = 4.5 V, IOL = 12 mA, VIN = VIH or VIL VCC = 4.5 V, IOH = -2.0 mA, VIN = VIH or VIL VIL = 0.5 V, VIH = 3.0 V, ftog = 25 MHz VCC = 5.0 V, VOUT = 0.5 V, TA = +25C, see 4.3.1d VCC = 5.0 V, VI = 2.0 V, f = 1.0 MHz, TA = +25C, see 4.3.1c VCC = 5.0 V, VI/O/Q = 2.0 V, f = 1.0 MHz, TA = +25C, see 4.3.1c See 4.3.1e Device type 01-03, 05,06 04, 07-14 01-03, 05,06 04, 07-14 All All All All 01-04, 07,09, 11,13 05,06, 08,10, 12,14 All All All All Group A sub groups 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1 4 4 7,8A,8B Limits Min Max -10 10 -100 10 -10 10 -100 10 0.5 2.4 VSS 0.8 -0.5 2.0 VCC +1.0 130 65 -30 -150 10 10 Unit A A V V V V mA mA pF pF See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89839 A REVISION LEVEL F SHEET 4 TABLE I. Electrical performance characteristics - Continued. Test Input or feedback to nonregistered output Clock to output delay 5/ Input to output enable Input to output register enable 5/ Symbol tPD tCO tEA1 tEA2 Conditions -55C TC +125C VSS = 0 V, 4.5 V VCC 5.5 V unless otherwise specified VCC = 4.5 V, see figures 3 and 4 4/ Device type 01 02 06 03 09,10, 13,14 04 05,08, 12 07 11 01 02 06 03 09,10,12 04 13,14 05,08 07 11 01 02,06 03,09, 10,13,14 04,11 05,08, 12 07 01,08 02,06 03,09, 10,13,14 04,11 05,12 07 Group A sub groups 9,10,11 9,10,11 9,10,11 9,10,11 Limits Min Max 2.0 30 2.0 20 3.0 20 2.0 15 3.0 15 2.0 10 3.0 25 1.0 7.5 3.0 10.0 1.0 20 1.0 15 2.0 15 1.0 12 2.0 12 1.0 7.0 2.0 10.0 2.0 15 1.0 6 2.0 7.0 30 20 15 10 25 9.0 25 18 15 10 20 7.0 Unit ns ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89839 A REVISION LEVEL F SHEET 5 TABLE I. Electrical performance characteristics - Continued. Test Input to output disable 6/ Input to output register disable 5/ 6/ Clock frequency without feedback 5/ 7/ Clock frequency with feedback 5/ Symbol tER1 tER2 fCLK1 fCLK2 Conditions -55C TC +125C VSS = 0 V, 4.5 V VCC 5.5 V unless otherwise specified VCC = 4.5 V, see figures 3 and 4 4/ Device type 01 02,06 03,09, 10,13,14 04,11 05,08, 12 07 01,08 02,06 03,09, 10,13,14 04,11 05,12 07 01 12 02,06 13,14 03,09, 10 04 11 05,08 07 01 02,06 12 03,09, 10 04 13,14 05,08 11 07 Group A sub groups 9,10,11 9,10,11 9,10,11 9,10,11 Limits Min Max 30 20 15 10 25 7.0 25 18 15 10 20 7.0 0.0 33.3 0.0 37.0 0.0 41.6 0.0 45.5 0.0 50.0 0.0 62.5 0.0 58.0 0.0 33.3 0.0 100.0 0.0 22.2 0.0 33.3 0.0 40.0 0.0 41.6 0.0 58.5 0.0 50.0 0.0 28.5 0.0 62.5 0.0 76.9 Unit ns ns MHz MHz See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89839 A REVISION LEVEL F SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test Input or feedback setup time, before rising clock 5/ Input or feedback hold time after rising clock 5/ Clock pulse width, high 5/ Clock pulse width, low 5/ Symbol tS tH tPWH tPWL Conditions -55C TC +125C VSS = 0 V, 4.5 V VCC 5.5 V unless otherwise specified VCC = 4.5 V, see figures 3 and 4 4/ Device type 01 02,06, 12 03,09, 10,13,14 04,11 05,08 07 01 - 10 11 - 14 01 02,06, 12 03,09, 10 04,13,14 05,08 07 11 01 02,06, 12 03,09, 10 04,13, 14 05,08 07 11 Group A sub groups 9,10,11 9,10,11 9,10,11 9,10,11 Limits Unit Min Max 25 ns 15 12 10 20 7.0 0 ns 0.5 15 ns 12 10 8.0 15 5.0 6.0 15 ns 12 10 8.0 15 5.0 6.0 These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. This parameter may be tested at a frequency other than 25MHz, but shall be guaranteed to the specified limits at 25MHz. Not more than one output at a time should be shorted. Short circuit test duration should not exceed 1 second (see 4.3.1d). AC tests are performed with input rise and fall times (10 percent to 90 percent) of 3.0 ns, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and the output load of figure 3. Input pulse levels are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 5/ Test applies only to registered outputs. 6/ Transition is measured at steady-state high level -500 mV or steady-state low level +500 mV on the output from the 1.5 V level on the input. 7/ Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to the limits specified in table I. 1/ 2/ 3/ 4/ STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89839 A REVISION LEVEL F SHEET 7 Device types All Case outlines R, S, 2 Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 I/CLK I I I I I I I I GND I/ OE I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q 12 13 14 15 16 17 18 19 20 VCC FIGURE 1. Terminal connections. Inputs Output I/CLK I/ OE I I I I I I I I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q X X X X X X X X X X H H H H H H H H X = Don't care state H = logic high FIGURE 2. Truth tables (unprogrammed). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89839 A REVISION LEVEL F SHEET 8 R1 Test CL (minimum) 390 50 pF tEA1, tEA2 Active high = infinity Active low = 390 50 pF tER1, tER2 Active high = infinity 5.0 pF tPD, tCO, fCLK, fCLK2 Active low = 390 NOTE: CL = load capacitance and includes jig and probe capacitance. FIGURE 3. Output load circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89839 A REVISION LEVEL F SHEET 9 FIGURE 4. Switching waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89839 A REVISION LEVEL F SHEET 10 TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (per method 5005, table I) Interim electrical parameters (method 5004) --- Final electrical test parameters (method 5004) 1*, 2, 3, 7*, 8A, 8B 9, 10,11 Group A test requirements (method 5005) 1,2,3,4**,7,8A,8B, 9, 10,11 Groups C and D end-point electrical parameters (method 5005) 2, 3, 7, 8A, 8B * indicates PDA applies to subgroups 1 and 7. ** see 4.3.1c. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for nonJAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MILPRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MILPRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table (unprogrammed devices). The truth table for unprogrammed devices shall be as specified on figure 2. 3.2.4 Programmed devices. The requirements for supplying programmed devices are not a part of this drawing. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. 3.5.1 Certification/compliance mark. A compliance indicator "C" shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator "C" shall be replaced with a "Q" or "QML" certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF38535, appendix A and the requirements herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89839 A REVISION LEVEL F SHEET 11 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Endurance A reprogrammability test shall be completed as part of the vendor's reliability process. This reprogrammability test shall be done for initial characterization and after any design or process changes which may affect the reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of program/erase endurance cycles listed in section 1.3 herein. The vendor's procedure shall be under document control and shall be made available upon request. 3.11 Retention A data retention stress test shall be completed as part of the vendor's reliability monitors. This test shall be done for initial characterization and after any design or process changes which may affect data retention. The methods and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military temperature range. The vendor's procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with the test data. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125C, minimum. (3) Devices shall be burned-in containing a pattern that assures all inputs and I/O's are dynamically switched. This pattern must have all cells programmed in a high or low state (not neutralized). (4) The burn-in pattern shall be read before and after burn-in. Devices having any logic array bits not in the proper state shall constitute a device failure and shall be added as failures for PDA calculation. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN and CI/O/Q measurements) shall be measured only for the initial test and after process or design changes which may affect capacitance. Sample size is fifteen devices with no failures and all input and output terminals tested. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89839 A REVISION LEVEL F SHEET 12 d. IOS measurements in subgroup 1 shall be measured only for the initial test and after process or design changes which may affect IOS. Sample size is 15 devices with no failures, and all output terminals tested. e. Subgroups 7 and 8 shall include verification of the truth table. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA = +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. (4) All devices shall be programmed with a pattern that assures all inputs and I/O's are dynamically switched. 4.4 Programming procedures. The programming procedures shall be as specified by the device manufacturer and shall be made available to the user on request. 4.5 Erasing procedures. The erasing procedures shall be as specified by the device manufacturer and shall be made available to the user on request. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0547. 6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MILHDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89839 A REVISION LEVEL F SHEET 13 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 07-04-24 Approved sources of supply for SMD 5962-89839 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-8983901RA 3/ 66675 PALCE16V8H-25E4/BRA GAL16V8D-30LD/883C 5962-89839012A 3/ 3/ PALCE16V8H-25E4/B2A GAL16V8A-30LR/883C 5962-8983902RA 3/ 3/ 66675 GAL16V8L20J/883 PALCE16V8H-20E4/BRA GAL16V8D-20LD/883C 5962-89839022A 3/ 66675 PALCE16V8H-20E4/B2A GAL16V8A-20LR/883C 5962-8983902SA 3/ 5962-8983903RA 3/ 3/ 66675 GAL16V8L15J/883 PALCE16V8H-15E4/BRA GAL16V8D-15LD/883C 5962-89839032A 3/ 66675 PALCE16V8H-15E4/B2A GAL16V8D-15LR/883C 5962-8983903SA 3/ 5962-8983904RA 66675 3/ 0C7V7 GAL16V8D-10LD/883C ATF16V8-10GM/883 PALCE16V8-10DMB 5962-89839042A 66675 3/ 0C7V7 GAL16V8D-10LR/883C ATF16V8B-10NM/883 PALCE16V8-10LMB 5962-8983905RA 3/ GAL16V8A-25QD/883C 5962-89839052A 3/ GAL16V8A-25QR/883C 5962-8983906RA 3/ GAL16V8A-20QD/883C 5962-89839062A 3/ GAL16V8A-20QR/883C 5962-8983907RA 66675 GAL16V8D-7LD/883 5962-89839072A 66675 GAL16V8D-7LR/883 5962-8983908RA 0C7V7 PALCE16V8L-25DMB GAL16V8L20W/883 GAL16V8L15W/883 5962-89839082A 0C7V7 PALCE16V8L-25LMB 5962-8983909RA 0C7V7 PALCE16V8-15DMB 5962-89839092A 0C7V7 PALCE16V8-15LMB 5962-8983910RA 0C7V7 PALCE16V8L-15DMB 5962-89839102A 0C7V7 PALCE16V8L-15LMB See footnotes at end of table. Page 1 of 2 Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 5962-8983911RA 0C7V7 PALCE16V8-10DMB 2/ 5962-89839112A 0C7V7 PALCE16V8-10LMB 5962-8983912RA 0C7V7 PALCE16V8L-25DMB 5962-89839122A 0C7V7 PALCE16V8L-25LMB 5962-8983913RA 0C7V7 PALCE16V8-15DMB 5962-89839132A 0C7V7 PALCE16V8-15LMB 5962-8983914RA 0C7V7 PALCE16V8L-15DMB 5962-89839142A 0C7V7 PALCE16V8L-15LMB 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed, contact the Vendor to determine its availability. 2/ Caution: Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source. Vendor CAGE number Vendor name and address 66675 Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124-6421 0C7V7 QP Semiconductor 2945 Oakmead Village Court Santa Clara, CA 95051 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. Page 2 of 2