IDT71028S15YI - Integrated Device Technology, Inc.

FEBRUARY 2001

DSC-2966/08

1

Features

◆◆

◆256K x 4 advanced high-speed CMOS static RAM

◆◆

◆Equal access and cycle times

— Commercial and Industrial: 12/15/20ns

◆◆

◆One Chip Select plus one Output Enable pin

◆◆

◆Bidirectional data inputs and outputs directly

TTL-compatible

◆◆

◆Low power consumption via chip deselect

◆◆

◆Available in 400 mil Plastic SOJ package.

Description

The IDT71028 is a 1,048,576-bit high-speed static RAM orga-

nized as 256K x 4. It is fabricated using IDT’s high-perfomance, high-

reliability CMOS technology. This state-of-the-art technology, com-

bined with innovative circuit design techniques, provides a cost-

effective solution for high-speed memory needs.

The IDT71028 has an output enable pin which operates as fast

as 6ns, with address access times as fast as 12ns. All bidirectional

inputs and outputs of the IDT71028 are TTL-compatible and oper-

ation is from a single 5V supply. Fully static asynchronous circuitry

is used, requiring no clocks or refresh for operation.

The IDT71028 is packaged in a 28-pin 400 mil Plastic SOJ.

Functional Block Diagram

A17

A0

I/O CONTROL

I/O0–I/O3

CONTROL

LOGIC

WE

OE

CS

2966 drw 01

4

ADDRESS

DECODER 1,048,576-BIT

MEMORY

ARRAY

•

CMOS Static RAM

1 Meg (256K x 4-Bit)

IDT71028

6.42

2

IDT71028 CMOS Static RAM

1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges

Symbol

Parameter

Min.

Typ.

Max.

Unit

VCC Supply Volt age 4.5 5.0 5.5 V

GND Ground 0 0 0 V

VIH Input High Voltage 2.2 ____ VCC+0.5 V

VIL Input Low Voltage –0. 5(1) ____ 0.8 V

2966 tbl 04

Recommended DC Operating

Conditions

Absolute Maximum Ratings(1)

Pin Configuration

Capacitance

(TA = +25°C, f = 1.0MHz, SOJ package)

SOJ

Top View

Truth Table(1,2)

5

6

7

8

9

12

13

14

GND

A0

A1

A2

1

2

3

4

28

27

26

25

24

23

22

21

20

17

16

15

SO28-6

A3

A4

A5

A7

A17

A16

A15

A14

NC

A13

OE

WE

I/O0

2966 drw 02

A810 19

A12

A911 18

A11

A10

VCC

A6

CS I/O1

I/O2

I/O3NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. VTERM must not exceed VCC + 0.5V.

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

NOTE:

1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.

NOTES:

1. H = VIH, L = VIL, x = Don't care.

2. VLC = 0.2V, VHC = VCC -0.2V.

3. Other inputs ≥VHC or ≤VLC.

CS OE WE

I/O

Function

LLHDATA

OUT

Read D at a

LXLDATA

IN

Write Dat a

L H H High-Z Output D isabled

H X X High-Z Deselect ed – S tandby (I

SB

)

V

HC

(3) X X High-Z Deselect ed – S tandby (I

SB1

)

2966 tbl 01

Symbol

Rating

Value

Unit

V

TERM

(2) Term in al Voltage wit h Respect to GND –0.5 to + 7.0 V

T

A

Operating Tem perature 0 to +70 oC

T

BIAS

Tem perature Under Bias –55 to +125 oC

T

STG

Sto rage Tem perat ure –55 to +125 oC

P

T

Pow er Dissipation 1.25 W

I

OUT

DC Output Current 50 m A

2966 tbl 02

Symbol

Parameter

(1)

Conditions

Max.

Unit

C

IN

Input Capacitance V

IN

= 3dV 8 pF

C

I/O

I/O C apacitance V

OUT

= 3dV 8 pF

2966 tbl 03

Recommended Operating

Temperature and Supply Voltage

Grade

Temperature

V

SS

V

SS

Commercial

0

O

C to +70

O

C

0V

5.0V ± 10%

Industrial

–40

O

C to +85

O

C

0V

5.0V ± 10%

2966 t bl 05

6.42

IDT71028 CMOS Static RAM

1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges

3

71028S12

71028S15

71028S20

Symbol

Parameters

Com'l.

Ind.

Com'l.

Ind.

Com'l.

Ind.

Unit

I

CC

Dy namic Op e rati ng Curre nt,

CS ≤ V

IL

, Outp uts Op en,

V

CC

= Max., f = f

MAX

(2)

155 170 150 165 145 160 mA

I

SB

S tand by P o we r Sup p ly Curre nt (TTL Le v e l)

CS ≥ V

IH

, Outp uts Op en,

V

CC

= Max., f=f

MAX

(2)

40 40 40 40 40 40 mA

I

SB1

Full Standby Power Supply Current

(CMOS Lev e l), CS ≥ V

HC

, Outp uts Op en,

V

CC

= Max., f = 0(2), V

IN

≤ V

LC

or V

IN

≥ V

HC

10 10 10 10 10 10 mA

2966 tb l 07

Symbol

Parameter

Test Condition

IDT71028

Unit

Min.

Max.

|I

L

I

| Input Leakage Current V

CC

= Max., V

IN

= GND to V

CC

___ 5µA

|I

LO

| Output Leakag e Current V

CC

= Max., CS = V

IH

, V

OUT

= GND to V

CC

___ 5µA

V

OL

Output Low Voltage I

OL

= 8m A, V

CC

= Min. ___ 0.4 V

V

OH

Output High Vo ltage I

OH

= –4mA, V

CC

= M in. 2.4 ___ V

2966 tbl 06

DC Electrical Characteristics(1)

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)

*Including jig and scope capacitance.

AC Test Conditions

Figure 1. AC Test Load Figure 2. AC Test Load

(for t CLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)

DC Electrical Characteristics

(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)

2966 drw 03

480Ω

255Ω

30pF

DATAOUT

5V

2966 drw 04

480Ω

255Ω

5pF*

DATAOUT

5V

AC Test Loads

NOTES:

1. All values are maximum guaranteed values.

2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.

Input Pulse Lev els GND to 3. 0V

Input Rise/Fall Tim es 3ns

Input Tim ing Reference Levels 1.5V

Output R eference Levels 1.5V

AC Test Load See Figures 1 and 2

2966 tbl 08

6.42

4

IDT71028 CMOS Static RAM

1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges

71028S12

71028S15

71028S20

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle

t

RC

Read C y cle Tim e 12 — 15 — 20 — ns

t

AA

Address Access Tim e — 12 — 15 — 20 ns

t

ACS

Chip Select Access Tim e — 12 — 15 — 20 ns

t

CLZ

(1) Ch ip S elect to O ut put in Low-Z 3 — 3 — 3 — ns

t

CHZ

(1) Chip Deselect to Output in High-Z 060708ns

t

OE

O utput Enable to Output Valid — 6 — 7 — 8 ns

t

OLZ

(1) Output Enable t o O utput in Low -Z 0 — 0 — 0 — ns

t

OHZ

(1) Output Disable to Output in High-Z 050507ns

t

OH

Output Hold from Address Cha nge 4 — 4 — 4 — ns

t

PU

(1) Ch ip Select to Pow er-Up Tim e 0 — 0 — 0 — ns

t

PD

(1) Chip Deselect to Power-Dow n Tim e — 12 — 15 — 20 ns

Write C ycle

t

WC

Write Cycle Tim e 12 — 15 — 20 — ns

t

AW

Address Valid t o End-of-Write 10 — 12 — 15 — ns

t

CW

Chip Select t o End-of -Write 10 — 12 — 15 — ns

t

AS

Address Set-Up Tim e 0 — 0 — 0 — ns

t

WP

Write Pulse Width 10 — 12 — 15 — ns

t

WR

Write Recovery Time 0—0—0—ns

tDW Dat a Valid to End-of-Write 7 — 8 — 9 — ns

t

DH

Data Hold Time 0—0—0—ns

t

OW

(1) Out put Active from End-of-Writ e 3 — 3 — 4 — ns

t

WHZ

(1) Write Enable to Outpu t in High-Z 0 5 0508ns

2966 tbl 09

AC Electrical Characteristics

(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)

NOTE:

1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.

6.42

IDT71028 CMOS Static RAM

1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges

5

Timing Waveform of Read Cycle No. 1(1)

Timing Waveform of Read Cycle No. 2(1,2,4)

NOTES:

1. WE is HIGH for Read Cycle.

2. Device is continuously selected, CS is LOW.

3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

DATAOUT

ADDRESS

2966 drw 06

tRC

tAA

tOH tOH

DATAOUT VALIDPREVIOUS DATAOUT VALID

ADDRESS

2966 drw 05

OE

CS

DATAOUT

(5) (5) (5)

(5)

DATAOUT VALID

HIGH IMPEDANCE

tAA

tRC

tOE

tACS

tOLZ

tCHZ

tCLZ

(3)

tOHZ

VCC SUPPLY

CURRENT

tPU tPD

ICC

ISB

6.42

6

IDT71028 CMOS Static RAM

1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)

NOTES:

1. A write occurs during the overlap of a LOW CS and a LOW WE.

2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed

on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

CS

ADDRESS

WE

2966 drw 08

DATAIN VALID

tAW

tWC

tCW

tAS tWR

tDW tDH

DATAIN

ADDRESS

CS

WE

DATAOUT

DATAIN 2966 drw 07

(6)

(3) (3)

(2)

(5) (5)

DATAIN VALID

HIGH IMPEDANCE

tWC

tAS

tWHZ

tWP

tCHZ

tOW

tDW tDH

tWR

tAW

6.42

IDT71028 CMOS Static RAM

1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges

7

Ordering Information

S

Power

XX

Speed

XX

Package

X

Process/

Temperature

Range

Blank

ICommercial (0°C to +70°C)

Industrial (–40°C to +85°C)

Y

12

15

20

71028

Device

Type

IDT

Speed in nanoseconds

2966 drw 09

400-mil Small Outline J-Bend (SO28-6)

6.42

8

IDT71028 CMOS Static RAM

1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges

Datasheet Document History

09/23/99: Updated to new format

Pg. 1–4, 7 Added industrial temperature range offerings

Pg. 1, 3, 4, 7 Removed 17ns speed grade

Pg. 6 Revised notes and footnotes on Write Cycle No. 1 and No. 2 diagrams

Pg. 8 Added Datasheet Document History

03/14/00 Pg. 3 Revised ISB to accomidate speed functionality

08/09/00 Not recommended for new designs

02/01/01 Removed "Not recommended for new designs"

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 sramhelp@idt.com

Santa Clara, CA 95054 fax: 408-492-8674 800-544-7726, x4033

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.