CMOS Static RAM 1 Meg (256K x 4-Bit) Features IDT71028 Description 256K x 4 advanced high-speed CMOS static RAM Equal access and cycle times -- Commercial and Industrial: 12/15/20ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly TTL-compatible Low power consumption via chip deselect Available in 400 mil Plastic SOJ package. The IDT71028 is a 1,048,576-bit high-speed static RAM organized as 256K x 4. It is fabricated using IDT's high-perfomance, highreliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a costeffective solution for high-speed memory needs. The IDT71028 has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns. All bidirectional inputs and outputs of the IDT71028 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71028 is packaged in a 28-pin 400 mil Plastic SOJ. Functional Block Diagram A0 * * ADDRESS DECODER * 1,048,576-BIT MEMORY ARRAY * * * A17 I/O0-I/O3 CS WE OE 4 4 I/O CONTROL CONTROL LOGIC 2966 drw 01 FEBRUARY 2001 1 (c)2000 Integrated Device Technology, Inc. DSC-2966/08 IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges Pin Configuration Absolute Maximum Ratings(1) Symbol A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CS OE GND VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 WE 1 28 27 2 3 26 25 4 24 5 23 6 SO28-6 22 7 21 8 9 20 10 19 11 18 17 12 13 16 15 14 Rating Value Unit VTERM (2) Terminal Voltage with Respect to GND -0.5 to +7.0 V TA Operating Temperature 0 to +70 o C TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -55 to +125 o PT Power Dissipation 1.25 IOUT DC Output Current 50 C C W mA 2966 tbl 02 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V. 2966 drw 02 SOJ Top View Capacitance (TA = +25C, f = 1.0MHz, SOJ package) Truth Table(1,2) CS OE WE I/O L L H DATA OUT Read Data L X L DATA IN Write Data L H H High-Z Output Disabled X X High-Z Deselected - Standby (ISB) X X High-Z Deselected - Standby (ISB1) H VHC (3) Function CIN Input Capacitance CI/O I/O Capacitance Conditions Max. Unit VIN = 3dV 8 pF VOUT = 3dV 8 pF 2966 tbl 03 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 2966 tbl 01 NOTES: 1. H = VIH , L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC. Recommended DC Operating Conditions Symbol Recommended Operating Temperature and Supply Voltage Grade Temperature VSS VSS Commercial 0OC to +70OC 0V 5.0V 10% -40OC to +85OC 0V 5.0V 10% Industrial Parameter(1) Symbol Parameter VCC Supply Voltage GND Ground VIH VIL Input High Voltage Input Low Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 ____ VCC+0.5 V ____ 0.8 (1) -0.5 V 2966 tbl 04 NOTE: 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle. 2966 tbl 05 6.42 2 IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges DC Electrical Characteristics (VCC = 5.0V 10%, Commercial and Industrial Temperature Ranges) IDT71028 Symbol Parameter Test Condition Min. Max. Unit |ILI| Input Leakage Current VCC = Max., VIN = GND to VCC ___ 5 A |ILO| Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to VCC ___ 5 A IOL = 8mA, V CC = Min. ___ 0.4 V 2.4 ___ V Output Low Voltage VOL VOH Output High Voltage IOH = -4mA, V CC = Min. 2966 tbl 06 DC Electrical Characteristics(1) (VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V) 71028S12 Symbol Parameters 71028S15 71028S20 Com'l. Ind. Com'l. Ind. Com'l. Ind. Unit ICC Dynamic Operating Current, CS VIL, Outputs Open, VCC = Max., f = fMAX(2) 155 170 150 165 145 160 mA ISB Standby Power Supply Current (TTL Level) CS VIH, Outputs Open, VCC = Max., f=fMAX(2) 40 40 40 40 40 40 mA ISB1 Full Standby Power Supply Current (CMOS Level), CS VHC, Outputs Open, VCC = Max., f = 0(2), VIN VLC or VIN VHC 10 10 10 10 10 10 mA NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at f MAX); f = 0 means no address input lines are changing. 2966 tbl 07 AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2966 tbl 08 AC Test Loads 5V 5V 480 480 DATA OUT DATA OUT 30pF 5pF* 255 255 2966 drw 04 2966 drw 03 *Including jig and scope capacitance. Figure 2. AC Test Load Figure 1. AC Test Load (for t CLZ, t OLZ, tCHZ, tOHZ , tOW, and tWHZ) 6.42 3 IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VCC = 5.0V 10%, Commercial and Industrial Temperature Ranges) 71028S12 Symbol Parameter 71028S15 71028S20 Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 12 -- 15 -- 20 -- ns tAA Address Access Time -- 12 -- 15 -- 20 ns tACS Chip Select Access Time -- 12 -- 15 -- 20 ns (1) Chip Select to Output in Low-Z 3 -- 3 -- 3 -- ns (1) tCHZ Chip Deselect to Output in High-Z 0 6 0 7 0 8 ns tOE Output Enable to Output Valid -- 6 -- 7 -- 8 ns Output Enable to Output in Low-Z 0 -- 0 -- 0 -- ns Output Disable to Output in High-Z 0 5 0 5 0 7 ns tCLZ tOLZ (1) tOHZ (1) tOH Output Hold from Address Change 4 -- 4 -- 4 -- ns tPU (1) Chip Select to Power-Up Time 0 -- 0 -- 0 -- ns tPD (1) Chip Deselect to Power-Down Time -- 12 -- 15 -- 20 ns tWC Write Cycle Time 12 -- 15 -- 20 -- ns tAW Address Valid to End-of-Write 10 -- 12 -- 15 -- ns tCW Chip Select to End-of-Write 10 -- 12 -- 15 -- ns tAS Address Set-Up Time 0 -- 0 -- 0 -- ns tWP Write Pulse Width 10 -- 12 -- 15 -- ns tWR Write Recovery Time 0 -- 0 -- 0 -- ns tDW Data Valid to End-of-Write 7 -- 8 -- 9 -- ns Data Hold Time 0 -- 0 -- 0 -- ns tOW Output Active from End-of-Write 3 -- 3 -- 4 -- ns tWHZ(1) Write Enable to Output in High-Z 0 5 0 5 0 8 ns Write Cycle tDH (1) NOTE: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. 6.42 4 2966 tbl 09 IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) tRC ADDRESS tAA OE tOE tOLZ CS tCLZ DATAOUT VCC SUPPLY ICC CURRENT ISB (5) (5) tACS (3) tCHZ HIGH IMPEDANCE (5) tOHZ (5) DATAOUT VALID tPD tPU 2966 drw 05 Timing Waveform of Read Cycle No. 2(1,2,4) tRC ADDRESS tAA tOH DATAOUT tOH PREVIOUS DATAOUT VALID DATAOUT VALID 2966 drw 06 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state. 6.42 5 IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tWP (2) tAS tWR WE tWHZ DATAOUT (6) tOW (5) HIGH IMPEDANCE (3) (5) (3) tDH tDW DATAIN tCHZ DATAIN VALID 2966 drw 07 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4) tWC ADDRESS tAW CS tAS tWR tCW WE tDW DATAIN tDH DATAIN VALID 2966 drw 08 NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP . 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state. 6.42 6 IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges Ordering Information IDT 71028 Device Type S XX XX X Power Speed Package Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C) Y 400-mil Small Outline J-Bend (SO28-6) 12 15 20 Speed in nanoseconds 2966 drw 09 6.42 7 IDT71028 CMOS Static RAM 1 Meg (256K x 4-Bit) Commercial and Industrial Temperature Ranges Datasheet Document History 09/23/99: 03/14/00 08/09/00 02/01/01 Pg. 1-4, 7 Pg. 1, 3, 4, 7 Pg. 6 Pg. 8 Pg. 3 Updated to new format Added industrial temperature range offerings Removed 17ns speed grade Revised notes and footnotes on Write Cycle No. 1 and No. 2 diagrams Added Datasheet Document History Revised ISB to accomidate speed functionality Not recommended for new designs Removed "Not recommended for new designs" CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 8 for Tech Support: sramhelp@idt.com 800-544-7726, x4033