austriamicrosystems AG is now ams AG The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30 8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 e-Mail: ams_sales@ams.com Please visit our website at www.ams.com AS3693A QFN48 austriamicrosystems Product Specification, Confidential al id AS3693A -16 Channel high precision LED driver for LCD Backlight am lc s on A te G nt st il The AS3693A is a 16 channels high precision LED driver with build in PWM generators for building backlight panels in LCD-TV-sets. External clock and synchronizing inputs allow the synchronization of the LCD backlight with the TV picture. Local dimming and scan dimming is supported by 16 independent PWM generators with programmable delay, period and duty cycle. Three free configurable dynamic power feedback circuits make the device usable for white LED as well as RGB backlights. Build in safety features include thermal shutdown as well as open and short LED detection. All circuit parameters are programmable via I2C or SPI interface. 2 Key Features ca Te ch 16 Channel LED driver Output current 70mA (150mA) per channel Output voltage 0.4V to 50V Absolute current accuracy +/- 0.5% Output slew rate programmable Current programmable with external resistor Linear current control with 8 - bit DAC Linear current control with external analog voltage Digital current control with 16 independent PWM generators Free programmable 12 bit resolution ( period, high time and delay ) Overvoltage detection ( short LED ) Undervoltage detection ( open LED ) Temperature shutdown Fault interrupt output H-Sync, V-Sync inputs to synchronize with TVset Internal or external PWM - clock I2C interface SPI interface 5 bit device - address (sets device address and interface mode) Automatic supply regulation feedback Each output can be assigned to red, green or blue feedback. Package QFN48 6x6mm, 0.4mm pitch, QFN48 7x7mm, 0.5mm pitch ni lv 1 General Description www.austriamicrosystems.com 3 Applications * LED backlighting for LCD - TV sets and monitors Revision 1.14 / 2010 1 - 39 AS3693A QFN48 austriamicrosystems 4 Block Diagram Reference, DAC PWM PWM Fault detectors PWM SMPS feedback PWM am lc s on A te G nt st il PWM lv PWM al id V2_5 REF Vreg FBB FBG FBR Vsupply PWM PWM AS3693A PWM PWM PWM PWM 86 byte registers PWM Addr2 Addr1 SDA SCL CS SDO Vsync Hsync SPI / I2C Interface V2_5 Te ch ni ca PWM PWM Fault PWM www.austriamicrosystems.com Revision 1.14 / 2010 2 - 39 AS3693A QFN48 austriamicrosystems Table of Contents General Description ....................................................................................................................................... 1 Key Features.................................................................................................................................................. 1 Applications.................................................................................................................................................... 1 Block Diagram................................................................................................................................................ 2 Characteristics ............................................................................................................................................... 4 5.1 Absolute Maximum Ratings .................................................................................................................... 4 5.2 Operating Conditions .............................................................................................................................. 5 5.3 Electrical Characteristics......................................................................................................................... 5 6 Typical Operation Characteristics .................................................................................................................. 7 6.1 Output current vs Output Voltage ........................................................................................................... 7 6.2 Vsupply vs VREG and V2.5 at startup .................................................................................................... 7 6.3 9us Slew Rate ......................................................................................................................................... 8 6.4 Supply Regulation ................................................................................................................................... 8 7 Block Description ........................................................................................................................................... 9 7.1 Feedback Circuit ..................................................................................................................................... 9 7.1.1 Feedback Selection ....................................................................................................................... 10 7.1.2 Voltage fault registers .................................................................................................................... 11 7.2 Curreg 1-16........................................................................................................................................... 11 7.3 PWM - modes ...................................................................................................................................... 13 7.3.1 SYNC mode (PWM_MODE = 00) .................................................................................................. 13 7.3.2 ASYNC - mode (PWM_MODE = 01) ............................................................................................ 14 7.3.3 SIGMA DELTA - mode (PWM_MODE = 10) ................................................................................. 15 7.4 PWM - high time, period and delay registers ....................................................................................... 16 7.5 Shunt Regulator .................................................................................................................................... 17 7.5.1 Undervoltage lockout ..................................................................................................................... 17 7.6 Over temperature control ...................................................................................................................... 17 7.7 Device address setup ........................................................................................................................... 18 7.7.1 I2C Device Address setup ............................................................................................................. 18 7.7.2 SPI Device Address setup ............................................................................................................. 18 7.8 Digital interface ..................................................................................................................................... 19 7.8.1 I2C interface .................................................................................................................................. 19 7.8.2 SPI interface .................................................................................................................................. 21 8 Register map................................................................................................................................................ 23 9 Pinout and Packaging .................................................................................................................................. 26 9.1 Pinout.................................................................................................................................................... 26 9.2 Package drawing QFN48, 6x6mm, 0.4mm pitch .................................................................................. 28 9.3 Package drawing QFN48, 7x7mm, 0.5mm pitch .................................................................................. 31 9.4 Package Drawing MLF48...................................................................................................................... 34 10 Ordering Information .................................................................................................................................... 38 Copyright............................................................................................................................................................. 39 Disclaimer ........................................................................................................................................................... 39 Contact Information ............................................................................................................................................. 39 Te ch ni ca am lc s on A te G nt st il lv al id 1 2 3 4 5 www.austriamicrosystems.com Revision 1.14 / 2010 3 - 39 AS3693A QFN48 austriamicrosystems 5 Characteristics 5.1 Absolute Maximum Ratings Stresses beyond those listed in Table 1 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in Section 5 Electrical Characteristics is not implied. Table 1 - Absolute Maximum Ratings Symbol Parameter Min Max Unit Note 1 al id Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VDDMAX Supply for LED's -0.3 >50 V See notes VINVREG VREG supply voltage -0.3 7.0 V Applicable for pin VREG IINVREG Maximum Vreg current 100 mA VIN2.5V 2.5 V Pins V2_5+0.3V V lv -0.3 Maximum Current flowing into Vreg Applicable for 2.5V pins 4 -0.3 VREG+ 0.3V V Applicable for 5V pins 50V Pins -0.3 55 V Applicable for CURR1, CURR2, CURR3 up to CURR16 IIN Input Pin Current -25 +25 mA At 25C, Norm: Jedec 17 TSTRG Storage Temperature Range -55 150 C Humidity 5 85 % Non condensing -4000 4000 V Norm: MIL 883 E Method 3015 -2000 2000 V Norm: MIL 883 E Method 3015 W At T At Ta = 25C, no airflow for QFN48 6x6mm on two layer FR43 Cu PCB am lc s on A te G nt st il 5V Pins VIN5V VIN50V VESD Electrostatic Discharge on Pins Curr1 - Curr16 Electrostatic Discharge on all Pins PT Total Power Dissipation 3.8W PDERATE PT Derating Factor 40 TBODY Body Temperature during Soldering 260 mW/ 3 See notes C C according to IPC/JEDEC J-STD020C ca VESD 2 Notes: Te ch ni 1, As the AS3693A is not directly connected to this supply. Only the parameters VINVREG, VIN5V and VIN50V have to be guaranteed by the application 2, All pins except CURR1 to CURR16 and 2.5V 3, Copper area > 9 cm, thermal vias 4, 2.5V Pins are Fault, SDO, ADDR1 and ADDR2 www.austriamicrosystems.com Revision 1.14 / 2010 4 - 39 AS3693A QFN48 austriamicrosystems 5.2 Operating Conditions Table 2 - Operating Conditions VDD Main Supply VDDTOL Main Supply Voltage Tolerance Supply (shunt regulated by AS3693A) VREGINT VREGEXT Min Typ -20 Max Unit Note Not Limited V Supply is not directly connected to the AS3693A - see section `Shunt Regulator' +20 % Applies only for supply VREG is connected via Rvdd 5.0 5.2 5.4 V If internally (shunt-)regulated by ZD1 3.3 4.5 4.9 V If externally supplied TAMB Ambient Temperature -20 25 85 C VUVL Under voltage lockout voltage 2.6 2.8 3.0 V al id Parameter If Vreg < UVUL current sources are turned off lv Symbol ( Addr 0x01,Addr 0x02 = 0x00 ) Supply Current (Chip current consumption) 20 Maximum Supply current 30 Maximum Current Into VREG - mA PIN (Supply current + shunt regulator current). 350 uA Max Unit am lc s on A te G nt st il IVREG Excluding current through shunt regulator (ZD1) - see section mA `Shunt Regulator'. Note: Take care of the Power dissipation of the external Resistor. IVREG_M AX Condition: externally supplied IVREG EXT_OFF Curr_reg1-16 off (register 01h = 00h, register 02h = 00h) 5.3 Electrical Characteristics Table 3 - Analog Electrical Characteristics Parameter Min VCURR Current Source CURR1 to CURR16 Voltage Compliance 0.41 50.0 V at 70mA 0.9 50 V at 150mA ca Symbol Current Source Range 0 150 (3) ch ICURR, Current Source Tolerance Te TOL Note mA ICURRx = 250mV / Rix (x=1...16) Using 250mV reference -0.5 +0.5 % ni ICURR Typ @25C TJUNCTION, excluding variation of external resistors Using 250mV reference (1) -1.5 +1.5 % -20C to +100C TJUNCTION, -20C to +85C TAMB, excluding variation of external resistors; V(CURRx) <= 4.0V Using DAC reference -1.6 +1.6 % VDAC =250mV ( Data = 0x80 ) @25C TJUNCTION, excluding variation of external resistors DAC_INL DAC INL -4 +4 VC Automatic Supply Regulation trip point 0.5 1 www.austriamicrosystems.com Revision 1.14 / 2010 LSB DAC integral nonlinearity V See section `Feedback Circuit (DCDC_Regulation_Trip_Point)'. 5 - 39 AS3693A QFN48 austriamicrosystems Symbol Parameter VC,GAIN Automatic Supply Regulation gain TOVTEMP Over temperature Limit Thyst Over temperature hysteresis CLK Internal Clock for PWM Min Typ Max 2.0 130 140 150 10 400 500 Unit Note mA/V Voltage to current ratio; output current range typ. 0 to 200uA C Maximum junction temperature (2) C 600 KHz Clock for internal PWM generation 1, Accuracy at +100C guaranteed by design and verified by laboratory characterization al id Notes: 2, If the temperature exceeds the over temperature limit, the PWM will be turned off. If the temperature decreases, the PWM is activated again. The register settings are not reset. Table 4 - Digital Input pins characteristics (SDI,VSYNC,HSYNC,SCL,CS) Parameter Min VIH High Level Input voltage VIL Low Level Input voltage f_SCL f_HSYNC Typ Max Unit 1.3 VREG V -0.3 0.4 V Maximum SCL Frequency 10 MHz Maximum HSYNC Frequency 10 MHz Note am lc s on A te G nt st il Symbol lv 3, To obtain higher currents use more than one current sink in parallel or use AS3693B (external transistors) Output driver is slew rate limited ( Register: Curreg_Control 0x0D ) SYNC-mode: ts_VH Vsync setup time before rising edge of Hsync 15 ns PWM values are updated with first rising edge of Hsync while Vsync = 1 ( see 7.3.1.1 ) th_VH Vsync hold time after rising edge of Hsync 15 ns ts_SCISCL Setup time SDI,SCL 15 ns SPI interface mode th_SCLSCI Hold time SCL,SDI 15 ns SPI interface mode ts_CSSCL Setup time CS,SCL 15 ns SPI interface mode th_SCLCS Hold time SCL, CS 15 ns SPI interface mode 1.3 us I2C interface mode 100 ns I2C interface mode 160 ns I2C interface mode 160 ns I2C interface mode ca Bus free time between tBUF Start condition Hold time for repeated Start condition ch Tholdstart Setup time for repeated ni Tsetupstart Stop and Start conditions Te Tsetupstop Setup time for Stop condition Table 5 - Digital output pins characteristics (SDO) Symbol Parameter Min VOH High Level Output voltage VOL Low Level Output voltage www.austriamicrosystems.com Typ Max Unit 2.4 2.5 V -0.3 0.4 V Revision 1.14 / 2010 Note 6 - 39 AS3693A QFN48 austriamicrosystems 6 Typical Operation Characteristics 6.1 Output current vs Output Voltage 0,16 0,12 0,1 150mA 0,08 75mA lv 25mA 0,06 0 am lc s on A te G nt st il 0,04 0,02 al id 0,14 0 5 10 15 20 25 Te ch ni ca 6.2 Vsupply vs VREG and V2.5 at startup www.austriamicrosystems.com Channel 1 = VREG Channel 2 = V2_5 Channel3 = Vsupply Revision 1.14 / 2010 7 - 39 AS3693A QFN48 austriamicrosystems am lc s on A te G nt st il lv al id 6.3 9us Slew Rate Channel 1 = Voltage on Current Source Channel 2 + Voltage on RES Pin Te ch ni ca 6.4 Supply Regulation www.austriamicrosystems.com Channel 1 = DCDC VOUT (30V) Channel 2 = Voltage on RES Pin Channel 3 = Voltage on Curr Pin Revision 1.14 / 2010 8 - 39 AS3693A QFN48 7 austriamicrosystems Block Description 7.1 Feedback Circuit The AS3693A supports a flexible feedback selection for external DCDC - supplies. Beside the default setup for RGGB lighting, each channel can be assigned to an external DCDC feedback loop. This feedback circuit is important to reduce power dissipation of the device. Table 6 - Feedback Control Addr: 04h Enables and Disables the Different Feedback modes Bit Bit Name Default Access 0 Feedback on 0 R/W 1 = Feedback circuit is active 0 = The entire feedback loop is disabled 1 Feedback on PWM 0 R/W The feedback regulator is only active, if PWM = 1 2 Open_Led_Det_on 0 R/W 3 Short_det_on 4 Short Led Detect Voltage(VSL) 7:6 DCDC_regulation_trip Point (VC) lv Description al id Feedback control am lc s on A te G nt st il Enables open led detection comparators 0 = Open Led Detection disabled 1 = Open Led Detection enabled. Level: Ucurrx = 100mV Enables short detection 0 = Short detection off 1 = Sort Detection on Short led detection trip voltage ( debounced 3mS ) 00 = 2V 01 = 3V Trip point voltage of the DCDC-feedback regulation circuit. (NOTE: This value has to be adjusted if analog ref select bit is changed.) 00 = 0.5V (Note use for Currents up to 70 mA) 01 = 0.6V (Note use for Currents up to 80 mA) 10 = 0.8V (Note use for Currents up to 110 mA) 11 = 1.0V (Note use for Currents up to 150 mA) 0 R/W R/W R/W Te ch ni ca 00 www.austriamicrosystems.com Revision 1.14 / 2010 9 - 39 AS3693A QFN48 7.1.1 austriamicrosystems Feedback Selection In the AS3693A, each led - string feedback can be assigned to the specific led-supply, to minimize the power consumption in the system. It can be chosen in between FBR, FBG and FBB. DCDC Converter for VDD (Internal or externa)l From main supply R1 R3 Vfb R2 C1 al id Voltage Feedback input for DCDC Feedback resistor divider (part of DCDC converter circuit) AS3693 lv ANALOG REGULATION CIRCUIT 16 REGULATORS 3...16 2 1 am lc s on A te G nt st il FB R FB G FB B NOFB VC SHORTLED VSL OPENLED VOL REF Q2 R5 Table 7 - Feedback Selection Addr: 05h,06h,07h,08h Feedback Select 1-4 This register controls the Feedback of the Automatic feedback loop Bit Name Default Access 1:0 FB1_Select FB5_Select FB9_Select FB13_Select 00 R/W FB2_Select FB6_Select FB10_Select FB14_Select 00 R/W 5:4 FB3_Select FB7_Select FB11_Select FB15_Select 00 R/W 7:6 FB4_Select FB8_Select FB12_Select FB16_Select 00 R/W ch ni ca Bit Te 3:2 www.austriamicrosystems.com Description Selects the feedback of the voltage regulators 00= regulator on FBR 01= regulator on FBG 10= regulator on FBB 11= regulator not connected to FB Selects the feedback of the voltage regulators 00= regulator on FBR 01= regulator on FBG 10= regulator on FBB 11= regulator not connected to FB Selects the feedback of the voltage regulators 00= regulator on FBR 01= regulator on FBG 10= regulator on FBB 11= regulator not connected to FB Selects the feedback of the voltage regulators 00= regulator on FBR 01= regulator on FBG 10= regulator on FBB 11= regulator not connected to FB Revision 1.14 / 2010 10 - 39 AS3693A QFN48 austriamicrosystems 7.1.2 Voltage fault registers In this registers an open or short led fault can be detected. If an open or short led error occurs, pin fault is pulled to 0 (3 ms debounced ). Remark: At 100% PWM duty cycle, short led fault detection is not available. Please set PWM to 99% duty cycle. Open led fault detection is available at 100% PWM duty cycle. Table 8 - Fault Registers Addr: 09h-0ch This register shows a fault on any led string 3:2 5:4 7:6 Default Fault_Reg 1 Fault_Reg 5 Fault_Reg 9 Fault_Reg 13 Fault_Reg 2 Access 00 Fault_Reg 6 Fault_Reg 10 Fault_Reg 14 Fault_Reg 3 Fault_Reg 7 Fault_Reg 11 Fault_Reg 15 Fault_Reg 4 Fault_Reg 8 Fault_Reg 12 00 Description R Shows a error on any led string 00 = no fault 01 = open led 10 = short led R Shows a error on any led string 00 = no fault 01 = open led 10 = short led am lc s on A te G nt st il 1:0 Bit Name lv Bit al id Voltage Fault 1,2,3,4 00 R Shows a error on any led string 00 = no fault 01 = open led 10 = short led 00 R Shows a error on any Led string 00 = no Fault 01 = open Led 10 = short Led Fault_Reg 16 7.2 Curreg 1-16 Each current source can be turned on and off separately. Table 9 -Reg. Control 1 Addr: 01h Reg. Control1 Bit Name Default Access 7:0 Curreg 1-8_ON R/W ch ni ca Bit 00000000 This register enables or disables the curreg 1 - 8 Description Enables or disables the current regulators 0 = regulator off 1 = regulator on Table 10- Reg.Control 2 Reg. Control2 This Register enables or disables the curreg 9-16 Bit Bit Name Default Access 7:0 Curreg 9 -16_ON 00000000 Te Addr: 02h R/W www.austriamicrosystems.com Description Enables or disables the current regulators 0 = regulator off 1 = regulator on Revision 1.14 / 2010 11 - 39 AS3693A QFN48 austriamicrosystems Table 11 -CURREG_CONTROL Addr: 0dh Curreg Control Controls Rise, Fall times and References of the Curreg. Default Access Analog Ref Select 00 R/W 3:2 SLEW_RATE_CONT ROL 00 R/W 5:4 PWM_LOW_LEVEL 00 R/W 7 boost mode Voltage reference for the current regulators can be chosen with these options. 00 = 250mV reference 01 = external reference 10 = DAC reference 11 = do not use SLEW - RATE - Control. Adjusts the rise and fall time of the current switching 00 = typ. 9us 01 = typ. 6us 10 = typ. 3us 11 = typ. 1us Note: Test bits for internal use only Gives +30% current. only available in internal reference mode. am lc s on A te G nt st il 1:0 Description al id Bit Name lv Bit 0 R/W AS3693A Reference Sources Analog Ref Select 3-16 2 0,5% VREF 250mV 1 PWM 8Bit DAC 0...500mV External Reference ca Curreg ni Table 12 - Ref_DAC_Voltage Addr: 0eh Ref_DAC_Voltage ch The Regulation Voltage can be chosen in this register Bit Name Te Bit 7...0 Ref_DAC_Voltage www.austriamicrosystems.com Default 00 Access Description R/W Reference voltage for current regulators. (Note: If Analog Ref Select = 10, the regulation voltage can be adjusted here. 00000000 = 0mV 00000001 ... 01111111 = 250 mV .. 11111111= 500mV Revision 1.14 / 2010 12 - 39 AS3693A QFN48 austriamicrosystems 7.3 PWM - modes Table 14- PWM CONTROL Addr: 0fh PWM_CONTROL Controls the different PWM modes and Internal or external PWM Default Access PWM_MODE 01 R/W 2 PWM INT/EXT 1 R/W 3 VSYNC_INVERT 0 R/W 00 Sync mode 01 Async - mode 10 Sigma - delta mode 11 not used NOTE: Sync and sigma - delta mode can only be used with PWM INT = 0. 0 PWM generator uses external H and Vsync clock 1 PWM generator uses internal 500kHz clock. 0 VSYNC active high (PWM triggers on rising edge) 1 VSYNC active low (PWM triggers on falling edge) am lc s on A te G nt st il 1:0 Description al id Bit Name lv Bit Note: If Vsync or Hsync is not used, connect it to GND. 7.3.1 SYNC mode (PWM_MODE = 00) In this mode the PWM is synchronized with VSYNC and HSYNC. Reg: N V s ync Delay Res et Or R Hs ync Counter Reg: P Compare Compare P WM ca Reg: M Te ch ni Setup options: Delay (N) = registers 0h32 to 0h51 High Time (M) = registers 0h12 to 0h31 PWM Period (P) = register 0h10 www.austriamicrosystems.com Revision 1.14 / 2010 13 - 39 AS3693A QFN48 austriamicrosystems P WM duration = t vsync V sync Hs ync P WM Reset P*t > t reset with Vsync hsync vsync Delay =N * t hsync P WM P WM s ignal: High time = M * t hsync hsync vsync P WM P WM s ignal: High time = M * t hsync Restart P WM P eriode = P * t hsync hsync am lc s on A te G nt st il 7.3.1.1 SYNC - mode PWM - generator update cycle. -Store new values from serial interface -Update delay immediately VSYNC Delayed VSYNC (internal) -no new data -new data Update HighTime, Period ca PWM lv P*t < t Repetitive PWM reset with P * t al id P WM P eriode = t vsyunc Shift new data in PWM - State maschine Restart PWM ni VSYNC Te ch HSYNC 7.3.2 ASYNC - mode (PWM_MODE = 01) This PWM is synchronized with Hsync or internal 500KHz clock. The registers are updated with each serial data. www.austriamicrosystems.com Revision 1.14 / 2010 14 - 39 AS3693A QFN48 austriamicrosystems Reset V s ync R Reg: P Counter Hs ync Compare Compare P WM al id Reg: M High time (M) = registers 0h12 to 0h 31 PWM period (P) = register 0h10 lv Hs ync AsyncMode Repetitive PWM no Reset Syncronized on Hsync or internal Clock P WM hsync am lc s on A te G nt st il P WM s ignal: High time = M * t P WM P eriode = P * t hsync 7.3.3 SIGMA DELTA - mode (PWM_MODE = 10) This PWM is synchronized with Hsync or internal 500KHz clock Hs ync Reg: M = INCREMENT Counter P = SIZE P WM Setup options: Increment (M) = registers 0h12 to 0h 31 Counter size (P) = register 0h10 H sync ca SD - Mode P WM - P E R IOD P uls e dens ity bitstream M % Te ch ni SD www.austriamicrosystems.com Revision 1.14 / 2010 15 - 39 AS3693A QFN48 austriamicrosystems 7.4 PWM - high time, period and delay registers Table 15 - Curreg1-16_DELAY_LSB Addr: 32h - 50h CURREGX_DELAY_LSB Default Access 7:0 CurregX_DELAY_LS B R/W Description Defines the delay time of the PWM Table 16 - Curreg1-16_DELAY_MSB Addr: 32h-51h CURREGX_DELAY_LSB am lc s on A te G nt st il Defines delay of the different PWM's Bit 3:0 al id Bit Name lv Bit 00000000 Defines delay of the different PWM's Bit Name Default Access CurregX_DELAY_MS B 0000 R/W Description Defines the delay time of the PWM Table 17- PWM_PERIOD_LSB Addr: 10h PWM - Period - LSB Default Access 7:0 PWM_PERIOD_LSB R/W Description Defines the period of the PWM ca Bit Name 11111111 Defines PWM - Periode Bit Table 18- PWM_PERIOD_MSB Addr: 11h PWM - Period - MSB Bit Bit Name Default Access PWM_PERIOD_MSB 0000 R/W ch 3:0 ni Defines PWM - Periode Description Defines the period of the PWM Addr: 12h-30h CURREGX_HT_LSB Defines High Time of PWM Bit Bit Name 7:0 Curreg1_HT_LSB www.austriamicrosystems.com Default Access 0 Te Table 19- Curreg1-16_HT_LSB R/W Description Defines PWM high time Revision 1.14 / 2010 16 - 39 AS3693A QFN48 austriamicrosystems Table 20- Curreg1-16_HT_MSB Addr: 13h-31h CURREGX_HT_MSB Defines High Time of PWM Bit Bit Name Default Access 3:0 Curreg1_HT_MSB 0000 R/W Description Defines PWM high time al id 7.5 Shunt Regulator The external resistor Rvdd has to be choosen according to the following formula: VDDMIN is the minimum voltage of the supply, where Rvdd is connected VDDMIN - 5,4V 20mA am lc s on A te G nt st il Rvdd = lv The supply of the AS3693A is generated from the high voltage supply. To obtain a 5V regulated supply, a series resistor Rvdd is used together with an internal zener diode (ZD1). An external capacitor Cvdd is used to filter the supply on the pin VREG. This ensures enough supply current (IVREGMAX) for the AS3693A under minimum supply voltage VDDMIN. If a stable 5V supply within the operating conditions limits of VREGEXT is already existing in the system it is possible to supply the AS3693A directly. In this case remove the resistor Rvdd and connected this supply directly to VREG. 7.5.1 Undervoltage lockout The undervoltage lockout is an additional safety feature to prevent LED-current under abnormal Vreg conditions. If the supply voltage Vreg is below 2.8V (e.g. device is supplied only by the voltage of the serial interface) the device gets a reset. 3.3V to 5.4V Vreg Reset 2.8V Register 0x01 Register 0x02 ni ca Reset 7.6 Over temperature control ch Table 14- Overtemp Control Te Addr:55h Over temperature Control Controls the temperature functions Bit Bit Name Default Access 0 overtemp_on 1 R/W 1 ov_temp 0 R/W www.austriamicrosystems.com Description Enables the over temperature protection 0 = Protection off 1 = Protection on Displays temperature status 0 = Normal operation 1 = Over temperature shutdown Revision 1.14 / 2010 17 - 39 AS3693A QFN48 austriamicrosystems 7.7 Device address setup The I2C and SPI - Device address can be set via PIN ADDR1 and ADDR2. The AS3693A offers 31 I2C or 32 SPI addresses, which can be set via external resistor. ADDR2 bit 2 decides if I2C or SPI interface is used. AS3693 Flexible 6- Bit Address Programming with 2 external resistors. al id Digital Digital Registers PWM - Generator 6 Bit I2C ADDRESS ADC ADDR2 R2 am lc s on A te G nt st il R1 lv ADDR1 Table 13- Device Address Device Adress Setup: I2C ADDRESS I2C ADDRESS Options Bit Bit Name Default Device ADDR1 5:3 Device ADDR2 000 000 Description Lower 3 bits of device address Note: don't use address 00h 000 open 001 320k 010 160k 011 80k 100 40k 101 20k 110 10k 111 0 Upper 3 bits of device address 000 open Note: activates I2C - mode 001 320k Note: activates I2C - mode 010 160k Note: activates I2C - mode 011 80k Note: activates I2C - mode 100 40k Note: activates SPI - mode 101 20k Note: activates SPI - mode 110 10k Note: activates SPI - mode 111 0 Note: activates SPI - mode R ca 2:0 Access ni R ch 7.7.1 I2C Device Address setup BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 (ADDR2<2>) ADDR2<1> ADDR2<0> ADDR1<2> ADDR1<1> ADDR1<0> R/W Te BIT 7 0 7.7.2 SPI Device Address setup BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 1 (ADDR2<2>) ADDR2<1> ADDR2<0> ADDR1<2> ADDR1<1> ADDR1<0> www.austriamicrosystems.com Revision 1.14 / 2010 18 - 39 AS3693A QFN48 austriamicrosystems 7.8 Digital interface The AS3693A can be controlled with two types of interfaces. 7.8.1 I2C interface 7.8.1.1 Feature List al id Fast-mode capability (max. SCL-frequency is 400 kHz) Write formats: Single-Byte-Write, Page-Write Read formats: Current-Address-Read, Random-Read, Sequential-Read SDA input delay and SCL spike filtering by integrated RC-components * * * * 7.8.1.2 Transfer Formats 2 S DW A WA A reg_data S Sr DW DR WA A N P white field grey field WA++ A P 2 START condition after STOP repeated START device address for write device address for read word address acknowledge no acknowledge stop condition slave as receiver slave as transmitter increment word address internally am lc s on A te G nt st il write register, WA++ lv Figure 1 - I C Byte-Write: Figure 2 - I C Page-Write: S DW A WA A reg_data 1 A reg_data 2 ... A reg_data n A P write register WA++ write register WA++ write register WA++ Byte-Write and Page-Write are used to write data to the slave. The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The device-write address is followed by the word address. After the word address any number of data bytes can be send to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations. ni ca For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed st by the 1 register byte transmitted from the slave. In Read-Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally. The diagrams below show various read formats available: 2 ch Figure 3 - I C Random-Read: DW A Te S WA A Sr DR A data read register WA++ N P WA++ Random-Read and Sequential-Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master. The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address. st In order to change the data direction a repeated START condition is issued on the 1 SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes www.austriamicrosystems.com Revision 1.14 / 2010 19 - 39 AS3693A QFN48 austriamicrosystems the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus. 2 Figure 4 - I C Sequential-Read: DW A WA A Sr DR A data 1 A data 2 ... A data n read register WA++ N P al id S WA++ lv Sequential-Read is the extended form of Random-Read, as more than one register-data bytes are transferred subsequently. In difference to the Random-Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently. 2 S DR am lc s on A te G nt st il Figure 5 - I C Current-Address-Read: A data 1 read register WA++ A data 2 read register WA++ ... A data n read register WA++ N P WA++ Te ch ni ca To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the DeviceRead address. Analogous to Random-Read, a single byte transfer is terminated with a not-acknowledge after the st 1 register byte. Analogous to Sequential-Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition. www.austriamicrosystems.com Revision 1.14 / 2010 20 - 39 AS3693A QFN48 7.8.2 austriamicrosystems SPI interface SPI - Interface Pins OUTPUT Digital SDI FAULT Control -Registers PWM - Generator SCL SDO CS VSYNC al id HSYNC lv ADDR1 ADDR2 am lc s on A te G nt st il SPI Mode - Digital Interface Pins: CS(N) Chip Select input SDO Serial Data output SDI Serial Data input SCL Serial Clock input VSYNC Video Sync signal input HSYNC Video Sync signal input ADDR1 Device Address pins (can be ADDR2 set via resistor). 7.8.2.1 Read Sequence CS1 0 1 SCK 2 3 4 5 6 7 8 9 8 Bit Device Address SDI (SDA) 7 6 5 4 3 2 10 11 13 14 1 0 12 7 Bit Register Address 1 0 6 5 4 3 2 15 16 17 18 7 6 5 19 20 21 22 23 2 1 0 R/W 1 Data Out High Impedance 4 3 ca SDO Te ch ni 7.8.2.2 Page Read Sequence www.austriamicrosystems.com Revision 1.14 / 2010 21 - 39 AS3693A QFN48 austriamicrosystems 7.8.2.3 Write Sequence CS1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 TWC SCL 8 Bit Device Address 7 6 5 4 3 R/W 7 Bit Address 2 0 1 5 6 4 3 10 11 2 1 12 13 0 Data Byte 0 7 6 5 4 3 2 1 0 al id SDI (SDA) High Impedance SDO CS1 0 1 2 3 4 5 6 7 8 9 14 15 16 17 18 19 8 Bit Device Address SDI (SDA) 7 6 5 CS1 24 25 7 6 SCK 4 26 3 27 7 Bit Register Address 2 28 1 6 0 5 4 3 29 30 31 32 33 34 2 1 0 7 6 5 Data Byte 2 21 22 23 5 4 3 35 R/W 1 2 36 0 0 Data Byte 1 7 37 38 39 2 1 0 6 5 Data Byte 3 4 3 4 3 2 1 0 Data Byte n (32 max) 7 6 5 4 3 2 1 0 Te ch ni ca SD (SDA) 20 am lc s on A te G nt st il SCK lv 7.8.2.4 Page Write Sequence www.austriamicrosystems.com Revision 1.14 / 2010 22 - 39 AS3693A QFN48 austriamicrosystems 8 Register map Name Def ault B7 b6 b5 B4 b3 b2 b1 b0 Reg. Control1 01h 00h Curreg 8_ON Curreg7 _ON Curreg6 _ON Curreg5 _ON Curreg4 _ON Curreg 3_ON Curreg 2_ON Curreg1 _ON Reg Control 2 02h 00h Curreg 16_ON Curreg1 5_ON Curreg1 4_ON Curreg1 3_ON Curreg1 2_ON Curreg 11_ON Curreg 10_ON Curreg9 _ON Short_Led Detect Voltage SHORT _DET_ ON OPEN_ LED _DET _ON Feedba ck_on_ PWM FEEDB ACK_O N Feedback Control 04h 00h DCDC_REGULATI ON_TRIP_POINT Fedback Select 1 05h 00h FB4_ Select FB3_ Select FB2_ Select Fedback Select 2 06h 00h FB8_ Select FB7_ Select FB6_ Select FB5_ Select Fedback Select 3 07h 00h FB12_ Select FB11_ Select FB10_ Select FB9_ Select Fedback Select 4 08h 00h FB16_ Select FB15_ Select FB14_ Select FB13_ Select Voltage_Fault 1 09h 00h Fault_Reg4 Fault_Reg3 Fault_Reg2 Fault_Reg1 Voltage_Fault 2 0Ah 00h Fault_Reg8 Fault_Reg7 Fault_Reg6 Fault_Reg5 Voltage_Fault 3 0Bh 00h Fault_Reg12 Fault_Reg11 Fault_Reg10 Fault_Reg9 Voltage_Fault 4 0Ch 00h Fault_Reg16 Fault_Reg15 Fault_Reg14 Fault_Reg13 CURREG_CONTR OL 0Dh 00h PWM_LOW_LEVE L RC_SEL Select Ref Ref_DAC_Voltage 0Eh 00h PWM -CONTROL 0Fh 04h PWMPERIOD_LSB 10h FFh PWM-PERIODMSB 11h 00h Curreg1_HT_LSB 12h 00h Curreg1_HT_MSB 13h 00h Curreg2_HT_LSB 14h 00h Curreg2_HT_MSB 15h 00h Curreg3_HT_LSB 16h 00h Curreg3_HT_MSB 17h 00h Curreg4_HT_LSB 18h 00h Curreg4_HT_MSB 19h 00h Curreg5_HT_LSB 1Ah 00h Te al id Addr Curreg5_HT_MSB 1Bh 00h Curreg6_HT_LSB 1Ch 00h Curreg6_HT_MSB 1Dh 00h Curreg7_HT_LSB 1Eh 00h Curreg7_HT_MSB 1Fh 00h Curreg8_HT_LSB 20h 00h Curreg8_HT_MSB 21h 00h am lc s on A te G nt st il lv FB1_Select switch_ output_ driver Vref_DAC VSYNC _INVER T PWM - MODE PWM - period - MSB Curreg1_HT_LSB Curreg1_HT_MSB Curreg2_HT_LSB Curreg2_HT_MSB Curreg3_HT_LSB ni ch www.austriamicrosystems.com PWMINT/EX T PWM -PERIOD - LSB ca boost mode Curreg3_HT_ MSB Curreg4_HT_LSB Curreg4_HT_ MSB Curreg5_HT_LSB Curreg5_HT_ MSB Curreg6_HT_LSB Curreg6_HT_ MSB Curreg7_HT_LSB Curreg7_HT_ MSB Curreg8_HT_LSB Curreg8_HT_ MSB Revision 1.14 / 2010 23 - 39 AS3693A QFN48 Def ault Curreg9_HT_LSB 22h 00h Curreg9_HT_MSB 23h 00h Curreg10_HT_LSB 24h 00h Curreg10_HT_MSB 25h 00h Curreg11_HT_LSB 26h 00h Curreg11_HT_MSB 27h 00h Curreg12_HT_LSB 28h 00h Curreg12_HT_MSB 29h 00h Curreg13_HT_LSB 2Ah 00h Curreg13_HT_MSB 2Bh 00h Curreg14_HT_LSB 2Ch 00h Curreg14_HT_MSB 2Dh 00h Curreg15_HT_LSB 2Eh 00h Curreg15_HT_MSB 2Fh Curreg16_HT_LSB 30h 00h Curreg16_HT_MSB 31h 00h Curreg1_DELAY_L SB 32h 00h Curreg1_ DELAY _MSB 33h 00h Curreg2_ DELAY _LSB 34h 00h Curreg2_ DELAY _MSB 35h 00h Curreg3_ DELAY _LSB 36h 00h Curreg3_ DELAY _MSB 37h 00h Curreg4_ DELAY _LSB 38h 00h Curreg4_ DELAY _MSB 39h 00h Curreg5_DELAY_L SB 3Ah 00h Curreg5_DELAY_M SB 3Bh 00h Curreg6_DELAY_L SB 3Ch 00h Curreg6_DELAY_M SB 3Dh 00h Curreg7_DELAY_L SB 3Eh 00h Curreg7_DELAY_M SB 3Fh 00h Curreg8_DELAY_L SB 40h 00h Curreg8_DELAY_M SB 41h 00h B7 b5 B4 b3 b2 b1 b0 Curreg9_HT_LSB Curreg9_HT_ MSB Curreg10_HT_LSB Curreg10_HT_ MSB Curreg11_HT_LSB Curreg11_HT_ MSB Curreg12_HT_LSB Curreg12_HT_MSB Curreg13_HT_LSB Curreg13_HT_MSB Curreg14_HT_LSB Curreg14_HT_MSB Curreg15_HT_LSB Curreg15_HT_MSB ca am lc s on A te G nt st il 00h ni ch Te b6 al id Addr lv Name austriamicrosystems www.austriamicrosystems.com Curreg16_HT_LSB Curreg16_HT_MSB Curreg1_DELAY_LSB Curreg1_DELAY_MSB Curreg2_DELAY_LSB Curreg2_DELAY_MSB Curreg3_DELAY_LSB Curreg3_DELAY_ MSB Curreg4_DELAY_LSB Curreg4_DELAY_ MSB Curreg5_DELAY_LSB Curreg5_DELAY_ MSB Curreg6_DELAY_LSB Curreg6_DELAY_ MSB Curreg7_DELAY_LSB Curreg7_DELAY_ MSB Curreg8_DELAY_LSB Curreg8_DELAY_ MSB Revision 1.14 / 2010 24 - 39 AS3693A QFN48 Addr Def ault Curreg9_DELAY_L SB 42h 00h Curreg9_DELAY_M SB 43h 00h Curreg10_DELAY_ LSB 44h 00h Curreg10_DELAY_ MSB 45h 00h Curreg11_DELAY_ LSB 46h 00h Curreg11_DELAY_ MSB 47h 00h Curreg12_DELAY_ LSB 48h 00h Curreg12_DELAY_ MSB 49h 00h Curreg13_DELAY_ LSB 4Ah 00h Curreg13_DELAY_ MSB 4Bh 00h Curreg14_DELAY_ LSB 4Ch 00h Curreg14_DELAY_ MSB 4Dh 00h Curreg15_DELAY_ LSB 4Eh 00h Curreg15_DELAY_ MSB 4Fh 00h Curreg16_DELAY_ LSB 50h 00h Curreg16_DELAY_ MSB 51h 00h Overtemp control 55h 01h ASIC ID1 5Ch CAh 1 1 0 0 57h 0 1 0 1 B7 b5 B4 b3 b2 b1 Curreg9_DELAY_ MSB Curreg10_DELAY_LSB al id Curreg10_DELAY_ MSB Curreg11_DELAY_LSB Curreg11_DELAY_ MSB Curreg12_DELAY_LSB am lc s on A te G nt st il Curreg12_DELAY_MSB Curreg13_DELAY_LSB Curreg13_DELAY_MSB Curreg14_DELAY_LSB Curreg14_DELAY_MSB Curreg15_DELAY_LSB Curreg15_DELAY_MSB Curreg16_DELAY_LSB Curreg16_DELAY_LSB 1 0 ov_temp ov_temp _on 1 0 REVISION Te ch ni 5Dh b0 Curreg9_DELAY_LSB ca ASIC ID2 b6 lv Name austriamicrosystems www.austriamicrosystems.com Revision 1.14 / 2010 25 - 39 AS3693A QFN48 austriamicrosystems 9 Pinout and Packaging 9.1 Pinout Pin Name 1 RES1 2 CURR1 3 FBG 4 FBB 5 REF(EXT) 6 GND(SENSE) 7 VREG 8 V2_5 9 ADDR2 10 ADDR1 11 CURR2 12 RES2 13 RES3 14 CURR3 15 RES4 16 CURR4 17 RES5 18 CURR5 19 CURR6 20 RES6 21 CURR7 22 RES7 23 CURR8 24 RES8 25 ni Table 5 - Pinlist CURR9 Description al id AIO Connect to current set resistor R1 AI Reference pin for PWM = 1 voltage, if not used leave open AIO GND supply connection (sense) am lc s on A te G nt st il AIO Shunt regulator supply; connect to Rvdd and Cvdd lv AIO Current Source 1 output Automatic supply regulation for GREEN led strings; if not AIO used, leave open Automatic supply regulation for BLUE led strings; if not AIO used, leave open AIO Digital supply, connect 1uF blocking capacitor AIO Connect to external resistor for serial interface address selection, AIO Connect to external resistor for serial interface address selection. AIO Current Source 2 output AIO Connect to current set resistor R2 AIO Connect to current set resistor R3 AIO Current Source 3 output AIO Connect to current set resistor R4 AIO Current Source 4 output AIO Connect to current set resistor R5 AIO Current Source 5 output AIO Current Source 6 output AIO Connect to current set resistor R6 AIO Current Source 7 output ca AIO Connect to current set resistor R7 AIO Current Source 8 output AIO Connect to current set resistor R8 AIO Connect to current set resistor R9 AIO Current Source 9 output Automatic supply regulation for RED led strings; if not AIO used, leave open ch 26 RES9 Type FBR 28 VSYNC DI Video sync signal , NOTE: Connect to GND in ASYNC MODE 29 HSYNC DI Video sync signal or external clock input in ASYNC mode 30 CS DI SPI : CS - function, I2C: connect to GND 31 SCL DI SPI/ I2C: Serial interface clock input. 32 SDA DI SPI/ I2C: Serial interface data I/O. 33 SDO DO SPI: digital data output, I2C: leave open 34 FAULT Te 27 DO FAULT PIN, open drain output. Connect pull up resistor to V2_5 www.austriamicrosystems.com Revision 1.14 / 2010 26 - 39 AS3693A QFN48 austriamicrosystems Table 5 - Pinlist Pin Name Type Description 35 CURR10 36 RES10 AIO Connect to current set resistor R10 37 RES11 AIO Connect to current set resistor R11 38 CURR11 39 RES12 40 CURR12 41 RES13 42 CURR13 AIO Current Source 13 output 43 CURR14 AIO Current Source 14 output 44 RES14 45 CURR15 46 RES15 47 CURR16 48 RES16 49 (EP) GND AIO Current Source 10 output AIO Current Source 11 output AIO Connect to current set resistor R13 AIO Connect to current set resistor R14 AIO Current Source 15 output am lc s on A te G nt st il AIO Connect to current set resistor R15 lv AIO Current Source 12 output al id AIO Connect to current set resistor R12 AIO Current Source 16 output AIO Connect to current set resistor R16 VSS Supply connection; add as many vias to S ground plane as possible. AIO...Analog pin DI...Digital input. Protected with clamp to 2.5V DO...Digital output. Protected with clamp to 2.5V S... VSS supply Te ch ni ca Note: Connect any unused current output channel as follows: - CURRx = open, Resx = GND www.austriamicrosystems.com Revision 1.14 / 2010 27 - 39 AS3693A QFN48 austriamicrosystems Te ch ni ca am lc s on A te G nt st il lv al id 9.2 Package drawing QFN48, 6x6mm, 0.4mm pitch www.austriamicrosystems.com Revision 1.14 / 2010 28 - 39 AS3693A QFN48 Te ch ni ca am lc s on A te G nt st il lv al id austriamicrosystems www.austriamicrosystems.com Revision 1.14 / 2010 29 - 39 AS3693A QFN48 Te ch ni ca am lc s on A te G nt st il lv al id austriamicrosystems www.austriamicrosystems.com Revision 1.14 / 2010 30 - 39 AS3693A QFN48 austriamicrosystems Te ch ni ca am lc s on A te G nt st il lv al id 9.3 Package drawing QFN48, 7x7mm, 0.5mm pitch www.austriamicrosystems.com Revision 1.14 / 2010 31 - 39 AS3693A QFN48 Te ch ni ca am lc s on A te G nt st il lv al id austriamicrosystems www.austriamicrosystems.com Revision 1.14 / 2010 32 - 39 AS3693A QFN48 Te ch ni ca am lc s on A te G nt st il lv al id austriamicrosystems www.austriamicrosystems.com Revision 1.14 / 2010 33 - 39 AS3693A QFN48 austriamicrosystems Te ch ni ca am lc s on A te G nt st il lv al id 9.4 Package Drawing MLF48 www.austriamicrosystems.com Revision 1.14 / 2010 34 - 39 AS3693A QFN48 lv al id austriamicrosystems am lc s on A te G nt st il MLF 7x7, 0.5mm pitch: Package Type: VKKD-4,6,8 Body size: 7x7mm Lead pitch: 0.5mm Te ch ni ca MLF 6x6, 0.4mm pitch: Package Type: VJJE/VJJE-1 Body size: 6x6mm Lead pitch: 0.4mm www.austriamicrosystems.com Revision 1.14 / 2010 35 - 39 AS3693A QFN48 Te ch ni ca am lc s on A te G nt st il lv al id austriamicrosystems www.austriamicrosystems.com Revision 1.14 / 2010 36 - 39 AS3693A QFN48 Te ch ni ca am lc s on A te G nt st il lv al id austriamicrosystems www.austriamicrosystems.com Revision 1.14 / 2010 37 - 39 AS3693A QFN48 austriamicrosystems 10 Ordering Information Table 6 - Ordering Information Marking AS3693A-ZQFT-6x6 AS3693A AS3693A-ZQFT-7x7 AS3693A-ZMFT-6x6 AS3693A AS3693A QFN48 6x6mm Delivery Form Tape & Reel 0.4mm pich QFN48 7x7mm Tape & Reel 0.5mm pich MLF48 6x6mm Tape & Reel 0.4mm pich MLF48 7x7mm Tape & Reel 0.5mm pich Description Package size = 6x6mm Pitch = 0.4mm, Pb-Free Package size = 7x7mm Pitch = 0.5mm, Pb-Free Package size = 6x6mm Pitch = 0.4mm, Pb-Free Package size = 7x7mm Pitch = 0.5mm, Pb-Free Te ch ni ca am lc s on A te G nt st il lv AS3693A-ZMFT-7x7 AS3693A Package Type al id Part Number www.austriamicrosystems.com Revision 1.14 / 2010 38 - 39 AS3693A QFN48 austriamicrosystems Copyright Copyright (c) 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, AustriaEurope. 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