General Description
The MAX1162 low-power, 16-bit analog-to-digital con-
verter (ADC) features a successive-approximation ADC,
automatic power-down, fast 1.1µs wakeup, and a high-
speed SPI™/QSPI™/MICROWIRE™-compatible inter-
face. The MAX1162 operates with a single +5V analog
supply and features a separate digital supply, allowing
direct interfacing with +2.7V to +5.25V digital logic.
At the maximum sampling rate of 200ksps, the
MAX1162 consumes typically 2.75mA. Power con-
sumption is typically 13.75mA (AVDD = DVDD = +5V) at
a 200ksps (max) sampling rate. AutoShutdown™
reduces supply current to 140µA at 10ksps and to less
than 10µA at reduced sampling rates.
Excellent dynamic performance and low power, com-
bined with ease of use and small package size (10-pin
µMAX®and 10-pin DFN) make the MAX1162 ideal for
battery-powered and data-acquisition applications or
for other circuits with demanding power consumption
and space requirements.
Applications
Motor Control
Industrial Process Control
Industrial I/O Modules
Data-Acquisition Systems
Thermocouple Measurements
Accelerometer Measurements
Portable- and Battery-Powered Equipment
Features
o16-Bit Resolution, No Missing Codes
o+5V Single-Supply Operation
oAdjustable Logic Level (+2.7V to +5.25V)
oInput-Voltage Range: 0 to VREF
oInternal Track/Hold, 4MHz Input Bandwidth
oSPI/QSPI/MICROWIRE-Compatible Serial Interface
oSmall 10-Pin µMAX or 10-Pin DFN Package
oLow Power
2.75mA at 200ksps
140µA at 10ksps
0.1µA in Power-Down Mode
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
________________________________________________________________
Maxim Integrated Products
1
1
2
3
4
5
10
9
8
7
6
AIN
AGND
DVDD
DGNDCS
AGND
AVDD
REF
MAX1162
µMAX/DFN
TOP VIEW
DOUTSCLK
Pin Configuration
Ordering Information
19-2525; Rev 1; 4/10
Functional Diagram appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART TEMP
RANGE
PIN-
PACKAGE
INL
(LSB)
MAX1162BCUB+ 0°C to +70°C 10 µMAX ±2
MAX1162BC_B* 0°C to +70°C 10 DFN ±2
MAX1162CCUB+ 0°C to +70°C 10 µMAX ±4
MAX1162CC_B* 0°C to +70°C 10 DFN ±4
MAX1162BEUB+ -40°C to +85°C 10 µMAX ±2.5
MAX1162BE_B* -40°C to +85°C 10 DFN ±2.5
MAX1162CEUB+ -40°C to +85°C 10 µMAX ±4
MAX1162CE_B* -40°C to +85°C 10 DFN ±4
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
*
Future product—contact factory for DFN package availability.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
EVALUATION KIT
AVAILABLE
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V, CREF = 4.7µF,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
AIN, REF to AGND ...................................-0.3V to (AVDD + 0.3V)
SCLK, CS to DGND ..................................................-0.3V to +6V
DOUT to DGND .......................................-0.3V to (DVDD + 0.3V)
Maximum Current Into Any Pin ...........................................50mA
Continuous Power Dissipation (TA= +70°C)
10-Pin µMAX (derate 5.6mW/°C above +70°C) ..........444mW
Operating Temperature Ranges
MAX1162_CUB .................................................0°C to +70°C
MAX1162_EUB ..............................................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 1)
Resolution 16 Bits
TA = -40°C -2.5 +2.5
TA = 0°C -2 +2
MAX1162B
TA = +85°C -2 +2
TA = -40°C -4 +4
TA = 0°C -4 +4
Relative Accuracy (Note 2) INL
MAX1162C
TA = +85°C -4 +4
LSB
TA = -40°C NMC* 2
TA = 0°C NMC* 1.75MAX1162B
TA = +85°C NMC* 1.75
TA = -40°C -2 +2
TA = 0°C -2 +2
Differential Nonlinearity DNL
MAX1162C
TA = +85°C -2 +2
LSB
Transition Noise RMS noise ±0.65 LSBRMS
Offset Error 0.1 1 mV
Gain Error (Note 3) ±0.002 ±0.01 %FSR
Offset Drift 0.4 ppm/oC
Gain Drift (Note 3) 0.2 ppm/oC
*NMC = No missing code.
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V, CREF = 4.7µF,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096VP-
Signal-to-Noise Plus Distortion SINAD 86 89.5 dB
Signal-to-Noise Ratio SNR 87 90 dB
Total Harmonic Distortion THD -90 dB
Spurious-Free Dynamic Range SFDR 92 103 dB
Full-Power Bandwidth -3dB point 4 MHz
Full-Linear Bandwidth SINAD > 86dB 10 kHz
CONVERSION RATE
Conversion Time tCONV (Note 4) 5 240 µs
Serial Clock Frequency fSCLK 0.1 4.8 MHz
Aperture Delay tAD 15 ns
Aperture Jitter tAJ <50 ps
Sample Rate fSfSCLK / 24 200 ksps
Track/Hold Acquisition Time tACQ 1.1 µs
ANALOG INPUT (AIN)
Input Range VAIN 0V
REF V
Input Capacitance CAIN 40 pF
EXTERNAL REFERENCE
Input-Voltage Range VREF 3.8 AVDD V
VREF = +4.096V, fSCLK = 4.8MHz 100
VREF = +4.096V, SCLK idle 0.01Input Current IREF
CS = DVDD, SCLK idle 0.01
µA
DIGITAL INPUTS (SCLK, CS)
Input High Voltage VIH DVDD = +2.7V to +5.25V 0.7 x
DVDD V
Input Low Voltage VIL DVDD = +2.7V to +5.25V 0.3 x
DVDD V
Input Leakage Current IIN VIN = 0 to DVDD ±0.1 ±1 µA
Input Hysteresis VHYST 0.2 V
Input Capacitance CIN 15 pF
DIGITAL OUTPUT (DOUT)
Output High Voltage VOH ISOURCE = 0.5mA, DVDD = +2.7V to +5.25V DVDD -
0.25V V
ISINK = 10mA, DVDD = +4.75V to +5.25V 0.7
Output Low Voltage VOL ISINK = 1.6mA, DVDD = +2.7V to +5.25V 0.4 V
Three-State Output Leakage
Current ILCS = DVDD ±0.1 ±10 µA
Three-State Output Capacitance COUT CS = DVDD 15 pF
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS (Figures 1, 2, 3, and 6)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V, TA= TMIN
to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time tACQ 1.1 µs
SCLK to DOUT Valid tDO CDOUT = 50pF 50 ns
CS Fall to DOUT Enable tDV CDOUT = 50pF 80 ns
CS Rise to DOUT Disable tTR CDOUT = 50pF 80 ns
CS Pulse Width tCSW 50 ns
CS Fall to SCLK Rise Setup tCSS 100 ns
CS Rise to SCLK Rise Hold tCSH 0ns
SCLK High Pulse Width tCH 65 ns
SCLK Low Pulse Width tCL 65 ns
SCLK Period tCP 208 ns
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V, CREF = 4.7µF,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
Analog Supply AVDD 4.75 5.25 V
Digital Supply DVDD 2.7 5.25 V
200ksps 2.75 3.25
100ksps 1.4
10ksps 0.14
Analog Supply Current IAVDD CS = DGND
1ksps 0.014
mA
200ksps 0.6 1.0
100ksps 0.3
10ksps 0.03
Digital Supply Current IDVDD
CS = DGND,
DOUT = all
zeros
1ksps 0.003
mA
Shutdown Supply Current IAVDD +
IDVDD
CS = DVDD, SCLK = idle 0.1 10 µA
Power-Supply Rejection Ratio PSRR AVDD = DVDD = +4.75V to +5.25V, full-scale
input (Note 5) 68 dB
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
_______________________________________________________________________________________ 5
Note 1: AVDD = DVDD = +5V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Offset and reference errors nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
TIMING CHARACTERISTICS (Figures 1, 2, 3, and 6)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF =
+4.096V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time tACQ 1.1 µs
SCLK to DOUT Valid tDO CDOUT = 50pF 100 ns
CS Fall to DOUT Enable tDV CDOUT = 50pF 100 ns
CS Rise to DOUT Disable tTR CDOUT = 50pF 80 ns
CS Pulse Width tCSW 50 ns
CS Fall to SCLK Rise Setup tCSS 100 ns
CS Rise to SCLK Rise Hold tCSH 0ns
SCLK High Pulse Width tCH 65 ns
SCLK Low Pulse Width tCL 65 ns
SCLK Period tCP 208 ns
INL vs. OUTPUT CODE
MAX1162 toc01
OUTPUT CODE
INL (LSB)
524293932213107 26214
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
-2.0
0 65536
DNL vs. OUTPUT CODE
MAX1162 toc02
OUTPUT CODE
DNL (LSB)
52429393222621413107
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
-2.0
0 65536 908070605040302010
-120
-100
-80
-60
-40
-20
0
-140
0 100
MAX1162 FFT
MAX1162 toc03
FREQUENCY (kHz)
MAGNITUDE (dB)
Typical Operating Characteristics
(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CLOAD = 50pF, CREF = 4.7µF, VREF = +4.096V, TA= +25°C, unless otherwise noted.)
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CLOAD = 50pF, CREF = 4.7µF, VREF = +4.096V, TA= +25°C, unless otherwise noted.)
0
4
2
8
6
12
10
14
18
16
20
4.75 4.85 4.95 5.05 5.15 5.25
MAX1162 toc10
SUPPLY VOLTAGE (V)
ISHDN (nA)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1162 toc11
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (nA)
603510-15
50
25
100
75
150
125
0
-40 85
SINAD vs. FREQUENCY
MAX1162 toc04
FREQUENCY (kHz)
SINAD (dB)
101
10
20
30
40
50
60
70
80
90
100
0
0.1 100
SFDR vs. FREQUENCY
MAX1162 toc05
FREQUENCY (kHz)
SFDR (dB)
101
10
20
30
40
50
60
70
80
90
100
110
120
0
0.1 100
THD vs. FREQUENCY
MAX1162 toc06
FREQUENCY (kHz)
THD (dB)
1010.1 100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
SUPPLY CURRENT
vs. CONVERSION RATE
MAX1162 toc07
CONVERSION RATE (kHz)
SUPPLY CURRENT (mA)
0.01
0.1
1
10
0.001
0.01 0.1 1 10 100 1000
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1162 toc08
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
5.155.054.954.854.75 5.25
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
SUPPLY CURRENT
vs. TEMPERATURE
MAX1162 toc09
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15-40 85
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CLOAD = 50pF, CREF = 4.7µF, VREF = +4.096V, TA= +25°C, unless otherwise noted.)
-1000
-400
-600
-800
-200
0
200
400
600
800
1000
4.75 4.954.85 5.05 5.15 5.25
OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1162 toc12
SUPPLY VOLTAGE (V)
OFFSET ERROR (µV)
-1000
-400
-600
-800
-200
0
200
400
600
800
1000
-40 10-15 35 60 85
OFFSET ERROR VS. TEMPERATURE
MAX1162 toc13
TEMPERATURE (°C)
OFFSET ERROR (µV)
-0.020
-0.015
-0.010
-0.005
0
0.005
0.010
0.015
0.020
4.75 4.85 4.95 5.05 5.15 5.25
GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1162 toc14
SUPPLY VOLTAGE (V)
GAIN ERROR (%)
-0.020
-0.015
-0.010
-0.005
0
0.005
0.010
0.015
0.020
-40 -15 10 35 60 85
GAIN ERROR vs. TEMPERATURE
MAX1162 toc15
TEMPERATURE (°C)
GAIN ERROR (%)
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
8 _______________________________________________________________________________________
Detailed Description
The MAX1162 includes an input track-and-hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 16-bit out-
put. Figure 4 shows the MAX1162 in its simplest config-
uration. The serial interface requires only three digital
lines (SCLK, CS, and DOUT) and provides an easy
interface to microprocessors (µPs).
The MAX1162 has two power modes: normal and shut-
down. Driving CS high places the MAX1162 in shut-
down, reducing the supply current to 0.1µA (typ), while
pulling CS low places the MAX1162 in normal operating
mode. Falling edges on CS initiate conversions that are
driven by SCLK. The conversion result is available at
DOUT in unipolar serial format. The serial data stream
consists of eight zeros followed by the data bits (MSB
first). Figure 3 shows the interface timing diagram.
Analog Input
Figure 5 illustrates the input sampling architecture of
the ADC. The voltage applied at REF sets the full-scale
input voltage.
Track-and-Hold (T/H)
In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive DAC samples the analog input.
During the acquisition, the analog input (AIN) charges
capacitor CDAC. The acquisition interval ends on the
falling edge of the sixth clock cycle (Figure 6). At this
instant, the T/H switches open. The retained charge on
CDAC represents a sample of the input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to zero within the limits of
16-bit resolution. At the end of the conversion, force CS
high and then low to reset the input side of the CDAC
switches back to AIN, and charge CDAC to the input
signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal. Use the following formula to calculate acqui-
sition time:
tACQ = 13(RS+ RIN) x 35pF
where RIN = 800Ω, RS= the input signal’s source
impedance, and tACQ is never less than 1.1µs. A
source impedance less than 1kΩdoes not significantly
affect the ADC’s performance.
To improve the input signal bandwidth under AC condi-
tions, drive AIN with a wideband buffer (>4MHz) that can
drive the ADC’s input capacitance and settle quickly.
Pin Description
PIN NAME FUNCTION
1 REF External Reference Voltage Input. Sets the analog voltage range. Bypass to AGND with a 4.7µF
capacitor.
2AV
DD Analog +5V Supply Voltage. Bypass to AGND (pin 3) with a 0.1µF capacitor.
3, 9 AGND Analog Ground. Connect pins 3 and 9 together. Place star ground at pin 3.
4CS
Active-Low Chip-Select Input. Forcing CS high places the MAX1162 in shutdown with a typical
current of 0.1µA. A high-to-low transition on CS activates normal operating mode and initiates a
conversion.
5 SCLK Serial Clock Input. SCLK drives the conversion process and clocks out data at data rates up to
4.8MHz.
6DOUT
Serial Data Output. Data changes state on SCLK’s falling edge. DOUT is high impedance when CS
is high.
7 DGND Digital Ground
8DV
DD Digital Supply Voltage. Bypass to DGND with a 0.1µF capacitor.
10 AIN Analog Input
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
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_______________________________________________________________________________________ 9
Input Bandwidth
The ADC’s input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use anti-alias filtering.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to AVDD or AGND, allow the input to swing from
AGND - 0.3V to AVDD + 0.3V, without damaging the
device.
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
SCLK
DOUT
tCSS
tCH
tCL
tDV
tCSH
tCSW
tTR
tDO
tCP
CS
TIMING NOT TO SCALE.
Figure 3. Detailed Serial Interface Timing
SCLK
DOUT
AGND
DGND
AIN
REF
AVDD
DVDD
DOUT
SCLK
CS
AIN
VREF
+5V
+5V
4.7µF
0.1µF
0.1µF
GND
MAX1162
CS
Figure 4. Typical Operating Circuit
DOUT
a) VOL TO VOH b) HIGH-Z TO VOL AND VOH TO VOL
DOUT
1mA
1mA
DGND DGND
CLOAD = 50pF CLOAD = 50pF
VDD
Figure 1. Load Circuits for DOUT Enable Time and SCLK to
DOUT Delay Time
DOUT
a) VOH TO HIGH-Z b) VOL TO HIGH-Z
DOUT
1mA
1mA
DGND DGND
CLOAD = 50pF CLOAD = 50pF
VDD
Figure 2. Load Circuits for DOUT Disable Time
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
10 ______________________________________________________________________________________
Digital Interface
Initialization after Power-Up and
Starting a Conversion
The digital interface consists of two inputs, SCLK and
CS, and one output, DOUT. A logic high on CS places
the MAX1162 in shutdown (AutoShutdown) and places
DOUT in a high-impedance state. A logic low on CS
places the MAX1162 in the fully powered mode.
To start a conversion, pull CS low. A falling edge on CS
initiates an acquisition. SCLK drives the A/D conversion
and shifts out the conversion results (MSB first) at DOUT.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CS and SCLK digital inputs (Figures 6
and 7). Ensure that the duty cycle on SCLK is between
40% and 60% at 4.8MHz (the maximum clock frequen-
cy). For lower clock frequencies, ensure that the mini-
mum high and low times are at least 65ns.
Conversions with SCLK rates less than 100kHz can
result in reduced accuracy due to leakage.
Note: Coupling between SCLK and the analog
inputs (AIN and REF) may result in an offset.
Variations in frequency, duty cycle, or other aspects
of the clock signal’s shape result in changing offset.
A CS falling edge initiates an acquisition sequence.
The analog input is stored in the capacitive DAC,
DOUT changes from high impedance to logic low, and
the ADC begins to convert after the sixth clock cycle.
SCLK drives the conversion process and shifts out the
conversion result on DOUT.
SCLK begins shifting out the data (MSB first) after the
falling edge of the 8th SCLK pulse. Twenty-four falling
clock edges are needed to shift out the eight leading
zeros and 16 data bits. Extra clock pulses occurring
after the conversion result has been clocked out, and
prior to the rising edge of CS, produce trailing zeros at
DOUT and have no effect on the converter operation.
Force CS high after reading the conversion’s LSB to
reset the internal registers and place the MAX1162 in
shutdown. For maximum throughput, force CS low
again to initiate the next conversion immediately after
the specified minimum time (tCSW).
Note: Forcing CS high in the middle of a conversion
immediately aborts the conversion and places the
MAX1162 in shutdown.
CDAC 32pF RIN
800Ω
HOLD
HOLD
CSWITCH
3pF
AIN
REF
GND
ZERO
CAPACITIVE DAC
AUTO-ZERO
RAIL
TRACK
TRACK
Figure 5. Equivalent Input Circuit
CS
SCLK 2016 24
1214 86
DOUT D15 D14 D13 D12 D11 D10 D9 D1 D0D8 D5 D4 D3 D2D7 D6
tCSH
tTR
tDO
tACQ
tCSS tCH
tCL
tDV
Figure 6. External Timing Diagram
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
______________________________________________________________________________________ 11
Output Coding and
Transfer Function
The data output from the MAX1162 is binary and Figure
8 depicts the nominal transfer function. Code transitions
occur halfway between successive-integer LSB values
(VREF = 4.096V and 1LSB = 63µV or 4.096V/65536).
Applications Information
External Reference
The MAX1162 requires an external reference with a
+3.8V and AVDD voltage range. Connect the external
reference directly to REF. Bypass REF to AGND (pin 3)
with a 4.7µF capacitor. When not using a low-ESR
bypass capacitor, use a 0.1µF ceramic capacitor in
parallel with the 4.7µF capacitor. Noise on the refer-
ence degrades conversion accuracy.
The input impedance at REF is 40kΩfor DC currents.
During a conversion the external reference at REF must
deliver 100µA of DC load current and have an output
impedance of 10Ωor less.
For optimal performance, buffer the reference through
an op amp and bypass the REF input. Consider the
MAX1162’s equivalent input noise (38µVRMS) when
choosing a reference.
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy. If the input signal is multi-
plexed, switch the input channel immediately after acqui-
sition, rather than near the end of or after a conversion
(Figure 9). This allows the maximum time for the input
buffer amplifier to respond to a large step change in the
input signal. The input amplifier must have a slew rate of
at least 2V/µs to complete the required output-voltage
change before the beginning of the acquisition time.
At the beginning of the acquisition, the internal sampling
capacitor array connects to AIN (the amplifier output),
causing some output disturbance. Ensure that the sampled
voltage has settled before the end of the acquisition time.
Digital Noise
Digital noise can couple to AIN and REF. The conver-
sion clock (SCLK) and other digital signals active dur-
ing input acquisition contribute noise to the conversion
result. Noise signals synchronous with the sampling
interval result in an effective input offset. Asynchronous
signals produce random noise on the input, whose
high-frequency components can be aliased into the fre-
COMPLETE CONVERSION SEQUENCE
CONVERSION 0 CONVERSION 1
POWERED UPPOWERED UP POWERED DOWN
DOUT
CS
TIMING NOT TO SCALE.
Figure 7. Shutdown Sequence
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
123
0FS
FS - 3/2LSB
FS = VREF
INPUT VOLTAGE (LSB)
1LSB = VREF
65536
Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF,
Zero Scale (ZS) = GND
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
12 ______________________________________________________________________________________
quency band of interest. Minimize noise by presenting
a low impedance (at the frequencies contained in the
noise signal) at the inputs. This requires bypassing AIN
to AGND, or buffering the input with an amplifier that
has a small-signal bandwidth of several MHz, or prefer-
ably both. AIN has 4MHz (typ) of bandwidth.
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the MAX1162’s
total harmonic distortion (THD = -102dB at 1kHz) at fre-
quencies of interest. If the chosen amplifier has insuffi-
cient common-mode rejection, which results in degraded
THD performance, use the inverting configuration (posi-
tive input grounded) to eliminate errors from this source.
Low temperature-coefficient, gain-setting resistors reduce
linearity errors caused by resistance changes due to self-
heating. To reduce linearity errors due to finite amplifier
gain, use amplifier circuits with sufficient loop gain at the
frequencies of interest.
DC Accuracy
To improve DC accuracy, choose a buffer with an offset
much less than the MAX1162’s offset (1mV (max) for +5V
supply), or whose offset can be trimmed while maintain-
ing stability over the required temperature range.
Serial Interfaces
The MAX1162’s interface is fully compatible with SPI,
QSPI, and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s ser-
ial interface as master, so that the CPU generates the
serial clock for the MAX1162. Select a clock frequency
between 100kHz and 4.8MHz:
1) Use a general-purpose I/O line on the CPU to pull
CS low.
2) Activate SCLK for a minimum of 24 clock cycles.
The serial data stream of eight leading zeros fol-
lowed by the MSB of the conversion result begins at
the falling edge of CS. DOUT transitions on SCLK’s
falling edge and the output is available in MSB-first
A0
A1
CLK
CHANGE MUX INPUT HERE
CONVERSION
IN1 A0 A1
IN2
IN3
IN4
OUT
ACQUISITION
4-TO-1
MUX
AIN
CS
MAX1162
CS
TIMING NOT TO SCALE.
Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
______________________________________________________________________________________ 13
format. Observe the SCLK to DOUT valid timing
characteristic. Clock data into the µP on SCLK’s ris-
ing edge.
3) Pull CS high at or after the 24th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the least significant bit (D0 = LSB).
4) With CS high, wait at least 50ns (tCSW) before start-
ing a new conversion by pulling CS low. A conver-
sion can be aborted by pulling CS high before the
conversion ends. Wait at least 50ns before starting a
new conversion.
Data can be output in three 8-bit sequences or continu-
ously. The bytes contain the results of the conversion
padded with eight leading zeros before the MSB. If the
serial clock has not been idled after the LSB (D0) and
CS has been kept low, DOUT sends trailing zeros.
SPI and MICROWIRE Interfaces
When using the SPI (Figure 10a) or MICROWIRE
(Figure 10b) interfaces, set CPOL = 0 and CPHA = 0.
Conversion begins with a falling edge on CS (Figure
10c). Three consecutive 8-bit readings are necessary
to obtain the entire 16-bit result from the ADC. DOUT
data transitions on the serial clock’s falling edge. The
first 8-bit data stream contains all leading zeros. The
second 8-bit data stream contains the MSB through D8.
The third 8-bit data stream contains D7 through D0.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX1162 supports a maximum
fSCLK of 4.8MHz. Figure 11a shows the MAX1162 con-
nected to a QSPI master and Figure 11b shows the
associated interface timing.
CS
SCLK
DOUT
I/O
SCK
MISO
SPI VDD
SS
MAX1162
Figure 10a. SPI Connections
MAX1162
CS
MICROWIRE
SCLK
DOUT
I/O
SK
SI
Figure 10b. MICROWIRE Connections
DOUT*
CS
SCLK
1ST BYTE READ 2ND BYTE READ
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
HIGH-Z
3RD BYTE READ
LSB
D1 D0D7 D6 D5 D4 D3 D2
2420
1612
8
641
D15 D14 D13 D12 D11 D10 D9 D8 D7
00000000
TIMING NOT TO SCALE.
Figure 10c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
14 ______________________________________________________________________________________
PIC16 with SSP Module and
PIC17 Interface
The MAX1162 is compatible with a PIC16/PIC17 micro-
controller (µC) using the synchronous serial-port (SSP)
module.
To establish SPI communication, connect the controller
as shown in Figure 12a. Configure the PIC16/PIC17 as
system master, by initializing its synchronous serial-port
control register (SSPCON) and synchronous serial-port
status register (SSPSTAT) to the bit patterns shown in
Tables 1 and 2.
In SPI mode, the PIC16/PIC17 µC allows 8 bits of data
to be synchronously transmitted and received simulta-
CS
QSPI
SCLK
DOUT
CS
SCK
MISO
VDD
SS
MAX1162
SCK
SDI
GND
PIC16/17
I/O
SCLK
DOUT
CS
VDD VDD
MAX1162
Figure 11a. QSPI Connections
Figure 12a. SPI Interface Connection for a PIC16/PIC17
DOUT*
CS
SCLK
*WHEN CS IS HIGH, DOUT = HIGH-Z MSB
2016
D15 D14 D13 D12 D11 D10 D9 HIGH-Z
D1 D0
24
1214 86
D8 D5 D4 D3
LSB
D7 D6
END OF
ACQUISITION D2
Figure 11b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
CONTROL BIT MAX1162
SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL BIT7 X Write Collision Detection Bit
SSPOV BIT6 X Receive Overflow Detect Bit
SSPEN BIT5 1
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
CKP BIT4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3 BIT3 0
SSPM2 BIT2 0
SSPM1 BIT1 0
SSPM0 BIT0 1
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects
fCLK = fOSC / 16.
Table 1. Detailed SSPCON Register Contents
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
______________________________________________________________________________________ 15
neously. Three consecutive 8-bit readings (Figure 12b)
are necessary to obtain the entire 16-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the µC on SCLK’s rising edge.
The first 8-bit data stream contains all zeros. The sec-
ond 8-bit data stream contains the MSB through D8.
The third 8-bit data stream contains bits D7 through D0.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-fit straight line fit or a
line drawn between the endpoints of the transfer func-
tion, once offset and gain errors have been nulled. The
static linearity parameters for the MAX1162 are mea-
sured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of 1LSB guarantees no missing
codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between samples. Aperture delay (tAD) is the
time between the falling edge of the sampling clock
and the instant when the actual sample is taken.
CONTROL BIT MAX1162
SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT)
SMP BIT7 0 SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time.
CKE BIT6 1 SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial clock.
D/A BIT5 X Data Address Bit
P BIT4 X Stop Bit
S BIT3 X Start Bit
R/W BIT2 X Read/Write Bit Information
UA BIT1 X Update Address
BF BIT0 X Buffer Full Status Bit
Table 2. Detailed SSPSTAT Register Contents
DOUT*
CS
SCLK
1ST BYTE READ 2ND BYTE READ
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
HIGH-Z
3RD BYTE READ
LSB
D1 D0D7 D6 D5 D4 D3 D2
2420
1612
D15 D14 D13 D12 D11 D10 D9 D8
00000000 D7
TIMING NOT TO SCALE.
Figure 12b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
X = Don’t care.
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
16 ______________________________________________________________________________________
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADCs res-
olution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals,
excluding the DC offset.
Effective Number of Bits
Effective number of bits (ENOB) indicate the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantiza-
tion noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
Figure 13 shows the effective number of bits as a func-
tion of the MAX1162’s input frequency.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V1is the fundamental amplitude and V2through
V5are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest fre-
quency component.
Supplies, Layout, Grounding,
and Bypassing
Use PC boards with separate analog and digital
ground planes. Do not use wire-wrap boards. Connect
the two ground planes together at the MAX1162 (pin 3).
Isolate the digital supply from the analog with a low-
value resistor (10Ω) or ferrite bead when the analog
and digital supplies come from the same source
(Figure 14).
THD VVVV
V
=× +++
⎡
⎣
⎢
⎢
⎢
⎤
⎦
⎥
⎥
⎥
20 22324252
1
log
SINAD dB Signal
Noise Distortion
RMS
RMS
( ) log=× +
()
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
20
INPUT FREQUENCY (kHz)
EFFECTIVE BITS
101
2
4
6
8
10
12
14
16
0
0.1 100
ENOB vs. INPUT FREQUENCY
Figure 13. Effective Number of Bits vs. Input Frequency
SCLK
DOUT
AGND
DGND
AIN
10Ω
REF
AVDD
DVDD
DOUT
SCLK
CS
AIN
VREF
+5V
4.7µF
0.1µF
0.1µF
GND
MAX1162
CS
Figure 14. Powering AVDD and DVDD from a Single Supply
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
______________________________________________________________________________________ 17
Constraints on sequencing the power supplies and
inputs are as follows:
• Apply AGND before DGND.
• Apply AIN and REF after AVDD and AGND
are present.
•DV
DD is independent of the supply sequencing.
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.05Ωcreates an error
voltage of about 250µV, 4LSB error with a +4V full-
scale system.
The board layout should ensure that digital and analog
signal lines are kept separate. Do not run analog and
digital (especially the SCLK and DOUT) lines parallel to
one another. If one must cross another, do so at right
angles.
The ADCs high-speed comparator is sensitive to high-
frequency noise on the AVDD power supply. Bypass an
excessively noisy supply to the analog ground plane
with a 0.1µF capacitor in parallel with a 1µF to 10µF
low-ESR capacitor. Keep capacitor leads short for best
supply-noise rejection.
AIN
TRACK AND
HOLD
16-BIT SAR
ADC
CONTROL
DVDD
DGND
CS
AGND
AVDD
REF
DOUT
SCLK
MAX1162
OUTPUT
BUFFER
Functional Diagram
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
10 µMAX U10-2 21-0061
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 7/02 Initial release —
1 4/10 Changed analog supply current and added lead-free information 1, 3, 5
