STIXL | ae SN54ABT573A, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS190B JANUARY 1991 - MARCH 1996 SN54ABT573A ... JOR W PACKAGE SN74ABT573A ... DB, DW, OR N PACKAGE (TOP VIEW) State-of-the-Art EPIC-IIB BiCMOS Design Significantly Reduces Power Dissipation @ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds SE tl, ~ coll Veo 200 V Using Machine Model 1D fJ2 19{] 1 (C = 200 pF, R = 0) op {ls _iaf}20 Latch-Up Performance Exceeds 500 mA 3D []4 17[] 3Q Per JEDEC Standard JESD-17 4D [5 16]] 4Q @ Typical Vo;_p (Output Ground Bounce) 5D [6 151] 5Q <1Vat Voc = 5 V, Ta = 25C 6D []7 141} 6Q @ High-Drive Outputs (-32-mA Ion, 7D Je = 13f] 70 64-MA Io.) 8D f{]9 121] 8Q @ Package Options Include Plastic GND []10 npLe Smaill-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), and Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) SN54ABT573A ... FK PACKAGE (TOP VIEW) Oo lu a a6 09 PRODUCTION DATA information ie current es of date. Products conform to standard warrenty. testing of all parameters. Packages description 3D 43 2 1 20 960 20 These 8-bit latches feature 3-state outputs 4DUs5 re 3Q designed specifically for driving highly capacitive SDH 6 16L] 4Q or relatively low-impedance loads. They are 6D 7 15{] 5a particularly suitable for implementing buffer 7D a 10 11121 ial 6Q registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ABT573A are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enabie (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to Voc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ABT573<A is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed circuit board area. The SN54ABT573A is characterized for operation over the full military temperature range of 55C to 125C. The SN74ABT573A is characterized for operation from 40C to 85C. A Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-IIB is a trademark of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated specications per the terms of Texas inetruments . Production processing does not necessarily include vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1SN54ABT573A, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS190B ~ JANUARY 1991 - MARCH 1996 eae FUNCTION TABLE (each latch) INPUTS OUTPUT OE LE D Q L H H H L H L L L L xX Qo H xX x Zz logic symbolt logic diagram (positive logic) cE oe a " OE 11 2 19 LE 1D 3 3 1a 2D 2Q C1 19 4 17 2 1Q 3D 3Q 1D 1D 5 16 4D 4Q 6 15 5D 5Q 7 14 Y 6D 6Q 8 13 , -_ 7D 3 2 7a ap 80 To Seven Other Channels t This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)+ Supply voltage range, Vo ... ccc ccc ete eee ee eee ee eet e een n ene e ones -0.5Vto7V Input voltage range, V; (see Note 1) 0.0... cece cece cece e eee e eee eeeneneeeanes -O0.5Vto7V Voltage range applied to any output in the high state or power-off state, VQ ............. -0.5Vto5.5V Current into any output in the low state, lo: SNS4ABT573A 1... ccc cece cence teens 96 mA SN74ABTS73A .. 2. cee ence eet eees 128 mA Input clamp current, Iq (Vp <0) oe. cece eee renee nent e ee eee en eeen eee eennes -18 mA Output clamp current, lox (VQ <0)... ccc ccc een n nent e nent ene t nee n enn en tenses -50 mA Maximum power dissipation at Ta = 55C (in still air) (see Note 2): DB package .................00. 0.6 W DW package ................... 16W N package ..................00. 1.3W Storage temperature range, Tytg ... 06. cece eee ete c eee t tenn eee e eee nee ennes ~65C to 150C + Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils, except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. vy TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 @ DALLAS, TEXAS 75265SN54ABT573A, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS a recommended operating conditions (see Note 3) SCBS190B JANUARY 1991 - MARCH 1996 ed SN5S4ABT573A | SN74ABT573A MIN MAX MIN MAX UNIT Voc Supply voitage 45 5.5 4.5 5.5 Vv VIH High-level input voltage 2 2 Vv VIL Low-level input voltage 0.8 0.8 Vv Vv Input voltage 0 Vcc 0 Voc Vv IOH High-level output current ~24 -32) mA OL Low-level output current 48 64] mA At/Av Input transition rise or fall rate Outputs enabled 5 5] ns/V Ta Operating free-air temperature -55 125 40 85 C NOTE 3: Unused or floating inputs must be held high or low. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) Ta = 25C SN54ABT573A | SN74ABT573A PARAMETER TEST CONDITIONS UNIT MIN TyPt MAX| MIN MAX| MIN MAX Vik Voc =4.5V, |y=-18mA -1.2 -1.2 12] Vv Voc =45V, loH=-3mA 2.5 25 25 Voc =5V, 10H =-3 mA 3 3 3 VOH v IOH = -24 mA 2 2 Voc =4.5V 10H =-32 mA 2 2 lo = 48 mA 0.55 0.55 VOL Voc =4.5V Vv lo = 64 mA 0.55* 0.55 \ Voc =5.5V, Vi=Vocor GND +1 +1 +1 pA lozH Veco =55V, Vo=2.7V 101 101 io] pa lozL Voc =5.5V, Vo=05V -104 -107 -101] pA loft Voc = 9, ViorVo s4.5V +100 +100 pA ICEX Voc=55V, Vo=55V | Outputs high 50 50 50] pA iot WVoc=55V, Vo=2.5V ~50 -100 -180] -50 -180] -50 -180] mA Outputs high 1 250 250 250 pA Voc =55V, Io=0, mA loc Vie Voc or GND Outputs low 24 = 30 30 30 Outputs disabled 0.5 250 250 250 pA Voc =5.5V, One input at 3.4 V, Aloc$ Other Inputs at Voc or GND 1S 1s 15] mA Cj VWy=2.5Vo0r0.5V 3.5 pF Co Vo =2.5Vo0r05V 6.5 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. t All typical values are at Voc = 5 V. + Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input that is at the specified TTL voltage level rather than Vcc or GND. I This data sheet limit may vary among suppliers. wy TEXAS INSTRUMENTS POST OFFICE BOX 655303 @ DALLAS, TEXAS 75265SN54ABT573A, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS190B - JANUARY 1991 - MARCH 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) ae oe SNS4ABTS73A | MIN MAX MIN MAX tw Pulse duration, LE high 3.3 3.3 ns High 1.9 25 tsy Setup time, data before LEL Cow is 25 ns th Hold time, data after LEL 1 2.5 ns timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) 1 aoe SN74ABTS73A | MIN MAX MIN MAX tw Pulse duration, LE high 3.3 3.3 ns High 1.9 1.9 toy Setup time, data before LEL Low 15 - ns th Hold time, data after LEL 1.8t 1.eT ns t This data sheet limit may vary among suppliers. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C, = 50 pF (unless otherwise noted) (see Figure 1) Vec =5V, FROM TO SN54ABTS73A Ta = 25C PARAMETER (INPUT) (OUTPUT) A UNIT MIN TYP MAX MIN MAX tPLH o Q 1.9 3.2 5.4 1.4 6.4 ns tPHL 2.2 4.2 5.7 1.6 6.7 t 2.2 4 6.1 2 7.1 PLH LE Q ns {PHL 3.2 5.2 6.7 2.8 75 t 1.2 3.2 4.7 0.8 6.2 PZH OE Q ns tp2L 2.7 47 6.2 2 7.2 t = 2.5 49 6.4 2.2 7.7 PHZ OE Q ns tpLz 2 4.2 6 1.4 7 vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS, TEXAS 75265SN54ABT573A, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS190B JANUARY 1991 - MARCH 1996 ee switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C, = 50 pF (unless otherwise noted) (see Figure 1) Vec =5V, FROM TO Ta = 25C SN74ABT573A PARAMETER (INPUT) (OUTPUT) A UNIT MIN TYP MAX MIN MAX tPLH b Q 1.9 3.2 5.4 1.9 5.9 ns tPHL 22 42 57! 22 6.2 t 2.2 4 64 2.2 6.6 PLH LE Q ns tPHL 32 52 67 3.2 7.2 _ 1.2 3.2 47 1.2 5.2 tPZH OE Q ; ; ns tezL 2.5 47 62] 25 6.7 _ 2.5 4.9 6.4 2.5 7.1T {PHZ OE Q ns tpLz 2 4.2 6 2 6.5 t This data sheet limit may vary among suppliers. wy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5SN54ABT573A, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS190B - JANUARY 1991 MARCH 1996 PARAMETER MEASUREMENT INFORMATION 7V st TEST St From Output sna Open tpLHAPHL Open Under Test T GND tpLztpzL 7V Cy = 50 pF tpHz/tpzH Open (see Note A) i 500 2 LOAD CIRCUIT FOR OUTPUTS Timing Input ld tw > | | 3V Input 1.5 x Xs Vv Data Input OV VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3V 3V Input Output 15V (see Note B) Xs V Xs V ov Control x SV x OV tPZL > tPLH 7 oe tPHL Vo Output aN uz + 3.5V Waveform 1 Output | Lisv : sy Slat 7V | \1.5V | E Vou +03 y VOL | VOL | | (see Note C) tpHz ae tpHL >| k>- tPLH cue ZH _ utpu __ sv | Cay VOH Waveform 2 ieV Vouo3v OH Output . . $1 at Open , ~ VOL (gee Note C) = OV , VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. B c. D C_ includes probe and jig capacitance. . Allinput pulses are supplied by generators having the following characteristics: PRR < 10 MHz, Zo = 50 Q, tp $2.5 ns, tfs 2.5 ns. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with intemal conditions such that the output is high except when disabled by the output control. . The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS, TEXAS 75265