9 kHz to 30 GHz, Silicon, SP4T Switch ADRF5045 Data Sheet Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Broadband telecommunications systems GND GND RF2 GND 24 23 22 21 20 19 1 ADRF5045 18 GND GND 2 50 50 17 VDD RFC 3 16 V1 GND 4 15 V2 GND 5 14 VSS 13 GND DRIVER GND 10 11 12 GND 9 RF3 8 GND 7 GND 6 RF4 GND 50 16314-001 50 GND APPLICATIONS RF1 FUNCTIONAL BLOCK DIAGRAM Ultrawideband frequency range: 9 kHz to 30 GHz Nonreflective 50 design Low insertion loss: 2.4 dB at 20 GHz to 30 GHz High isolation: 45 dB at 20 GHz to 30 GHz High input linearity P1dB: 28 dBm typical IP3: 50 dBm typical High power handling 24 dBm through path 24 dBm terminated path ESD rating: 1500 V HBM No low frequency spurious 0.1 dB settling time (50% VCTL to 0.1 dB final RF output): 6 s 24-terminal LGA package GND FEATURES Figure 1. GENERAL DESCRIPTION The ADRF5045 is a general-purpose, single-pole, four-throw (SP4T) switch manufactured using a silicon process. It comes in a 24-terminal land grid array (LGA) package and provides high isolation and low insertion loss from 9 kHz to 30 GHz. Rev. A This broadband switch requires dual supply voltages, +3.3 V and -3.3 V, and provides complementary metal-oxide semiconductor (CMOS)/low voltage transistor-transistor logic (LVTTL) logiccompatible control. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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Technical Support www.analog.com ADRF5045 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics .............................................7 Applications ...................................................................................... 1 Insertion Loss, Return Loss, and Isolation ................................7 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Input 0.1 dB, 1 dB Power Compression, and Third-Order Intercept .........................................................................................9 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 10 Specifications .................................................................................... 3 Applications Information ............................................................. 11 Absolute Maximum Ratings ........................................................... 5 Evaluation Board ........................................................................ 11 Thermal Resistance ...................................................................... 5 Probe Matrix Board ................................................................... 13 Power Derating Curves ............................................................... 5 Outline Dimensions ....................................................................... 14 ESD Caution.................................................................................. 5 Ordering Guide .......................................................................... 14 Pin Configuration and Function Descriptions ............................ 6 Interface Schematics .................................................................... 6 REVISION HISTORY 3/2020--Rev. 0 to Rev. A Changes to Digital Control Inputs Parameter, Table 2 .............. 5 Added Endnote 1, Table 2; Renumbered Sequentially ............... 5 Changes to Theory of Operation Section.................................... 10 12/2017--Revision 0: Initial Version Rev. A | Page 2 of 14 Data Sheet ADRF5045 SPECIFICATIONS VDD = 3.3 V, VSS = -3.3 V, V1 = 0 V or 3.3 V, V2 = 0 V or 3.3 V, and TCASE = 25C, 50 system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS Between RFC and RF1 to RF4 (On) (Worst Case) Symbol ISOLATION Between RFC and RF1 to RF4 (Off) (Worst Case) RETURN LOSS RFC and RF1 to RF4 (On) RF1 to RF4 (Off) SWITCHING TIME Rise and Fall On and Off Settling 0.1 dB 0.05 dB INPUT LINEARITY Power Compression 0.1 dB 1 dB Third-Order Intercept SUPPLY CURRENT Positive Negative DIGITAL CONTROL INPUTS Voltage Low High Current Low and High RECOMMENDED OPERATING CONDITONS Supply Voltage Positive Negative Digital Control Voltage tRISE, tFALL tON, tOFF P0.1dB P1dB IP3 IDD ISS Test Conditions/Comments Min 0.009 Typ Max 30,000 Unit MHz 9 kHz to 10 GHz 10 GHz to 20 GHz 20 GHz to 30 GHz 1.5 1.7 2.4 dB dB dB 9 kHz to 10 GHz 10 GHz to 20 GHz 20 GHz to 30 GHz 58 53 45 dB dB dB 9 kHz to 10 GHz 10 GHz to 20 GHz 20 GHz to 30 GHz 9 kHz to 10 GHz 10 GHz to 20 GHz 20 GHz to 30 GHz 16 25 17 21 17 11 dB dB dB dB dB dB 10% to 90% of radio frequency (RF) output 50% VCTL to 90% of RF output 2 4 s s 50% VCTL to 0.1 dB of final RF output 50% VCTL to 0.05 dB of final RF output 6 7 s s 26 28 50 dBm dBm dBm Two-tone input power = 14 dBm each tone, f = 1 MHz VDD, VSS pins Typical at VCTL = 0 V or 3.3 V, maximum at VCTL = 0.8 V or 1.4 V Typical at VCTL = 0 V or 3.3 V, maximum at VCTL = 0.8 V or 1.4 V V1, V2 pins VINL VINH 3 20 A 110 130 A 0.8 3.3 V V 0 1.2 IINL, IINH <1 VDD VSS VCTL 3.15 -3.45 0 Rev. A | Page 3 of 14 A 3.45 -3.15 VDD V V V ADRF5045 Parameter RFx Input Power Through Path Data Sheet Symbol PIN Terminated Path Hot Switching Case Temperature Test Conditions/Comments TCASE = 85C RF signal is applied to RFC or through connected RF1/RF2 RF signal is applied to terminated RF1/RF2 RF signal is present at RFC while switching between RF1 and RF2 TCASE Min -40 Rev. A | Page 4 of 14 Typ Max Unit 24 dBm 24 dBm 21 dBm +85 C Data Sheet ADRF5045 ABSOLUTE MAXIMUM RATINGS For recommended operating conditions, see Table 1. POWER DERATING CURVES 4 Table 2. Parameter Supply Voltage Positive Negative Digital Control Inputs1 Rating 2 RFx Input Power2 (f = 500 kHz to 30 GHz, TCASE = 85C) Through Path Terminated Path Hot Switching Temperature Junction, TJ Storage Range Reflow (Moisture Sensitivity Level 3 (MSL3) Rating) Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) RFC, RF1 to RF4 Pins Other Pins POWER DERATING (dB) 0 -0.3 V to +3.6 V -3.6 V to +0.3 V -0.3 V to VDD + 0.3 V or 3.3 mA, whichever occurs first -4 -6 -8 -10 25 dBm 25 dBm 22 dBm -14 10k 100k 1M 10M 100M 1G 10G 100G FREQUENCY (Hz) 135C -65C to +150C 260C 16314-002 -12 Figure 2. Power Derating for Through Path and Hot Switching vs. Frequency, TCASE = 85C 4 2 Overvoltages at digital control inputs are clamped by internal diodes. Current must be limited to the maximum rating given. 2 For power derating less than 500 kHz, see Figure 2 and Figure 3. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. 100k 1M 10M 100M FREQUENCY (Hz) 1G 10G 100G Figure 3. Power Derating for Terminated Path vs. Frequency, TCASE = 85C ESD CAUTION Table 3. Thermal Resistance C/W C/W -8 -14 10k JC is the junction to case bottom (channel to package bottom) thermal resistance. 400 160 -6 -12 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Unit -4 -10 THERMAL RESISTANCE JC -2 16314-003 1500 V 2000 V POWER DERATING (dB) 0 1 Package Type CC-24-4 Through Path Terminated Path -2 Rev. A | Page 5 of 14 ADRF5045 Data Sheet GND RF1 GND GND RF2 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 23 22 21 20 19 GND 1 18 GND GND 2 17 VDD RFC 3 ADRF5045 16 V1 GND 4 TOP VIEW (Not to Scale) 15 V2 7 8 9 10 11 12 RF3 GND GND GND 13 GND 14 6 RF4 5 GND GND GND VSS 16314-004 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO THE RF/DC GROUND OF THE PCB. Figure 4. Pin Configuration (Top View) Table 4. Pin Function Descriptions Pin No. 1, 2, 4 to 7, 9, 10, 12, 13, 18, 19, 21, 22, 24 3 Mnemonic GND Description Ground. These pins must be connected to the RF/dc ground of the PCB. RFC 8 RF4 11 RF3 14 15 16 17 20 VSS V2 V1 VDD RF2 23 RF1 RF Common Port. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. See Figure 5 for the interface schematic. RF4 Port. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. See Figure 5 for the interface schematic. RF3 Port. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. See Figure 5 for the interface schematic. Negative Supply Voltage. Control Input 2. See Table 5 for the control voltage truth table. Control Input 1. See Table 5 for the control voltage truth table. Positive Supply Voltage. RF2 Port. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. See Figure 5 for the interface schematic. RF1 Port. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. See Figure 5 for the interface schematic. Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB. EPAD V1, V2 16314-006 RFC, RF1, RF2, RF3, RF4 16314-005 INTERFACE SCHEMATICS Figure 6. Digital Pins (V1 and V2) Interface Schematic Figure 5. RFx Pins (RFC and RF1 to RF4) Interface Schematic Rev. A | Page 6 of 14 Data Sheet ADRF5045 TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, AND ISOLATION 0 -0.5 -0.5 -1.0 -1.0 INSERTION LOSS (dB) 0 -1.5 -2.0 -2.5 -3.0 -3.5 -5.0 0 5 -2.0 -2.5 -3.0 -3.5 -4.0 RF1 RF2 RF3 RF4 -4.5 -1.5 +85C +25C -40C -4.5 10 15 20 25 30 35 40 FREQUENCY (GHz) -5.0 0 5 10 15 20 25 30 35 40 FREQUENCY (GHz) Figure 7. Insertion Loss vs. Frequency for RF1, RF2, RF3, and RF4 16314-010 -4.0 16314-007 INSERTION LOSS (dB) Insertion loss and return loss measured on the probe matrix board using ground signal ground (GSG) probes close to the RFx pins; isolation measured on the evaluation board because signal coupling between the probes limits the isolation performance of the ADRF5045 on the probe matrix board. Figure 10. Insertion Loss vs. Frequency over Various Temperatures Between RFC and RF1 0 0 -5 -5 -10 -10 -20 -25 -20 -25 -30 -30 -35 -35 -40 0 5 10 15 20 25 30 35 40 FREQUENCY (GHz) -40 0 5 10 15 20 25 30 35 40 FREQUENCY (GHz) Figure 8. Return Loss vs. Frequency for RFC Figure 11. Return Loss vs. Frequency for RF1, RF2, RF3, and RF4 0 RFC TO RF2 RFC TO RF3 RFC TO RF4 -10 -20 -30 -30 ISOLATION (dB) -20 -40 -50 -60 -40 -50 -60 -70 -80 -80 -90 -90 -100 5 10 15 20 25 30 35 FREQUENCY (GHz) 40 16314-009 -70 0 RFC TO RF1 RFC TO RF3 RFC TO RF4 -10 Figure 9. Isolation vs. Frequency, RFC to RF1 On -100 0 5 10 15 20 25 30 35 FREQUENCY (GHz) Figure 12. Isolation vs. Frequency, RFC to RF2 On Rev. A | Page 7 of 14 40 16314-012 0 ISOLATION (dB) -15 16314-011 RETURN LOSS (dB) -15 16314-008 RETURN LOSS (dB) ON OFF ADRF5045 Data Sheet 0 RFC TO RF1 RFC TO RF2 RFC TO RF4 -20 -30 -30 ISOLATION (dB) -20 -40 -50 -60 -50 -60 -70 -80 -80 -90 -90 -100 5 10 15 20 25 30 35 40 FREQUENCY (GHz) Figure 13. Isolation vs. Frequency, RFC to RF3 On RF1 TO RF1 TO RF1 TO RF2 TO RF2 TO RF3 TO -10 -20 -30 RF2 RF3 RF4 RF3 RF4 RF4 -40 -50 -60 -70 -80 5 10 15 20 25 FREQUENCY (GHz) 30 35 40 16314-014 -90 -100 0 -100 0 5 10 15 20 25 30 35 FREQUENCY (GHz) Figure 15. Isolation vs. Frequency, RFC to RF4 On 0 CHANNEL TO CHANNEL ISOLATION (dB) -40 -70 0 RFC TO RF1 RFC TO RF2 RFC TO RF3 -10 16314-013 ISOLATION (dB) -10 Figure 14. Channel to Channel Isolation vs. Frequency, RFC to RF1 On Rev. A | Page 8 of 14 40 16314-015 0 Data Sheet ADRF5045 INPUT 0.1 dB, 1 dB POWER COMPRESSION, AND THIRD-ORDER INTERCEPT 32 32 30 30 28 28 26 26 INPUT P0.1dB (dBm) 24 22 20 18 20 18 14 +85C +25C -40C 10 0 5 10 15 +85C +25C -40C 12 20 FREQUENCY (GHz) 10 10k 16314-016 12 Figure 16. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over Various Temperatures 30 28 28 26 26 INPUT P1dB (dBm) 32 20 18 10M 100M 1G Figure 19. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over Various Temperatures (Low Frequency Detail) 30 22 1M FREQUENCY (Hz) 32 24 100k 16314-019 14 16 24 22 20 18 16 14 14 +85C +25C -40C 10 0 5 10 15 +85C +25C -40C 12 20 FREQUENCY (GHz) 10 10k 16314-017 12 Figure 17. Input 1 dB Power Compression (P1dB) vs. Frequency over Various Temperatures 55 50 50 INPUT IP3 (dBm) 55 35 10M 100M 1G Figure 20. Input 1 dB Power Compression (P1dB) vs. Frequency over Various Temperatures (Low Frequency Detail) 60 40 1M FREQUENCY (Hz) 60 45 100k 16314-020 INPUT P1dB (dBm) 22 16 16 30 45 40 35 30 +85C +25C -40C 25 20 0 5 10 15 20 25 +85C +25C -40C 25 30 FREQUENCY (GHz) 16314-018 INPUT IP3 (dBm) 24 Figure 18. Input IP3 vs. Frequency over Various Temperatures 20 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 21. Input IP3 vs. Frequency over Various Temperatures (Low Frequency Detail) Rev. A | Page 9 of 14 16314-021 INPUT P0.1dB (dBm) All large signal performance parameters were measured on the evaluation board. ADRF5045 Data Sheet THEORY OF OPERATION The ADRF5045 requires a positive supply voltage applied to the VDD pin and a negative supply voltage applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to minimize RF coupling. The ADRF5045 incorporates a driver to perform logic functions internally and to provide the user with the advantage of a simplified control interface. The driver features two digital control input pins (V1 and V2) that control the state of the RF paths. Depending on the logic level applied to the V1 and V2 pins, one RF path is in an insertion loss state, while the other three paths are in an isolation state (see Table 5). The insertion loss path conducts the RF signal equally well in both directions between the RF throw port and the RF common port, and the isolation paths provides high loss between the RF throw ports terminated to internal 50 resistors and the insertion loss path. The ideal power-up sequence for the ADRF5045 is as follows: 1. 2. 3. 4. Connect GND. Power up VDD and VSS. Powering up VSS after VDD avoids current transients on VDD during ramp-up. Apply the digital control inputs, V1 and V2. Applying the digital control inputs before the VDD supply may inadvertently forward bias and damage the internal ESD protection structures. In such a case, use a series 1 k resistor to limit the current flowing in to the control pin. If the control pins are not driven to a valid logic state (for example, if the controller output is in a high impedance state) after VDD is powered up, it is recommended to use pull-up and pull-down resistors. Apply an RF input signal. The design is bidirectional. The RF input signal can be applied to the RFC port, while the RF throw ports are outputs, or vice versa. The RF ports are dc-coupled to 0 V, and no dc blocking is required at the RF ports when the RF line potential is equal to 0 V. The ideal power-down sequence is the reverse order of the power-up sequence. Table 5. Control Voltage Truth Table Digital Control Input V1 V2 Low Low High Low Low High High High RF1 to RFC Insertion loss (on) Isolation (off) Isolation (off) Isolation (off) RF2 to RFC Isolation (off) Insertion loss (on) Isolation (off) Isolation (off) Rev. A | Page 10 of 14 RF Paths RF3 to RFC Isolation (off) Isolation (off) Insertion loss (on) Isolation (off) RF4 to RFC Isolation (off) Isolation (off) Isolation (off) Insertion loss (on) Data Sheet ADRF5045 APPLICATIONS INFORMATION through vias as possible are arranged around transmission lines and under the exposed pad of the package. EVALUATION BOARD Figure 22 shows the top view of the ADRF5045-EVALZ, and Figure 23 shows the cross sectional view of the ADRF5045EVALZ. 16314-023 Figure 24 shows the actual ADRF5045-EVALZ with component placement. Two power supply ports are connected to the VDD and VSS test points (TP1 and TP4), control voltages are connected to the V1 and V2 test points (TP2 and TP3), and the ground reference is connected to the GND test point (TP5). Figure 22. Evaluation Board Layout, Top View W = 14mil 0.5oz Cu (0.7mil) G = 5mil 0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil) H = 8mil 16314-024 0.5oz Cu (0.7mil) Figure 24. Evaluation Board Component Placement 0.5oz Cu (0.7mil) 0.5 oz Cu (0.7mil) 16314-022 TOTAL THICKNESS 62mil RO4003 T = 0.7mil Figure 23. Evaluation Board (Cross Sectional View) The ADRF5045-EVALZ is a 4-layer evaluation board. Each copper layer is 0.7 mil (0.5 oz) and separated by dielectric materials. All RF and dc traces are routed on the top copper layer, and the inner and bottom layers are grounded planes that provide a solid ground for the RF transmission lines. The top dielectric material is 8 mil Rogers RO4003, offering optimal high frequency performance. The middle and bottom dielectric materials provide mechanical strength. The overall board thickness is 62 mil, which allows 2.4 mm RF launchers to be connected at the board edges. On the control traces (V1 and V2), a 0 resistor connects the test points to the pins on the ADRF5045. On the supply traces (VDD and VSS), a 100 pF bypass capacitor filters high frequency noise. Additionally, unpopulated components positions are available for applying extra bypass capacitors. The RF input and output ports (RFC, RF1, RF2, RF3, and RF4) are connected through 50 transmission lines to the 2.4 mm RF launchers (J1 to J5). These high frequency RF launchers are by contact and not soldered onto the board. A thru calibration line connects the unpopulated J6 and J7 launchers; this transmission line is used to estimate the loss of the PCB over the environmental conditions being evaluated. The schematic of the ADRF5045-EVALZ is shown in Figure 25. The RF transmission lines were designed using a coplanar waveguide (CPWG) model, with a trace width of 14 mil and a ground clearance of 5 mil, to have a characteristic impedance of 50 . For optimal RF and thermal grounding, as many plated Rev. A | Page 11 of 14 ADRF5045 J1 Data Sheet 1 RF2 2345 AGND 1 J2 RF1 PAD PAD 24 GND 23 RF1 22 GND 21 GND 20 RF2 19 GND 2345 1 1 V1 0 R2 0 GND GND TP5 AGND R1 TP2 TP3 TP4 V2 C7 0.1F DNI AGND C8 0.1F DNI AGND VSS AGND C2 100pF 1 TP1 1 8 7 GND GND C5 10F DNI AGND 1 GND RF3 6 AGND GND AGND C4 0.1F DNI AGND 12 5 2345 U1 ADRF5045 RFC 11 4 GND RF4 3 GND RFC 9 2 1 J3 18 GND 17 VDD 16 V1 15 V2 14 VSS 13 GND GND 10 1 VDD C1 100pF 1 AGND AGND RF4 C3 0.1F DNI AGND C6 10F DNI AGND J4 2345 AGND 1 RF3 J5 2345 1 1 THRU_CAL J6 J7 2345 DNI AGND DNI 543 2 AGND 16314-025 AGND Figure 25. ADRF5045-EVALZ Evaluation Board Schematic Table 6. Evaluation Board Components Component C1, C2 C5, C6 C3, C4, C7, C8 J1 to J7 R1, R2 TP1 to TP5 U1 PCB Default Value 100 pF 10 F 0.1 F Not applicable 0 Not applicable ADRF5045 08-042615-01 Description Capacitors, C0402 package Capacitors, C3216 package, do not install (DNI) Capacitors, C0402 package, DNI 2.4 mm end launch connector (Southwest Microwave: 1492-04A-5) Resistors, 0402 package Through-hole mount test point ADRF5045 digital attenuator, Analog Devices, Inc. Evaluation PCB, Analog Devices Rev. A | Page 12 of 14 Data Sheet ADRF5045 PROBE MATRIX BOARD Figure 26 shows the cross sectional view of the probe matrix board and Figure 27 shows the top view of the probe matrix board. Measurements were made using 535 m GSG probes at close proximity to the RFx pins. Unlike the ADRF5045-EVALZ, probing reduces reflections caused by mismatch arising from connectors, cables, and board layout, resulting in a more accurate measurement of the performance of the ADRF5045. W = 16mil 0.5oz Cu (0.7mil) G = 6mil 0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil) H = 12mil 1oz Cu (1.4mil) Figure 27. Probe Board Layout (Top View) RF traces for a through reflect line (TRL) calibration are designed on the board itself. A nonzero line length compensates for board loss at calibration. The actual board duplicates the same layout in matrix form to assemble multiple devices at once. Insertion loss and input and output return losses were measured on this probe matrix board. Isolation performance measured on the probe matrix board is limited due to signal coupling between the RF probes that are in close proximity. Therefore, RF port to port isolation was measured on the ADRF5045-EVALZ. FR4 1oz Cu (1.4mil) FR4 0.5 oz Cu (0.7mil) 16314-028 TOTAL THICKNESS 62mil RO4003 T = 0.7mil 16314-027 The probe matrix board is a 4-layer board that uses a 12 mil Rogers RO4003 as the top dielectric material. The external copper layer is 0.7 mil and the internal copper layers are 1.4 mil. The RF transmission lines were designed using a CPWG model, with a 16 mil width and a ground spacing of 6 mil, to have a characteristic impedance of 50 . Figure 26. Probe Matrix Board (Cross Sectional View) Rev. A | Page 13 of 14 ADRF5045 Data Sheet OUTLINE DIMENSIONS PIN A1 CORNER AREA 4.10 4.00 3.90 0.30 0.25 0.20 0.35 0.30 0.25 PIN 1 INDICATOR 0.30 x 0.45 24 19 1 18 2.40 BSC SQ 2.50 REF SQ 0.50 BSC TOP VIEW 13 6 7 12 BOTTOM VIEW SIDE VIEW 0.53 REF PKG-005263 0.37 0.33 0.28 FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 08-11-2016-A 0.125 BSC 0.96 MAX Figure 28. 24-Terminal Land Grid Array [LGA] (CC-24-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF5045BCCZN ADRF5045BCCZN-R7 ADRF5045-EVALZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 24-Terminal Land Grid Array [LGA] 24-Terminal Land Grid Array [LGA] Evaluation Board Z = RoHS Compliant Part. (c)2017-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16314-3/20(A) Rev. A | Page 14 of 14 Package Option CC-24-4 CC-24-4