ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER General Description Features The ICS853011C is a low skew, high performance 1-to-2 Differential-to-2.5V, 3.3V LVPECL/ECL HiPerClockSTM Fanout Buffer and a member of the HiPerClockS TM family of High Performance Clock Solutions from IDT. The ICS853011C is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS853011C ideal for those clock distribution applications demanding well defined performance and repeatability. * * * Two differential 2.5V or 3.3V LVPECL/ECL outputs * * Output frequency: >2.5GHz * * * * * Additive phase jitter, RMS: 0.16ps (typical) * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V ICS * * PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input Output skew: 15ps (maximum) Part-to-part skew: 130ps (maximum) Propagation delay: 330ps (maximum) LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment Block Diagram Q0 PCLK Pulldown nPCLK Pullup/Pulldown One differential PCLK, nPCLK input pair Q0 nQ0 Q1 nQ1 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VCC PCLK nPCLK VEE ICS853011C 8 Lead SOIC, 150MIL 3.90mm x 4.90mm x 1.37mm package body M Package Top View ICS853011C 8 Lead TSSOP, 118mil 3.0mm x 3.0mm x 0.97 package body G Package Top View IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 1 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. LVPECL/ECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL/ECL interface levels. 5 VEE Power Negative supply pin. 6 nPCLK Input Pullup/ Pulldown Inverting differential LVPECL clock input. VCC/2 default when left floating. 7 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 8 VCC Power Positive supply pin. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter RPULLUP Input Pullup Resistor 37 k RPULLDOWN Input Pulldown Resistor 75 k IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Test Conditions 2 Minimum Typical Maximum Units ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V (LVPECL mode, VEE = 0V) Negative Supply Voltage, VEE -4.6V (ECL mode, VCC = 0V) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Operating Temperature Range, TA -40C to 85C Storage Temperature, TSTG -65C to 150C Package Thermal Impedance, JA (Junction-to-Ambient) for 8 Lead SOIC 112.7C/W (0 lfpm) Package Thermal Impedance, JA (Junction-to-Ambient) for 8 Lead TSSOP 101.7C/W (0 mps) DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40C to 85C Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current Test Conditions IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 3 Minimum Typical Maximum Units 2.375 3.3 3.8 V 24 mA ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Table 3B. LVPECL DC Characteristics, VCC = 3.3V; VEE = 0V, TA = -40C to 85C -40C Symbol Parameter VOH 25C 80C Min Typ Max Min Typ Max Min Typ Max Units Output High Current; NOTE 1 2.175 2.275 2.38 2.225 2.295 2.37 2.22 2.295 2.365 V VOL Output Low Current; NOTE 1 1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63 V VPP Peak-to-Peak Input Voltage 150 800 1200 150 800 1200 150 800 1200 V VCMR Input High Voltage Common Mode Range; NOTE 2, 3 1.2 3.3 1.2 3.3 1.2 3.3 V IIH Input High Current 150 A IIL Input Low Current PCLK/nPCLK 150 150 PCLK -10 -10 -10 A nPCLK -150 -150 -150 A Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. Table 3C. LVPECL DC Characteristics, VCC = 2.5V; VEE = 0V, TA = -40C to 85C -40C Symbol Parameter VOH 25C 80C Min Typ Max Min Typ Max Min Typ Max Units Output High Current; NOTE 1 1.375 1.475 1.58 1.425 1.495 1.57 1.42 1.495 1.565 V VOL Output Low Current; NOTE 1 0.605 0.745 0.88 0.625 0.72 0.815 0.64 0.735 0.83 V VPP Peak-toPeak Input Voltage 150 800 1200 150 800 1200 150 800 1200 V VCMR Input High Voltage Common Mode Range; NOTE 2, 3 1.2 2.5 1.2 2.5 1.2 2.5 V IIH Input High Current 150 A IIL Input Low Current PCLK/nPCLK 150 150 PCLK -10 -10 -10 A nPCLK -150 -150 -150 A Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 4 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Table 3D. ECL DC Characteristics, VCC = 0V; VEE = -3.8V to -2.375V, TA = -40C to 85C -40C Symbol Parameter 25C 80C Min Typ Max Min Typ Max Min Typ Max Units VOH Output High Current; NOTE 1 -1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.08 -1.005 -0.935 V VOL Output Low Current; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V VPP Peak-toPeak Input Voltage 150 800 1200 150 800 1200 150 800 1200 V VCMR Input High Voltage Common Mode Range; NOTE 2, 3 0 VEE+1.2 0 VEE+1.2 0 V IIH Input High Current PCLK/ nPCLK 150 A Input Low Current PCLK -10 -10 -10 A IIL nPCLK -150 -150 -150 A VEE+1.2 150 150 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. AC Electrical Characteristics Table 4. AC Characteristics, VCC = 0V; VEE = -3.8V to -2.375V or, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40C to 85C -40C Symbol Parameter Min fMAX Output Frequency tPD Propagation Delay; NOTE 1 tjit Additive Phase Jitter, RMS; refer to Additive Phase Jitter section tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Part-to-Part Skew; NOTE 3, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle 20% to 80% Typ 25C Max Min Typ >2.5 170 320 80C Max Min Typ >2.5 180 0.16 330 190 0.16 Max Units >2.5 GHz 345 ps 0.16 ps 15 15 15 ps 150 150 150 ps 100 250 100 250 100 250 ps 48 52 48 52 48 52 % All parameters are measured at f 1.4GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 5 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. 0 Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.16ps (typical) -10 -20 -30 SSB Phase Noise dBc/Hz -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 10M 100M meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 1M 6 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Parameter Measurement Information 2V VCC VCC Qx SCOPE nPCLK V Cross Points PP V CMR PCLK LVPECL nQx VEE VEE -1.8V to -0.375V LVPECL Output Load AC Test Circuit nQx Differential Input Level nQx Par t 1 Qx Qx nQy nQy Par t 2 Qy Qy tsk(o) tsk(pp) Part-to-Part Skew Output Skew nPCLK nQ0, nQ1 80% 80% PCLK VSW I N G Q0, Q1 20% 20% tR nQ0, nQ1 tF Q0, Q1 tPD Output Rise/Fall Time IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Propagation Delay 7 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Parameter Measurement Information, continued nQ0, nQ1 Q0, Q1 t PW t odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input PCLK V_REF C1 0.1u nPCLK R2 1K Figure 1. Single-Ended Signal Driving Differential Input IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 8 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER LVPECL Clock Input Interface most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK/nPCLK accepts LVPECL, LVDS, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 Zo = 50 R2 50 Zo = 50 PCLK R1 100 PCLK Zo = 50 nPCLK Zo = 50 nPCLK HiPerClockS PCLK/nPCLK CML HiPerClockS PCLK/nPCLK CML Built-In Pullup Figure 2B. HiPerClockS PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver Figure 2A. HiPerClockS PCLK/nPCLK Input Driven by an Open Collector CML Driver 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 3.3V LVPECL Zo = 50 Zo = 50 C1 Zo = 50 C2 PCLK PCLK VBB Zo = 50 nPCLK PCLK/nPCLK nPCLK HiPerClockS Input LVPECL R1 84 R2 84 R5 100 - 200 R2 50 3.3V 2.5V 3.3V Zo = 50 3.3V R3 120 R1 50 Figure 2D. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple Figure 2C. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver 2.5V R6 100 - 200 C1 R4 120 PCLK Zo = 60 R5 100 PCLK VBB C2 nPCLK Zo = 50 PCLK/nPCLK LVDS Zo = 60 R1 1k nPCLK SSTL R1 120 R2 120 HiPerClockS PCLK/nPCLK R2 1k C3 0.1F Figure 2F. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVDS Driver Figure 2E. HiPerClockS PCLK/nPCLK Input Driven by an SSTL Driver IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 9 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Recommendations for Unused Output Pins Outputs: LVPECL Outputs: All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 3.3V Zo = 50 125 FOUT FIN 125 Zo = 50 Zo = 50 FOUT 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o FIN 50 Zo = 50 VCC - 2V RTT 84 Figure 3A. 3.3V LVPECL Output Termination IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 84 Figure 3B. 3.3V LVPECL Output Termination 10 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Termination for 2.5V LVPECL Outputs ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250 R3 250 50 + 50 + 50 - 50 2.5V LVPECL Driver - R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 4A. 2.5V LVPECL Driver Termination Example Figure 4B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50 + 50 - 2.5V LVPECL Driver R1 50 R2 50 Figure 4C. 2.5V LVPECL Driver Termination Example IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 11 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS53011C. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS53011C is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 24mA = 91.2mW * Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW Total Power_MAX (3.8V, with all outputs switching) = 91.2mW + 61.88mW = 153.08mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow or 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5A below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.153W * 103.3C/W = 100.8C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 5A. Thermal Resitance JA for 8 Lead SOIC, Forced Convection JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3C/W 128.5C/W 115.5C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7C/W 103.3C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Table 5B. Thermal Resitance JA for 8 Lead TSSOP, Forced Convection JA by Velocity Meters Per Second Multi-Layer PCB, JEDEC Standard Test Boards IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 0 1 2 101.7C/W 90.5C/W 89.8C/W 12 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCC Q1 VOUT RL 50 VCC - 2V Figure 5. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC - 2V. * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.935V (VCC_MAX - VOH_MAX) = 0.935V * For logic low, VOUT = VOL_MAX = VCC_MAX - 1.67V (VCC_MAX - VOL_MAX) = 1.67V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.935V)/50] * 0.935V = 19.92mW Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 13 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Reliability Information Table 6A. JA vs. Air Flow Table for an 8 Lead SOIC JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3C/W 128.5C/W 115.5C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7C/W 103.3C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Table 6B. JA vs. Air Flow Table for an 8 Lead TSSOP JA by Velocity Meters Per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 101.7C/W 90.5C/W 89.8C/W Transistor Count The transistor count for ICS853011C is: 96 Pin compatible with MC100LVEP11 and SY100EP11U Package Outline and Package Dimension Package Outline - G Suffix for 8 Lead TSSOP Table 7A. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.10 A1 0 0.15 A2 0.79 0.97 b 0.22 0.38 c 0.08 0.23 D 3.00 Basic E 4.90 Basic E1 3.00 Basic e 0.65 Basic e1 1.95 Basic L 0.40 0.80 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-187 IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 14 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Package Outline - M Suffix for 8 Lead SOIC Table 7B. Package Dimensions for 8 Lead SOIC All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 Basic H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Reference Document: JEDEC Publication 95, MS-012 IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 15 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Ordering Information Table 8. Ordering Information Part/Order Number ICS853011CM ICS853011CMT ICS853011CMLF ICS853011CMLFT ICS853011CG ICS853011CGT ICS853011CGLF ICS853011CGLFT Marking 853011C 853011C 3011CLF 3011CLF 011C 011C 11CL 11CL Package 8 Lead SOIC 8 Lead SOIC "Lead-Free" 8 Lead SOIC "Lead-Free" 8 Lead SOIC 8 Lead TSSOP 8 Lead TSSOP "Lead-Free" 8 Lead TSSOP "Lead-Free" 8 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 16 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Revision History Sheet Rev Table Page Description of Change A T8 16 Ordering Information table - added lead-free marking for TSSOP package. 6/12/07 A T7B 15 Corrected Package Dimensions Table for 8 Lead SOIC. 7/28/08 IDTTM / ICSTM 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Date 17 ICS853011CM REV. A JULY 28, 2008 ICS853011C LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER Contact Information: www.IDT.com www.IDT.com Sales Technical Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) (c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA