1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1Y
1Z
1,2EN
2Z
2Y
2A
GND
VCC
4A
4Y
4Z
3,4EN
3Z
3Y
3A
NPACKAGE
(TOP VIEW) logic diagram(positivelogic)
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
4A
3A
2A
1A 1
7
9
15
2
3
6
5
10
11
14
13
1,2EN 4
3,4EN 12
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
4A
3A
2A
1A 1
9
11
19
2
4
8
6
12
14
18
16
1,2EN 5
3,4EN 15
logicdiagram(positivelogic)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1A
1Y
NC
1Z
1,2EN
2Z
NC
2Y
2A
GND
VCC
4A
4Y
NC
4Z
3,4EN
3Z
NC
3Y
3A
20-DWPACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1Y
1Z
1,2EN
2Z
2Y
2A
GND
VCC
4A
4Y
4Z
3,4EN
3Z
3Y
3A
16-DWPACKAGE
(TOP VIEW)
SN65LBC174A
SN75LBC174A
www.ti.com
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
Check for Samples: SN65LBC174A SN75LBC174A
1FEATURES • Output ESD Protection: 12 kV
2• Designed for TIA/EIA-485, TIA/EIA-422 and • Driver Positive- and Negative-Current Limiting
ISO 8482 Applications • Power-Up and Power-Down Glitch-Free for
• Signaling Rates (1) up to 30 Mbps Line Insertion Applications
• Propagation Delay Times < 11 ns • Thermal Shutdown Protection
• Low Standby Power Consumption 1.5-mA Max • Industry Standard Pin-Out, Compatible With
SN75174, MC3487, DS96174, LTC487, and
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units MAX3042
bps (bits per second).
DESCRIPTION
The SN65LBC174A and SN75LBC174A are quadruple differential line drivers with 3-state outputs, designed for
TIA/EIA-485 (RS-485), TIA/EIA-422 (RS-422), and ISO 8482 applications.
These devices are optimized for balanced multipoint bus transmission at signaling rates up to 30 million bits per
second. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate
and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise
coupling to the environment.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2LinBiCMOS is a registered trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LBC174A
SN75LBC174A
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
Each driver features current limiting and thermal-shutdown circuitry making it suitable for high-speed multipoint
applications in noisy environments. These devices are designed using LinBiCMOS®, facilitating low power
consumption and robustness.
The two EN inputs provide pair-wise driver enabling, or can be externally tied together to provide enable control
of all four drivers with one signal. When disabled or powered off, the driver outputs present a high-impedance to
the bus for reduced system loading.
The SN75LBC174A is characterized for operation over the temperature range of 0°C to 70°C. The
SN65LBC174A is characterized for operation over the temperature range of –40°C to 85°C.
Table 1. AVAILABLE OPTIONS
PACKAGE
16-PIN 20-PIN 16-PIN
TAPLASTIC SMALL OUTLINE (1) PLASTIC SMALL OUTLINE (1) PLASTIC THROUGH-HOLE
(JEDEC MS-013) (JEDEC MS-013) (JEDEC MS-001)
SN75LBC174A16DW SN75LBC174ADW SN75LBC174AN
0°C to 70°C MARKED AS 75LBC174A
SN65LBC174A16DW SN65LBC174DW SN65LBC174AN
–40°C to 85°C MARKED AS 65LBC174A
(1) Add R suffix for taped and reeled version.
Table 2. FUNCTION TABLE (EACH DRIVER)(1)
INPUT ENABLE OUTPUT OUTPUT
A EN Y Z
L H L H
H H H L
OPEN H H L
L OPEN L H
H OPEN H L
OPEN OPEN H L
X L Z Z
(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off)
2Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65LBC174A SN75LBC174A
SN65LBC174A
SN75LBC174A
www.ti.com
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE / UNIT
Supply voltage range, VCC (2) –0.3 V to 6 V
Voltage range at any bus (DC) –10 V to 15 V
Voltage range at any bus (transient pulse through 100 Ω, see Figure 8) –30 V to 30 V
Input voltage range at any A or EN terminal, VI–0.5 V to VCC + 0.5 V
Y, Z, and GND ±12 kV
Human body model (3)
Electrostatic All pins ±5 kV
discharge Charged-device model (4) All pins ±1 kV
Storage temperature range, Tstg –65°C to 150°C
Continuous power dissipation See Dissipation Rating Table
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to GND.
(3) Tested in accordance with JEDEC standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC standard 22, Test Method C101.
Table 3. DISSIPATION RATING TABLE
JEDEC BOARD TA≤25°C DERATING FACTOR (2) TA= 70°C TA= 85°C
PACKAGE (1) MODEL POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING
LOW K 1200 mW 9.6 mW/°C 769 mW 625 mW
16 DW HIGH K 2240 mW 17.9 mW/°C 1434 mW 1165 mW
LOW K 1483 mW 11.86 mW/°C 949 mW 771 mW
20 DW HIGH K 2753 mW 22 mW/°C 1762 mW 1432 mW
16 N LOW K 1150 mW 9.2 mW/°C 736 mW 598 mW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Voltage at any bus terminal Y, Z –7 12 V
High-level input voltage, VIH 2 VCC
A, EN V
Low-level input voltage, VIL 0 0.8
Output current –60 60 mA
SN75LBC174A 0 70
Operating free-air °C
temperature, TASN65LBC174A –40 85
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN65LBC174A SN75LBC174A
SN65LBC174A
SN75LBC174A
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VIK Input clamp voltage II= -18 mA –1.5 –0.77 V
VOOpen-circuit output voltage Y or Z, No load 0 VCC V
No load (open circuit) 3 VCC
Steady-state differential output voltage
|VOD(SS)| RL= 54 Ω, See Figure 1 1 1.6 2.5 V
magnitude(2) With common-mode loading, See Figure 2 1 1.6 2.5
Change in steady-state differential
ΔVOD(SS) See Figure 1 –0.1 0.1 V
output voltage between logic states
Steady-state common-mode output
VOC(SS) See Figure 3 2 2.4 2.8 V
voltage
Change in steady-state common-mode
ΔVOC(SS) See Figure 3 –0.02 0.02 V
output voltage between logic states
IIInput current A, EN –50 50 μA
VI= 0 V
IOS Short-circuit output current –200 200 mA
VI= VCC
VTEST = -7 V to 12 V, See
Figure 7
IOZ High-impedance-state output current EN at 0 V –50 50 μA
IO(OFF) Output current with power off VCC = 0 V –10 10
All drivers enabled 23
ICC Supply current VI= 0 V or VCC, No load mA
All drivers disabled 1.5
A inputs 13 pF
CIN Input Capacitance EN inputs 21 pF
(1) All typical values are at VCC = 5 V and 25°C.
(2) The minimum VOD may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the
possibly lower output signal into account in determining the maximum signal transmission distance.
SWITCHING CHARACTERISTICS
over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high level output 5.5 8 11 ns
tPHL Propagation delay time, high-to-low level output 5.5 8 11 ns
trDifferential output voltage rise time 3 7.5 11 ns
tfDifferential output voltage fall time 3 7.5 11 ns
RL= 54 Ω, CL= 50 pF,
See Figure 4 0.6 2
tsk(p) Pulse skew |tPLH – tPHL| ns
0.6 2
tsk(o) Output skew(1) 2 ns
tsk(pp) Part-to-part skew(2) 3 ns
tPZH Propagation delay time, high-impedance-to-high-level output 25 ns
See Figure 5
tPHZ Propagation delay time, high-level-output-to-high impedance 25 ns
tPZL Propagation delay time, high-impedance-to-low-level output 30 ns
See Figure 6
tPLZ Propagation delay time, low-level-output-to-high impedance 20 ns
(1) Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected
together.
(2) Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices
when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical
packages and test circuits.
4Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65LBC174A SN75LBC174A
GND
VI
AIOZ
IOY
Y
ZVOD VOY
II
VOZ
54 Ω
375 Ω
VTEST = –7 V to 12 V
Y
ZVOD
Input 60 Ω375 Ω
VI
A
VTEST
Y
ZVOC
27 Ω
A
50 Ω
Signal
Generator†CL = 50 pF‡
27 Ω
†PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
‡Includes probe and jig capacitance
SN65LBC174A
SN75LBC174A
www.ti.com
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009
PARAMETER MEASUREMENT INFORMATION
Figure 1. Test Circuit, VOD Without Common-Mode Loading
Figure 2. Test Circuit, VOD With Common-Mode Loading
Figure 3. VOC Test Circuit
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN65LBC174A SN75LBC174A
Y
ZVOD
RL = 54 Ω
A
50 Ω
Signal
Generator†
CL = 50 pF‡
90%
Output
0 V
10%
tf
≈ –1.5 V
≈ 1.5 V
tr
Input 0 V
3 V
tPHL
1.5 V
tPLH
†PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
‡Includes probe and jig capacitance
SN65LBC174A
SN75LBC174A
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Output Switching Test Circuit and Waveforms
6Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65LBC174A SN75LBC174A
S1
A
50 Ω
Signal
Generator†
Output
2.3 V
Input 0 V
3 V
1.5 V
tPZH 0.5 V
0 V
VOH
tPHZ
3 V or 0 V w
Input
RL = 110 ΩCL = 50 pF‡
Output
EN
Z
Y
†PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
‡Includes probe and jig capacitance
§3 V if testing Y output, 0 V if testing Z output
SN65LBC174A
SN75LBC174A
www.ti.com
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 5. Enable Timing Test Circuit and Waveforms, tPZH and tPHZ
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN65LBC174A SN75LBC174A
S1
A
Output
2.3 V
Input 0 V
3 V
1.5 V
tPZL
0.5 V
5 V
VOL
tPLZ
0 V or 3 V w
RL = 110 Ω
CL = 50 pF‡
Output
5 V
50 Ω
Signal
Generator†
Input
EN
Z
Y
†PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
‡Includes probe and jig capacitance
§3 V if testing Y output, 0 V if testing Z output
SN65LBC174A
SN75LBC174A
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. Enable Timing Test Circuit and Waveforms, tPZL and tPLZ
8Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65LBC174A SN75LBC174A
Voltage Source
VTEST = –7 V to 12 V
Slew Rate ≤ 1.2 V/µs
VI
VTEST
IO
Y
Z
VCC
A or EN Input
1 kΩ
9 V
Input
100 kΩ
VCC
Output
16 V
Y or Z Output
16 V
20 V
17 V
16 V
16 V
SN65LBC174A
SN75LBC174A
www.ti.com
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 7. Test Circuit, Short-Circuit Output Current
Figure 8. Test Circuit Waveform, Transient Overvoltage Test
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN65LBC174A SN75LBC174A
V =5.25V
CC
V =5V
CC
V =4.75V
CC
I OutputCurrent mA
O- -
V DifferentialOutputVoltage V
OD - -
80
3.5
100
3
2
4
1
2.5
0.5
0
1.5
0 20 40 60
V =5.25V
CC
V =5V
CC
V =4.75V
CC
T Free-AirTemperature C
A- -
o
V DifferentialOutputVoltage V
OD - -
80 100
2
1
2.5
0.5
0
1.5
-60 0 20 60-40 -20 40
R =54
C =50pF
(EachChannel)
L
L
W
SignalingRate Mbps-
I SupplyCurrent(FourChannels) mA
CC - -
1
142
10 100
140
136
144
132
138
130
128
134
V =5.25V
CC
V =4.75V
CC
T Free- AirTemperature C
A-
o
-
PropigationDelayTime ns-
-40
8
-20 0
7.5
6.5
8.5
5.5
7
5
6
40 60 80
20
SN65LBC174A
SN75LBC174A
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009
www.ti.com
TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE DIFFERENTIAL OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT FREE-AIR TEMPERATURE
Figure 9. Figure 10.
PROPAGATION DELAY TIME SUPPLY CURRENT (FOUR CHANNELS)
vs vs
FREE-AIR TEMPERATURE SIGNALING RATE
Figure 11. Figure 12.
10 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65LBC174A SN75LBC174A
RL = 54 Ω
CL = 50 pF
V SupplyVoltage V
CC - -
V DifferentialOutputVoltage V
OD - -
5.5 6
2.5
1.5
3
0.5
0
2
0 2.5 3.5 4.50.5 1 4
R =54
LW
1
1.5 2 3 5
SN65LBC174A
SN75LBC174A
www.ti.com
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE EYE PATTERN, PSEUDORANDOM DATA AT+ 30 Mbps
Figure 13. Figure 14.
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN65LBC174A SN75LBC174A
TMS320F243
DSP
(Controller)
SPISIMO
SN65LBC174A SN65LBC175A TMS320F241
DSP
(Embedded
Application)
SPISIMO
IOPA1
SPISTE SPISTE
SPICLK
IOPA0
IOPA1
(Enable)
IOPA0
(Handshake
/Status)
SPICLK
SPISOMI SPISOMI
IOPA2
(Enable) IOPA2
SN65LBC174A
SN75LBC174A
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009
www.ti.com
APPLICATION INFORMATION
Figure 15. Typical Application Circuit, DSP-to-DSP Link via Serial Peripheral Interface
REVISION HISTORY
Changes from Original (October 2000) to Revision A Page
• Changed multiple items throught the data sheet. ................................................................................................................. 1
Changes from Revision A (February 2001) to Revision B Page
• Changed DW Package appearance ..................................................................................................................................... 1
• Added Figure 13 ................................................................................................................................................................. 11
Changes from Revision B (June 2001) to Revision C Page
• Changed Features bullet From: Output ESD Protection Exceeds 13 kV To: Output ESD Protection: 11 kV ...................... 1
• Changed Features bullet for Industry Standard From: Compatible With SN75174, MC3487, and DS96174 To:
Compatible With SN75174, MC3487, DS96174, LTC487, and MAX3042 ........................................................................... 1
Changes from Revision C (May 2003) to Revision D Page
• Changed the AVAILABLE OPTIONS table ........................................................................................................................... 2
• Changed Electrostatic discharge-Human body model-Y, Z, and GND From: 13kV To: 11kV ............................................. 3
• Changed the DISSIPATION RATING TABLE ...................................................................................................................... 3
12 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65LBC174A SN75LBC174A
SN65LBC174A
SN75LBC174A
www.ti.com
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009
Changes from Revision D (June 2008) to Revision E Page
• Changed Features bullet From: Output ESD Protection Exceeds 11 kV To: Output ESD Protection: 12 kV ...................... 1
• Changed Electrostatic discharge-Human body model-Y, Z, and GND From: 11kV To: 12kV ............................................. 3
• From: A, G, G To: A, EN ....................................................................................................................................................... 4
Changes from Revision E (July 2008) to Revision F Page
• Changed FUNCTION TABLE header From: ENABLE G To: ENABLE EN .......................................................................... 2
• Added CIN - Input Capacitance to the Electrical Characteristics table .................................................................................. 4
• Changed the location of the EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAM ............................................. 9
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN65LBC174A SN75LBC174A
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LBC174A16DW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC174A16DWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC174A16DWR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC174A16DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC174ADW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC174ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC174ADWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC174ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC174AN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPD N / A for Pkg Type
SN75LBC174A16DW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC174A16DWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC174A16DWR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC174A16DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC174ADW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC174ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC174ADWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC174ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC174AN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPD N / A for Pkg Type
SN75LBC174ANE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPD N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
PACKAGE OPTION ADDENDUM
www.ti.com 23-Oct-2009
Addendum-Page 1
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65LBC174A :
•Enhanced Product: SN65LBC174A-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 23-Oct-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LBC174A16DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
SN65LBC174ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN75LBC174A16DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LBC174A16DWR SOIC DW 16 2000 367.0 367.0 38.0
SN65LBC174ADWR SOIC DW 20 2000 367.0 367.0 45.0
SN75LBC174A16DWR SOIC DW 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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