This is information on a product in full production.
April 2019 DS12110 Rev 7 1/357
STM32H742xI/G STM32H743xI/G
32-bit Arm
®
Cortex
®
-M7 480MHz MCUs, up to 2MB Flash,
up to 1MB RAM, 46 com. and analog interfaces
Datasheet - production data
Features
Core
•32-bit Arm® Cortex®-M7 core with double-
precision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache; frequency
up to 480 MHz, MPU, 1027 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
Memories
•Up to 2 Mbytes of Flash memory with read-
while-write support
•Up to 1 Mbyte of RAM: 192 Kbytes of TCM
RAM (inc. 64 Kbytes of ITCM RAM +
128 Kbytes of DTCM RAM for time critical
routines), Up to 864 Kbytes of user SRAM, and
4 Kbytes of SRAM in Backup domain
•Dual mode Quad-SPI memory interface
running up to 133 MHz
•Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND Flash
memory clocked up to 100 MHz in
Synchronous mode
•CRC calculation unit
Security
•ROP, PC-ROP, active tamper
General-purpose input/outputs
•Up to 168 I/O ports with interrupt capability
Reset and power management
•3 separate power domains which can be
independently clock-gated or switched off:
– D1: high-performance capabilities
– D2: communication peripherals and timers
– D3: reset/clock control/power management
•1.62 to 3.6 V application supply and I/Os
•POR, PDR, PVD and BOR
•Dedicated USB power embedding a 3.3 V
internal regulator to supply the internal PHYs
•Embedded regulator (LDO) with configurable
scalable output to supply the digital circuitry
•Voltage scaling in Run and Stop mode (6
configurable ranges)
•Backup regulator (~0.9 V)
•Voltage reference for analog peripheral/VREF+
•Low-power modes: Sleep, Stop, Standby and
VBAT supporting battery charging
Low-power consumption
•VBAT battery operating mode with charging
capability
•CPU and domain power state monitoring pins
•2.95 µA in Standby mode (Backup SRAM OFF,
RTC/LSE ON)
Clock management
•Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 32 kHz LSI
•External oscillators: 4-48 MHz HSE,
32.768 kHz LSE
•3× PLLs (1 for the system clock, 2 for kernel
clocks) with Fractional mode
FBGA
LQFP100
(14 x 14 mm)
LQFP144
(20 x 20 mm)
LQFP176
(24 x 24 mm)
LQFP208
(28 x 28 mm)
UFBGA169
(7 x 7 mm)
UFBGA176+25
(10 x 10 mm)
FBGA
TFBGA100
(8 x 8 mm)(1)
TFBGA240+25
(14 x 14 mm)
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STM32H742xI/G STM32H743xI/G
2/357 DS12110 Rev 7
Interconnect matrix
•3 bus matrices (1 AXI and 2 AHB)
•Bridges (5× AHB2-APB, 2× AXI2-AHB)
4 DMA controllers to unload the CPU
•1× high-speed master direct memory access
controller (MDMA) with linked list support
•2× dual-port DMAs with FIFO
•1× basic DMA with request router capabilities
Up to 35 communication peripherals
•4× I2Cs FM+ interfaces (SMBus/PMBus)
•4× USARTs/4x UARTs (ISO7816 interface,
LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
•6× SPIs, 3 with muxed duplex I2S audio class
accuracy via internal audio PLL or external
clock, 1x I2S in LP domain (up to 150 MHz)
•4x SAIs (serial audio interface)
•SPDIFRX interface
•SWPMI single-wire protocol master I/F
•MDIO Slave interface
•2× SD/SDIO/MMC interfaces (up to 125 MHz)
•2× CAN controllers: 2 with CAN FD, 1 with
time-triggered CAN (TT-CAN)
•2× USB OTG interfaces (1FS, 1HS/FS) crystal-
less solution with LPM and BCD
•Ethernet MAC interface with DMA controller
•HDMI-CEC
•8- to 14-bit camera interface (up to 80 MHz)
11 analog peripherals
•3× ADCs with 16-bit max. resolution (up to 36
channels, up to 3.6 MSPS)
•1× temperature sensor
•2× 12-bit D/A converters (1 MHz)
•2× ultra-low-power comparators
•2× operational amplifiers (7.3 MHz bandwidth)
•1× digital filters for sigma delta modulator
(DFSDM) with 8 channels/4 filters
Graphics
•LCD-TFT controller up to XGA resolution
•Chrom-ART graphical hardware Accelerator™
(DMA2D) to reduce CPU load
•Hardware JPEG Codec
Up to 22 timers and watchdogs
•1× high-resolution timer (2.1 ns max
resolution)
•2× 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input (up to 240 MHz)
•2× 16-bit advanced motor control timers (up to
240 MHz)
•10× 16-bit general-purpose timers (up to
240 MHz)
•5× 16-bit low-power timers (up to 240 MHz)
•2× watchdogs (independent and window)
•1× SysTick timer
•RTC with sub-second accuracy and hardware
calendar
Debug mode
•SWD & JTAG interfaces
•4-Kbyte Embedded Trace Buffer
True random number generators (3
oscillators each)
96-bit unique ID
All packages are ECOPACK®2 compliant
Table 1. Device summary
Reference Part number
STM32H742xI/G
STM32H742VI, STM32H742ZI,
STM32H742II, STM32H742BI,
STM32H742XI, STM32H742AI,
STM32H742VG, STM32H742ZG,
STM32H742IG, STM32H742BG,
STM32H742XG, STM32H742AG
STM32H743xI/G
STM32H743VI, STM32H743ZI,
STM32H743II, STM32H743BI,
STM32H743XI, STM32H743AI,
STM32H743VG, STM32H743ZG,
STM32H743IG, STM32H743BG,
STM32H743XG, STM32H743AG
DS12110 Rev 7 3/357
STM32H742xI/G STM32H743xI/G Contents
7
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.6 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.7 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.7.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.7.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.10 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 35
3.13 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 35
3.14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 35
3.15 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.16 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.17 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.18 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.20 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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3.21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.22 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.23 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 39
3.24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.25 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.26 JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.27 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.28 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.28.1 High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.28.2 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.28.3 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.28.4 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.28.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 45
3.28.6 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.28.7 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.28.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.29 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 46
3.30 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.31 Universal synchronous/asynchronous receiver transmitter (USART) . . . 47
3.32 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 48
3.33 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 49
3.34 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.35 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.36 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 50
3.37 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 51
3.38 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 51
3.39 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 51
3.40 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 52
3.41 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 52
3.42 High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.43 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6 Electrical characteristics (rev Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 109
6.3.4 Embedded reset and power control block characteristics . . . . . . . . . . 110
6.3.5 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 137
6.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.18 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
6.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.3.20 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.3.21 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 178
6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.3.24 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Contents STM32H742xI/G STM32H743xI/G
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6.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.3.27 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 183
6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 186
6.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 189
6.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 190
6.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.3.32 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.3.33 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 207
7 Electrical characteristics (rev V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
7.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
7.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 217
7.3.4 Embedded reset and power control block characteristics . . . . . . . . . . 218
7.3.5 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 232
7.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 233
7.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 237
7.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
7.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
7.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
7.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 245
7.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
7.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
7.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
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7.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
7.3.18 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
7.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
7.3.20 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
7.3.21 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
7.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 291
7.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
7.3.24 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
7.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
7.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
7.3.27 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 295
7.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 297
7.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 300
7.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 301
7.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
7.3.32 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
8.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
8.2 TFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
8.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
8.4 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
8.5 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
8.6 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
8.7 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
8.8 TFBGA240+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
8.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
8.9.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32H742xI/G and STM32H743xI/G features and peripheral counts. . . . . . . . . . . . . . . 19
Table 3. System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 4. DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 6. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 7. Flash memory and SRAM memory mapping for STM32H742xI/G . . . . . . . . . . . . . . . . . . . 54
Table 8. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 9. Pin/ball definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 10. Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 11. Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 12. Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 13. Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 14. Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 15. Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 16. Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 17. Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 18. Port I alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 19. Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 20. Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 25. VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 26. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 109
Table 27. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 28. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 29. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 30. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 31. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 32. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 33. Typical consumption in Run mode and corresponding performance
versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 34. Typical current consumption batch acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 35. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 115
Table 36. Typical and maximum current consumption in Stop mode, regulator ON. . . . . . . . . . . . . 116
Table 37. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 116
Table 38. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 117
Table 39. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 40. Peripheral current consumption in Stop, Standby and VBAT mode . . . . . . . . . . . . . . . . . 124
Table 41. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 42. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 43. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 44. 4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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12
Table 45. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 46. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 47. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 48. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 49. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 50. PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 51. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 52. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 53. Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 135
Table 54. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 55. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 56. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 57. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 58. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 59. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 60. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 61. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 141
Table 62. Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 142
Table 63. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 64. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 65. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 66. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 149
Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 149
Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 150
Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 151
Table 70. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 71. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 152
Table 72. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 73. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 154
Table 74. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 75. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 76. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 77. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 78. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 79. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 80. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 81. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 82. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 83. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 84. QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 85. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 86. Dynamics characteristics: Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 87. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 88. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 89. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 90. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 91. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 92. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 93. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 94. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 95. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 96. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
List of tables STM32H742xI/G STM32H743xI/G
10/357 DS12110 Rev 7
Table 97. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 98. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 99. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 100. DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 101. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 102. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 103. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 104. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 105. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 106. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 107. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 108. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 109. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 110. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 201
Table 111. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 202
Table 112. USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 113. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 114. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 115. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 116. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 117. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 118. Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 119. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 120. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 121. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 122. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 123. Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 124. VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 125. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 217
Table 126. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 127. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 128. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 129. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 130. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 131. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 132. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 133. Typical and maximum current consumption in Stop, LDO regulator ON . . . . . . . . . . . . . 223
Table 134. Typical and maximum current consumption in Sleep mode, LDO regulator. . . . . . . . . . . 224
Table 135. Typical and maximum current consumption in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 136. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 225
Table 137. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 138. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 139. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 140. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 141. 4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 142. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
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Table 143. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 144. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 145. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 146. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 147. PLL characteristics (wide VCO frequency range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 148. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 149. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 150. Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 242
Table 151. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 152. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 153. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 154. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 155. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 156. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 157. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 158. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 249
Table 159. Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 250
Table 160. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 161. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 162. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 163. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 256
Table 164. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 256
Table 165. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 258
Table 166. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 258
Table 167. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 168. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 260
Table 169. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 170. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 261
Table 171. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 172. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 173. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 174. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 175. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Table 176. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Table 177. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Table 178. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Table 179. SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 180. LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 181. QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 182. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 183. Delay Block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 184. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 185. Minimum sampling time vs RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 186. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 187. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Table 188. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 189. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 190. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 191. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 192. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 193. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 194. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
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Table 195. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 196. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 197. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 198. DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Table 199. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Table 200. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 201. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 202. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 203. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 204. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Table 205. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Table 206. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Table 207. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Table 208. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Table 209. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 315
Table 210. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 316
Table 211. Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Table 212. Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 319
Table 213. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 320
Table 214. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 320
Table 215. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Table 216. Dynamics SWD characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Table 217. LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Table 218. TFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Table 219. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 328
Table 220. LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Table 221. UFBGA169 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Table 222. LQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Table 223. LQFP208 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Table 224. UFBGA176+25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Table 225. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 345
Table 226. TFBG240+25 ball package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Table 227. TFBGA240+25 recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . 349
Table 228. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Table 229. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
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List of figures
Figure 1. STM32H742xI/G block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 2. STM32H743xI/G block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 3. Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 4. STM32H743xI/G bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 5. LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 6. TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 7. LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 8. UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 9. LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 10. UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 11. LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 12. TFBGA240+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 13. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 14. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 15. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 16. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 17. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 19. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 20. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 21. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 22. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 148
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 150
Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 28. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 29. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 31. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 32. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 33. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 34. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 162
Figure 35. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 163
Figure 36. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 37. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 38. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 39. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 40. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 41. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 42. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 174
Figure 43. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 174
Figure 44. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 45. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 46. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 47. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 48. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
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Figure 49. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 50. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 51. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 52. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 53. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 54. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 55. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 56. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 57. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 58. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 59. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 60. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 61. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 62. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 63. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 64. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 65. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 66. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 67. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 68. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 69. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 70. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 71. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 72. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 73. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 74. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 75. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 76. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 77. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 255
Figure 78. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 257
Figure 79. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 80. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 81. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 82. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 266
Figure 83. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 84. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 85. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 86. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 271
Figure 87. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 272
Figure 88. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 89. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Figure 90. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Figure 91. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Figure 92. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 93. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 94. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 286
Figure 95. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 286
Figure 96. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 97. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 98. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Figure 99. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 100. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
DS12110 Rev 7 15/357
STM32H742xI/G STM32H743xI/G List of figures
15
Figure 101. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 102. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 103. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 104. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 105. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 106. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Figure 107. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Figure 108. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 109. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 110. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Figure 111. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 112. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 113. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 114. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 115. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Figure 116. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Figure 117. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 118. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Figure 119. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Figure 120. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Figure 121. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 122. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 123. TFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Figure 124. TFBGA100 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Figure 125. TFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Figure 126. LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Figure 127. LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 128. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Figure 129. UFBGA169 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Figure 130. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Figure 131. LQFP176 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Figure 132. LQFP176 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Figure 133. LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Figure 134. LQFP208 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Figure 135. LQFP208 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 136. LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Figure 137. UFBGA176+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Figure 138. UFBGA176+25 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 139. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Figure 140. TFBGA240+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Figure 141. TFBGA240+25 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Figure 142. TFBGA240+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Introduction STM32H742xI/G STM32H743xI/G
16/357 DS12110 Rev 7
1 Introduction
This document provides information on STM32H742xI/G STM32H743xI/G microcontrollers,
such as description, functional overview, pin assignment and definition, electrical
characteristics, packaging, and ordering information.
This document should be read in conjunction with the STM32H742xI/G STM32H743xI/G
reference manual (RM0433), available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core, please refer to the Cortex®-M7 Technical
Reference Manual, available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS12110 Rev 7 17/357
STM32H742xI/G STM32H743xI/G Description
54
2 Description
STM32H742xI/G and STM32H743xI/G devices are based on the high-performance Arm®
Cortex®-M7 32-bit RISC core operating at up to 480 MHz. The Cortex® -M7 core features a
floating point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and
single-precision data-processing instructions and data types. STM32H742xI/G and
STM32H743xI/G devices support a full set of DSP instructions and a memory protection unit
(MPU) to enhance application security.
STM32H742xI/G and STM32H743xI/G devices incorporate high-speed embedded
memories with a dual-bank Flash memory of up to 2 Mbytes, up to 1 Mbyte of RAM
(including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of
backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected
to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect
supporting internal and external memory access.
All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power
RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor
control, five low-power timers, a true random number generator (RNG). The devices support
four digital filters for external sigma-delta modulators (DFSDM). They also feature standard
and advanced communication interfaces.
•Standard peripherals
–Four I
2Cs
– Four USARTs, four UARTs and one LPUART
– Six SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization.
– Four SAI serial audio interfaces
– One SPDIFRX interface
– One SWPMI (Single Wire Protocol Master Interface)
– Management Data Input/Output (MDIO) slaves
– Two SDMMC interfaces
– A USB OTG full-speed and a USB OTG high-speed interface with full-speed
capability (with the ULPI)
– One FDCAN plus one TT-FDCAN interface
– An Ethernet interface
– Chrom-ART Accelerator™
– HDMI-CEC
•Advanced peripherals including
– A flexible memory control (FMC) interface
– A Quad-SPI Flash memory interface
– A camera interface for CMOS sensors
– An LCD-TFT display controller (only available on STM32H743xI/G)
– A JPEG hardware compressor/decompressor (only available on STM32H743xI/G)
Refer to Table 2: STM32H742xI/G and STM32H743xI/G features and peripheral counts for
the list of peripherals available on each part number.
Description STM32H742xI/G STM32H743xI/G
18/357 DS12110 Rev 7
STM32H742xI/G and STM32H743xI/G devices operate in the –40 to +85 °C temperature
range from a 1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by
using an external power supervisor (see Section 3.5.2: Power supply supervisor) and
connecting the PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V
with the embedded power voltage detector enabled.
Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages
except LQFP100 to allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H742xI/G and STM32H743xI/G devices are offered in 8 packages ranging from 100
pins to 240 pins/balls. The set of included peripherals changes with the device chosen.
These features make STM32H742xI/G and STM32H743xI/G microcontrollers suitable for a
wide range of applications:
•Motor drive and application control
•Medical equipment
•Industrial applications: PLC, inverters, circuit breakers
•Printers, and scanners
•Alarm systems, video intercom, and HVAC
•Home audio appliances
•Mobile applications, Internet of Things
•Wearable devices: smart watches.
Figure 1 and Figure 2 shows the device block diagrams.
STM32H742xI/G STM32H743xI/G Description
DS12110 Rev 7 19/357
Table 2. STM32H742xI/G and STM32H743xI/G features and peripheral counts
Peripherals
STM32H 742VG
STM32H742ZG
STM32H742AG
STM32H742IG
STM32H742BG
STM32H742XG
STM32H743VG
STM32H743ZG
STM32H743AG
STM32H743IG
STM32H743BG
STM32H743XG
STM32H 742VI
STM32H742ZI
STM32H742AI
STM32H742II
STM32H742BI
STM32H742XI
STM32H743VI
STM32H743ZI
STM32H743AI
STM32H743II
STM32H743BI
STM32H743XI
Flash memory in Kbytes 2 x 512 Kbytes 2 x 1 Mbyte
SRAM in
Kbytes
SRAM
mapped onto
AXI bus
384 512 384 512
SRAM1
(D2 domain) 32 128 32 128
SRAM2
(D2 domain) 16 128 16 128
SRAM3
(D2 domain) -32-32
SRAM4
(D3 domain) 64 64 64 64
TCM RAM
in Kbytes
ITCM RAM
(instruction) 64 64 64 64
DTCM RAM
(data) 128 128 128 128
Backup SRAM (Kbytes) 4
FMC Yes
GPIOs 82 114 131 140 168 82 114 131 140 168 82 114 131 140 168 82 114 131 140 168
Quad-SPI Yes
Ethernet Yes
Description STM32H742xI/G STM32H743xI/G
20/357 DS12110 Rev 7
Timers
High-
resolution 1
General-
purpose 10
Advanced-
control (PWM) 2
Basic 2
Low-power 5
Random number generator Yes
Communi-
cation
interfaces
SPI / I2S6/3(1)
I2C 4
USART/
UART/
LPUART
4/4
/1
SAI 4
SPDIFRX 4 inputs
SWPMI Yes
MDIO Yes
SDMMC 2
FDCAN/TT-
FDCAN 1/1
USB OTG_FS Yes
USB
OTG_HS Yes
Ethernet and camera
interface Yes
Table 2. STM32H742xI/G and STM32H743xI/G features and peripheral counts (continued)
Peripherals
STM32H 742VG
STM32H742ZG
STM32H742AG
STM32H742IG
STM32H742BG
STM32H742XG
STM32H743VG
STM32H743ZG
STM32H743AG
STM32H743IG
STM32H743BG
STM32H743XG
STM32H 742VI
STM32H742ZI
STM32H742AI
STM32H742II
STM32H742BI
STM32H742XI
STM32H743VI
STM32H743ZI
STM32H743AI
STM32H743II
STM32H743BI
STM32H743XI
STM32H742xI/G STM32H743xI/G Description
DS12110 Rev 7 21/357
LCD-TFT - Yes - Yes
JPE G Codec - Yes - Yes
Chrom-ART Accelerator™
(DMA2D) Yes
16-bit ADCs
Number of channels
3
Up to 36
12-bit DAC
Number of channels
Yes
2
Comparators 2
Operational amplifiers 2
DFSDM Yes
Maximum CPU frequency 480MHz(2)(3)/400 MHz
Operating voltage
1.71
to
3.6
V(4)
1.62 to 3.6 V(5)
1.71
to
3.6
V(4)
1.62 to 3.6 V(5)
1.71
to
3.6
V(4)
1.62 to 3.6 V(5)
1.71
to
3.6
V(4)
1.62 to 3.6 V(5)
Operating temperatures
Ambient temperatures: –40 up to +85 °C(6)
Junction temperature: –40 to + 125 °C
Package
LQFP100
TFBGA100(7)
LQFP144
UFBGA169(7)
LQFP176
UFBGA176+25
LQFP208
TFBGA240+25
LQFP100
TFBGA100(7)
LQFP144
UFBGA169(7)
LQFP176
UFBGA176+25
LQFP208
TFBGA240+25
LQFP100
TFBGA100(7)
LQFP144
UFBGA169(7)
LQFP176
UFBGA176+25
LQFP208
TFBGA240+25
LQFP100
TFBGA100(7)
LQFP144
UFBGA169(7)
LQFP176
UFBGA176+25
LQFP208
TFBGA240+25
1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
2. The maximum CPU frequency of 480 MHz can be obtained on devices revision V.
3. The product junction temperature must be kept within the –40 to +105 °C temperature range.
Table 2. STM32H742xI/G and STM32H743xI/G features and peripheral counts (continued)
Peripherals
STM32H 742VG
STM32H742ZG
STM32H742AG
STM32H742IG
STM32H742BG
STM32H742XG
STM32H743VG
STM32H743ZG
STM32H743AG
STM32H743IG
STM32H743BG
STM32H743XG
STM32H 742VI
STM32H742ZI
STM32H742AI
STM32H742II
STM32H742BI
STM32H742XI
STM32H743VI
STM32H743ZI
STM32H743AI
STM32H743II
STM32H743BI
STM32H743XI
Description STM32H742xI/G STM32H743xI/G
22/357 DS12110 Rev 7
4. Since the LQFP100 package does not feature the PDR_ON pin (tied internally to VDD), the minimum VDD value for this package is 1.71 V.
5. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay
above 1.71 V with the embedded power voltage detector enabled.
6. The product junction temperature must be kept within the –40 to +125 °C temperature range.
7. This package is under development. Please contact STMicroelectronics for details.
DS12110 Rev 7 23/357
STM32H742xI/G STM32H743xI/G Description
54
Figure 1. STM32H742xI/G block diagram
MSv48805V5
TT-FDCAN1
FDCAN2
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
AXI/AHB12 (240MHz)
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
APB1 30MHz
TX, RX
SCL, SDA, SMBAL as AF
APB1 120 MHz (max)
MDMA
PK[7:0]
4 compl. chan.(TIM8_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4], ETR,
BKIN as AF
RX, TX, SCK, CTS, RTS as AF
SCL, SDA, SMBAL as AF
SCL, SDA, SMBAL as AF
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
TX, RX
RX, TX as AF
RX, TX as AF
RX, TX, SCK
CTS, RTS as AF
RX, TX, SCK, CTS,
RTS as AF
1 channel as AF
smcard
irDA
1 channel as AF
2 channels as AF
4 channels
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
RX, TX as AF
FIFO
CHROM-ART
(DMA2D)
SD, SCK, FS, MCLK, D/CK[4:1] as
AF
FIFO
CLK, CS,D[7:0]
64-bit AXI BUS-MATRIX
CEC as AF
IN[1:4] as AF
MDC, MDIO
AXIM
AXIM
Arm CPU
Cortex-M7
480 MHz
AHBP
AHBS
TRACECK
TRACED[3:0]
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
JTAG/SW
ETM
I-Cache
16KB
D-Cache
16KB
I-TCM
64KB
D-TCM
64KB
16 Streams
FIFO
SDMMC1
SDMMC_D[7:0],SDMMC_D[7:3,1]Dir
SDMMC_D0dir, SDMMC_D2dir
CMD, CMDdir, CK, Ckin,
CKio as AF
FIFO
DMA1
FIFOs
8 Stream
DMA2
FIFOs
ETHER
MAC
FIFO
SDMMC2
FIFO
OTG_HS
FIFO
OTG_FS
FIFO
SRAM1
32 KB
8 Stream
FMC_signals
DMA/ DMA/ DMA/
PHY PHY
MII / RMII
MDIO
as AF
DP, DM, STP,
NXT,ULPI:CK
, D[7:0], DIR,
ID, VBUS
AHB1 (240MHz)
ADC1
DAC_OUT1, DAC_OUT2 as AF
16b
AXI/AHB34 (240MHz)
WWDG
AHB2 (240MHz)
AHB2 (240MHz)
PA..J[15:0]
HSYNC, VSYNC, PIXCLK, D[13:0]
SAI3
MOSI, MISO, SCK, NSS as AF
MOSI, MISO, SCK, NSS as AF
smcard
irDA 32-bit AHB BUS-MATRIX
AHB4 (240MHz)
BDMA
DMA
Mux2
Up to 20 analog inputs
common to ADC1 & 2
HSEM
AHB4 (240MHz)
AHB3
AHB4
AHB4
AHB4
AHB4
AHB4
VDDA, VSSA
NRESET
WKUP[5:0]
@VDD
RCC
Reset &
control
OSC32_IN
OSC32_OUT
VBAT = 1.8 to 3.6 V
AWU
VDD12 BBgen + POWER MNGT
LS LS
OSC_IN
OSC_OUT
RTC_TS
RTC_TAMP[1:3]
RTC_OUT
RTC_REFIN
VDDMMC33 = 1.8 to 3.6V
VDDUSB33 = 3.0 to 3.6 V
VDD = 1.8 to 3.6 V
VSS
VCAP
@VDD
@VDD33
@VSW
PWRCTRL
AHB4 (240MHz)
SUPPLY SUPERVISION
Int
POR
reset
@VDD
WDG_LS_D1
LPTIM1_IN1, LPTIM1_IN2,
LPTIM1_OUT as AF
OPAMPx_VINM
OPAMPx_VINP
OPAMPx_VOUT as AF
HRTIM1_CH[A..E]x
HRTIM1_FLT[5:1],
HRTIM1_FLT[5:1]_in, SYSFLT
DFSDM1_CKOUT,
DFSDM1_DATAIN[0:7],
DFSDM1_CKIN[0:7]
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
SDMMC_
D[7:0],
CMD, CK as AF
Up to 17 analog inputs
common to ADC1 and 2
SD, SCK, FS, MCLK,
D[3;1], CK[2:1] as AF
SCL, SDA, SMBAL as AF
COMPx_INP, COMPx_INM,
COMPx_OUT as AF
LPTIM5_OUT as AF
D-TCM
64KB
AHB/APB
Quad-SPI
1 MB FLASH
1 MB FLASH
384 KB AXI
SRAM
FMC
Delay block
DCMI AHB/APB
HRTIM1
DFSDM1
SD, SCK, FS, MCLK, CK[2:1] as AF
FIFO
SAI2
SD, SCK, FS, MCLK, D[3:1],
CK[2:1] as AF
FIFO
SAI1
SPI5
TIM17
TIM16
TIM15
SPI4
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF SPI1/I2S1
USART6
RX, TX, SCK, CTS, RTS as AF irDA USART1
TIM1/PWM 16b
TIM8/PWM 16b
ABP2 120 MHz (max)
ADC3
GPIO PORTA.. J
GPIO PORTK
SAI4
COMP1&2
LPTIM5
LPTIM4_OUT as AF LPTIM4
LPTIM3_OUT as AF LPTIM3
I2C4
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF SPI6/I2S6
RX, TX, CK, CTS, RTS as AF LPUART1
LPTIM2
VREF
SYSCFG
EXTI WKUP
CRC
DAP
RNG
DMA
Mux1
To APB1-2
peripherals
SRAM2
16 KB
ADC2
AHB/APB
TIM6 16b
TIM7 16b
SWPMI
TIM2
32b
TIM3
16b
TIM4
16b
TIM5
32b
TIM12
16b
TIM13
16b
TIM14
16b
USART2
smcard
irDA
USART3
UART4
UART5
UART7
RX, TX as AF
UART8
SPI2/I2S2
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI3/I2S3
Digital filter
MDIOs
FIFO
10 KB SRAM
RAM
I/F
USBCR
SPDIFRX1
HDMI-CEC
DAC
LPTIM1
OPAMP1&2
AHB/APB
XTAL 32 kHz
RTC
Backup registers
XTAL OSC
4- 48 MHz
HS RC
LS RC
PLL1+PLL2+PLL3
POR/PDR/BOR
PVD
smcard
Voltage
regulator
3.3 to 1.2V
LSI
HSI
CSI
HSI48
LPTIM2_IN1, LPTIM2_IN2 and
LPTIM2_OUT
AHB1 (240MHz)
DP, DM, ID,
VBUS
64 KB SRAM 4 KB BKP
RAM
AHB4
32-bit AHB BUS-MATRIX
APB4 100 MHz (max)
APB4 100 MHz (max)
APB4 120 MHz (max)
IWDG
Temperature
sensor
Description STM32H742xI/G STM32H743xI/G
24/357 DS12110 Rev 7
Figure 2. STM32H743xI/G block diagram
MSv41922V13
TT-FDCAN1
FDCAN2
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
AXI/AHB12 (240MHz)
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
APB1 30MHz
TX, RX
SCL, SDA, SMBAL as AF
APB1 120 MHz (max)
MDMA
PK[7:0]
4 compl. chan.(TIM8_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4], ETR, BKIN as
AF
RX, TX, SCK, CTS, RTS as AF
SCL, SDA, SMBAL as AF
SCL, SDA, SMBAL as AF
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
TX, RX
RX, TX as AF
RX, TX as AF
RX, TX, SCK
CTS, RTS as AF
RX, TX, SCK, CTS,
RTS as AF
1 channel as AF
smcard
irDA
1 channel as AF
2 channels as AF
4 channels
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
RX, TX as AF
FIFO
LCD-TFT
FIFO
CHROM-ART
(DMA2D)
SD, SCK, FS, MCLK, D/CK[4:1] as
AF
FIFO
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE, LCD_CLK
CLK, CS,D[7:0]
64-bit AXI BUS-MATRIX
CEC as AF
IN[1:4] as AF
MDC, MDIO
AXIM
AXIM
Arm CPU
Cortex-M7
480 MHz
AHBP
AHBS
TRACECK
TRACED[3:0]
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
JTAG/SW
ETM
I-Cache
16KB
D-Cache
16KB
I-TCM
64KB
D-TCM
64KB
16 Streams
FIFO
SDMMC1
SDMMC_D[7:0],SDMMC_D[7:3,1]Dir
SDMMC_D0dir, SDMMC_D2dir
CMD, CMDdir, CK, Ckin,
CKio as AF
FIFO
DMA1
FIFOs
8 Stream
DMA2
FIFOs
ETHER
MAC
FIFO
SDMMC2
FIFO
OTG_HS
FIFO
OTG_FS
FIFO
SRAM1
128 KB
8 Stream
FMC_signals
DMA/ DMA/ DMA/
PHY PHY
MII / RMII
MDIO
as AF
DP, DM, STP,
NXT,ULPI:CK
, D[7:0], DIR,
ID, VBUS
AHB1 (240MHz)
ADC1
DAC_OUT1, DAC_OUT2 as AF
16b
AXI/AHB34 (240MHz)
JPEGWWDG
AHB2 (240MHz)
AHB2 (240MHz)
PA..J[15:0]
HSYNC, VSYNC, PIXCLK, D[13:0]
SAI3
MOSI, MISO, SCK, NSS as AF
MOSI, MISO, SCK, NSS as AF
smcard
irDA 32-bit AHB BUS-MATRIX
AHB4 (240MHz)
BDMA
DMA
Mux2
Up to 20 analog inputs
common to ADC1 & 2
HSEM
AHB4 (240MHz)
AHB3
AHB4
AHB4
AHB4
AHB4
AHB4
VDDA, VSSA
NRESET
WKUP[5:0]
@VDD
RCC
Reset &
control
OSC32_IN
OSC32_OUT
VBAT = 1.8 to 3.6 V
AWU
VDD12 BBgen + POWER MNGT
LS LS
OSC_IN
OSC_OUT
RTC_TS
RTC_TAMP[1:3]
RTC_OUT
RTC_REFIN
VDDMMC33 = 1.8 to 3.6V
VDDUSB33 = 3.0 to 3.6 V
VDD = 1.8 to 3.6 V
VSS
VCAP
@VDD
@VDD33
@VSW
PWRCTRL
AHB4 (240MHz)
SUPPLY SUPERVISION
Int
POR
reset
@VDD
WDG_LS_D1
LPTIM1_IN1, LPTIM1_IN2,
LPTIM1_OUT as AF
OPAMPx_VINM
OPAMPx_VINP
OPAMPx_VOUT as AF
HRTIM1_CH[A..E]x
HRTIM1_FLT[5:1],
HRTIM1_FLT[5:1]_in, SYSFLT
DFSDM1_CKOUT,
DFSDM1_DATAIN[0:7],
DFSDM1_CKIN[0:7]
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
SDMMC_
D[7:0],
CMD, CK as AF
Up to 17 analog inputs
common to ADC1 and 2
SD, SCK, FS, MCLK,
D[3;1], CK[2:1] as AF
SCL, SDA, SMBAL as AF
COMPx_INP, COMPx_INM,
COMPx_OUT as AF
LPTIM5_OUT as AF
D-TCM
64KB
AHB/APB
Quad-SPI
Up to 1 MB
FLASH
Up to 1 MB
FLASH
512 KB AXI
SRAM
FMC
Delay block
DCMI AHB/APB
HRTIM1
DFSDM1
SD, SCK, FS, MCLK, CK[2:1] as AF
FIFO
SAI2
SD, SCK, FS, MCLK, D[3:1],
CK[2:1] as AF
FIFO
SAI1
SPI5
TIM17
TIM16
TIM15
SPI4
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF SPI1/I2S1
USART6
RX, TX, SCK, CTS, RTS as AF irDA USART1
TIM1/PWM 16b
TIM8/PWM 16b
APB2 120 MHz (max)
ADC3
GPIO PORTA.. J
GPIO PORTK
SAI4
COMP1&2
LPTIM5
LPTIM4_OUT as AF LPTIM4
LPTIM3_OUT as AF LPTIM3
I2C4
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF SPI6/I2S6
RX, TX, CK, CTS, RTS as AF LPUART1
LPTIM2
VREF
SYSCFG
EXTI WKUP
CRC
DAP
RNG
DMA
Mux1
To APB1-2
peripherals
SRAM2
128 KB
SRAM3
32 KB
ADC2
AHB/APB
TIM6 16b
TIM7 16b
SWPMI
TIM2
32b
TIM3
16b
TIM4
16b
TIM5
32b
TIM12
16b
TIM13
16b
TIM14
16b
USART2
smcard
irDA
USART3
UART4
UART5
UART7
RX, TX as AF
UART8
SPI2/I2S2
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI3/I2S3
Digital filter
MDIOs
FIFO
10 KB SRAM
RAM
I/F
USBCR
SPDIFRX1
HDMI-CEC
DAC
LPTIM1
OPAMP1&2
AHB/APB
XTAL 32 kHz
RTC
Backup registers
XTAL OSC
4- 48 MHz
HS RC
LS RC
PLL1+PLL2+PLL3
POR/PDR/BOR
PVD
smcard
Voltage
regulator
3.3 to 1.2V
LSI
HSI
CSI
HSI48
LPTIM2_IN1, LPTIM2_IN2 and
LPTIM2_OUT
AHB1 (240MHz)
DP, DM, ID,
VBUS
64 KB SRAM 4 KB BKP
RAM
AHB4
32-bit AHB BUS-MATRIX
APB4 100 MHz (max)
APB4 100 MHz (max)
APB4 120 MHz (max)
IWDG
Temperature
sensor
DS12110 Rev 7 25/357
STM32H742xI/G STM32H743xI/G Functional overview
54
3 Functional overview
3.1 Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
•Six-stage dual-issue pipeline
•Dynamic branch prediction
•Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
•64-bit AXI interface
•64-bit ITCM interface
•2x32-bit DTCM interfaces
The following memory interfaces are supported:
•Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
•Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
•AXI Bus interface to optimize Burst transfers
•Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 and Figure 2 shows the general block diagram of the STM32H742xI/G and
STM32H743xI/G family.
Note: Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
3.2 Memory protection unit (MPU)
The memory protection unit (MPU) manages the CPU access rights and the attributes of the
system resources. It has to be programmed and enabled before use. Its main purposes are
to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by
a privileged task, but also to protect data processes or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
Functional overview STM32H742xI/G STM32H743xI/G
26/357 DS12110 Rev 7
3.3 Memories
3.3.1 Embedded Flash memory
The STM32H742xI/G and STM32H743xI/G devices embed up to 2 Mbytes of Flash memory
that can be used for storing programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing
both code and data constants. Each word consists of:
•One Flash word (8 words, 32 bytes or 256 bits)
•10 ECC bits.
The Flash memory is divided into two independent banks. Each bank is organized as
follows:
•A user Flash memory block of 512 Kbytes (STM32H7xxxG) or 1-Mbyte (STM32H7xxxI)
containing eight user sectors of 128 Kbytes (4 K Flash memory words)
•128 Kbytes of System Flash memory from which the device can boot
•2 Kbytes (64 Flash words) of user option bytes for user configuration
3.3.2 Embedded SRAM
All devices feature:
•384 (STM32H742xI/G) or 512 Kbytes (STM32H743xI/G) of AXI-SRAM mapped onto
AXI bus on D1 domain.
•SRAM1 mapped on D2 domain: 32 (STM32H742xI/G) or 128 Kbytes
(STM32H743xI/G)
•SRAM2 mapped on D2 domain: 16 (STM32H742xI/G) or 128 Kbytes
(STM32H743xI/G)128 Kbytes
•SRAM3 mapped on D2 domain: 32 Kbytes (STM32H743xI/G only)
•SRAM4 mapped on D3 domain: 64 Kbytes
•4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses,
and is retained in Standby or VBAT mode.
•RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. either They can be accessed
either from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave
of the CPU(AHBP):
– 64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the CPU.
– 128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs.
DS12110 Rev 7 27/357
STM32H742xI/G STM32H743xI/G Functional overview
54
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
•7 ECC bits are added per 32-bit word.
•8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
3.4 Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•All Flash address space
•All RAM address space: ITCM, DTCM RAMs and SRAMs
•The System memory bootloader
The boot loader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller System memory Boot mode application note (AN2606) for details.
3.5 Power supply management
3.5.1 Power supply scheme
STM32H742xI/G STM32H743xI/G power supply voltages are the following:
•VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD
pins.
•VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE
•VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
OPAMP.
•VDD33USB and VDD50USB:
VDD50USB can be supplied through the USB cable to generate the VDD33USB via the
USB internal regulator. This allows supporting a VDD supply different from 3.3 V.
The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.
•VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
•VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register and
Functional overview STM32H742xI/G STM32H743xI/G
28/357 DS12110 Rev 7
ODEN bit in the SYSCFG_PWRCR register. The VCORE domain is split into the
following power domains that can be independently switch off.
– D1 domain containing some peripherals and the Cortex®-M7 core.
– D2 domain containing a large part of the peripherals.
– D3 domain containing some peripherals and the system control.
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 3):
•When VDD is below 1 V, other power supplies (VDDA, VDD33USB, VDD50USB) must
remain below VDD + 300 mV.
•When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.
Figure 3. Power-up/power-down sequence
1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB.
MSv47490V1
0.3
1
VBOR0
3.6
Operating modePower-on Power-down time
V
VDDX(1)
VDD
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
DS12110 Rev 7 29/357
STM32H742xI/G STM32H743xI/G Functional overview
54
3.5.2 Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
•Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold.
The devices remain in Reset mode when VDD is below this threshold,
•Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
•Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to
2.7 V) can be configured through option bytes. A reset is generated when VDD drops
below this threshold.
3.5.3 Voltage regulator
The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can
be independently switched off.
Voltage regulator output can be adjusted according to application needs through 6 power
supply levels:
•Run mode (VOS0 to VOS3)
– Scale 0: boosted performance (available only with LDO regulator)
– Scale 1: high performance
– Scale 2: medium performance and consumption
– Scale 3: optimized performance and low-power consumption
•Stop mode (SVOS3 to SVOS5)
– Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
– Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled
The peripheral functionality is disabled but wakeup from Stop mode is possible
through GPIO or asynchronous interrupt.
Functional overview STM32H742xI/G STM32H743xI/G
30/357 DS12110 Rev 7
3.6 Low-power strategy
There are several ways to reduce power consumption on STM32H742xI/G and
STM32H743xI/G:
•Decrease the dynamic power consumption by slowing down the system clocks even in
Run mode and by individually clock gating the peripherals that are not used.
•Save power consumption when the CPU is idle, by selecting among the available low-
power mode according to the user application needs. This allows achieving the best
compromise between short startup time, low-power consumption, as well as available
wakeup sources.
The devices feature several low-power modes:
•CSleep (CPU clock stopped)
•CStop (CPU sub-system clock stopped)
•DStop (Domain bus matrix clock stopped)
•Stop (System clock stopped)
•DStandby (Domain powered down)
•Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
the Cortex®-Mx core is set after returning from an interrupt service routine.
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.
Table 3. System vs domain low-power mode
System power mode D1 domain power
mode
D2 domain power
mode
D3 domain power
mode
Run DRun/DStop/DStandby DRun/DStop/DStandby DRun
Stop DStop/DStandby DStop/DStandby DStop
Standby DStandby DStandby DStandby
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STM32H742xI/G STM32H743xI/G Functional overview
54
3.7 Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), the system frequency can be changed without modifying the
baudrate.
3.7.1 Clock management
The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
•Internal oscillators:
– 64 MHz HSI clock
– 48 MHz RC oscillator
– 4 MHz CSI clock
– 32 kHz LSI clock
•External oscillators:
– HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated
from a crystal/ceramic resonator)
– LSE clock: 32.768 kHz
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
3.7.2 System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
•Power-on reset (pwr_por_rst)
•Brownout reset
•Low level on NRST pin (external reset)
•Window watchdog
•Independent watchdog
•Software reset
•Low-power mode security reset
•Exit from Standby
Functional overview STM32H742xI/G STM32H743xI/G
32/357 DS12110 Rev 7
3.8 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs (except debug pins) are in Analog mode to reduce power
consumption (refer to GPIOs register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.9 Bus-interconnect matrix
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow
interconnecting bus masters with bus slaves (see Figure 4).
Figure 4 shows STM32H743xI/G bus matrix. All peripherals may not be available for
STM32H742xI/G (refer to Table 2: STM32H742xI/G and STM32H743xI/G features and
peripheral counts).
STM32H742xI/G STM32H743xI/G Functional overview
DS12110 Rev 7 33/357
Figure 4. STM32H743xI/G bus matrix
MSv46613V2
AXIM
DMA2 Ethernet
MAC SDMMC2DMA1 USBHS1 USBHS2
APB1
SDMMC1 MDMA DMA2D LTDC
BDMA
APB4
Cortex-M7
I$
16KB
D$
16KB
AHBP
DMA1_MEM
DMA1_PERIPH
DMA2_MEM
DMA2_PERIPH
APB3
32-bit AHB bus matrix
D2 domain
64-bit AXI bus matrix
D1 domain
32-bit AHB bus matrix
D3 domain
DTCM
128 Kbyte
ITCM
64 Kbyte
Flash A
Up to 1 Mbyte
Flash B
Up to 1 Mbyte
AXI SRAM
512 Kbyte
QSPI
FMC
SRAM1 128
Kbyte
SRAM2 128
Kbyte
SRAM3
32 Kbyte
AHB1
AHB2
AHB4
SRAM4
64 Kbyte
Backup
SRAM
4 Kbyte
AHBS
CPU
D2-to-D1 AHB
D2-to-D3 AHB
D1-to-D2 AHB
D1-to-D3 AHB
32-bit bus
64-bit bus
Bus multiplexer
Legend
Master interface
Slave interface
AHB3
AXI
AHB
APB
APB2
TCM
Functional overview STM32H742xI/G STM32H743xI/G
34/357 DS12110 Rev 7
3.10 DMA controllers
The devices feature four DMA instances to unload CPU activity:
•A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface and a dedicated AHB interface to
access Cortex®-M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA
controllers located in D2 domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers
and linked list transfers.
•Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request
router capabilities.
•One basic DMA (BDMA) located in D3 domain, with request router capabilities.
The DMA request router could be considered as an extension of the DMA controller. It
routes the DMA peripheral requests to the DMA controller itself. This allowing managing the
DMA requests with a high flexibility, maximizing the number of DMA requests that run
concurrently, as well as generating DMA requests from peripheral output trigger or DMA
event.
3.11 Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphical accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•Rectangle filling with a fixed color
•Rectangle copy
•Rectangle copy with pixel format conversion
•Rectangle composition with blending and pixel format conversion
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also
supports block based YCbCr to handle JPEG decoder output.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
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3.12 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller which is able to manage 16
priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines
of the Cortex®-M7 with FPU core.
•Closely coupled NVIC gives low-latency interrupt processing
•Interrupt entry vector table address passed directly to the core
•Allows early processing of interrupts
•Processing of late arriving, higher-priority interrupts
•Support tail chaining
•Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13 Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up
the processor, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 89 independent event/interrupt lines split as 28 configurable events
and 61 direct events .
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
3.14 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
Functional overview STM32H742xI/G STM32H743xI/G
36/357 DS12110 Rev 7
3.15 Flexible memory controller (FMC)
The FMC controller main features are the following:
•Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (4 memory banks)
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•8-,16-,32-bit data bus width
•Independent Chip Select control for each memory bank
•Independent configuration for each memory bank
•Write FIFO
•Read FIFO for SDRAM controller
•The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
3.16 Quad-SPI memory interface (QUADSPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting Single, Dual or Quad-SPI Flash memories. It supports both single and
double datarate operations.
It can operate in any of the following modes:
•Direct mode through registers
•External Flash status register polling mode
•Memory mapped mode.
Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data
accesses are supported as well as code execution.
The opcode and the frame format are fully programmable.
3.17 Analog-to-digital converters (ADCs)
The STM32H742xI/G and STM32H743xI/G devices embed three analog-to-digital
converters, which resolution can be configured to 16, 14, 12, 10 or 8 bits.
Each ADC shares up to 20 external channels, performing conversions in the Single-shot or
Scan mode. In Scan mode, automatic conversion is performed on a selected group of
analog inputs.
Additional logic functions embedded in the ADC interface allow:
•Simultaneous sample and hold
•Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC
converted values to a destination location without any software action.
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STM32H742xI/G STM32H743xI/G Functional overview
54
In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer.
3.18 Temperature sensor
STM32H742xI/G and STM32H743xI/G devices embed a temperature sensor that generates
a voltage (VTS) that varies linearly with the temperature. This temperature sensor is
internally connected to ADC3_IN18. The conversion range is between 1.7 V and 3.6 V. It
can measure the device junction temperature ranging from −40 up to +125 °C.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the System memory
area, which is accessible in Read-only mode.
3.19 VBAT operation
The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
To optimize battery duration, this power domain is supplied by VDD when available or by the
voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched
when the PDR detects that VDD dropped below the PDR level.
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by VDD, in which case, the VBAT mode is not functional.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
Functional overview STM32H742xI/G STM32H743xI/G
38/357 DS12110 Rev 7
3.20 Digital-to-analog converters (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•two DAC converters: one for each output channel
•8-bit or 12-bit monotonic output
•left or right data alignment in 12-bit mode
•synchronized update capability
•noise-wave generation
•triangular-wave generation
•dual DAC channel independent or simultaneous conversions
•DMA capability for each channel including DMA underrun error detection
•external triggers for conversion
•input voltage reference VREF+ or internal VREFBUF reference.
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.
3.21 Ultra-low-power comparators (COMP)
STM32H742xI/G and STM32H743xI/G devices embed two rail-to-rail comparators (COMP1
and COMP2). They feature programmable reference voltage (internal or external),
hysteresis and speed (low speed for low-power) as well as selectable output polarity.
The reference voltage can be one of the following:
•An external I/O
•A DAC output channel
•An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and be combined into a window comparator.
3.22 Operational amplifiers (OPAMP)
STM32H742xI/G and STM32H743xI/G devices embed two rail-to-rail operational amplifiers
(OPAMP1 and OPAMP2) with external or internal follower routing and PGA capability.
The operational amplifier main features are:
•PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
•One positive input connected to DAC
•Output connected to internal ADC
•Low input bias current down to 1 nA
•Low input offset voltage down to 1.5 mV
•Gain bandwidth up to 7.3 MHz
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STM32H742xI/G STM32H743xI/G Functional overview
54
The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
3.23 Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from internal ADC
peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•8 multiplexed input digital serial channels:
– configurable SPI interface to connect various SD modulator(s)
– configurable Manchester coded 1 wire interface support
– PDM (Pulse Density Modulation) microphone input support
– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
– clock output for SD modulator(s): 0..20 MHz
•alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
– internal sources: ADC data or memory data streams (DMA)
•4 digital filter modules with adjustable digital signal processing:
–Sinc
x filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
– integrator: oversampling ratio (1..256)
•up to 24-bit output data resolution, signed output data format
•automatic data offset correction (offset stored in register by user)
•continuous or single conversion
•start-of-conversion triggered by:
– software trigger
– internal timers
– external events
– start-of-conversion synchronously with first digital filter module (DFSDM0)
•analog watchdog feature:
– low value and high value data threshold registers
– dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
– input from final output data or from selected input digital serial channels
– continuous monitoring independently from standard conversion
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40/357 DS12110 Rev 7
•short circuit detector to detect saturated analog input values (bottom and top range):
– up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
– monitoring continuously each input serial channel
•break signal generation on analog watchdog event or on short circuit detector event
•extremes detector:
– storage of minimum and maximum values of final conversion data
– refreshed by software
•DMA capability to read the final conversion data
•interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•“regular” or “injected” conversions:
– “regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
– “injected” conversions for precise timing and with high conversion priority
3.24 Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It
features:
•Programmable polarity for the input pixel clock and synchronization signals
•Parallel data communication can be 8-, 10-, 12- or 14-bit
•Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•Supports Continuous mode or Snapshot (a single frame) mode
•Capability to automatically crop the image
3.25 LCD-TFT controller
The LCD-TFT display controller (only available on STM32H743xI/G) provides a 24-bit
parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a
Table 4. DFSDM implementation
DFSDM features DFSDM1
Number of filters 4
Number of input
transceivers/channels 8
Internal ADC parallel input X
Number of external triggers 16
Regular channel information in
identification register X
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STM32H742xI/G STM32H743xI/G Functional overview
54
broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following
features:
•2 display layers with dedicated FIFO (64x64-bit)
•Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
•Up to 8 input color formats selectable per layer
•Flexible blending between two layers using alpha value (per pixel or constant)
•Flexible programmable parameters for each layer
•Color keying (transparency color)
•Up to 4 programmable interrupt events
•AXI master interface with burst of 16 words
3.26 JPEG Codec (JPEG)
The JPEG Codec (only available on STM32H743xI/G) can encode and decode a JPEG
stream as defined in the ISO/IEC 10918-1 specification. It provides an fast and simple
hardware compressor and decompressor of JPEG images with full management of JPEG
headers.
The JPEG codec main features are as follows:
•8-bit/channel pixel depths
•Single clock per pixel encoding and decoding
•Support for JPEG header generation and parsing
•Up to four programmable quantization tables
•Fully programmable Huffman tables (two AC and two DC)
•Fully programmable minimum coded unit (MCU)
•Encode/decode support (non simultaneous)
•Single clock Huffman coding and decoding
•Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
•Support for single greyscale component
•Ability to enable/disable header processing
•Fully synchronous design
•Configuration for High-speed decode mode
3.27 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.28 Timers and watchdogs
The devices include one high-resolution timer, two advanced-control timers, ten general-
purpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 5 compares the features of the advanced-control, general-purpose and basic timers.
Functional overview STM32H742xI/G STM32H743xI/G
42/357 DS12110 Rev 7
Table 5. Timer feature comparison
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Comple-
mentary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)
High-
resolution
timer
HRTIM1 16-bit Up
/1 /2 /4
(x2 x4 x8
x16 x32,
with DLL)
Yes 10 Yes 480 480
Advanced
-control
TIM1,
TIM8 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 Yes 120 240
General
purpose
TIM2,
TIM5 32-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 No 120 240
TIM3,
TIM4 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 No 120 240
TIM12 16-bit Up
Any
integer
between 1
and
65536
No 2 No 120 240
TIM13,
TIM14 16-bit Up
Any
integer
between 1
and
65536
No 1 No 120 240
TIM15 16-bit Up
Any
integer
between 1
and
65536
Yes 2 1 120 240
TIM16,
TIM17 16-bit Up
Any
integer
between 1
and
65536
Yes 1 1 120 240
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STM32H742xI/G STM32H743xI/G Functional overview
54
3.28.1 High-resolution timer (HRTIM1)
The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy
timings, such as PWM or phase-shifted pulses.
It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can
be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection
purposes and 10 inputs to handle external events such as current limitation, zero voltage or
zero current switching.
The HRTIM1 timer is made of a digital kernel clocked at 480 MHz The high-resolution is
available on the 10 outputs in all operating modes: variable duty cycle, variable frequency,
and constant ON time.
The slave timers can be combined to control multiswitch complex converters or operate
independently to manage multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events
such as analog or digital feedbacks signals.
HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also
offers specific modes and features to offload the CPU: DMA requests, Burst mode
controller, Push-pull and Resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost
converters, either in voltage or current mode, as well as lighting application (fluorescent or
LED). It can also be used as a general purpose timer, for instance to achieve high-resolution
PWM-emulated DAC.
Basic TIM6,
TIM7 16-bit Up
Any
integer
between 1
and
65536
Yes 0 No 120 240
Low-
power
timer
LPTIM1,
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5
16-bit Up
1, 2, 4, 8,
16, 32, 64,
128
No 0 No 120 240
1. The maximum timer clock is up to 480 MHz depending on TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.
Table 5. Timer feature comparison (continued)
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Comple-
mentary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)
Functional overview STM32H742xI/G STM32H743xI/G
44/357 DS12110 Rev 7
3.28.2 Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•Input capture
•Output compare
•PWM generation (Edge- or Center-aligned modes)
•One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.28.3 General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32H742xI/G
and STM32H743xI/G devices (see Table 5 for differences).
•TIM2, TIM3, TIM4, TIM5
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and
TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit
prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and
a 16-bit prescaler. All timers feature 4 independent channels for input capture/output
compare, PWM or One-pulse mode output. This gives up to 16 input capture/output
compare/PWMs on the largest packages.
TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers or used as simple timebases.
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54
3.28.4 Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.28.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
The low-power timers have an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
•16-bit up counter with 16-bit autoreload register
•16-bit compare register
•Configurable output: pulse, PWM
•Continuous / One-shot mode
•Selectable software / hardware input trigger
•Selectable clock source:
•Internal clock source: LSE, LSI, HSI or APB clock
•External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
•Programmable digital glitch filter
•Encoder mode
3.28.6 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.28.7 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
Debug mode.
3.28.8 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
•A 24-bit downcounter
•Autoreload capability
•Maskable system interrupt generation when the counter reaches 0
•Programmable clock source.
Functional overview STM32H742xI/G STM32H743xI/G
46/357 DS12110 Rev 7
3.29 Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•Two programmable alarms.
•On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•Three anti-tamper detection pins with programmable filter.
•Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
•17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
•A 32.768 kHz external crystal (LSE)
•An external resonator or oscillator (LSE)
•The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
•The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
DS12110 Rev 7 47/357
STM32H742xI/G STM32H743xI/G Functional overview
54
3.30 Inter-integrated circuit interface (I2C)
STM32H742xI/G and STM32H743xI/G devices embed four I2C interfaces.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•I2C-bus specification and user manual rev. 5 compatibility:
– Slave and Master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
•System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
•Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
•Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•Wakeup from Stop mode on address match
•Programmable analog and digital noise filters
•1-byte buffer with DMA capability
3.31 Universal synchronous/asynchronous receiver transmitter
(USART)
STM32H742xI/G and STM32H743xI/G devices have four embedded universal synchronous
receiver transmitters (USART1, USART2, USART3 and USART6) and four universal
asynchronous receiver transmitters (UART4, UART5, UART7 and UART8). Refer to Table 6
for a summary of USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire Half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
12.5 Mbit/s.
USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816
compliant) and SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode
is enabled by software and is disabled by default.
Functional overview STM32H742xI/G STM32H743xI/G
48/357 DS12110 Rev 7
All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can
be done on:
•Start bit detection
•Any received data frame
•A specific programmed data frame
•Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
3.32 Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half
duplex single wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
Table 6. USART features
USART modes/features(1)
1. X = supported.
USART1/2/3/6 UART4/5/7/8
Hardware flow control for modem X X
Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode (Master/Slave) X -
Smartcard mode X -
Single-wire Half-duplex communication X X
IrDA SIR ENDEC block X X
LIN mode X X
Dual clock domain and wakeup from low power mode X X
Receiver timeout interrupt X X
Modbus communication X X
Auto baud rate detection X X
Driver Enable X X
USART data length 7, 8 and 9 bits
Tx/Rx FIFO X X
Tx/Rx FIFO size 16
DS12110 Rev 7 49/357
STM32H742xI/G STM32H743xI/G Functional overview
54
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
•Start bit detection
•Any received data frame
•A specific programmed data frame
•Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.33 Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that
allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Full-
duplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the
frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in Master or Slave mode, in Simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
I2S interfaces is/are configured in Master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency. All I2S interfaces support 16x 8-
bit embedded Rx and Tx FIFOs with DMA capability.
3.34 Serial audio interfaces (SAI)
The devices embed 4 SAIs (SAI1, SAI2, SAI3 and SAI4) that allow designing many stereo
or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An
SPDIF output is available when the audio block is configured as a transmitter. To bring this
level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks.
Each block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
Functional overview STM32H742xI/G STM32H743xI/G
50/357 DS12110 Rev 7
3.35 SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
•Up to 4 inputs available
•Automatic symbol rate detection
•Maximum symbol rate: 12.288 MHz
•Stereo stream from 32 to 192 kHz supported
•Supports Audio IEC-60958 and IEC-61937, consumer applications
•Parity bit management
•Communication using DMA for audio samples
•Communication using DMA for control and user channel information
•Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.36 Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
•Full-duplex communication mode
•automatic SWP bus state management (active, suspend, resume)
•configurable bitrate up to 2 Mbit/s
•automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
DS12110 Rev 7 51/357
STM32H742xI/G STM32H743xI/G Functional overview
54
3.37 Management Data Input/Output (MDIO) slaves
The devices embed an MDIO slave interface it includes the following features:
•32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
– 32 x 16-bit firmware read/write, MDIO read-only output data registers
– 32 x 16-bit firmware read-only, MDIO write-only input data registers
•Configurable slave (port) address
•Independently maskable interrupts/events:
– MDIO Register write
– MDIO Register read
– MDIO protocol error
•Able to operate in and wake up from Stop mode
3.38 SD/SDIO/MMC card host interfaces (SDMMC)
Two SDMMC host interfaces are available. They support MultiMediaCard System
Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card
specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a
stack of MMC Version 4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
3.39 Controller area network (FDCAN1, FDCAN2)
The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol
specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including
event synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is
shared between the two FDCAN1 and FDCAN2 modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.
Functional overview STM32H742xI/G STM32H743xI/G
52/357 DS12110 Rev 7
3.40 Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2
supports only full-speed operations. They both integrate the transceivers for full-speed
operation (12 Mbit/s) and are able to operate from the internal HSI48 oscillator. OTG-HS1
features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using
the USB OTG-HS1 in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripherals are compliant with the USB 2.0 specification and with the
OTG 2.0 specification. They have software-configurable endpoint setting and supports
suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
•Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
•Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•9 bidirectional endpoints (including EP0)
•16 host channels with periodic OUT support
•Software configurable to OTG1.3 and OTG2.0 modes of operation
•USB 2.0 LPM (Link Power Management) support
•Battery Charging Specification Revision 1.2 support
•Internal FS OTG PHY support
•External HS or HS OTG operation supporting ULPI in SDR mode (OTG_HS1 only)
The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can
be clocked using the 60 MHz output.
•Internal USB DMA
•HNP/SNP/IP inside (no need for any external resistor)
•For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.41 Ethernet MAC interface with dedicated DMA controller (ETH)
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
DS12110 Rev 7 53/357
STM32H742xI/G STM32H743xI/G Functional overview
54
The devices include the following features:
•Supports 10 and 100 Mbit/s rates
•Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
•Tagged MAC frame support (VLAN support)
•Half-duplex (CSMA/CD) and full-duplex operation
•MAC control sublayer (control frames) support
•32-bit CRC generation and removal
•Several address filtering modes for physical and multicast address (multicast and
group addresses)
•32-bit status code for each transmitted or received frame
•Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
•Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
•Triggers interrupt when system time becomes greater than target time
3.42 High-definition multimedia interface (HDMI)
- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.43 Debug infrastructure
The devices offer a comprehensive set of debug and trace features to support software
development and system integration.
•Breakpoint debugging
•Code execution tracing
•Software instrumentation
•JTAG debug port
•Serial-wire debug port
•Trigger input and output
•Serial-wire trace port
•Trace port
•Arm® CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry
standard debugging tools.
The trace port performs data capture for logging and analysis.
Memory mapping STM32H742xI/G STM32H743xI/G
54/357 DS12110 Rev 7
4 Memory mapping
Refer to Table 7 for details on STM32H742xI/G Flash and SRAM block memory mapping
and to the product line reference manual for information on the boundary addresses for all
STM32H742xI/G peripherals.
Details on STM32H743xGxI/G Flash and SRAM block memory mapping and boundary
addresses for all STM32H743xI/G peripherals are given in the product line reference
manual.
Table 7. Flash memory and SRAM memory mapping for STM32H742xI/G
Memory Size in Kbytes Start address
RAM area
Backup SRAM 4 0x3880 0000
SRAM4 64 0x3800 0000
SRAM2 16 0x3002 0000
SRAM1 32 0x3000 0000
AXI-SRAM 384 0x2400 0000
DTCM 128 0x2000 0000
Code area
System memory 2 0x1FF4 0000
System memory 0x1FF0 0000
Flash memory 2048 0x0800 0000
ITCM 64 0x0000 0000
DS12110 Rev 7 55/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
5 Pin descriptions
Figure 5. LQFP100 pinout
1. The above figure shows the package top view.
MSv41918V4
VDD
VSS
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VCAP
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 100-pins 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2_C 17 59 PD12
PC3_C 18 58 PD11
VSSA 19 57 PD10
VREF+ 20 56 PD9
VDDA 21 55 PD8
PA0 22 54 PB15
PA1 23 53 PB14
PA2 24 52 PB13
PA3 25 51 PB12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VSS
VDD
Pin descriptions STM32H742xI/G STM32H743xI/G
56/357 DS12110 Rev 7
Figure 6. TFBGA100 pinout
1. The above figure shows the package top view.
MSv46177V2
PC14-
OSC32_IN PC13 PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13
12345678910
A
B
C
D
E
F
G
H
J
K
PC15-
OSC32_OUT VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12
PH0-OSC_IN VSS PE4 PE1 PB5 PC12 PA9 PA11
PH1-
OSC_OUT VDD PE5 PA10
NRST PC2_C PE6 PC7
PC0 PC1
VSSA PA0
VDDA PA1 PA5 PB14
VSS PA2 PA6 PD13
VDD PA3 PA7 PB1 PE9 PB12 PD8 PD12
PE0 BOOT0 PD7 PD4
PD6 PD3
PD0 PA8
VSS VSS VSS VCAP PD1 PC9
PC3_C VDDLDO VDD VDD33USB PDR_ON PC8
PA4 PC4 PB2 PE10 PE14 PD15 PD11
PC6
PB15
PC5 PE7 PE11 PE15 PD14 PD10
PB0 PE8 PE12 PB10 PB13 PD9
PE13 PB11
VCAP
DS12110 Rev 7 57/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
Figure 7. LQFP144 pinout
1. The above figure shows the package top view.
MSv41917V4
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VCAP
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PC15-OSC32_OUT 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDD33USB
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 144-pins 91 PG6
PF7 19 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2_C 28 81 PD12
PC3_C 29 80 PD11
VDD 30 79 PD10
VSSA 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VDD
Pin descriptions STM32H742xI/G STM32H743xI/G
58/357 DS12110 Rev 7
Figure 8. UFBGA169 ballout
1. The above figure shows the package top view.
MSv45339V4
A
B
C
D
E
F
G
H
J
K
L
M
N
12345678910111213
PE4 PE2 VDD PI6 PB6 PI2 VDD PG10 PD5 VDD PC12 PC10 PI0
PC15-
OSC32_
OUT
PE3 VSS VDDLDO PB8 PB4 PI3 PG11 PD6 VSS PC11 PA14 PI1
PC14-
OSC32_
IN
PE5 PDR_ON PB9 PB5 PG14 PG9 PD4 PD1 PA15 VSS VDD
VDD VSS PC13 PE0 PB7 PG13 PD7 PD3 PD0 PA13 VDDLDO VCAP
PI11 PI7 VBAT
PE1
PF3 BOOT0 PG15 PG12 PD2 PA10 PA9 PA8 PA12
PI13 PI12 PF0
PF1
PF5 PF7 PB3 PG4 PC6 PC7 PC9 PC8 PA11
VDD VSS PF4
PF2
PF9 NRST PF13 PE7 PG6 PG7 PG8 VDD50_
USB
VDD33_
USB
PH0-
OSC_
IN
PH1-
OSC_
OUT
PF10
PF6
PJ1 PA4 PF14 PE8 PG2 PG3 PG5 VSS VDD
PC1 VSSA
PF8
PA0 PA7 PF15 PE9 PE14 PD11 PD13 PD15 PD14
PC3_C PH4
PJ0
PA6 PC4 PG0 PE13 PH10 PH12 PD9 PD10 PD12
VDDA VREF+ PH5
PA1
PB1 PB2 PG1 PE12 PB10 PH11 PB13 VSS VDD
VDD VSS PH3
PA5
PB0 PF11 VSS PE10 PB11 VDDLDO VSS PD8 PB15
PA2 PH2 PA3 VDD PC5 PF12 VDD PE11 PE15 VCAP VDD PB12 PB14
PC0
PE6
PC2_C
VSS
DS12110 Rev 7 59/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
Figure 9. LQFP176 pinout
1. The above figure shows the package top view.
PINOUT UNDER DEVELOPMENT
MSv41916V5
PI7
PI6
PI5
PI4
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VDD
VSS
PI3
PI2
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PE2 1132 PI1
PE3 2 131 PI0
PE4 3 130 PH15
PE5 4 129 PH14
PE6 5 128 PH13
VBAT 6 127 VDD
PI8 7 126 VSS
PC13 8 125 VCAP
PC14-OSC32_IN 9 124 PA13
PC15-OSC32_OUT 10 123 PA12
PI9 11 122 PA11
PI10 12 121 PA10
PI11 13 120 PA9
VSS 14 119 PA8
VDD 15 118 PC9
PF0 16 117 PC8
PF1 17 116 PC7
PF2 18 115 PC6
PF3 19 114 VDD33USB
PF4 20 113 VSS
PF5 21 112 PG8
VSS 22 176-pins 111 PG7
VDD 23 110 PG6
PF6 24 109 PG5
PF7 25 108 PG4
PF8 26 107 PG3
PF9 27 106 PG2
PF10 28 105 PD15
PH0-OSC_IN 29 104 PD14
PH1-OSC_OUT 30 103 VDD
NRST 31 102 VSS
PC0 32 101 PD13
PC1 33 100 PD12
PC2_C 34 99 PD11
PC3_C 35 98 PD10
VDD 36 97 PD9
VSSA 37 96 PD8
VREF+ 38 95 PB15
VDDA 39 94 PB14
PA0 40 93 PB13
PA1 41 92 PB12
PA2 42 91 VDD
PH2 43 90 VSS
PH3 44 89 PH12
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
PH4
PH5
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VDD
PH6
PH7
PH8
PH9
PH10
PH11
Pin descriptions STM32H742xI/G STM32H743xI/G
60/357 DS12110 Rev 7
Figure 10. UFBGA176+25 ballout
1. The above figure shows the package top view.
MSv41912V3
123456789101112131415
APE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13
BPE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12
CVBAT PI7 PI6 PI5 VDD PDR_ON VDD VDD VDD PG9 PD5 PD1 PI3 PI2 PA11
DPC13 PI8 PI9 PI4 VSS BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10
E
PC14-
OSC32_
IN
PF0 PI10 PI11 PH13 PH14 PI0 PA9
F
PC15-
OSC32_
OUT
VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP PC9 PA8
GPH0-
OSC_IN VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7
H
PH1-
OSC_
OUT
PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDD
33USB PG8 PC6
JNRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6
KPF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3
LPF10 PF9 PF8 PH11 PH10 PD15 PG2
MVSSA PC0 PC1 PC2_C PC3_C PB2 PG1 VSS VSS VCAP PH6 PH8 PH9 PD14 PD13
NVREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10
PVREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8
RVDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15
VSS
DS12110 Rev 7 61/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
Figure 11. LQFP208 pinout
1. The above figure shows the package top view.
MSv41915V3
PI7
PI6
PI5
PI4
VDD
PDR_ON
VSS
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
PK7
PK6
PK5
PK4
PK3
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PJ15
PJ14
PJ13
PJ12
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VDD
PI3
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
PE2 1156 PI2
PE3 2 155 PI1
PE4 3 154 PI0
PE5 4 153 PH15
PE6 5 152 PH14
VBAT 6 151 PH13
PI8 7 150 VDD
PC13 8 149 VSS
PC14-OSC32_IN 9 148 VCAP
PC15-OSC32_OUT 10 147 PA13
PI9 11 146 PA12
PI10 12 145 PA11
PI11 13 144 PA10
VSS 14 143 PA9
VDD 15 142 PA8
PF0 16 141 PC9
PF1 17 140 PC8
PF2 18 139 PC7
PI12 19 138 PC6
PI13 20 137 VDD33USB
PI14 21 136 VSS
PF3 22 135 PG8
PF4 23 134 PG7
PF5 24 133 PG6
VSS 25 208-pins 132 PG5
VDD 26 131 PG4
PF6 27 130 PG3
28 129 PG2
PF8 29 128 PK2
PF9 30 127 PK1
PF10 31 126 PK0
PH0-OSC_IN 32 125 VSS
PH1-OSC_OUT 33 124 VDD
NRST 34 123 PJ11
PC0 35 122 PJ10
PC1 36 121 PJ9
PC2_C 37 120 PJ8
PC3_C 38 119 PJ7
VDD 39 118 PJ6
VSSA 40 117 PD15
VREF+ 41 116 PD14
VDDA 42 115 VDD
PA0 43 114 VSS
PA1 44 113 PD13
PA2 45 112 PD12
PH2 46 111 PD11
PH3 47 110 PD10
PH4 48 109 PD9
PH5 49 108 PD8
PA3 50 107 PB15
VSS 51 106 PB14
VDD 52 105 PB13
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
PA4
PA5
PA6
PA7
PC4
PC5
VDD
VSS
PB0
PB1
PB2
PI15
PJ0
PJ1
PJ2
PJ3
PJ4
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VSS
VDD
PJ5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
VDD
PB12
PF7
Pin descriptions STM32H742xI/G STM32H743xI/G
62/357 DS12110 Rev 7
Figure 12. TFBGA240+25 ballout
1. The above figure shows the package top view.
MSv41911V2
VSS PI6 PI5 PI4 PB5 VDD
LDO VCAP PK5 PG10 PG9 PD5 PD4 PC10 PA15 PI1 PI0 VSS
VBAT VSS PI7 PE1 PB6 VSS PB4 PK4 PG11 PJ15 PD6 PD3 PC11 PA14 PI2 PH15 PH14
PC15-
OSC32_
OUT
PE2 PE0 PB7 PB3 PK6 PK3 PG12 VSS PD7 PC12 VSS PI3 PA13 VSS VDD
LDO
PE5 PE4 PE3 PB9 PB8 PG15 PK7 PG14 PG13 PJ14 PJ12 PD2 PD0 PA10 PA9 PH13 VCAP
NC PI9 PC13 PI8 PE6 VDD PDR_
ON
BOO
T0 VDD PJ13 VDD PD1 PC8 PC9 PA8 PA12 PA11
NC NC PI10 PI11 VDD PC7 PC6 PG8 PG7 VDD33
USB
PF2 NC PF1 PF0 VDD VSS VSS VSS VSS VSS VDD PG5 PG6 VSS VDD50
USB
PI12 PI13 PI14 PF3 VDD VDD PG4 PG3 PG2 PK2
PH0-
OSC_IN VSS PF5 PF4 VDD PK0 PK1 VSS VSS
NRST PF6 PF7 PF8 VDD VDD PJ11 VSS NC NC
VDDA PC0 PF10 PF9 VDD VDD PJ10 VSS NC NC
VREF+ PC1 PC2 PC3 VDD VDD PJ9 VSS NC NC
VREF- PH2 PA2 PA1 PA0 PJ0 VDD VDD PE10 VDD VDD VDD PJ8 PJ7 PJ6 VSS NC
VSSA PH3 PH4 PH5 PI15 PJ1 PF13 PF14 PE9 PE11 PB10 PB11 PH10 PH11 PD15 PD14 VDD
PC2_C PC3_C PA6 VSS PA7 PB2 PF12 VSS PF15 PE12 PE15 PJ5 PH9 PH12 PD11 PD12 PD13
PA0_C PA1_C PA5 PC4 PB1 PJ2 PF11 PG0 PE8 PE13 PH6 VSS PH8 PB12 PB15 PD10 PD9
VSS PA3 PA4 PC5 PB0 PJ3 PJ4 PG1 PE7 PE14 VCAP VDD
LDO PH7 PB13 PB14 PD8 VSS
PC14-
OSC32_
IN
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
PH0-
OSC_
OUT
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1234567891011121314151617
DS12110 Rev 7 63/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
Table 9 and Table 10 to Table 20 show STM32H743xI/G pin/ball definition and alternate
functions, respectively. Refer to Table 2 for the features and peripherals available on
STM32H742xI/G devices.
Table 8. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
ANA Analog-only Input
I/O structure
FT 5 V tolerant I/O
TT 3.3 V tolerant I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Option for TT and FT I/Os
_f I2C FM+ option
_a analog option (supplied by VDDA)
_u USB option (supplied by VDD33USB)
_h High-speed low-voltage I/O
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
Pin functions
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
Pin descriptions STM32H742xI/G STM32H743xI/G
64/357 DS12110 Rev 7
Table 9. Pin/ball definition
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
1 A3 1 A2 A2 1 1 C3 PE2 I/O FT_h -
TRACECLK, SAI1_CK1,
SPI4_SCK,
SAI1_MCLK_A,
SAI4_MCLK_A,
QUADSPI_BK1_IO2,
SAI4_CK1,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
-
2 B3 2 B2 A1 2 2 D3 PE3 I/O FT_h -
TRACED0, TIM15_BKIN,
SAI1_SD_B, SAI4_SD_B,
FMC_A19, EVENTOUT
-
3 C3 3 A1 B1 3 3 D2 PE4 I/O FT_h -
TRACED1, SAI1_D2,
DFSDM1_DATIN3,
TIM15_CH1N,
SPI4_NSS, SAI1_FS_A,
SAI4_FS_A, SAI4_D2,
FMC_A20, DCMI_D4,
LCD_B0, EVENTOUT
-
4 D3 4 C3 B2 4 4 D1 PE5 I/O FT_h -
TRACED2, SAI1_CK2,
DFSDM1_CKIN3,
TIM15_CH1, SPI4_MISO,
SAI1_SCK_A,
SAI4_SCK_A, SAI4_CK2,
FMC_A21, DCMI_D6,
LCD_G0, EVENTOUT
-
5 E3 5 C2 B3 5 5 E5 PE6 I/O FT_h -
TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI, SAI1_SD_A,
SAI4_SD_A, SAI4_D1,
SAI2_MCLK_B,
TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
-
- - - M4 H10 - - A1 VSS S - - - -
-- -A3- - - - VDD S -- - -
6 B2 6 E3 C1 6 6 B1 VBAT S - - - -
- - - - J6 - - B2 VSS S - - - -
- - - - D2 7 7 E4 PI8 I/O FT - EVENTOUT RTC_TAMP2/
WKUP3
7 A2 7 D3 D1 8 8 E3 PC13 I/O FT - EVENTOUT
RTC_TAMP1/
RTC_TS/
WKUP2
- - - - J7 - - B6 VSS S - - - -
DS12110 Rev 7 65/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
8 A1 8 C1 E1 9 9 C2
PC14-
OSC32_
IN
(OSC32_
IN)(1)
I/O FT - EVENTOUT OSC32_IN
9 B1 9 B1 F1 10 10 C1
PC15-
OSC32_
OUT
(OSC32_
OUT)(1)
I/O FT - EVENTOUT OSC32_
OUT
- - - - D3 11 11 E2 PI9 I/O FT_h -
UART4_RX,
FDCAN1_RX, FMC_D30,
LCD_VSYNC,
EVENTOUT
-
- - - - E3 12 12 F3 PI10 I/O FT_h -
FDCAN1_RXFD_MODE,
ETH_MII_RX_ER,
FMC_D31, LCD_HSYNC,
EVENTOUT
- - - E1 E4 13 13 F4 PI11 I/O FT -
LCD_G6,
OTG_HS_ULPI_DIR,
EVENTOUT
WKUP4
- C2 - D2 F2 14 14 A17 VSS S - - - -
- D2 - D1 F3 15 15 E6 VDD S - - - -
-- - - - - -E1
(2) NC - - - - -
-- - - - - -F1
(3) NC - - - - -
-- - - - - -G2
(4) NC - - - - -
- - 10 F3 E2 16 16 G4 PF0 I/O FT_f - I2C2_SDA, FMC_A0,
EVENTOUT -
- - 11 E4 H3 17 17 G3 PF1 I/O FT_f - I2C2_SCL, FMC_A1,
EVENTOUT -
- - 12 F4 H2 18 18 G1 PF2 I/O FT - I2C2_SMBA, FMC_A2,
EVENTOUT -
- - - F2 - - 19 H1 PI12 I/O FT - LCD_HSYNC,
EVENTOUT -
- - - F1 - - 20 H2 PI13 I/O FT - LCD_VSYNC,
EVENTOUT -
- - - - - - 21 H3 PI14 I/O FT_h - LCD_CLK, EVENTOUT -
- - 13 E5 J2 19 22 H4 PF3 I/O FT_
ha - FMC_A3, EVENTOUT ADC3_INP5
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H742xI/G STM32H743xI/G
66/357 DS12110 Rev 7
- - 14 G3 J3 20 23 J5 PF4 I/O FT_
ha - FMC_A4, EVENTOUT ADC3_INN5,
ADC3_INP9
- - 15 F5 K3 21 24 J4 PF5 I/O FT_
ha - FMC_A5, EVENTOUT ADC3_INP4
10 - 16 B10 G2 22 25 C10 VSS S - - - -
11 - 17 G1 G3 23 26 E9 VDD S - - - -
- - 18 G4 K2 24 27 K2 PF6 I/O FT_
ha -
TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
SAI4_SD_B,
QUADSPI_BK1_IO3,
EVENTOUT
ADC3_INN4,
ADC3_INP8
- - 19 F6 K1 25 28 K3 PF7 I/O FT_
ha -
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B,
UART7_TX,
SAI4_MCLK_B,
QUADSPI_BK1_IO2,
EVENTOUT
ADC3_INP3
- - 20 H4 L3 26 29 K4 PF8 I/O FT_
ha -
TIM16_CH1N,
SPI5_MISO,
SAI1_SCK_B,
UART7_RTS/UART7_DE
, SAI4_SCK_B,
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
ADC3_INN3,
ADC3_INP7
- - 21 G5 L2 27 30 L4 PF9 I/O FT_
ha -
TIM17_CH1N,
SPI5_MOSI, SAI1_FS_B,
UART7_CTS,
SAI4_FS_B, TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
ADC3_INP2
- - 22 H3 L1 28 31 L3 PF10 I/O FT_
ha -
TIM16_BKIN, SAI1_D3,
QUADSPI_CLK,
SAI4_D3, DCMI_D11,
LCD_DE, EVENTOUT
ADC3_INN2,
ADC3_INP6
12 C1 23 H1 G1 29 32 J2
PH0-
OSC_IN
(PH0)
I/O FT - EVENTOUT OSC_IN
13 D1 24 H2 H1 30 33 J1
PH1-
OSC_OUT
(PH1)
I/O FT - EVENTOUT OSC_OUT
14 E1 25 G6 J1 31 34 K1 NRST I/O RST - - -
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12110 Rev 7 67/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
15 F1 26 J1 M2 32 35 L2 PC0 I/O FT_a -
DFSDM1_CKIN0,
DFSDM1_DATIN4,
SAI2_FS_B,
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC123_
INP10
16 F2 27 J2 M3 33 36 M2 PC1 I/O FT_
ha -
TRACED0, SAI1_D1,
DFSDM1_DATIN0,
DFSDM1_CKIN4,
SPI2_MOSI/I2S2_SDO,
SAI1_SD_A, SAI4_SD_A,
SDMMC2_CK, SAI4_D1,
ETH_MDC,
MDIOS_MDC,
EVENTOUT
ADC123_
INN10,
ADC123_
INP11,
RTC_TAMP3/W
KUP5
-- - - - - -M3
(5) PC2 I/O FT_a -
CDSLEEP,
DFSDM1_CKIN1,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0,
EVENTOUT
ADC123_
INN11,
ADC123_
INP12
17
(6) E2(6) 28(6) K2(6) M4(6) 34(6) 37(6) R1(5) PC2_C ANA TT_a - ADC3_INN1,
ADC3_INP0
-- - - - - -M4
(5) PC3 I/O FT_a - CSLEEP,
DFSDM1_DATIN1,
SPI2_MOSI/I2S2_SDO,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
ADC12_INN12,
ADC12_INP13
18
(6) F3(6) 29(6) K1(6) M5(6) 35(6) 38(6) R2(5) PC3_C ANA TT_a - ADC3_INP1
- F5 30 - G3 36 39 E11 VDD S - - - -
- E6 - B3 J10 - - C13 VSS S - - - -
19 G1 31 J3 M1 37 40 P1 VSSA S - - - -
- - - - N1 - - N1 VREF- S - - - -
20 -(7) 32 L2 P1 38 41 M1 VREF+ S - - - -
21 H1 33 L1 R1 39 42 L1 VDDA S - - - -
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H742xI/G STM32H743xI/G
68/357 DS12110 Rev 7
22 G2 34 J5 N3 40 43 N5(5) PA0 I/O FT_a - TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
TIM15_BKIN,
USART2_CTS/USART2_
NSS, UART4_TX,
SDMMC2_CMD,
SAI2_SD_B,
ETH_MII_CRS,
EVENTOUT
ADC1_INP16,
WKUP0
-- - - - - -T1
(5) PA0_C ANA TT_a - ADC12_INN1,
ADC12_INP0
23 H2 35 K4 N2 41 44 N4(5) PA1 I/O FT_
ha -TIM2_CH2, TIM5_CH2,
LPTIM3_OUT,
TIM15_CH1N,
USART2_RTS/USART2_
DE, UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCLK_B,
ETH_MII_RX_CLK/ETH_
RMII_REF_CLK,
LCD_R2, EVENTOUT
ADC1_INN16,
ADC1_INP17
-- - - - - -T2
(5) PA1_C ANA TT_a - ADC12_INP1
24 J2 36 N1 P2 42 45 N3 PA2 I/O FT_a -
TIM2_CH3, TIM5_CH3,
LPTIM4_OUT,
TIM15_CH1,
USART2_TX,
SAI2_SCK_B,
ETH_MDIO,
MDIOS_MDIO, LCD_R1,
EVENTOUT
ADC12_INP14,
WKUP1
- - - N2F44346 N2 PH2 I/O
FT_
ha -
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B,
ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
ADC3_INP13
-K1 - M1 - - - F5 VDD S - - - -
- J1 - M7 J8 - - C16 VSS S - - - -
-- -M3G44447P2 PH3 I/O
FT_
ha -
QUADSPI_BK2_IO1,
SAI2_MCLK_B,
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
ADC3_INN13,
ADC3_INP14
- - - K3H44548 P3 PH4 I/OFT_fa-
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT,
LCD_G4, EVENTOUT
ADC3_INN14,
ADC3_INP15
-- -L3J44649P4 PH5 I/OFT_fa-
I2C2_SDA, SPI5_NSS,
FMC_SDNWE,
EVENTOUT
ADC3_INN15,
ADC3_INP16
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12110 Rev 7 69/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
25 K2 37 N3 R2 47 50 U2 PA3 I/O FT_
ha -
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT,
TIM15_CH2,
USART2_RX, LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
ADC12_INP15
26 - 38 G2 K6 - 51 F2(4) VSS S - - - -
- - - - L4 48 - - VSS S - - - -
27 - 39 - K4 49 52 G5 VDD S - - - -
28 G3 40 H6 N4 50 53 U3 PA4 I/O TT_a -
D1PWREN, TIM5_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK, SPI6_NSS,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
ADC12_INP18,
DAC1_OUT1
29 H3 41 L4 P4 51 54 T3 PA5 I/O TT_
ha -
D2PWREN,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
SPI6_SCK,
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
ADC12_INN18,
ADC12_INP19,
DAC1_OUT2
30 J3 42 K5 P3 52 55 R3 PA6 I/O FT_a -
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
SPI6_MISO, TIM13_CH1,
TIM8_BKIN_COMP12,
MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
ADC12_INP3
31 K3 43 J6 R3 53 56 R5 PA7 I/O TT_a -
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SDO,
SPI6_MOSI, TIM14_CH1,
ETH_MII_RX_DV/ETH_R
MII_CRS_DV,
FMC_SDNWE,
EVENTOUT
ADC12_INN3,
ADC12_INP7,
OPAMP1_VINM
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H742xI/G STM32H743xI/G
70/357 DS12110 Rev 7
32 G4 44 K6 N5 54 57 T4 PC4 I/O TT_a -
DFSDM1_CKIN2,
I2S1_MCK,
SPDIFRX1_IN3,
ETH_MII_RXD0/ETH_R
MII_RXD0, FMC_SDNE0,
EVENTOUT
ADC12_INP4,
OPAMP1_
VOUT,
COMP1_INM
33 H4 45 N5 P5 55 58 U4 PC5 I/O TT_a -
SAI1_D3,
DFSDM1_DATIN2,
SPDIFRX1_IN4,
SAI4_D3,
ETH_MII_RXD1/ETH_R
MII_RXD1,
FMC_SDCKE0,
COMP1_OUT,
EVENTOUT
ADC12_INN4,
ADC12_INP8,
OPAMP1_
VINM
-- -N4- -59G13VDD S -- - -
- - - H12 J9 - 60 R4 VSS S - - - -
34 J4 46 M5 R5 56 61 U5 PB0 I/O FT_a -
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
DFSDM1_CKOUT,
UART4_CTS, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2,
LCD_G1, EVENTOUT
ADC12_INN5,
ADC12_INP9,
OPAMP1_VINP,
COMP1_INP
35 K4 47 L5 R4 57 62 T5 PB1 I/O TT_u -
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN1,
LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
LCD_G0, EVENTOUT
ADC12_INP5,
COMP1_INM
36 G5 48 L6 M6 58 63 R6 PB2 I/O FT_
ha -
RTC_OUT, SAI1_D1,
DFSDM1_CKIN1,
SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
SAI4_SD_A,
QUADSPI_CLK,
SAI4_D1, EVENTOUT
COMP1_INP
-- - - - -64P5 PI15I/OFT-LCD_G2, LCD_R0,
EVENTOUT -
-- -J4- -65N6 PJ0 I/OFT- LCD_R7, LCD_R1,
EVENTOUT -
- - - H5 - - 66 P6 PJ1 I/O FT - LCD_R2, EVENTOUT -
- - - - - - 67 T6 PJ2 I/O FT - LCD_R3, EVENTOUT -
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12110 Rev 7 71/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
- - - - - - 68 U6 PJ3 I/O FT - LCD_R4, EVENTOUT -
- - - - - - 69 U7 PJ4 I/O FT - LCD_R5, EVENTOUT -
- - 49 M6 R6 59 70 T7 PF11 I/O FT_a -
SPI5_MOSI, SAI2_SD_B,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
ADC1_INP2
- - 50 N6 P6 60 71 R7 PF12 I/O FT_
ha - FMC_A6, EVENTOUT ADC1_INN2,
ADC1_INP6
- - 51 M11 M8 61 72 J3 VSS S - - - -
- - 52 - N86273 H5 VDD S - - - -
- - 53 G7 N6 63 74 P7 PF13 I/O FT_
ha -
DFSDM1_DATIN6,
I2C4_SMBA, FMC_A7,
EVENTOUT
ADC2_INP2
- - 54 H7 R7 64 75 P8 PF14 I/O FT_
fha -
DFSDM1_CKIN6,
I2C4_SCL, FMC_A8,
EVENTOUT
ADC2_INN2,
ADC2_INP6
- - 55 J7 P7 65 76 R9 PF15 I/O FT_fh - I2C4_SDA, FMC_A9,
EVENTOUT -
- - 56 K7 N7 66 77 T8 PG0 I/O FT_h - FMC_A10, EVENTOUT -
- - - M2 F6 - - J16 VSS S - - - -
- - - A10 - - - H13 VDD S - - - -
- - 57 L7 M7 67 78 U8 PG1 I/O TT_h - FMC_A11, EVENTOUT OPAMP2_
VINM
37 H5 58 G8 R8 68 79 U9 PE7 I/O TT_
ha -
TIM1_ETR,
DFSDM1_DATIN2,
UART7_RX,
QUADSPI_BK2_IO0,
FMC_D4/FMC_DA4,
EVENTOUT
OPAMP2_
VOUT,
COMP2_INM
38 J5 59 H8 P8 69 80 T9 PE8 I/O TT_
ha -
TIM1_CH1N,
DFSDM1_CKIN2,
UART7_TX,
QUADSPI_BK2_IO1,
FMC_D5/FMC_DA5,
COMP2_OUT,
EVENTOUT
OPAMP2_
VINM
39 K5 60 J8 P9 70 81 P9 PE9 I/O TT_
ha -
TIM1_CH1,
DFSDM1_CKOUT,
UART7_RTS/UART7_DE
, QUADSPI_BK2_IO2,
FMC_D6/FMC_DA6,
EVENTOUT
OPAMP2_VINP,
COMP2_INP
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H742xI/G STM32H743xI/G
72/357 DS12110 Rev 7
- - 61 C12 M9 71 82 J17 VSS S - - - -
- - 62C13N97283J13 VDD S - - - -
40 G6 63 M8 R9 73 84 N9 PE10 I/O FT_
ha -
TIM1_CH2N,
DFSDM1_DATIN4,
UART7_CTS,
QUADSPI_BK2_IO3,
FMC_D7/FMC_DA7,
EVENTOUT
COMP2_INM
41 H6 64 N8 P10 74 85 P10 PE11 I/O FT_
ha -
TIM1_CH2,
DFSDM1_CKIN4,
SPI4_NSS, SAI2_SD_B,
FMC_D8/FMC_DA8,
LCD_G3, EVENTOUT
COMP2_INP
42 J6 65 L8 R10 75 86 R10 PE12 I/O FT_h -
TIM1_CH3N,
DFSDM1_DATIN5,
SPI4_SCK,
SAI2_SCK_B,
FMC_D9/FMC_DA9,
COMP1_OUT, LCD_B4,
EVENTOUT
-
43 K6 66 K8 N11 76 87 T10 PE13 I/O FT_h -
TIM1_CH3,
DFSDM1_CKIN5,
SPI4_MISO, SAI2_FS_B,
FMC_D10/FMC_DA10,
COMP2_OUT, LCD_DE,
EVENTOUT
-
- - - L12 F7 - - T12 VSS S - - - -
- - - H13 - - - K13 VDD S - - - -
44 G7 67 J9 P11 77 88 U10 PE14 I/O FT_h -
TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B,
FMC_D11/FMC_DA11,
LCD_CLK, EVENTOUT
-
45 H7 68 N9 R11 78 89 R11 PE15 I/O FT_h -
TIM1_BKIN,
FMC_D12/FMC_DA12,
TIM1_BKIN_COMP12/
COMP_TIM1_BKIN,
LCD_R7, EVENTOUT
-
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12110 Rev 7 73/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
46 J7 69 L9 R12 79 90 P11 PB10 I/O FT_f -
TIM2_CH3,
HRTIM_SCOUT,
LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7,
USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
-
47 K7 70 M9 R13 80 91 P12 PB11 I/O FT_f -
TIM2_CH4,
HRTIM_SCIN,
LPTIM2_ETR,
I2C2_SDA,
DFSDM1_CKIN7,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, LCD_G5,
EVENTOUT
-
48 F8 71 N10 M10 81 92 U11 VCAP S - - - -
49 E4 - - K7 - 93 - VSS S - - - -
- - - M10 - - - U12 VDDLDO
(8) S-- - -
50 - 72 M1 N10 82 94 L13 VDD S - - - -
- - - - - - 95 R12 PJ5 I/O FT - LCD_R6, EVENTOUT -
-- - -M118396T11 PH6 I/OFT-
TIM12_CH1,
I2C2_SMBA, SPI5_SCK,
ETH_MII_RXD2,
FMC_SDNE1, DCMI_D8,
EVENTOUT
-
- - - - N12 84 97 U13 PH7 I/O FT_fa -
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1,
DCMI_D9, EVENTOUT
-
-- - -M128598T13 PH8 I/O
FT_fh
a-
TIM5_ETR, I2C3_SDA,
FMC_D16,
DCMI_HSYNC, LCD_R2,
EVENTOUT
-
- - - - F8 - - - VSS S - - - -
- - - L13 - - - M13 VDD S - - - -
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H742xI/G STM32H743xI/G
74/357 DS12110 Rev 7
- - - - M13 86 99 R13 PH9 I/O FT_h -
TIM12_CH2,
I2C3_SMBA, FMC_D17,
DCMI_D0, LCD_R3,
EVENTOUT
-
- - - K9 L13 87 100 P13 PH10 I/O FT_h -
TIM5_CH1, I2C4_SMBA,
FMC_D18, DCMI_D1,
LCD_R4, EVENTOUT
-
- - - L10 L12 88 101 P14 PH11 I/O FT_fh -
TIM5_CH2, I2C4_SCL,
FMC_D19, DCMI_D2,
LCD_R5, EVENTOUT
-
- - - K10 K12 89 102 R14 PH12 I/O FT_fh -
TIM5_CH3, I2C4_SDA,
FMC_D20, DCMI_D3,
LCD_R6, EVENTOUT
-
- - - - H12 90 - N16 VSS S - - - -
- - - N11 J12 91 103 P17 VDD S - - - -
51 K8 73 N12 P12 92 104 T14 PB12 I/O FT_u -
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1,
USART3_CK,
FDCAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RM
II_TXD0, OTG_HS_ID,
TIM1_BKIN_COMP12,
UART5_RX, EVENTOUT
52 J8 74 L11 P13 93 105 U14 PB13 I/O FT_u -
TIM1_CH1N,
LPTIM2_OUT,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
USART3_CTS/USART3_
NSS, FDCAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RM
II_TXD1, UART5_TX,
EVENTOUT
OTG_HS_
VBUS
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12110 Rev 7 75/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
53 H10 75 N13 R14 94 106 U15 PB14 I/O FT_u -
TIM1_CH2N,
TIM12_CH1,
TIM8_CH2N,
USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
USART3_RTS/
USART3_DE,
UART4_RTS/UART4_DE
, SDMMC2_D0,
OTG_HS_DM,
EVENTOUT
-
54 G10 76 M13 R15 95 107 T15 PB15 I/O FT_u -
RTC_REFIN,
TIM1_CH3N,
TIM12_CH2,
TIM8_CH3N,
USART1_RX,
SPI2_MOSI/I2S2_SDO,
DFSDM1_CKIN2,
UART4_CTS,
SDMMC2_D1,
OTG_HS_DP,
EVENTOUT
-
55 K9 77 M12 P15 96 108 U16 PD8 I/O FT_h -
DFSDM1_CKIN3,
SAI3_SCK_B,
USART3_TX,
SPDIFRX1_IN2,
FMC_D13/FMC_DA13,
EVENTOUT
-
56 J9 78 K11 P14 97 109 T17 PD9 I/O FT_h -
DFSDM1_DATIN3,
SAI3_SD_B,
USART3_RX,
FDCAN2_RXFD_MODE,
FMC_D14/FMC_DA14,
EVENTOUT
-
57 H9 79 K12 N15 98 110 T16 PD10 I/O FT_h -
DFSDM1_CKOUT,
SAI3_FS_B,
USART3_CK,
FDCAN2_TXFD_MODE,
FMC_D15/FMC_DA15,
LCD_B3, EVENTOUT
-
- - - N7 - - - N12 VDD S - - - -
- - - - F9 - - U17 VSS S - - - -
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H742xI/G STM32H743xI/G
76/357 DS12110 Rev 7
58 G9 80 J10 N14 99 111 R15 PD11 I/O FT_h -
LPTIM2_IN2,
I2C4_SMBA,
USART3_CTS/USART3_
NSS,
QUADSPI_BK1_IO0,
SAI2_SD_A, FMC_A16,
EVENTOUT
-
59 K10 81 K13 N13 100 112 R16 PD12 I/O FT_fh -
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
USART3_RTS/USART3_
DE, QUADSPI_BK1_IO1,
SAI2_FS_A, FMC_A17,
EVENTOUT
-
60 J10 82 J11 M15 101 113 R17 PD13 I/O FT_fh -
LPTIM1_OUT,
TIM4_CH2, I2C4_SDA,
QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
EVENTOUT
-
- - 83 - K8 102 114 - VSS S - - - -
- - 84 - J13 103 115 N11 VDD S - - - -
61 H8 85 J13 M14 104 116 P16 PD14 I/O FT_h -
TIM4_CH3,
SAI3_MCLK_B,
UART8_CTS,
FMC_D0/FMC_DA0,
EVENTOUT
-
62 G8 86 J12 L14 105 117 P15 PD15 I/O FT_h -
TIM4_CH4,
SAI3_MCLK_A,
UART8_RTS/UART8_DE
, FMC_D1/FMC_DA1,
EVENTOUT
-
-- - - - -118N15 PJ6 I/OFT-
TIM8_CH2, LCD_R7,
EVENTOUT -
-- - - - -119N14 PJ7 I/OFT-
TRGIN, TIM8_CH2N,
LCD_G0, EVENTOUT -
-- - - - - -N10VDD S - -
- - - - F10 - - R8 VSS S - -
- - - - - - 120 N13 PJ8 I/O FT -
TIM1_CH3N, TIM8_CH1,
UART8_TX, LCD_G1,
EVENTOUT
-
- - - - - - 121 M14 PJ9 I/O FT -
TIM1_CH3, TIM8_CH1N,
UART8_RX, LCD_G2,
EVENTOUT
-
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12110 Rev 7 77/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
- - - - - - 122 L14 PJ10 I/O FT -
TIM1_CH2N, TIM8_CH2,
SPI5_MOSI, LCD_G3,
EVENTOUT
-
- - - - - - 123 K14 PJ11 I/O FT -
TIM1_CH2, TIM8_CH2N,
SPI5_MISO, LCD_G4,
EVENTOUT
-
- - - - - - 124 N8 VDD S - -
- - - - G6 - 125 U1 VSS S - - - -
-- - - - - -
N17
(2) NC - - - - -
-- - - - - -
M16
(2) NC - - - - -
-- - - - - -
M17
(2) NC - - - - -
- - - - - - - K15 VSS S - - - -
- - - - - - - L16(2) NC - - - - -
- - - - - - - L17(2) NC - - - - -
-- - - - - -
K16
(2) NC - - - - -
-- - - - - -
K17
(2) NC - - - - -
- - - - - - - L15 VSS S - - - -
- - - - - - 126 J14 PK0 I/O FT -
TIM1_CH1N, TIM8_CH3,
SPI5_SCK, LCD_G5,
EVENTOUT
-
- - - - - - 127 J15 PK1 I/O FT -
TIM1_CH1, TIM8_CH3N,
SPI5_NSS, LCD_G6,
EVENTOUT
-
- - - - - - 128 H17 PK2 I/O FT -
TIM1_BKIN, TIM8_BKIN,
TIM8_BKIN_COMP12,
TIM1_BKIN_COMP12,
LCD_G7, EVENTOUT
-
- - 87 H9 L15 106 129 H16 PG2 I/O FT_h -
TIM8_BKIN,
TIM8_BKIN_COMP12,
FMC_A12, EVENTOUT
-
- - 88 H10 K15 107 130 H15 PG3 I/O FT_h -
TIM8_BKIN2,
TIM8_BKIN2_COMP12,
FMC_A13, EVENTOUT
-
- - - - G7 - - - VSS S - - - -
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H742xI/G STM32H743xI/G
78/357 DS12110 Rev 7
-- - - - - -N7 VDD S -- - -
- - 89 F8 K14 108 131 H14 PG4 I/O FT_h -
TIM1_BKIN2,
TIM1_BKIN2_COMP12,
FMC_A14/FMC_BA0,
EVENTOUT
-
- - 90 H11 K13 109 132 G14 PG5 I/O FT_h -
TIM1_ETR,
FMC_A15/FMC_BA1,
EVENTOUT
-
- - 91 G9 J15 110 133 G15 PG6 I/O FT_h -
TIM17_BKIN,
HRTIM_CHE1,
QUADSPI_BK1_NCS,
FMC_NE3, DCMI_D12,
LCD_R7, EVENTOUT
-
- - 92 G10 J14 111 134 F16 PG7 I/O FT_h -
HRTIM_CHE2,
SAI1_MCLK_A,
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
-
- - 93 G11 H14 112 135 F15 PG8 I/O FT_h -
TIM8_ETR, SPI6_NSS,
USART6_RTS/USART6_
DE, SPDIFRX1_IN3,
ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
-
- - 94 - G12 113 136 G16 VSS S - - - -
- - - G12 - - - G17 VDD50
USB S-- - -
- F6 95 G13 H13 114 137 F17 VDD33
USB S-- - -
-- - - - - -M5 VDD S -- - -
63 F10 96 F9 H15 115 138 F14 PC6 I/O FT_h -
HRTIM_CHA1,
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
I2S2_MCK, USART6_TX,
SDMMC1_D0DIR,
FMC_NWAIT,
SDMMC2_D6,
SDMMC1_D6, DCMI_D0,
LCD_HSYNC,
EVENTOUT
SWPMI_IO
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12110 Rev 7 79/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
64 E10 97 F10 G15 116 139 F13 PC7 I/O FT_h -
TRGIO, HRTIM_CHA2,
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3,
I2S3_MCK,
USART6_RX,
SDMMC1_D123DIR,
FMC_NE1,
SDMMC2_D7,
SWPMI_TX,
SDMMC1_D7, DCMI_D1,
LCD_G6, EVENTOUT
-
65 F9 98 F12 G14 117 140 E13 PC8 I/O FT_h -
TRACED1,
HRTIM_CHB1,
TIM3_CH3, TIM8_CH3,
USART6_CK,
UART5_RTS/UART5_DE
, FMC_NE2/FMC_NCE,
SWPMI_RX,
SDMMC1_D0, DCMI_D2,
EVENTOUT
-
66 E9 99 F11 F14 118 141 E14 PC9 I/O FT_fh -
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
QUADSPI_BK1_IO0,
LCD_G3,
SWPMI_SUSPEND,
SDMMC1_D1, DCMI_D3,
LCD_B2, EVENTOUT
-
- - - - G8 - - - VSS S - - -
-- - - - - -L5 VDD S -- -
67 D9 100 E12 F15 119 142 E15 PA8 I/O FT_
fha -
MCO1, TIM1_CH1,
HRTIM_CHB2,
TIM8_BKIN2, I2C3_SCL,
USART1_CK,
OTG_FS_SOF,
UART7_RX,
TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6,
EVENTOUT
-
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H742xI/G STM32H743xI/G
80/357 DS12110 Rev 7
68 C9 101 E11 E15 120 143 D15 PA9 I/O FT_u -
TIM1_CH2,
HRTIM_CHC1,
LPUART1_TX,
I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX,
FDCAN1_RXFD_MODE,
DCMI_D0, LCD_R5,
EVENTOUT
OTG_FS_VBUS
69 D10 102 E10 D15 121 144 D14 PA10 I/O FT_u -
TIM1_CH3,
HRTIM_CHC2,
LPUART1_RX,
USART1_RX,
FDCAN1_TXFD_MODE,
OTG_FS_ID,
MDIOS_MDIO, LCD_B4,
DCMI_D1, LCD_B1,
EVENTOUT
-
70 C10 103 F13 C15 122 145 E17 PA11 I/O FT_u -
TIM1_CH4,
HRTIM_CHD1,
LPUART1_CTS,
SPI2_NSS/I2S2_WS,
UART4_RX,
USART1_CTS/USART1_
NSS, FDCAN1_RX,
OTG_FS_DM, LCD_R4,
EVENTOUT
-
71 B10 104 E13 B15 123 146 E16 PA12 I/O FT_u -
TIM1_ETR,
HRTIM_CHD2,
LPUART1_RTS/
LPUART1_DE,
SPI2_SCK/I2S2_CK,
UART4_TX,
USART1_RTS/USART1_
DE, SAI2_FS_B,
FDCAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT
-
72 A10 105 D11 A15 124 147 C15
PA13
(JTMS/SW
DIO)
I/O FT - JTMS-SWDIO,
EVENTOUT -
73 E7 106 D13 F13 125 148 D17 VCAP S - - - -
74 E5 107 - F12 126 149 - VSS S - - - -
- - - D12 - - - C17 VDDLDO
(8) -- - -
75 - 108 - G13 127 150 K5 VDD S - - - -
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12110 Rev 7 81/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
- - - - E12 128 151 D16 PH13 I/O FT_h -
TIM8_CH1N, UART4_TX,
FDCAN1_TX, FMC_D21,
LCD_G2, EVENTOUT
-
- - - - E13 129 152 B17 PH14 I/O FT_h -
TIM8_CH2N,
UART4_RX,
FDCAN1_RX, FMC_D22,
DCMI_D4, LCD_G3,
EVENTOUT
-
- - - - D13 130 153 B16 PH15 I/O FT_h -
TIM8_CH3N,
FDCAN1_TXFD_MODE,
FMC_D23, DCMI_D11,
LCD_G4, EVENTOUT
-
- - - A13 E14 131 154 A16 PI0 I/O FT_h -
TIM5_CH4,
SPI2_NSS/I2S2_WS,
FDCAN1_RXFD_MODE,
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
-
- - - - G9 - - - VSS S - - - -
- - - B13 D14 132 155 A15 PI1 I/O FT_h -
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
TIM8_BKIN2_COMP12,
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
-
- - - A6 C14 133 156 B15 PI2 I/O FT_h -
TIM8_CH4,
SPI2_MISO/I2S2_SDI,
FMC_D26, DCMI_D9,
LCD_G7, EVENTOUT
-
- - - B7 C13 134 157 C14 PI3 I/O FT_h -
TIM8_ETR,
SPI2_MOSI/I2S2_SDO,
FMC_D27, DCMI_D10,
EVENTOUT
-
- - - - D9 135 - - VSS S - - - -
- - - - C9 136 158 - VDD S - - - -
76 A9 109 B12 A14 137 159 B14
PA14
(JTCK/SW
CLK)
I/O FT - JTCK-SWCLK,
EVENTOUT -
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H742xI/G STM32H743xI/G
82/357 DS12110 Rev 7
77 A8 110 C11 A13 138 160 A14 PA15
(JTDI) I/O FT -
JTDI,
TIM2_CH1/TIM2_ETR,
HRTIM_FLT1, CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
SPI6_NSS,
UART4_RTS/UART4_DE
, UART7_TX,
EVENTOUT
-
78 B9 111 A12 B14 139 161 A13 PC10 I/O FT_
ha -
HRTIM_EEV1,
DFSDM1_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX,
UART4_TX,
QUADSPI_BK1_IO1,
SDMMC1_D2, DCMI_D8,
LCD_R2, EVENTOUT
-
79 B8 112 B11 B13 140 162 B13 PC11 I/O FT_h -
HRTIM_FLT2,
DFSDM1_DATIN5,
SPI3_MISO/I2S3_SDI,
USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3, DCMI_D4,
EVENTOUT
-
80 C8 113 A11 A12 141 163 C12 PC12 I/O FT_h -
TRACED3,
HRTIM_EEV2,
SPI3_MOSI/I2S3_SDO,
USART3_CK,
UART5_TX,
SDMMC1_CK, DCMI_D9,
EVENTOUT
-
- - - - G10 - - - VSS S - - - -
81 D8 114 D10 B12 142 164 D13 PD0 I/O FT_h -
DFSDM1_CKIN6,
SAI3_SCK_A,
UART4_RX,
FDCAN1_RX,
FMC_D2/FMC_DA2,
EVENTOUT
-
82 E8 115 C10 C12 143 165 E12 PD1 I/O FT_h -
DFSDM1_DATIN6,
SAI3_SD_A, UART4_TX,
FDCAN1_TX,
FMC_D3/FMC_DA3,
EVENTOUT
-
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12110 Rev 7 83/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
83 B7 116 E9 D12 144 166 D12 PD2 I/O FT_h -
TRACED2, TIM3_ETR,
UART5_RX,
SDMMC1_CMD,
DCMI_D11, EVENTOUT
-
84 C7 117 D9 D11 145 167 B12 PD3 I/O FT_h -
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
USART2_CTS/USART2_
NSS, FMC_CLK,
DCMI_D5, LCD_G7,
EVENTOUT
-
85 D7 118 C9 D10 146 168 A12 PD4 I/O FT_h -
HRTIM_FLT3,
SAI3_FS_A,
USART2_RTS/USART2_
DE,
FDCAN1_RXFD_MODE,
FMC_NOE, EVENTOUT
-
86 B6 119 A9 C11 147 169 A11 PD5 I/O FT_h -
HRTIM_EEV3,
USART2_TX,
FDCAN1_TXFD_MODE,
FMC_NWE, EVENTOUT
-
- - 120 - D8 148 170 - VSS S - - - -
- - 121 - C8 149 171 - VDD S - - - -
87 C6 122 B9 B11 150 172 B11 PD6 I/O FT_h -
SAI1_D1,
DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A,
USART2_RX,
SAI4_SD_A,
FDCAN2_RXFD_MODE,
SAI4_D1, SDMMC2_CK,
FMC_NWAIT,
DCMI_D10, LCD_B2,
EVENTOUT
-
88 D6 123 D8 A11 151 173 C11 PD7 I/O FT_h -
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1,
USART2_CK,
SPDIFRX1_IN1,
SDMMC2_CMD,
FMC_NE1, EVENTOUT
-
- - - - - - 174 D11 PJ12 I/O FT - TRGOUT, LCD_G3,
LCD_B0, EVENTOUT -
- - - - - - 175 E10 PJ13 I/O FT - LCD_B4, LCD_B1,
EVENTOUT -
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H742xI/G STM32H743xI/G
84/357 DS12110 Rev 7
- - - - - - 176 D10 PJ14 I/O FT - LCD_B2, EVENTOUT -
- - - - - - 177 B10 PJ15 I/O FT - LCD_B3, EVENTOUT -
- - - - H6 - - - VSS S - - - -
-- -A7- - - - VDD S -- - -
- - 124 C8 C10 152 178 A10 PG9 I/O FT_h -
SPI1_MISO/I2S1_SDI,
USART6_RX,
SPDIFRX1_IN4,
QUADSPI_BK2_IO2,
SAI2_FS_B,
FMC_NE2/FMC_NCE,
DCMI_VSYNC,
EVENTOUT
-
- - 125 A8 B10 153 179 A9 PG10 I/O FT_h -
HRTIM_FLT5,
SPI1_NSS/I2S1_WS,
LCD_G3, SAI2_SD_B,
FMC_NE3, DCMI_D2,
LCD_B2, EVENTOUT
-
- - 126 B8 B9 154 180 B9 PG11 I/O FT_h -
LPTIM1_IN2,
HRTIM_EEV4,
SPI1_SCK/I2S1_CK,
SPDIFRX1_IN1,
SDMMC2_D2,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
-
- - 127 E8 B8 155 181 C9 PG12 I/O FT_h -
LPTIM1_IN1,
HRTIM_EEV5,
SPI6_MISO,
USART6_RTS/USART6_
DE, SPDIFRX1_IN2,
LCD_B4,
ETH_MII_TXD1/ETH_RM
II_TXD1, FMC_NE4,
LCD_B1, EVENTOUT
-
- - 128 D7 A8 156 182 D9 PG13 I/O FT_h -
TRACED0,
LPTIM1_OUT,
HRTIM_EEV10,
SPI6_SCK,
USART6_CTS/USART6_
NSS,
ETH_MII_TXD0/ETH_RM
II_TXD0, FMC_A24,
LCD_R0, EVENTOUT
-
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12110 Rev 7 85/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
- - 129 C7 A7 157 183 D8 PG14 I/O FT_h -
TRACED1,
LPTIM1_ETR,
SPI6_MOSI,
USART6_TX,
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_RM
II_TXD1, FMC_A25,
LCD_B0, EVENTOUT
-
- - 130 - D7 158 184 - VSS S - - - -
- - 131 - C7 159 185 - VDD S - - - -
- - - - - - 186 C8 PK3 I/O FT - LCD_B4, EVENTOUT -
- - - - - - 187 B8 PK4 I/O FT - LCD_B5, EVENTOUT -
- - - - - - 188 A8 PK5 I/O FT - LCD_B6, EVENTOUT -
- - - - - - 189 C7 PK6 I/O FT - LCD_B7, EVENTOUT -
- - - - - - 190 D7 PK7 I/O FT - LCD_DE, EVENTOUT -
- - - - H7 - - - VSS S - - - -
- - 132 E7 B7 160 191 D6 PG15 I/O FT_h -
USART6_CTS/USART6_
NSS, FMC_SDNCAS,
DCMI_D13, EVENTOUT
-
89 A7 133 F7 A10 161 192 C6
PB3(JTDO
/TRACES
WO)
I/O FT -
JTDO/TRACESWO,
TIM2_CH2,
HRTIM_FLT4,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
SPI6_SCK,
SDMMC2_D2,
CRS_SYNC, UART7_RX,
EVENTOUT
-
90 A6 134 B6 A9 162 193 B7 PB4(NJTR
ST) I/O FT -
NJTRST, TIM16_BKIN,
TIM3_CH1,
HRTIM_EEV6,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS,
SPI6_MISO,
SDMMC2_D3,
UART7_TX, EVENTOUT
-
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H742xI/G STM32H743xI/G
86/357 DS12110 Rev 7
91 C5 135 C6 A6 163 194 A5 PB5 I/O FT -
TIM17_BKIN, TIM3_CH2,
HRTIM_EEV7,
I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
SPI6_MOSI,
FDCAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10, UART5_RX,
EVENTOUT
-
- - - - H8 - - - VSS S - - - -
92 B5 136 A5 B6 164 195 B5 PB6 I/O FT_f -
TIM16_CH1N,
TIM4_CH1,
HRTIM_EEV8,
I2C1_SCL, CEC,
I2C4_SCL, USART1_TX,
LPUART1_TX,
FDCAN2_TX,
QUADSPI_BK1_NCS,
DFSDM1_DATIN5,
FMC_SDNE1, DCMI_D5,
UART5_TX, EVENTOUT
-
93 A5 137 D6 B5 165 196 C5 PB7 I/O FT_fa -
TIM17_CH1N,
TIM4_CH2,
HRTIM_EEV9,
I2C1_SDA, I2C4_SDA,
USART1_RX,
LPUART1_RX,
FDCAN2_TXFD_MODE,
DFSDM1_CKIN5,
FMC_NL, DCMI_VSYNC,
EVENTOUT
PVD_IN
94 D5 138 E6 D6 166 197 E8 BOOT0 I B - - VPP
95 B4 139 B5 A5 167 198 D5 PB8 I/O FT_fh -
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7,
I2C1_SCL, I2C4_SCL,
SDMMC1_CKIN,
UART4_RX,
FDCAN1_RX,
SDMMC2_D4,
ETH_MII_TXD3,
SDMMC1_D4, DCMI_D6,
LCD_B6, EVENTOUT
-
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12110 Rev 7 87/357
STM32H742xI/G STM32H743xI/G Pin descriptions
103
96 A4 140 C5 B4 168 199 D4 PB9 I/O FT_fh -
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
I2C4_SDA,
SDMMC1_CDIR,
UART4_TX,
FDCAN1_TX,
SDMMC2_D5,
I2C4_SMBA,
SDMMC1_D5, DCMI_D7,
LCD_B7, EVENTOUT
-
97 D4 141 D5 A4 169 200 C4 PE0 I/O FT_h -
LPTIM1_ETR,
TIM4_ETR,
HRTIM_SCIN,
LPTIM2_ETR,
UART8_RX,
FDCAN1_RXFD_MODE,
SAI2_MCLK_A,
FMC_NBL0, DCMI_D2,
EVENTOUT
-
98 C4 142 D4 A3 170 201 B4 PE1 I/O FT_h -
LPTIM1_IN2,
HRTIM_SCOUT,
UART8_TX,
FDCAN1_TXFD_MODE,
FMC_NBL1, DCMI_D3,
EVENTOUT
-
-- - - - - -A7VCAPS -- - -
99 - - - D5 - 202 - VSS S - - - -
- F7 143 C4 C6 171 203 E7 PDR_ON I FT - - -
-F4 - B4 - - - A6
VDDLDO
(8) S-- - -
100 - 144 - C5 172 204 - VDD S - - - -
- - - - D4 173 205 A4 PI4 I/O FT_h -
TIM8_BKIN,
SAI2_MCLK_A,
TIM8_BKIN_COMP12,
FMC_NBL2, DCMI_D5,
LCD_B4, EVENTOUT
-
- - - - C4 174 206 A3 PI5 I/O FT_h -
TIM8_CH1,
SAI2_SCK_A,
FMC_NBL3,
DCMI_VSYNC, LCD_B5,
EVENTOUT
-
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H742xI/G STM32H743xI/G
88/357 DS12110 Rev 7
- - - A4 C3 175 207 A2 PI6 I/O FT_h -
TIM8_CH2, SAI2_SD_A,
FMC_D28, DCMI_D6,
LCD_B6, EVENTOUT
-
- - - E2 C2 176 208 B3 PI7 I/O FT_h -
TIM8_CH3, SAI2_FS_A,
FMC_D29, DCMI_D7,
LCD_B7, EVENTOUT
-
- - - - H9 - - - VSS S - - - -
- - - - K9 - - - VSS S - - - -
- - - - K10 - - M15 VSS S - - - -
1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is
valid for all resets except for power-on reset.
2. This ball should remain floating.
3. This ball should not remain floating. It can be connected to VSS or VDD. It is reserved for future use.
4. This ball should be connected to VSS.
5. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG
register. Refer to the product reference manual for a detailed description of the switch configuration bits.
6. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on
Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product
reference manual for a detailed description of the switch configuration bits.
7. VREF+ pin, and consequently the internal voltage reference, are not available on the TFBGA100 package. On this package,
this pin is double-bonded to VDDA which can be connected to an external reference. The internal voltage reference buffer is
not available and must be kept disabled
8. When it is not available on a package, the VDDLDO pin is internally tied to VDD.
Table 9. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
STM32H742xI/G STM32H743xI/G Pin descriptions
DS12110 Rev 7 89/357
Table 10. Port A alternate functions
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4/
5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1/
3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD SYS
Port A
PA0 - TIM2_CH1/
TIM2_ETR TIM5_CH1 TIM8_ETR TIM15_BKIN - -
USART2_
CTS/
USART2_
NSS
UART4_TX SDMMC2_
CMD SAI2_SD_B ETH_MII_
CRS ---
EVENT-
OUT
PA1 - TIM2_CH2 TIM5_CH2 LPTIM3_
OUT
TIM15_
CH1N --
USART2_
RTS/
USART2_
DE
UART4_RX QUADSPI_
BK1_IO3
SAI2_MCLK
_B
ETH_MII_
RX_CLK/
ETH_RMII_
REF_CLK
- - LCD_R2 EVENT-
OUT
PA2 - TIM2_CH3 TIM5_CH3 LPTIM4_
OUT TIM15_CH1 - - USART2_
TX
SAI2_SCK_
B--ETH_MDIO
MDIOS_
MDIO - LCD_R1 EVENT-
OUT
PA3 - TIM2_CH4 TIM5_CH4 LPTIM5_
OUT TIM15_CH2 - - USART2_
RX - LCD_B2 OTG_HS_
ULPI_D0
ETH_MII_
COL - - LCD_B5 EVENT-
OUT
PA4 D1
PWREN -TIM5_ETR- -SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS
USART2_
CK SPI6_NSS - - - OTG_HS_
SOF
DCMI_
HSYNC
LCD_
VSYNC
EVENT-
OUT
PA5 D2
PWREN
TIM2_CH1/
TIM2_ETR -TIM8_
CH1N -SPI1_SCK
/I2S1_CK - - SPI6_SCK - OTG_HS_
ULPI_CK - - - LCD_R4 EVENT-
OUT
PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO
/I2S1_SDI - - SPI6_MISO TIM13_
CH1
TIM8_BKIN
_COMP12
MDIOS_
MDC
TIM1_BKIN
_COMP12
DCMI_PIX
CLK LCD_G2 EVENT-
OUT
PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1
N-SPI1_MOSI
/I2S1_SDO - - SPI6_MOSI TIM14_
CH1 -
ETH_MII_
RX_DV/
ETH_RMII_
CRS_DV
FMC_SDN
WE --
EVENT-
OUT
PA8 MCO1 TIM1_CH1 HRTIM_CH
B2
TIM8_BKIN
2I2C3_SCL - - USART1_
CK --
OTG_FS_
SOF UART7_RX TIM8_BKIN
2_COMP12 LCD_B3 LCD_R6 EVENT-
OUT
PA9 - TIM1_CH2 HRTIM_CH
C1
LPUART1_
TX I2C3_SMBA SPI2_SCK/
I2S2_CK -USART1_
TX -
FDCAN1_
RXFD_
MODE
- - - DCMI_D0 LCD_R5 EVENT-
OUT
PA10 - TIM1_CH3 HRTIM_CH
C2
LPUART1_
RX ---
USART1_
RX -
FDCAN1_
TXFD_
MODE
OTG_FS_ID MDIOS_
MDIO LCD_B4 DCMI_D1 LCD_B1 EVENT-
OUT
PA11 - TIM1_CH4 HRTIM_CH
D1
LPUART1_
CTS -SPI2_NSS
/I2S2_WS UART4_RX
USART1_
CTS/
USART1_
NSS
-FDCAN1_
RX
OTG_FS_
DM - - - LCD_R4 EVENT-
OUT
PA12 - TIM1_ETR HRTIM_CH
D2
LPUART1_
RTS/
LPUART1_
DE
-SPI2_SCK/
I2S2_CK UART4_TX
USART1_
RTS/
USART1_
DE
SAI2_FS_B FDCAN1_
TX
OTG_FS_
DP - - - LCD_R5 EVENT-
OUT
Pin descriptions STM32H742xI/G STM32H743xI/G
90/357 DS12110 Rev 7
Port A
PA13 JTMS-
SWDIO --- - ----------
EVENT-
OUT
PA14 JTCK-
SWCLK --- - ----------
EVENT-
OUT
PA15 JTDI TIM2_CH1/
TIM2_ETR
HRTIM_
FLT1 -CEC
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS SPI6_NSS
UART4_
RTS/
UART4_
DE
--UART7_TX---
EVENT-
OUT
Table 10. Port A alternate functions (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4/
5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1/
3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD SYS
Table 11. Port B alternate functions
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/5/
6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/3
/6/UART7/S
DMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD
/COMP
UART5/
LCD SYS
Port B
PB0 - TIM1_CH2N TIM3_CH3 TIM8_
CH2N --
DFSDM1_
CKOUT -UART4_
CTS LCD_R3 OTG_HS_
ULPI_D1
ETH_MII_
RXD2 - - LCD_G1 EVENT-
OUT
PB1 - TIM1_CH3N TIM3_CH4 TIM8_
CH3N --
DFSDM1_
DATIN1 - - LCD_R6 OTG_HS_
ULPI_D2
ETH_MII_
RXD3 - - LCD_G0 EVENT-
OUT
PB2 RTC_OUT - SAI1_D1 - DFSDM1_
CKIN1 - SAI1_SD_A
SPI3_
MOSI/I2S3_
SDO
SAI4_SD_
A
QUADSPI_
CLK SAI4_D1 - - - - EVENT-
OUT
PB3 JTDO/TRA
CESWO TIM2_CH2 HRTIM_
FLT4 --
SPI1_SCK/
I2S1_CK
SPI3_SCK/
I2S3_CK - SPI6_SCK SDMMC2_
D2 CRS_SYNC UART7_RX - - - EVENT-
OUT
PB4 NJTRST TIM16_
BKIN TIM3_CH1 HRTIM_
EEV6 -SPI1_MISO/
I2S1_SDI
SPI3_MISO/
I2S3_SDI
SPI2_NSS/I
2S2_WS
SPI6_
MISO
SDMMC2_
D3 -UART7_TX- - -
EVENT-
OUT
PB5 - TIM17_
BKIN TIM3_CH2 HRTIM_
EEV7 I2C1_SMBA SPI1_MOSI/
I2S1_SDO I2C4_SMBA SPI3_MOSI/
I2S3_SDO
SPI6_
MOSI
FDCAN2_
RX
OTG_HS_
ULPI_D7
ETH_PPS_
OUT
FMC_
SDCKE1
DCMI_
D10
UART5_
RX
EVENT-
OUT
PB6 - TIM16_
CH1N TIM4_CH1 HRTIM_
EEV8 I2C1_SCL CEC I2C4_SCL USART1_
TX
LPUART1_
TX
FDCAN2_
TX
QUADSPI_
BK1_NCS
DFSDM1_
DATIN5
FMC_
SDNE1 DCMI_D5 UART5_
TX
EVENT-
OUT
PB7 - TIM17_
CH1N TIM4_CH2 HRTIM_
EEV9 I2C1_SDA - I2C4_SDA USART1_
RX
LPUART1_
RX
FDCAN2_
TXFD_
MODE
-DFSDM1_
CKIN5 FMC_NL DCMI_
VSYNC -EVENT-
OUT
STM32H742xI/G STM32H743xI/G Pin descriptions
DS12110 Rev 7 91/357
Port B
PB8 - TIM16_CH1 TIM4_CH3 DFSDM1_
CKIN7 I2C1_SCL - I2C4_SCL SDMMC1_
CKIN UART4_RX FDCAN1_
RX
SDMMC2_
D4
ETH_MII_
TXD3
SDMMC1_
D4 DCMI_D6 LCD_B6 EVENT-
OUT
PB9 - TIM17_CH1 TIM4_CH4 DFSDM1_
DATIN7 I2C1_SDA SPI2_NSS/
I2S2_WS I2C4_SDA SDMMC1_
CDIR UART4_TX FDCAN1_
TX
SDMMC2_
D5
I2C4_
SMBA
SDMMC1_
D5 DCMI_D7 LCD_B7 EVENT-
OUT
PB10 - TIM2_CH3 HRTIM_
SCOUT
LPTIM2_IN
1I2C2_SCL SPI2_SCK/
I2S2_CK
DFSDM1_
DATIN7
USART3_
TX -QUADSPI_
BK1_NCS
OTG_HS_
ULPI_D3
ETH_MII_
RX_ER - - LCD_G4 EVENT-
OUT
PB11 - TIM2_CH4 HRTIM_
SCIN
LPTIM2_
ETR I2C2_SDA - DFSDM1_
CKIN7
USART3_
RX --
OTG_HS_
ULPI_D4
ETH_MII_
TX_EN/
ETH_RMII_
TX_EN
- - LCD_G5 EVENT-
OUT
PB12 - TIM1_BKIN - - I2C2_SMBA SPI2_NSS/
I2S2_WS
DFSDM1_
DATIN1
USART3_
CK -FDCAN2_
RX
OTG_HS_
ULPI_D5
ETH_MII_
TXD0/ETH_
RMII_TXD0
OTG_HS_
ID
TIM1_
BKIN_
COMP12
UART5_
RX
EVENT-
OUT
PB13 - TIM1_CH1N - LPTIM2_
OUT -SPI2_SCK/
I2S2_CK
DFSDM1_
CKIN1
USART3_
CTS/
USART3_
NSS
-FDCAN2_
TX
OTG_HS_
ULPI_D6
ETH_MII_
TXD1/ETH_
RMII_TXD1
--
UART5_
TX
EVENT-
OUT
PB14 - TIM1_CH2N TIM12_
CH1
TIM8_
CH2N USART1_TX SPI2_MISO/
I2S2_SDI
DFSDM1_
DATIN2
USART3_
RTS/
USART3_
DE
UART4_
RTS/
UART4_
DE
SDMMC2_
D0 --
OTG_HS_
DM --
EVENT-
OUT
PB15 RTC_
REFIN TIM1_CH3N TIM12_
CH2
TIM8_
CH3N USART1_RX SPI2_MOSI/
I2S2_SDO
DFSDM1_
CKIN2 -UART4_
CTS
SDMMC2_
D1 --
OTG_HS_
DP --
EVENT-
OUT
Table 11. Port B alternate functions (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/5/
6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/3
/6/UART7/S
DMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD
/COMP
UART5/
LCD SYS
Pin descriptions STM32H742xI/G STM32H743xI/G
92/357 DS12110 Rev 7
Table 12. Port C alternate functions
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD SYS
Port C
PC0 - - - DFSDM1_
CKIN0 --
DFSDM1_
DATIN4 -SAI2_FS_B - OTG_HS_
ULPI_STP -FMC_
SDNWE -LCD_R5 EVENT-
OUT
PC1 TRACED0 - SAI1_D1 DFSDM1_
DATIN0
DFSDM1_
CKIN4
SPI2_
MOSI/I2S2
_SDO
SAI1_SD_A - SAI4_SD_
A
SDMMC2_
CK SAI4_D1 ETH_MDC MDIOS_
MDC --
EVENT-
OUT
PC2 CDSLEEP - - DFSDM1_
CKIN1 -
SPI2_
MISO/I2S2
_SDI
DFSDM1_
CKOUT ---
OTG_HS_
ULPI_DIR
ETH_MII_
TXD2
FMC_SDNE
0--
EVENT-
OUT
PC3 CSLEEP - - DFSDM1_
DATIN1 -
SPI2_
MOSI/I2S2
_SDO
- ---
OTG_HS_
ULPI_NXT
ETH_MII_
TX_CLK
FMC_SDCK
E0 --
EVENT-
OUT
PC4 - - - DFSDM1_
CKIN2 -I2S1_
MCK ---
SPDIFRX1
_IN3 -
ETH_MII_
RXD0/ETH_
RMII_RXD0
FMC_SDNE
0--
EVENT-
OUT
PC5 - - SAI1_D3 DFSDM1_
DATIN2 ---- SPDIFRX1
_IN4 SAI4_D3
ETH_MII_
RXD1/ETH_
RMII_RXD1
FMC_SDCK
E0
COMP1_
OUT -EVENT-
OUT
PC6 - HRTIM_CH
A1 TIM3_CH1 TIM8_CH1 DFSDM1_
CKIN3
I2S2_
MCK -USART6_
TX
SDMMC1_
D0DIR
FMC_
NWAIT
SDMMC2_
D6 -SDMMC1_
D6 DCMI_D0 LCD_
HSYNC
EVENT-
OUT
PC7 TRGIO HRTIM_CH
A2 TIM3_CH2 TIM8_CH2 DFSDM1_
DATIN3 -I2S3_MCK USART6_
RX
SDMMC1_
D123DIR FMC_NE1 SDMMC2_
D7 SWPMI_TX SDMMC1_
D7 DCMI_D1 LCD_G6 EVENT-
OUT
PC8 TRACED1 HRTIM_CH
B1 TIM3_CH3 TIM8_CH3 - - - USART6_
CK
UART5_
RTS/
UART5_
DE
FMC_NE2/
FMC_NCE -SWPMI_RX SDMMC1_
D0 DCMI_D2 - EVENT-
OUT
PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN - - UART5_
CTS
QUADSPI_
BK1_IO0 LCD_G3 SWPMI_
SUSPEND
SDMMC1_
D1 DCMI_D3 LCD_B2 EVENT-
OUT
PC10 - - HRTIM_
EEV1
DFSDM1_
CKIN5 --
SPI3_SCK/
I2S3_CK
USART3_
TX UART4_TX QUADSPI_
BK1_IO1 --
SDMMC1_
D2 DCMI_D8 LCD_R2 EVENT-
OUT
PC11 - - HRTIM_
FLT2
DFSDM1_
DATIN5 --
SPI3_MISO/
I2S3_SDI
USART3_
RX UART4_RX QUADSPI_
BK2_NCS --
SDMMC1_
D3 DCMI_D4 - EVENT-
OUT
PC12 TRACED3 - HRTIM_
EEV2 ---
SPI3_MOSI/
I2S3_SDO
USART3_
CK UART5_TX - - - SDMMC1_
CK DCMI_D9 - EVENT-
OUT
PC13-- -- - - - --- - - - --
EVENT-
OUT
STM32H742xI/G STM32H743xI/G Pin descriptions
DS12110 Rev 7 93/357
Port C
PC14-- -- - - - --- - - - --
EVENT-
OUT
PC15-- -- - - - --- - - - --
EVENT-
OUT
Table 12. Port C alternate functions (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD SYS
Table 13. Port D alternate functions
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD SYS
Port D
PD0---
DFSDM1_
CKIN6 --
SAI3_SCK_
A-UART4_RX FDCAN1_
RX --
FMC_D2/
FMC_DA2 --
EVENT-
OUT
PD1---
DFSDM1_
DATIN6 --SAI3_SD_A - UART4_TX FDCAN1_
TX --
FMC_D3/
FMC_DA3 --
EVENT-
OUT
PD2 TRACED2 - TIM3_ETR - - - - - UART5_RX - - - SDMMC1_
CMD DCMI_D11 - EVENT-
OUT
PD3---
DFSDM1_
CKOUT -SPI2_SCK/
I2S2_CK -
USART2_
CTS/
USART2_
NSS
----FMC_CLK DCMI_D5 LCD_G7 EVENT-
OUT
PD4 - - HRTIM_
FLT3 ---SAI3_FS_A
USART2_
RTS/
USART2_
DE
-FDCAN1_R
XFD_MODE --FMC_NOE - - EVENT-
OUT
PD5 - - HRTIM_
EEV3 ----
USART2_
TX -FDCAN1_T
XFD_MODE --FMC_NWE - - EVENT-
OUT
PD6 - - SAI1_D1 DFSDM1_
CKIN4
DFSDM1_
DATIN1
SPI3_
MOSI/I2S3
_SDO
SAI1_SD_A USART2_
RX
SAI4_SD_
A
FDCAN2_R
XFD_MODE SAI4_D1 SDMMC2_
CK
FMC_
NWAIT DCMI_D10 LCD_B2 EVENT-
OUT
PD7---
DFSDM1_
DATIN4 -
SPI1_
MOSI/I2S1
_SDO
DFSDM1_
CKIN1
USART2_
CK -SPDIFRX1_
IN1 -SDMMC2_
CMD FMC_NE1 - - EVENT-
OUT
Pin descriptions STM32H742xI/G STM32H743xI/G
94/357 DS12110 Rev 7
Port D
PD8---
DFSDM1_
CKIN3 --
SAI3_SCK_
B
USART3_
TX -SPDIFRX1_
IN2 --
FMC_D13/
FMC_DA13 --
EVENT-
OUT
PD9---
DFSDM1_
DATIN3 --SAI3_SD_B USART3_
RX -FDCAN2_R
XFD_MODE --
FMC_D14/
FMC_DA14 --
EVENT-
OUT
PD10---
DFSDM1_
CKOUT --SAI3_FS_B USART3_
CK -FDCAN2_T
XFD_MODE --
FMC_D15/
FMC_DA15 -LCD_B3 EVENT-
OUT
PD11---
LPTIM2_
IN2 I2C4_SMBA - -
USART3_
CTS/
USART3_N
SS
-QUADSPI_
BK1_IO0 SAI2_SD_A - FMC_A16 - - EVENT-
OUT
PD12 - LPTIM1_IN1 TIM4_CH1 LPTIM2_
IN1 I2C4_SCL - -
USART3_
RTS/
USART3_
DE
-QUADSPI_
BK1_IO1 SAI2_FS_A - FMC_A17 - - EVENT-
OUT
PD13 - LPTIM1_
OUT TIM4_CH2 - I2C4_SDA - - -QUADSPI_
BK1_IO3
SAI2_SCK_
A-FMC_A18 - - EVENT-
OUT
PD14 - - TIM4_CH3 - - - SAI3_MCLK
_B -UART8_
CTS ---
FMC_D0/
FMC_DA0 --
EVENT-
OUT
PD15 - - TIM4_CH4 - - - SAI3_MCLK
_A -
UART8_
RTS/
UART8_
DE
---
FMC_D1/
FMC_DA1 --
EVENT-
OUT
Table 13. Port D alternate functions (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD SYS
STM32H742xI/G STM32H743xI/G Pin descriptions
DS12110 Rev 7 95/357
Table 14. Port E alternate functions
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD SYS
Port E
PE0 - LPTIM1_
ETR TIM4_ETR HRTIM_
SCIN
LPTIM2_
ETR ---UART8_RX
FDCAN1_
RXFD_
MODE
SAI2_
MCLK_A -FMC_NBL0 DCMI_D2 - EVENT-
OUT
PE1 - LPTIM1_IN2 - HRTIM_
SCOUT - ---UART8_TX
FDCAN1_
TXFD_
MODE
--FMC_NBL1 DCMI_D3 - EVENT-
OUT
PE2 TRACE
CLK -SAI1_CK1- -SPI4_SCK SAI1_MCLK
_A -SAI4_
MCLK_A
QUADSPI_
BK1_IO2 SAI4_CK1 ETH_MII_
TXD3 FMC_A23 - - EVENT-
OUT
PE3 TRACED0 - - - TIM15_BKIN - SAI1_SD_B - SAI4_SD_
B-- -FMC_A19 - - EVENT-
OUT
PE4 TRACED1 - SAI1_D2 DFSDM1_
DATIN3
TIM15_CH1
NSPI4_NSS SAI1_FS_A - SAI4_FS_A - SAI4_D2 - FMC_A20 DCMI_D4 LCD_B0 EVENT-
OUT
PE5 TRACED2 - SAI1_CK2 DFSDM1_
CKIN3 TIM15_CH1 SPI4_
MISO
SAI1_SCK_
A-SAI4_SCK
_A -SAI4_CK2 - FMC_A21 DCMI_D6 LCD_G0 EVENT-
OUT
PE6 TRACED3 TIM1_
BKIN2 SAI1_D1 - TIM15_CH2 SPI4_
MOSI SAI1_SD_A - SAI4_SD_
ASAI4_D1 SAI2_
MCLK_B
TIM1_BKIN
2_COMP12 FMC_A22 DCMI_D7 LCD_G1 EVENT-
OUT
PE7 - TIM1_ETR - DFSDM1_
DATIN2 ---UART7_RX - - QUADSPI_
BK2_IO0 -FMC_D4/
FMC_DA4 --
EVENT-
OUT
PE8 - TIM1_CH1N - DFSDM1_
CKIN2 ---UART7_TX - - QUADSPI_
BK2_IO1 -FMC_D5/
FMC_DA5
COMP2_
OUT -EVENT-
OUT
PE9 - TIM1_CH1 - DFSDM1_
CKOUT ---
UART7_
RTS/
UART7_
DE
--
QUADSPI_
BK2_IO2 -FMC_D6/
FMC_DA6 --
EVENT-
OUT
PE10 - TIM1_CH2N - DFSDM1_
DATIN4 ---
UART7_
CTS --
QUADSPI_
BK2_IO3 -FMC_D7/
FMC_DA7 --
EVENT-
OUT
PE11 - TIM1_CH2 - DFSDM1_
CKIN4 -SPI4_NSS- ---SAI2_SD_B - FMC_D8/
FMC_DA8 -LCD_G3 EVENT-
OUT
PE12 - TIM1_CH3N - DFSDM1_
DATIN5 -SPI4_SCK- ---
SAI2_SCK_
B-FMC_D9/
FMC_DA9
COMP1_
OUT LCD_B4 EVENT-
OUT
PE13 - TIM1_CH3 - DFSDM1_
CKIN5 -SPI4_
MISO - ---SAI2_FS_B - FMC_D10/
FMC_DA10
COMP2_
OUT LCD_DE EVENT-
OUT
Pin descriptions STM32H742xI/G STM32H743xI/G
96/357 DS12110 Rev 7
Port E
PE14 - TIM1_CH4 - - - SPI4_
MOSI - ---
SAI2_
MCLK_B -FMC_D11/
FMC_DA11 -LCD_CLK EVENT-
OUT
PE15 - TIM1_BKIN - - - - - --- -FMC_D12/
FMC_DA12
TIM1_BKIN
_COMP12/
COMP_
TIM1_BKIN
LCD_R7 EVENT-
OUT
Table 14. Port E alternate functions (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD SYS
STM32H742xI/G STM32H743xI/G Pin descriptions
DS12110 Rev 7 97/357
Table 15. Port F alternate functions
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD SYS
Port F
PF0----I2C2_SDA-------FMC_A0 - - EVENT-
OUT
PF1----I2C2_SCL-------FMC_A1 - - EVENT-
OUT
PF2----I2C2_SMBA-------FMC_A2 - - EVENT-
OUT
PF3---- - -------FMC_A3 - - EVENT-
OUT
PF4---- - -------FMC_A4 - - EVENT-
OUT
PF5---- - -------FMC_A5 - - EVENT-
OUT
PF6 - TIM16_CH1 - - - SPI5_NSS SAI1_SD_B UART7_RX SAI4_SD_
B
QUADSPI_
BK1_IO3 -----
EVENT-
OUT
PF7 - TIM17_CH1 - - - SPI5_SCK SAI1_MCLK
_B UART7_TX SAI4_
MCLK_B
QUADSPI_
BK1_IO2 -----
EVENT-
OUT
PF8 - TIM16_
CH1N -- -
SPI5_
MISO
SAI1_SCK_
B
UART7_
RTS/
UART7_
DE
SAI4_SCK
_B
TIM13_
CH1
QUADSPI_
BK1_IO0 ----
EVENT-
OUT
PF9 - TIM17_
CH1N -- -
SPI5_
MOSI SAI1_FS_B UART7_
CTS SAI4_FS_B TIM14_CH
1
QUADSPI_
BK1_IO1 ----
EVENT-
OUT
PF10 - TIM16_
BKIN SAI1_D3 - - - - - - QUADSPI_
CLK SAI4_D3 - - DCMI_D11 LCD_DE EVENT-
OUT
PF11---- -
SPI5_
MOSI - ---SAI2_SD_B - FMC_
SDNRAS DCMI_D12 - EVENT-
OUT
PF12---- - -------FMC_A6 - - EVENT-
OUT
PF13---
DFSDM1_
DATIN6 I2C4_SMBA - - - - - - - FMC_A7 - - EVENT-
OUT
PF14---
DFSDM1_
CKIN6 I2C4_SCL - - - - - - - FMC_A8 - - EVENT-
OUT
PF15----I2C4_SDA-------FMC_A9 - - EVENT-
OUT
Pin descriptions STM32H742xI/G STM32H743xI/G
98/357 DS12110 Rev 7
Table 16. Port G alternate functions
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/UART7
/SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD
/COMP
UART5/
LCD SYS
Port G
PG0---- - ---- - - -FMC_A10 - - EVENT
-OUT
PG1---- - ---- - - -FMC_A11 - - EVENT
-OUT
PG2---TIM8_BKIN- ---- - -
TIM8_BKIN_
COMP12 FMC_A12 - - EVENT
-OUT
PG3 - - - TIM8_
BKIN2 - ---- - -
TIM8_BKIN2
_COMP12 FMC_A13 - - EVENT
-OUT
PG4 - TIM1_
BKIN2 -- - ---- - -
TIM1_BKIN2
_COMP12
FMC_A14/
FMC_BA0 --
EVENT
-OUT
PG5 - TIM1_ETR - - - - - - - - - - FMC_A15/
FMC_BA1 --
EVENT
-OUT
PG6 - TIM17_
BKIN
HRTIM_
CHE1 - - ---- -
QUADSPI_
BK1_NCS -FMC_NE3 DCMI_
D12
LCD_
R7
EVENT
-OUT
PG7 - - HRTIM_
CHE2 ---
SAI1_
MCLK_A
USART6_
CK -- --FMC_INT DCMI_
D13
LCD_
CLK
EVENT
-OUT
PG8 - - - TIM8_ETR - SPI6_NSS -
USART6_
RTS/
USART6_
DE
SPDIFRX1
_IN3 --
ETH_PPS_
OUT
FMC_
SDCLK -LCD_
G7
EVENT
-OUT
PG9 - - - - -
SPI1_
MISO/I2S1
_SDI
-USART6_
RX
SPDIFRX1
_IN4
QUADSPI_
BK2_IO2 SAI2_FS_B - FMC_NE2/
FMC_NCE
DCMI_
VSYNC -EVENT
-OUT
PG10 - - HRTIM_
FLT5 --
SPI1_NSS/
I2S1_WS ---LCD_G3SAI2_SD_B - FMC_NE3 DCMI_D2 LCD_
B2
EVENT
-OUT
PG11 - LPTIM1_IN2 HRTIM_
EEV4 --
SPI1_SCK/
I2S1_CK --
SPDIFRX1
_IN1 -SDMMC2_D2
ETH_MII_
TX_EN/
ETH_RMII_
TX_EN
-DCMI_D3 LCD_
B3
EVENT
-OUT
PG12 - LPTIM1_IN1 HRTIM_
EEV5 --
SPI6_
MISO
USART6_
RTS/
USART6_
DE
SPDIFRX1
_IN2 LCD_B4 -
ETH_MII_
TXD1/ETH_
RMII_TXD1
FMC_NE4 - LCD_
B1
EVENT
-OUT
PG13 TRACED0 LPTIM1_
OUT
HRTIM_
EEV10 --SPI6_SCK -
USART6_
CTS/
USART6_
NSS
-- -
ETH_MII_
TXD0/ETH_
RMII_TXD0
FMC_A24 - LCD_
R0
EVENT
-OUT
STM32H742xI/G STM32H743xI/G Pin descriptions
DS12110 Rev 7 99/357
Port G
PG14 TRACED1 LPTIM1_
ETR -- -
SPI6_
MOSI -USART6_
TX
QUADSPI_
BK2_IO3 -
ETH_MII_
TXD1/ETH_
RMII_TXD1
FMC_A25 - LCD_
B0
EVENT
-OUT
PG15 - - - - - - -
USART6_
CTS/
USART6_
NSS
-- --
FMC_
SDNCAS
DCMI_
D13 -EVENT
-OUT
Table 16. Port G alternate functions (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/UART7
/SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD
/COMP
UART5/
LCD SYS
Pin descriptions STM32H742xI/G STM32H743xI/G
100/357 DS12110 Rev 7
Table 17. Port H alternate functions
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD SYS
Port H
PH0---- - ----------
EVENT-
OUT
PH1---- - ----------
EVENT-
OUT
PH2 - LPTIM1_IN2 - - - - - - - QUADSPI_
BK2_IO0
SAI2_SCK_
B
ETH_MII_
CRS
FMC_
SDCKE0 -LCD_R0 EVENT-
OUT
PH3 - - - - - - - - - QUADSPI_
BK2_IO1
SAI2_
MCLK_B
ETH_MII_
COL
FMC_
SDNE0 -LCD_R1 EVENT-
OUT
PH4 - - - - I2C2_SCL - - - - LCD_G5 OTG_HS_
ULPI_NXT ---LCD_G4 EVENT-
OUT
PH5 - - - - I2C2_SDA SPI5_NSS - - - - - - FMC_
SDNWE --
EVENT-
OUT
PH6 - - TIM12_
CH1 - I2C2_SMBA SPI5_SCK- --- -
ETH_MII_
RXD2
FMC_
SDNE1 DCMI_D8 - EVENT-
OUT
PH7 - - - - I2C3_SCL SPI5_
MISO - --- -
ETH_MII_
RXD3
FMC_
SDCKE1 DCMI_D9 - EVENT-
OUT
PH8 - - TIM5_ETR - I2C3_SDA - - - - - - - FMC_D16 DCMI_
HSYNC LCD_R2 EVENT-
OUT
PH9 - - TIM12_
CH2 - I2C3_SMBA - - - - - - - FMC_D17 DCMI_D0 LCD_R3 EVENT-
OUT
PH10 - - TIM5_CH1 - I2C4_SMBA - - - - - - - FMC_D18 DCMI_D1 LCD_R4 EVENT-
OUT
PH11 - - TIM5_CH2 - I2C4_SCL - - - - - - - FMC_D19 DCMI_D2 LCD_R5 EVENT-
OUT
PH12 - - TIM5_CH3 - I2C4_SDA - - - - - - - FMC_D20 DCMI_D3 LCD_R6 EVENT-
OUT
PH13 - - - TIM8_
CH1N ----UART4_TX FDCAN1_
TX --FMC_D21 -LCD_G2 EVENT-
OUT
PH14 - - - TIM8_
CH2N ----UART4_RX FDCAN1_
RX --FMC_D22 DCMI_D4 LCD_G3 EVENT-
OUT
PH15 - - - TIM8_
CH3N -----
FDCAN1_
TXFD_
MODE
--FMC_D23 DCMI_D11 LCD_G4 EVENT-
OUT
STM32H742xI/G STM32H743xI/G Pin descriptions
DS12110 Rev 7 101/357
Table 18. Port I alternate functions
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD SYS
Port I
PI0 - - TIM5_CH4 - - SPI2_NSS/
I2S2_WS ---
FDCAN1_
RXFD_
MODE
--FMC_D24 DCMI_D13 LCD_G5 EVENT-
OUT
PI1---
TIM8_
BKIN2 -SPI2_SCK/
I2S2_CK - --- -
TIM8_BKIN
2_COMP12 FMC_D25 DCMI_D8 LCD_G6 EVENT-
OUT
PI2---TIM8_CH4-
SPI2_
MISO/I2S2
_SDI
- ---- -FMC_D26 DCMI_D9 LCD_G7 EVENT-
OUT
PI3---TIM8_ETR-
SPI2_
MOSI/I2S2
_SDO
- ---- -FMC_D27 DCMI_D10 -EVENT-
OUT
PI4---TIM8_BKIN- -----
SAI2_
MCLK_A
TIM8_BKIN
_COMP12 FMC_NBL2 DCMI_D5 LCD_B4 EVENT-
OUT
PI5---TIM8_CH1- -----
SAI2_SCK_
A-FMC_NBL3 DCMI_
VSYNC LCD_B5 EVENT-
OUT
PI6---TIM8_CH2- -----SAI2_SD_A - FMC_D28 DCMI_D6 LCD_B6 EVENT-
OUT
PI7---TIM8_CH3- -----SAI2_FS_A - FMC_D29 DCMI_D7 LCD_B7 EVENT-
OUT
PI8---- - ----------
EVENT-
OUT
PI9---- - ---UART4_RX FDCAN1_
RX --FMC_D30 - LCD_
VSYNC
EVENT-
OUT
PI10---- - ----
FDCAN1_
RXFD_
MODE
-ETH_MII_
RX_ER FMC_D31 - LCD_
HSYNC
EVENT-
OUT
PI11---- - ----LCD_G6
OTG_HS_
ULPI_DIR ----
EVENT-
OUT
PI12---- - ---------
LCD_
HSYNC
EVENT-
OUT
PI13---- - ---------
LCD_
VSYNC
EVENT-
OUT
PI14---- - ---------
LCD_CLK EVENT-
OUT
PI15---- - ----LCD_G2----
LCD_R0 EVENT-
OUT
Pin descriptions STM32H742xI/G STM32H743xI/G
102/357 DS12110 Rev 7
Table 19. Port J alternate functions
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD SYS
Port J
PJ0 - - - - - - - - - LCD_R7 - - - - LCD_R1 EVENT-
OUT
PJ1---- - ---------LCD_R2 EVENT-
OUT
PJ2---- - ---------LCD_R3 EVENT-
OUT
PJ3---- - ---------LCD_R4 EVENT-
OUT
PJ4---- - ---------LCD_R5 EVENT-
OUT
PJ5---- - ---------LCD_R6 EVENT-
OUT
PJ6---TIM8_CH2- ---------LCD_R7 EVENT-
OUT
PJ7 TRGIN - - TIM8_
CH2N - - - --- - - - -LCD_G0 EVENT-
OUT
PJ8 - TIM1_CH3N - TIM8_CH1 - - - - UART8_TX - - - - - LCD_G1 EVENT-
OUT
PJ9 - TIM1_CH3 - TIM8_
CH1N ----UART8_RX - - - - - LCD_G2 EVENT-
OUT
PJ10 - TIM1_CH2N - TIM8_CH2 - SPI5_
MOSI - --- - - - -LCD_G3 EVENT-
OUT
PJ11 - TIM1_CH2 - TIM8_
CH2N -SPI5_
MISO - --- - - - -LCD_G4 EVENT-
OUT
PJ12 TRGOUT - - - - - - - - LCD_G3 - - - - LCD_B0 EVENT-
OUT
PJ13---- - ----LCD_B4----LCD_B1 EVENT-
OUT
PJ14---- - ---------LCD_B2 EVENT-
OUT
PJ15---- - ---------LCD_B3 EVENT-
OUT
STM32H742xI/G STM32H743xI/G Pin descriptions
DS12110 Rev 7 103/357
Table 20. Port K alternate functions
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD SYS
Port K
PK0 - TIM1_CH1N - TIM8_CH3 - SPI5_SCK- --- - - - -LCD_G5 EVENT-
OUT
PK1 - TIM1_CH1 - TIM8_
CH3N -SPI5_NSS- --- - - - -LCD_G6 EVENT-
OUT
PK2 - TIM1_BKIN - TIM8_BKIN - - - - - - TIM8_BKIN
_COMP12
TIM1_BKIN
_COMP12 --LCD_G7 EVENT-
OUT
PK3---- - ---------LCD_B4 EVENT-
OUT
PK4---- - ---------LCD_B5 EVENT-
OUT
PK5---- - ---------LCD_B6 EVENT-
OUT
PK6---- - ---------LCD_B7 EVENT-
OUT
PK7---- - ---------LCD_DE EVENT-
OUT
Electrical characteristics (rev Y) STM32H742xI/G STM32H743xI/G
104/357 DS12110 Rev 7
6 Electrical characteristics (rev Y)
6.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3).
6.1.2 Typical values
Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2).
6.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 13.
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 14.
Figure 13. Pin loading conditions Figure 14. Pin input voltage
MS19011V2
C = 50 pF
MCU pin
MS19010V2
MCU pin
VIN
DS12110 Rev 7 105/357
STM32H742xI/G STM32H743xI/G Electrical characteristics (rev Y)
322
6.1.6 Power supply scheme
Figure 15. Power supply scheme
1. N corresponds to the number of VDD pins available on the package.
2. A tolerance of +/- 20% is acceptable on decoupling capacitors.
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
MSv46116V3
BKUP
IOs
VDD domain
Analog domain
Core domain (VCORE)
Backup domain
D3 domain
(System
logic,
EXTI,
Peripherals,
RAM)
D1 domain
(CPU, peripherals,
RAM)
Level shifter
OPAMP,
Comparator
Voltage
regulator
ADC, DAC
Flash
D2 domain
(peripherals,
RAM)
Power
switch
Power switch
VCAP
VSS
VDDLDO
VBAT
VDDA
VREF+
VREF-
VSSA
Backup
regulator
VDD
Backup
RAM
Power switch
HSI, CSI,
HSI48,
HSE, PLLs
IOs
Power
switch
USB
regulator
VDD50USB
VDD33USB
VSS
VSS
VSS
REF_BUF
VSS
IO
logic
VREF+
USB
IOs
VSS
VSW
LSI, LSE,
RTC, Wakeup
logic, backup
registers,
Reset
IO
logic
VBKP
VBAT
charging
VREF-
VDDA
VBAT
1.2 to 3.6V
2 x 2.2μF
N(1) x 100 nF
+ 1 x 4.7 μF
100 nF
100 nF + 1 x 1 μF
4..7μF
100 nF
VDD
VDDLDO
100 nF + 1 x 1 μF
VREF
VDD33USB VDD50USB
Electrical characteristics (rev Y) STM32H742xI/G STM32H743xI/G
106/357 DS12110 Rev 7
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
6.1.7 Current consumption measurement
Figure 16. Current consumption measurement scheme
6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics,
Table 22: Current characteristics, and Table 23: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
ai14126
VBAT
VDD
VDDA
IDD_VBAT
IDD
Table 21. Voltage characteristics (1)
1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
Symbols Ratings Min Max Unit
VDDX - VSS
External main supply voltage (including VDD,
VDDLDO, VDDA, VDD33USB, VBAT)0.3 4.0 V
VIN(2)
2. VIN maximum must always be respected. Refer to Table 59 for the maximum allowed injected current
values.
Input voltage on FT_xxx pins VSS0.3
Min(VDD, VDDA,
VDD33USB, VBAT)
+4.0(3)(4)
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
V
Input voltage on TT_xx pins VSS-0.3 4.0 V
Input voltage on BOOT0 pin VSS 9.0 V
Input voltage on any other pins VSS-0.3 4.0 V
|VDDX|Variations between different VDDX power pins
of the same domain -50mV
|VSSx-VSS| Variations between all the different ground pins - 50 mV
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STM32H742xI/G STM32H743xI/G Electrical characteristics (rev Y)
322
Table 22. Current characteristics
Symbols Ratings Max Unit
ΣIVDD Total current into sum of all VDD power lines (source)(1)
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
620
mA
ΣIVSS Total current out of sum of all VSS ground lines (sink)(1) 620
IVDD Maximum current into each VDD power pin (source)(1) 100
IVSS Maximum current out of each VSS ground pin (sink)(1) 100
IIO Output current sunk by any I/O and control pin 20
ΣI(PIN)
Total output current sunk by sum of all I/Os and control pins(2)
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
140
Total output current sourced by sum of all I/Os and control pins(2) 140
IINJ(PIN)(3)(4)
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 21: Voltage characteristics for the maximum allowed input voltage
values.
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
PA5 5/+0
Injected current on PA4, PA5 0/0
ΣIINJ(PIN) Total injected current (sum of all I/Os and control pins)(5)
5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
±25
Table 23. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range −65 to +150
°C
TJMaximum junction temperature 125
Electrical characteristics (rev Y) STM32H742xI/G STM32H743xI/G
108/357 DS12110 Rev 7
6.3 Operating conditions
6.3.1 General operating conditions
Table 24. General operating conditions
Symbol Parameter Operating conditions Min Max Unit
VDD Standard operating voltage - 1.62(1) 3.6
V
VDDLDO Supply voltage for the internal regulator VDDLDO VDD 1.62(1) 3.6
VDD33USB Standard operating voltage, USB domain
USB used 3.0 3.6
USB not used 0 3.6
VDDA Analog operating voltage
ADC or COMP used 1.62
3.6
DAC used 1.8
OPAMP used 2.0
VREFBUF used 1.8
ADC, DAC, OPAMP,
COMP, VREFBUF not
used
0
VIN I/O Input voltage
TT_xx I/O 0.3 VDD+0.3
BOOT0 0 9
All I/O except BOOT0
and TT_xx 0.3
Min(VDD, VDDA,
VDD33USB) +3.6V
< 5.5V(2)(3)
PD
Power dissipation at
TA = 85 °C for suffix 6(4)
TFBGA240+25 - - 1093
mW
LQFP208 - - 943
LQFP176 - - 930
UFBGA176+25 - - 1070
UFBGA169 - - 1061
LQFP144 - - 915
LQFP100 - - 889
TFBGA100 - - 1018
TA
Ambient temperature for
the suffix 6 version
Maximum power dissipation –40 85
°C
Low-power dissipation(5) –40 105
Ambient temperature for
the suffix 3 version
Maximum power dissipation –40 125
Low-power dissipation(5) –40 130
TJ Junction temperature
range Suffix 6 version –40 125 °C
1. When RESET is released functionality is guaranteed down to VBOR0 min
2. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
3. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must
be disabled.
DS12110 Rev 7 109/357
STM32H742xI/G STM32H743xI/G Electrical characteristics (rev Y)
322
6.3.2 VCAP external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP pin. CEXT is specified in Table 25. Two external capacitors can be connected to
VCAP pins.
Figure 17. External capacitor CEXT
1. Legend: ESR is the equivalent series resistance.
6.3.3 Operating conditions at power-up / power-down
Subject to general operating conditions for TA.
Table 26. Operating conditions at power-up / power-down (regulator ON)
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 8.9: Thermal characteristics).
5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 8.9:
Thermal characteristics).
Table 25. VCAP operating conditions(1)
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
Symbol Parameter Conditions
CEXT Capacitance of external capacitor 2.2 µF(2)
2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.
ESR ESR of external capacitor < 100 mΩ
MS19044V2
ESR
R
Leak
C
Symbol Parameter Min Max Unit
tVDD
VDD rise time rate 0 ∞
µs/V
VDD fall time rate 10 ∞
tVDDA
VDDA rise time rate 0 ∞
VDDA fall time rate 10 ∞
tVDDUSB
VDDUSB rise time rate 0 ∞
VDDUSB fall time rate 10 ∞
Electrical characteristics (rev Y) STM32H742xI/G STM32H743xI/G
110/357 DS12110 Rev 7
6.3.4 Embedded reset and power control block characteristics
The parameters given in Table 27 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 24: General operating
conditions.
Table 27. Reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
tRSTTEMPO(1) Reset temporization
after BOR0 released - - 377 - µs
VBOR0 Brown-out reset threshold 0
Rising edge(1) 1.62 1.67 1.71
V
Falling edge 1.58 1.62 1.68
VBOR1 Brown-out reset threshold 1
Rising edge 2.04 2.10 2.15
Falling edge 1.95 2.00 2.06
VBOR2 Brown-out reset threshold 2
Rising edge 2.34 2.41 2.47
Falling edge 2.25 2.31 2.37
VBOR3 Brown-out reset threshold 3
Rising edge 2.63 2.70 2.78
Falling edge 2.54 2.61 2.68
VPVD0
Programmable Voltage
Detector threshold 0
Rising edge 1.90 1.96 2.01
Falling edge 1.81 1.86 1.91
VPVD1
Programmable Voltage
Detector threshold 1
Rising edge 2.05 2.10 2.16
Falling edge 1.96 2.01 2.06
VPVD2
Programmable Voltage
Detector threshold 2
Rising edge 2.19 2.26 2.32
Falling edge 2.10 2.15 2.21
VPVD3
Programmable Voltage
Detector threshold 3
Rising edge 2.35 2.41 2.47
Falling edge 2.25 2.31 2.37
VPVD4
Programmable Voltage
Detector threshold 4
Rising edge 2.49 2.56 2.62
Falling edge 2.39 2.45 2.51
VPVD5
Programmable Voltage
Detector threshold 5
Rising edge 2.64 2.71 2.78
Falling edge 2.55 2.61 2.68
VPVD6
Programmable Voltage
Detector threshold 6
Rising edge 2.78 2.86 2.94
Falling edge in Run mode 2.69 2.76 2.83
Vhyst_BOR_PVD
Hysteresis voltage of BOR
(unless BOR0) and PVD Hysteresis in Run mode - 100 - mV
IDD_BOR_PVD(1) BOR(2) (unless BOR0) and
PVD consumption from VDD
- - 0.630 µA
DS12110 Rev 7 111/357
STM32H742xI/G STM32H743xI/G Electrical characteristics (rev Y)
322
6.3.5 Embedded reference voltage
The parameters given in Table 28 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 24: General operating
conditions.
VAVM_0
Analog voltage detector for
VDDA threshold 0
Rising edge 1.66 1.71 1.76
V
Falling edge 1.56 1.61 1.66
VAVM_1
Analog voltage detector for
VDDA threshold 1
Rising edge 2.06 2.12 2.19
Falling edge 1.96 2.02 2.08
VAVM_2
Analog voltage detector for
VDDA threshold 2
Rising edge 2.42 2.50 2.58
Falling edge 2.35 2.42 2.49
VAVM_3
Analog voltage detector for
VDDA threshold 3
Rising edge 2.74 2.83 2.91
Falling edge 2.64 2.72 2.80
Vhyst_VDDA
Hysteresis of VDDA voltage
detector - - 100 - mV
IDD_PVM
PVM consumption from
VDD(1)
---0.25µA
IDD_VDDA
Voltage detector
consumption on VDDA(1) Resistor bridge - - 2.5 µA
1. Guaranteed by design.
2. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to
Section 6.3.6: Supply current characteristics).
Table 27. Reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 28. Embedded reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltages -40°C < TJ < 105°C,
VDD = 3.3 V 1.180 1.216 1.255 V
tS_vrefint(1)(2)
ADC sampling time when
reading the internal reference
voltage
-4.3--
µs
tS_vbat(1)(2)
VBAT sampling time when
reading the internal VBAT
reference voltage
-9--
Irefbuf(2) Reference Buffer
consumption for ADC VDDA=3.3 V 9 13.5 23 µA
ΔVREFINT(2)
Internal reference voltage
spread over the temperature
range
-40°C < TJ < 105°C - 5 15 mV
Tcoeff(2) Average temperature
coefficient
Average temperature
coefficient -2070ppm/°C
VDDcoeff(2) Average Voltage coefficient 3.0V < VDD < 3.6V - 10 1370 ppm/V
Electrical characteristics (rev Y) STM32H742xI/G STM32H743xI/G
112/357 DS12110 Rev 7
6.3.6 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 16: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•All I/O pins are in analog input mode.
•All peripherals are disabled except when explicitly mentioned.
•The Flash memory access time is adjusted with the minimum wait states number,
depending on the fACLK frequency (refer to the table “Number of wait states according to
CPU clock (frcc_c_ck) frequency and VCORE range” available in the reference manual).
•When the peripherals are enabled, the AHB clock frequency is the CPU frequency
divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.
The parameters given in Table 30 to Table 38 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 24: General
operating conditions.
VREFINT_DIV1 1/4 reference voltage - - 25 -
%
VREFINT
VREFINT_DIV2 1/2 reference voltage - - 50 -
VREFINT_DIV3 3/4 reference voltage - - 75 -
1. The shortest sampling time for the application can be determined by multiple iterations.
2. Guaranteed by design.
Table 28. Embedded reference voltage (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 29. Internal reference voltage calibration values
Symbol Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 1FF1E860 - 1FF1E861
DS12110 Rev 7 113/357
STM32H742xI/G STM32H743xI/G Electrical characteristics (rev Y)
322
Table 30. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, regulator ON(1)
Symbol Parameter Conditions frcc_c_ck
(MHz) Typ
Max(2)
unit
TJ =
25°C
TJ =
85°C
TJ =
105°C
TJ =
125°C
IDD
Supply
current in Run
mode
All
peripherals
disabled
VOS1
400 71 110 210 290 540
mA
30056----
VOS2
300 50 72 170 230 370
216 37 58 150 210 380
20035.5----
VOS3
200 33 50 130 190 300
180 30 47 130 180 290
168 28 45 130 180 290
144 25 41 120 180 290
60 13 28 110 160 280
25 10 24 99 160 270
All
peripherals
enabled
VOS1
400 165 220(3) 400 500(3) 840
300130----
VOS2
300 120 170 300 390 570
20083----
VOS3 200 78 110 220 300 470
1. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
2. Guaranteed by characterization results unless otherwise specified.
3. Guaranteed by test in production.
Electrical characteristics (rev Y) STM32H742xI/G STM32H743xI/G
114/357 DS12110 Rev 7
Table 31. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON, regulator ON
Symbol Parameter Conditions frcc_c_ck
(MHz) Typ
Max(1)
unit
TJ =
25°C
TJ =
85°C
TJ =
105°C
TJ =
125°C
IDD
Supply
current in Run
mode
All
peripherals
disabled
VOS1
400 105 160 310 420 750
mA
30055----
VOS2
300 50 72 160 230 370
21638----
20036----
VOS3
200 33 50 130 190 300
18030----
16829----
14426----
6014----
2514----
All
peripherals
enabled
VOS1
400 160 220 400 500 750
300130----
VOS2
300 120 160 300 390 560
20081----
VOS3 200 77 110 220 300 460
1. Guaranteed by characterization results unless otherwise specified.
Table 32. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF, regulator ON
Symbol Parameter Conditions frcc_c_ck
(MHz) Typ
Max(1)
unit
TJ =
25°C
TJ =
85°C
TJ =
105°C
TJ =
125°C
IDD
Supply
current in Run
mode
All
peripherals
disabled
VOS1 400 73 110 220 290 540
mA
VOS2 300 52 75 170 230 370
VOS3 200 34 52 130 190 300
All
peripherals
enabled
VOS1 400 135 190 360 470 730
VOS2 300 100 150 270 370 550
VOS3 200 70 100 210 300 460
1. Guaranteed by characterization results.
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STM32H742xI/G STM32H743xI/G Electrical characteristics (rev Y)
322
Table 33. Typical consumption in Run mode and corresponding performance
versus code position
Symbol Parameter
Conditions frcc_c_ck
(MHz) CoreMark Typ Unit IDD/
CoreMark Unit
Peripheral Code
IDD
Supply current
in Run mode
All
peripherals
disabled,
cache ON
ITCM 400 2012 71
mA
35
µA/
CoreMark
FLASH
A400 2012 105 52
AXI
SRAM 400 2012 105 52
SRAM1 400 2012 105 52
SRAM4 400 2012 105 52
All
peripherals
disabled
cache OFF
ITCM 400 2012 71 35
FLASH
A400 593 70.5 119
AXI
SRAM 400 344 70.5 205
SRAM1 400 472 74.5 158
SRAM4 400 432 72 167
Table 34. Typical current consumption batch acquisition mode
Symbol Parameter Conditions frcc_ahb_ck(AHB4)
(MHz) Typ unit
IDD
Supply current in
batch acquisition
mode
D1Standby,
D2Standby,
D3Run
VOS3 64 6.5
mA
D1Stop, D2Stop,
D3Run VOS3 64 12
Table 35. Typical and maximum current consumption in Sleep mode, regulator ON
Symbol Parameter Conditions frcc_c_ck
(MHz) Typ
Max(1)
unit
TJ =
25°C
TJ =
85°C
TJ =
105°C
TJ =
125°C
IDD(Sleep)
Supply
current in
Sleep mode
All
peripherals
disabled
VOS1
400 31.0 64 220 330 660
mA
300 24.5 57 210 330 650
VOS2
300 22.0 48 180 270 500
200 17.0 42 170 270 490
VOS3 200 15.5 37 150 230 400
1. Guaranteed by characterization results.
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Table 36. Typical and maximum current consumption in Stop mode, regulator ON
Symbol Parameter Conditions Typ
Max(1)
unit
TJ =
25°C
TJ =
85°C
TJ =
105°C
TJ =
125°C
IDD(Stop)
D1Stop,
D2Stop,
D3Stop
Flash
memory in
low-power
mode, no
IWDG
SVOS5 1.4 7.2(2) 49 75(2) 140
mA
SVOS4 1.95 11 66 110 200
SVOS3 2.85 16(2) 91 150(2) 240
Flash
memory ON,
no IWDG
SVOS5 1.65 7.2 49 75 140
SVOS4 2.2 11 66 110 180
SVOS3 3.15 16 91 150 300
D1Stop,
D2Standby,
D3Stop
Flash
memory
OFF, no
IWDG
SVOS5 0.99 5.1 35 60 97
SVOS4 1.4 7.5 47 79 130
SVOS3 2.05 12 64 110 170
Flash
memory ON,
no IWDG
SVOS5 1.25 5.5 35 61 98
SVOS4 1.65 7.8 47 80 130
SVOS3 2.3 12 65 110 170
D1Standby,
D2Stop,
D3Stop
Flash OFF,
no IWDG
SVOS5 0.57 3 21 36 57
SVOS4 0.805 4.5 27 47 74
SVOS3 1.2 6.7 37 63 99
D1Standby,
D2Standby,
D3Stop
SVOS5 0.17 1.1(2) 813
(2) 20
SVOS4 0.245 1.5 11 17 26
SVOS3 0.405 2.4(2) 15 23(2) 35
1. Guaranteed by characterization results.
2. Guaranteed by test in production.
Table 37. Typical and maximum current consumption in Standby mode
Symbol Parameter
Conditions Typ(3) Max (3 V)(1)
Unit
Backup
SRAM
RTC
& LSE 1.62 V 2.4 V 3 V 3.3 V TJ =
25°C
TJ =
85°C
TJ =
105°C
TJ =
125°C
IDD
(Standby)
Supply
current in
Standby
mode
OFF OFF 1.8 1.9 1.95 2.05 4(2) 18(3) 40(2) 90(3)
µA
ON OFF 3.4 3.4 3.5 3.7 8.2(3) 47(3) 83(3) 141(3)
OFF ON 2.4 3.5 3.86 4.12 - - - -
ON ON 3.95 5.1 5.46 5.97 - - - -
1. The maximum current consumption values are given for PDR OFF (internal reset OFF). When the PDR is OFF (internal
reset OFF), the current consumption is reduced by 1.2 µA compared to PDR ON.
2. Guaranteed by test in production.
3. Guaranteed by characterization results.
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322
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 60: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 39: Peripheral current
consumption in Run mode), the I/Os used by an application also contribute to the current
consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to
supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external)
connected to the pin:
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDx is the MCU supply voltage
fSW is the I/O switching frequency
CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT
Table 38. Typical and maximum current consumption in VBAT mode
Symbol Parameter
Conditions Typ(1) Max (3 V)
Unit
Backup
SRAM
RTC &
LSE 1.2 V 2 V 3 V 3.4 V TJ =
25°C
TJ =
85°C
TJ =
105°C
TJ =
125°C
IDD
(VBAT)
Supply
current in
standby
mode
OFF OFF 0.024 0.035 0.062 0.096 0.5(1) 4.1(1) 10(1) 24(1)
µA
ON OFF 1.4 1.6 1.8 1.8 4.4(1) 22(1) 48(1) 87(1)
OFF ON 0.24 0.45 0.62 0.73 - - - -
ON ON 1.97 2.37 2.57 2.77 - - - -
1. Guaranteed by characterization results.
ISW VDDx fSW CL
××=
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118/357 DS12110 Rev 7
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•At startup, all I/O pins are in analog input configuration.
•All peripherals are disabled unless otherwise mentioned.
•The I/O compensation cell is enabled.
•frcc_c_ck is the CPU clock. fPCLK = frcc_c_ck/4, and fHCLK = frcc_c_ck/2.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
–f
rcc_c_ck = 400 MHz (Scale 1), frcc_c_ck = 300 MHz (Scale 2),
frcc_c_ck = 200 MHz (Scale 3)
•The ambient operating temperature is 25 °C and VDD=3.3 V.
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322
Table 39. Peripheral current consumption in Run mode
Peripheral
IDD(Typ)
Unit
VOS1 VOS2 VOS3
AHB3
MDMA 8.3 7.6 7
µA/MHz
DMA2D212018
JPEG 24 23 21
FLASH 9.9 9 8.3
FMC registers 0.9 0.9 0.8
FMC kernel 6.1 5.5 5.3
QUADSPI
registers 1.5 1.4 1.3
QUADSPI kernel 0.9 0.8 0.7
SDMMC1
registers 87.26.8
SDMMC1 kernel 2.4 2 1.8
DTCM1 5.7 5 4.5
DTCM2 5.5 4.8 4.3
ITCM 3.2 2.9 2.6
D1SRAM1 7.6 6.8 6.1
AHB3 bridge 7.5 6.8 6.3
AHB1
DMA1 1.1 1 1
DMA2 1.7 1.4 1.1
ADC1/2 registers 3.9 3.2 3.1
ADC1/2 kernel 0.9 0.8 0.7
ART accelerator 5.5 4.5 4.2
ETH1MAC
16 14 13ETH1TX
ETH1RX
USB1 OTG
registers 15 14 13
USB1 OTG kernel - 8.5 8.5
USB1 ULPI 0.3 0.3 0.1
USB2 OTG
registers 15 13 12
USB2 OTG kernel - 8.6 8.6
USB2 ULPI 16 16 16
AHB1 Bridge 10 9.6 8.6
Electrical characteristics (rev Y) STM32H742xI/G STM32H743xI/G
120/357 DS12110 Rev 7
AHB2
DCMI 1.7 1.7 1.7
µA/MHz
RNG registers 1.8 1.4 1.2
RNG kernel - 9.6 9.6
SDMMC2
registers 13 12 11
SDMMC2 kernel 2.7 2.5 2.4
D2SRAM1 3.3 3.1 2.8
D2SRAM2 2.9 2.7 2.5
D2SRAM3 1.9 1.8 1.7
AHB2 bridge 0.1 0.1 0.1
AHB4
GPIOA 1.1 1 0.9
GPIOB 1 0.9 0.9
GPIOC 1.4 1.3 1.3
GPIOD 1.1 1 0.9
GPIOE 1 0.9 0.8
GPIOF 0.9 0.8 0.8
GPIOG 0.9 0.7 0.7
GPIOH 1 0.9 0.9
GPIOI 0.9 0.9 0.8
GPIOJ 0.9 0.8 0.8
GPIOK 0.9 0.8 0.7
CRC 0.5 0.4 0.4
BDMA 6.2 5.8 5.5
ADC3 registers 1.8 1.7 1.7
ADC3 kernel 0.1 0.1 0.1
Backup SRAM 1.9 1.8 1.8
Bridge AHB4 0.1 0.1 0.1
APB3
LCD-TFT 12 11 10
µA/MHzWWDG1 0.5 0.4 0.3
APB3 bridge 0.5 0.2 0.1
Table 39. Peripheral current consumption in Run mode (continued)
Peripheral
IDD(Typ)
Unit
VOS1 VOS2 VOS3
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STM32H742xI/G STM32H743xI/G Electrical characteristics (rev Y)
322
APB1
TIM2 3.5 3.2 2.9
µA/MHz
TIM3 3.4 3.1 2.7
TIM4 2.7 2.5 1.9
TIM5 3.2 2.9 2.5
TIM6 1 0.8 0.7
TIM7 1 0.9 0.7
TIM12 1.7 1.5 1.2
TIM13 1.5 1.3 1
TIM14 1.4 1.3 0.9
LPTIM1 registers 0.7 0.6 0.5
LPTIM1 kernel 2.3 2.1 1.9
WWDG2 0.6 0.4 0.4
SPI2 registers 1.8 1.5 1.2
SPI2 kernel 0.6 0.5 0.5
SPI3 registers 1.5 1.3 1.1
SPI3 kernel 0.6 0.5 0.5
SPDIFRX1
registers 0.6 0.5 0.3
SPDIFRX1 kernel 2.9 2.4 2.4
USART2 registers 1.4 1.3 1
USART2 kernel 4.7 4.1 4
USART3 registers 1.4 1.3 1
USART3 kernel 4.2 3.8 3.5
UART4 registers 1.5 1.1 1
UART4 kernel 3.7 3.6 3.2
Table 39. Peripheral current consumption in Run mode (continued)
Peripheral
IDD(Typ)
Unit
VOS1 VOS2 VOS3
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122/357 DS12110 Rev 7
APB1
(continued)
UART5 registers 1.4 1.4 1
µA/MHz
UART5 kernel 3.6 3.2 3.1
I2C1 registers 0.8 0.8 0.6
I2C1 kernel 2 1.8 1.7
I2C2 registers 0.7 0.7 0.4
I2C2 kernel 1.9 1.7 1.6
I2C3 registers 0.9 0.7 0.6
I2C3 kernel 2.1 1.9 1.9
HDMI-CEC
registers 0.5 0.3 0.3
DAC1/2 1.4 1.1 0.9
USART7 registers 1.9 1.8 1.3
USART7 kernel 4 3.5 3.3
USART8 registers 1.6 1.5 1.2
USART8 kernel 4 3.6 3.3
CRS 3.4 3.1 2.9
SWPMI registers 2.3 2 2
SWPMI kernel 0.1 0.1 0.1
OPAMP 0.5 0.4 0.4
MDIO 2.7 2.4 2.3
FDCAN registers 16 15 14
FDCAN kernel 7.8 7.6 7.1
Bridge APB1 0.1 0.1 0.1
Table 39. Peripheral current consumption in Run mode (continued)
Peripheral
IDD(Typ)
Unit
VOS1 VOS2 VOS3
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322
APB2
TIM1 5.1 4.8 4.3
µA/MHz
TIM8 5.4 4.9 4.6
USART1 registers 2.7 2.6 2.5
USART1 kernel 0.1 0.1 0.1
USART6 registers 2.6 2.5 2.5
USART6 kernel 0.1 0.1 0.1
SPI1 registers 1.8 1.6 1.6
SPI1 kernel 1 0.8 0.6
SPI4 registers 1.6 1.5 1.5
SPI4 kernel 0.5 0.4 0.4
TIM15 3.1 2.8 2.7
TIM16 2.4 2.1 2.1
TIM17 2.2 2 1.9
SPI5 registers 1.8 1.7 1.7
SPI5 kernel 0.6 0.5 0.3
SAI1 registers 1.5 1.4 1.4
SAI1 kernel 2 1.7 1.5
SAI2 registers 1.5 1.5 1.3
SAI2 kernel 2.2 1.9 1.8
SAI3 registers 1.8 1.6 1.6
SAI3 kernel 2.5 2.3 2.1
DFSDM1 registers 6 5.4 5.2
DFSDM1 kernel 0.9 0.8 0.7
HRTIM403735
Bridge APB2 0.1 0.1 0.1
Table 39. Peripheral current consumption in Run mode (continued)
Peripheral
IDD(Typ)
Unit
VOS1 VOS2 VOS3
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APB4
SYSCFG 1 0.7 0.7
µA/MHz
LPUART1
registers 1.1 1.1 1.1
LPUART1 kernel 2.6 2.4 2.1
SPI6 registers 1.6 1.5 1.4
SPI6 kernel 0.2 0.2 0.2
I2C4 registers 0.1 0.1 0.1
I2C4 kernel 2.4 2.1 2
LPTIM2 registers 0.5 0.5 0.5
LPTIM2 kernel 2.3 2.1 1.8
LPTIM3 registers 0.5 0.5 0.5
LPTIM3 kernel 2 2.1 1.5
LPTIM4 registers 0.5 0.5 0.5
LPTIM4 kernel 2 2 1.9
LPTIM5 registers 0.5 0.5 0.5
LPTIM5 kernel 2 1.8 1.5
COMP1/2 0.7 0.5 0.5
VREFBUF 0.6 0.4 0.4
RTC 1.2 1.1 1.1
SAI4 registers 1.6 1.5 1.4
SAI4 kernel 1.3 1.3 1.2
Bridge APB4 0.1 0.1 0.1
Table 40. Peripheral current consumption in Stop, Standby and VBAT mode
Symbol Parameter Conditions
Typ
Unit
3 V
IDD
RTC+LSE low drive - 2.32
µA
RTC+LSE medium-
low drive -2.4
RTC+LSE medium-
high drive -2.7
RTC+LSE High drive - 3
Table 39. Peripheral current consumption in Run mode (continued)
Peripheral
IDD(Typ)
Unit
VOS1 VOS2 VOS3
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322
6.3.7 Wakeup time from low-power modes
The wakeup times given in Table 41 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•For Stop or Sleep modes: the wakeup event is WFE.
•WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.
Table 41. Low-power mode wakeup timings
Symbol Parameter Conditions Typ(1) Max(1) Unit
tWUSLEEP(2) Wakeup from Sleep - 9 10
CPU
clock
cycles
tWUSTOP(2) Wakeup from Stop
VOS3, HSI, Flash memory in normal mode 4.4 5.6
µs
VOS3, HSI, Flash memory in low-power
mode 12 15
VOS4, HSI, Flash memory in normal mode 15 20
VOS4, HSI, Flash memory in low-power
mode 23 28
VOS5, HSI, Flash memory in normal mode 30 71
VOS5, HSI, Flash memory in low-power
mode 38 47
VOS3, CSI, Flash memory in normal mode 27 37
VOS3, CSI, Flash memory in low power
mode 36 50
VOS4, CSI, Flash memory in normal mode 38 48
VOS4, CSI, Flash memory in low-power
mode 47 61
VOS5, CSI, Flash memory in normal mode 52 64
VOS5, CSI, Flash memory in low-power
mode 62 77
tWUSTOP2(2) Wakeup from Stop,
clock kept running
VOS3, HSI, Flash memory in normal mode 2.6 3.4
VOS3, CSI, Flash memory in normal mode 26 36
tWUSTDBY(2) Wakeup from Standby
mode - 390 500
1. Guaranteed by characterization results.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
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126/357 DS12110 Rev 7
6.3.8 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
The external clock signal has to respect the Table 60: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 18.
Figure 18. High-speed external clock source AC timing diagram
Table 42. High-speed external user clock characteristics(1)
1. Guaranteed by design.
Symbol Parameter Min Typ Max Unit
fHSE_ext User external clock source frequency 4 25 50 MHz
VSW
(VHSEH −VHSEL)
OSC_IN amplitude 0.7VDD -V
DD V
VDC OSC_IN input voltage VSS -0.3V
SS
tW(HSE) OSC_IN high or low time 7 - - ns
ai17528b
OSC _I N
External
STM32
clock source
VHSEH
tf(HSE) tW(HSE)
IL
90 %
10 %
THSE
t
tr(HSE) tW(HSE)
fHSE_ext
VHSEL
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322
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 60: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 19.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 19. Low-speed external clock source AC timing diagram
Table 43. Low-speed external user clock characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext User external clock source frequency - - 32.768 1000 kHz
VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx -V
DDIOx V
VLSEL OSC32_IN input pin low level voltage - VSS -0.3 V
DDIOx
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time - 250 - - ns
1. Guaranteed by design.
ai17529b
OSC32_IN
External
STM32
clock source
VLSEH
tf(LSE) tW(LSE)
IL
90%
10%
TLSE
t
tr(LSE) tW(LSE)
fLSE_ext
VLSEL
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128/357 DS12110 Rev 7
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 44. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 20). CL1 and CL2 are usually
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Table 44. 4-48 MHz HSE oscillator characteristics(1)
Symbol Parameter Operating
conditions(2) Min Typ Max Unit
F Oscillator frequency - 4 - 48 MHz
RFFeedback resistor - - 200 - k
IDD(HSE) HSE current consumption
During startup(3) -- 4
mA
VDD=3 V, Rm=30
CL=10pF@4MHz -0.35 -
VDD=3 V, Rm=30
CL=10 pF at 8 MHz -0.40 -
VDD=3 V, Rm=30
CL=10 pF at 16 MHz -0.45 -
VDD=3 V, Rm=30
CL=10 pF at 32 MHz -0.65 -
VDD=3 V, Rm=30
CL=10 pF at 48 MHz -0.95 -
Gmcritmax Maximum critical crystal gm Startup - - 1.5 mA/V
tSU(4) Start-up time VDD is stabilized - 2 - ms
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
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STM32H742xI/G STM32H743xI/G Electrical characteristics (rev Y)
322
Figure 20. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 45. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
ai17530b
OSC_OU T
OSC_IN fHSE
CL1
RF
STM32
8 MHz
resonator
Resonator with
integrated capacitors
Bias
controlled
gain
REXT(1)
CL2
Table 45. Low-speed external user clock characteristics(1)
Symbol Parameter Operating conditions(2) Min Typ Max Unit
F Oscillator frequency - - 32.768 - kHz
IDD
LSE current
consumption
LSEDRV[1:0] = 00,
Low drive capability -290 -
nA
LSEDRV[1:0] = 01,
Medium Low drive capability -390 -
LSEDRV[1:0] = 10,
Medium high drive capability -550 -
LSEDRV[1:0] = 11,
High drive capability -900 -
Gmcritmax
Maximum critical crystal
gm
LSEDRV[1:0] = 00,
Low drive capability --0.5
µA/V
LSEDRV[1:0] = 01,
Medium Low drive capability - - 0.75
LSEDRV[1:0] = 10,
Medium high drive capability --1.7
LSEDRV[1:0] = 11,
High drive capability --2.7
tSU(3) Startup time VDD is stabilized - 2 - s
1. Guaranteed by design.
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130/357 DS12110 Rev 7
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 21. Typical application with a 32.768 kHz crystal
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
6.3.9 Internal clock source characteristics
The parameters given in Table 46 and Table 49 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 24: General
operating conditions.
48 MHz high-speed internal RC oscillator (HSI48)
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
ai17531b
OSC32_OU T
OSC32_IN fLSE
CL1
RF
STM32
32.768 kHz
resonator
Resonator with
integrated capacitors
Bias
controlled
gain
CL2
Table 46. HSI48 oscillator characteristics
Symbol Parameter Conditions Min Typ Max Unit
fHSI48 HSI48 frequency VDD=3.3 V, TJ=30 °C 47.5(1) 48 48.5(1) MHz
TRIM(2) USER trimming step - - 0.17 - %
USER TRIM
COVERAGE(3) USER TRIMMING Coverage ± 32 steps - ±5.45 - %
DuCy(HSI48)(2) Duty Cycle - 45 - 55 %
ACCHSI48_REL(3) Accuracy of the HSI48 oscillator over
temperature (factory calibrated)
VDD=1.62 to 3.6 V,
TJ=-40 to 125 °C –4.5 - 3.5 %
VDD(HSI48)(3) HSI48 oscillator frequency drift with
VDD(4)
VDD=3 to 3.6 V - 0.025 0.05
%
VDD=1.62 V to 3.6 V - 0.05 0.1
tsu(HSI48)(2) HSI48 oscillator start-up time - - 2.1 3.5 µs
IDD(HSI48)(2) HSI48 oscillator power consumption - - 350 400 µA
NT jitter Next transition jitter
Accumulated jitter on 28 cycles(5) - - ± 0.15 - ns
PT jitter Paired transition jitter
Accumulated jitter on 56 cycles(5) - - ± 0.25 - ns
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64 MHz high-speed internal RC oscillator (HSI)
4 MHz low-power internal RC oscillator (CSI)
1. Guaranteed by test in production.
2. Guaranteed by design.
3. Guaranteed by characterization.
4. These values are obtained by using the formula:
(Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) / Freq(1.62V).
5. Jitter measurements are performed without clock source activated in parallel.
Table 47. HSI oscillator characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fHSI HSI frequency VDD=3.3 V, TJ=30 °C 63.7(2) 64 64.3(2) MHz
TRIM HSI user trimming step
Trimming is not a multiple
of 32 - 0.24 0.32
%
Trimming is 128, 256 and
384 5.2 1.8 -
Trimming is 64, 192, 320
and 448 1.4 0.8 -
Other trimming are a
multiple of 32 (not
including multiple of 64
and 128)
0.6 0.25 -
DuCy(HSI) Duty Cycle - 45 - 55 %
ΔVDD (HSI)
HSI oscillator frequency drift over
VDD (reference is 3.3 V) VDD=1.62 to 3.6 V 0.12 - 0.03 %
ΔTEMP (HSI)
HSI oscillator frequency drift over
temperature (reference is 64 MHz)
TJ=-20 to 105 °C 1(3) -1
(3) %
TJ=40 to TJmax °C 2(3) -1
(3)
tsu(HSI) HSI oscillator start-up time - - 1.4 2 µs
tstab(HSI) HSI oscillator stabilization time at 1% of target frequency - 4 8 µs
IDD(HSI) HSI oscillator power consumption - - 300 400 µA
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
Table 48. CSI oscillator characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fCSI CSI frequency VDD=3.3 V, TJ=30 °C 3.96(2) 44.04
(2) MHz
TRIM Trimming step - - 0.35 - %
DuCy(CSI) Duty Cycle - 45 - 55 %
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Low-speed internal (LSI) RC oscillator
6.3.10 PLL characteristics
The parameters given in Table 50 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 24: General operating conditions.
TEMP (CSI) CSI oscillator frequency drift over
temperature
TJ = 0 to 85 °C - 3.7(3) 4.5(3)
%
TJ = 40 to 125 °C - 11(3) 7.5(3)
DVDD (CSI) CSI oscillator frequency drift over
VDD
VDD = 1.62 to 3.6 V - 0.06 0.06 %
tsu(CSI) CSI oscillator startup time - - 1 2 µs
tstab(CSI)
CSI oscillator stabilization time
(to reach ±3% of fCSI)- - 4 8 cycle
IDD(CSI) CSI oscillator power consumption - - 23 30 µA
1. Guaranteed by design.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
Table 48. CSI oscillator characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 49. LSI oscillator characteristics
Symbol Parameter Conditions Min Typ Max Unit
fLSI(1)
1. Guaranteed by characterization results.
LSI frequency
VDD = 3.3 V, TJ = 25 °C 31.4 32 32.6
kHz
TJ = –40 to 105 °C, VDD =
1.62 to 3.6 V 29.76 - 33.60
tsu(LSI)(2)
2. Guaranteed by design.
LSI oscillator startup time - - 80 130
µs
tstab(LSI)(2) LSI oscillator stabilization
time (5% of final value) - - 120 170
IDD(LSI)(2) LSI oscillator power
consumption - - 130 280 nA
Table 50. PLL characteristics (wide VCO frequency range)(1)
Symbol Parameter Conditions Min Typ Max Unit
fPLL_IN
PLL input clock - 2 - 16 MHz
PLL input clock duty cycle - 10 - 90 %
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fPLL_P_OUT PLL multiplier output clock P
VOS1 1.5 - 400(2)
MHz
VOS2 1.5 - 300
VOS3 1.5 - 200
fPLL_Q_OUT PLL multiplier output clock Q/R
VOS1 1.5 - 400(2)
VOS2 1.5 - 300
VOS3 1.5 - 200
fVCO_OUT PLL VCO output - 192 - 836
tLOCK PLL lock time
Normal mode - 50(3) 150(3)
µs
Sigma-delta mode
(CKIN ≥ 8 MHz) -58
(3) 166(3)
Jitter
Cycle-to-cycle jitter(4)
VCO = 192 MHz - 134 -
±ps
VCO = 200 MHz - 134 -
VCO = 400 MHz - 76 -
VCO = 800 MHz - 39 -
Long term jitter
Normal mode - ±0.7 -
%
Sigma-delta mode
(CKIN = 16 MHz) -±0.8 -
IDD(PLL)(3) PLL power consumption on VDD
VCO freq =
420 MHz
VDDA - 440 1150
µA
VCORE - 530 -
VCO freq =
150 MHz
VDDA - 180 500
VCORE - 200 -
1. Guaranteed by design unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation (400 MHz for VOS1, 300 MHz for VOS2,
200 MHz for VOS3).
3. Guaranteed by characterization results.
4. Integer mode only.
Table 50. PLL characteristics (wide VCO frequency range)(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 51. PLL characteristics (medium VCO frequency range)(1)
Symbol Parameter Conditions Min Typ Max Unit
fPLL_IN
PLL input clock - 1 - 2 MHz
PLL input clock duty cycle - 10 - 90 %
fPLL_OUT
PLL multiplier output clock P, Q,
R
VOS1 1.17 - 210
MHzVOS2 1.17 - 210
VOS3 1.17 - 200
fVCO_OUT PLL VCO output - 150 - 420 MHz
tLOCK PLL lock time
Normal mode - 60(2) 100(2) µs
Sigma-delta mode forbidden - - µs
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6.3.11 Memory characteristics
Flash memory
The characteristics are given at TJ = –40 to 125 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Jitter
Cycle-to-cycle jitter(3) -
VCO =
150 MHz -145-
+/-
ps
VCO =
300 MHz -91-
VCO =
400 MHz -64-
VCO =
420 MHz -63-
Period jitter fPLL_OUT =
50 MHz
VCO =
150 MHz -55-
+/-
ps
VCO =
400 MHz -30-
Long term jitter Normal mode
VCO =
150 MHz ---
%
VCO =
300 MHz ---
VCO =
400 MHz -+/-0.3-
I(PLL)(2) PLL power consumption on VDD
VCO freq =
420MHz
VDD - 440 1150
µA
VCORE - 530 -
VCO freq =
150MHz
VDD - 180 500
VCORE - 200 -
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by characterization results.
3. Integer mode only.
Table 51. PLL characteristics (medium VCO frequency range)(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 52. Flash memory characteristics
Symbol Parameter Conditions Min Typ Max Unit
IDD Supply current
Write / Erase 8-bit mode - 6.5 -
mA
Write / Erase 16-bit mode - 11.5 -
Write / Erase 32-bit mode - 20 -
Write / Erase 64-bit mode - 35 -
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Table 53. Flash memory programming (single bank configuration nDBANK=1)
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
tprog
Word (266 bits) programming
time
Program/erase parallelism x 8 - 290 580(2)
µs
Program/erase parallelism x 16 - 180 360
Program/erase parallelism x 32 - 130 260
Program/erase parallelism x 64 - 100 200
tERASE128KB Sector (128 KB) erase time
Program/erase parallelism x 8 - 2 4
s
Program/erase parallelism x 16 - 1.8 3.6
Program/erase parallelism x 32 -
tME Mass erase time
Program/erase parallelism x 8 - 13 26
Program/erase parallelism x 16 - 8 16
Program/erase parallelism x 32 - 6 12
Program/erase parallelism x 64 - 5 10
Vprog Programming voltage
Program parallelism x 8
1.62 - 3.6
V
Program parallelism x 16
Program parallelism x 32
Program parallelism x 64 1.8 - 3.6
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 10K erase operations.
Table 54. Flash memory endurance and data retention
Symbol Parameter Conditions
Value
Unit
Min(1)
NEND Endurance TJ = –40 to +125 °C (6 suffix versions) 10 kcycles
tRET
Data retention 1 kcycle at TA = 85 °C 30
Years
10 kcycles at TA = 55 °C 20
1. Guaranteed by characterization results.
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6.3.12 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 55. They are based on the EMS levels and classes
defined in application note AN1709.
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•Corrupted program counter
•Unexpected reset
•Critical Data corruption (control registers...)
Table 55. EMS characteristics
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on any I/O pin to induce
a functional disturbance VDD = 3.3 V, TA = +25 °C,
UFBGA240, frcc_c_ck =
400 MHz, conforms to
IEC 61000-4-2
3B
VFTB
Fast transient voltage burst limits to be applied
through 100 pF on VDD and VSS pins to induce a
functional disturbance
4B
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Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
6.3.13 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 56. EMI characteristics
Symbol Parameter Conditions Monitored
frequency band
Max vs.
[fHSE/fCPU]Unit
8/400 MHz
SEMI Peak level VDD = 3.6 V, TA = 25 °C, UFBGA240 package,
conforming to IEC61967-2
0.1 to 30 MHz 6
dBµV
30 to 130 MHz 5
130 MHz to 1 GHz 13
1 GHz to 2 GHz 7
EMI Level 2.5 -
Table 57. ESD absolute maximum ratings
Symbol Ratings Conditions Packages Class Maximum
value(1) Unit
VESD(HBM)
Electrostatic discharge
voltage (human body
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS-
001
All 1C 1000
V
VESD(CDM)
Electrostatic discharge
voltage (charge device
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS-
002
All C1 250
1. Guaranteed by characterization results.
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Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•A supply overvoltage is applied to each power supply pin
•A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
6.3.14 I/O current injection characteristics
As a general rule, a current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
Table 58. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latchup class TA = +25 °C conforming to JESD78 II level A
Table 59. I/O current injection susceptibility(1)
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
IINJ
PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15,
PJ12, PB4 50
mA
PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11 0 NA
PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4,
PA5, PH4, PH5, BOOT0 00
All other I/Os 5 NA
1. Guaranteed by characterization.
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6.3.15 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 60: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 24: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
Table 60. I/O static characteristics
Symbol Parameter Condition Min Typ Max Unit
VIL
I/O input low level voltage except
BOOT0
1.62 V<VDDIOx<3.6 V
--0.3V
DD(1)
V
I/O input low level voltage except
BOOT0 --
0.4VDD
0.1(2)
BOOT0 I/O input low level voltage - - 0.19VDD+
0.1(2)
VIH
I/O input high level voltage except
BOOT0
1.62 V<VDDIOx<3.6 V
0.7VDD(1) --
V
I/O input high level voltage except
BOOT0(3)
0.47VDD+
0.25(2) --
BOOT0 I/O input high level
voltage(3)
0.17VDD+
0.6(2) --
VHYS(2)
TT_xx, FT_xxx and NRST I/O
input hysteresis 1.62 V< VDDIOx <3.6 V
- 250 -
mV
BOOT0 I/O input hysteresis - 200 -
Ileak(4)
FT_xx Input leakage current(2)
0< VIN Max(VDDXXX)(9) --+/-250
nA
Max(VDDXXX) < VIN 5.5 V
(5)(6)(9) - - 1500
FT_u IO
0< VIN Max(VDDXXX)(9) --+/- 350
Max(VDDXXX) < VIN 5.5 V
(5)(6)(9) - - 5000(7)
TT_xx Input leakage current 0< VIN Max(VDDXXX) (9) --+/-250
VPP (BOOT0 alternate function)
0< VIN VDDIOX --15
VDDIOX < VIN 9 V 35
RPU
Weak pull-up equivalent
resistor(8) VIN=VSS 30 40 50
k
RPD
Weak pull-down equivalent
resistor(8) VIN=VDD(9) 30 40 50
CIO I/O pin capacitance - - 5 - pF
1. Compliant with CMOS requirement.
2. Guaranteed by design.
3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 A + [number of I/Os where VIN is applied on the pad] Ilkg(Max).
5. All FT_xx IO except FT_lu, FT_u and PC3.
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All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 22.
Figure 22. VIL/VIH for all I/Os except BOOT0
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
•The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 22).
•The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 22).
6. VIN must be less than Max(VDDXXX) + 3.6 V.
7. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be
disabled.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
9. Max(VDDXXX) is the maximum value of all the I/O supplies.
MSv46121V3
0
0.5
1
1.5
2
2.5
3
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Voltage
TLL requirement: VIHmin = 2 V
TLL requirement: VILmin = 0.8 V
CMOS requirement: V
IHmin
=0.7V
DD
CMOS requirement: V
ILmax
=0.3V
DD
Based on simulation V
IHmin
=0.47V
DD
+0.25
Based on simulation V
ILmax
=0.4V
DD
-0.1
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Output voltage levels
Unless otherwise specified, the parameters given in Table 61 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 24: General operating conditions. All I/Os are CMOS and TTL compliant.
Table 61. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8(1)
Symbol Parameter Conditions(3) Min Max Unit
VOL Output low level voltage
CMOS port(2)
IIO=8 mA
2.7 V VDD 3.6 V
-0.4
V
VOH Output high level voltage
CMOS port(2)
IIO=-8 mA
2.7 V VDD 3.6 V
VDD0.4 -
VOL(3) Output low level voltage
TTL port(2)
IIO=8 mA
2.7 V VDD 3.6 V
-0.4
VOH(3) Output high level voltage
TTL port(2)
IIO=-8 mA
2.7 V VDD 3.6 V
2.4 -
VOL(3) Output low level voltage IIO=20 mA
2.7 V VDD 3.6 V -1.3
VOH(3) Output high level voltage IIO=-20 mA
2.7 V VDD 3.6 V VDD1.3 -
VOL(3) Output low level voltage IIO=4 mA
1.62 V VDD 3.6 V -0.4
VOH (3) Output high level voltage IIO=-4 mA
1.62 VVDD<3.6 V VDD-0.4 -
VOLFM+(3) Output low level voltage for an FTf
I/O pin in FM+ mode
IIO= 20 mA
2.3 V VDD3.6 V -0.4
IIO= 10 mA
1.62 V VDD 3.6 V -0.4
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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Table 62. Output voltage characteristics for PC13, PC14, PC15 and PI8(1)
Symbol Parameter Conditions(3) Min Max Unit
VOL Output low level voltage
CMOS port(2)
IIO=3 mA
2.7 V VDD 3.6 V
-0.4
V
VOH Output high level voltage
CMOS port(2)
IIO=-3 mA
2.7 V VDD 3.6 V
VDD0.4 -
VOL(3) Output low level voltage
TTL port(2)
IIO=3 mA
2.7 V VDD 3.6 V
-0.4
VOH(3) Output high level voltage
TTL port(2)
IIO=-3 mA
2.7 V VDD 3.6 V
2.4 -
VOL(3) Output low level voltage IIO=1.5 mA
1.62 V VDD 3.6 V -0.4
VOH(3) Output high level voltage IIO=-1.5 mA
1.62 V VDD 3.6 V VDD0.4 -
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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Output buffer timing characteristics (HSLV option disabled)
The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the
product voltage is below 2.5 V.
Table 63. Output timing characteristics (HSLV OFF)(1)(2)
Speed Symbol Parameter conditions Min Max Unit
00
Fmax(3) Maximum frequency
C=50 pF, 2.7 V VDD3.6 V - 12
MHz
C=50 pF, 1.62 VVDD2.7 V - 3
C=30 pF, 2.7 VVDD3.6 V - 12
C=30 pF, 1.62 VVDD2.7 V - 3
C=10 pF, 2.7 VVDD3.6 V - 16
C=10 pF, 1.62 VVDD2.7 V - 4
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 2.7 V VDD3.6 V - 16.6
ns
C=50 pF, 1.62 VVDD2.7 V - 33.3
C=30 pF, 2.7 VVDD3.6 V - 13.3
C=30 pF, 1.62 VVDD2.7 V - 25
C=10 pF, 2.7 VVDD3.6 V - 10
C=10 pF, 1.62 VVDD2.7 V - 20
01
Fmax(3) Maximum frequency
C=50 pF, 2.7 V VDD3.6 V - 60
MHz
C=50 pF, 1.62 VVDD2.7 V - 15
C=30 pF, 2.7 VVDD3.6 V - 80
C=30 pF, 1.62 VVDD2.7 V - 15
C=10 pF, 2.7 VVDD3.6 V - 110
C=10 pF, 1.62 VVDD2.7 V - 20
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 2.7 V VDD3.6 V - 5.2
ns
C=50 pF, 1.62 VVDD2.7 V - 10
C=30 pF, 2.7 VVDD3.6 V - 4.2
C=30 pF, 1.62 VVDD2.7 V - 7.5
C=10 pF, 2.7 VVDD3.6 V - 2.8
C=10 pF, 1.62 VVDD2.7 V - 5.2
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10
Fmax(3) Maximum frequency
C=50 pF, 2.7 VVDD3.6 V(5) -85
MHz
C=50 pF, 1.62 VVDD2.7 V(5) -35
C=30 pF, 2.7 VVDD3.6 V(5) -110
C=30 pF, 1.62 VVDD2.7 V(5) -40
C=10 pF, 2.7 VVDD3.6 V(5) - 166
C=10 pF, 1.62 VVDD2.7 V(5) - 100
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 2.7 VVDD3.6 V(5) -3.8
ns
C=50 pF, 1.62 VVDD2.7 V(5) -6.9
C=30 pF, 2.7 VVDD3.6 V(5) -2.8
C=30 pF, 1.62 VVDD2.7 V(5) -5.2
C=10 pF, 2.7 VVDD3.6 V(5) -1.8
C=10 pF, 1.62 VVDD2.7 V(5) -3.3
11
Fmax(3) Maximum frequency
C=50 pF, 2.7 VVDD3.6 V(5) - 100
MHz
C=50 pF, 1.62 VVDD2.7 V(5) -50
C=30 pF, 2.7 VVDD3.6 V(5) - 133
C=30 pF, 1.62 VVDD2.7 V(5) -66
C=10 pF, 2.7 VVDD3.6 V(5) - 220
C=10 pF, 1.62 VVDD2.7 V(5) -85
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 2.7 VVDD3.6 V(5) -3.3
ns
C=50 pF, 1.62 VVDD2.7 V(5) -6.6
C=30 pF, 2.7 VVDD3.6 V(5) -2.4
C=30 pF, 1.62 VVDD2.7 V(5) -4.5
C=10 pF, 2.7 VVDD3.6 V(5) -1.5
C=10 pF, 1.62 VVDD2.7 V(5) -2.7
1. Guaranteed by design.
2. The frequency of the GPIOs that can be supplied in VBAT mode (PC13, PC14, PC15 and PI8) is limited to 2 MHz
3. The maximum frequency is defined with the following conditions:
(tr+tf) 2/3 T
Skew 1/20 T
45%<Duty cycle<55%
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
5. Compensation system enabled.
Table 63. Output timing characteristics (HSLV OFF)(1)(2) (continued)
Speed Symbol Parameter conditions Min Max Unit
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Output buffer timing characteristics (HSLV option enabled)
Table 64. Output timing characteristics (HSLV ON)(1)
Speed Symbol Parameter conditions Min Max Unit
00
Fmax(2) Maximum frequency
C=50 pF, 1.62 VVDD2.7 V - 10
MHzC=30 pF, 1.62 VVDD2.7 V - 10
C=10 pF, 1.62 VVDD2.7 V - 10
tr/tf(3)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 1.62 VVDD2.7 V - 11
nsC=30 pF, 1.62 VVDD2.7 V - 9
C=10 pF, 1.62 VVDD2.7 V - 6.6
01
Fmax(3) Maximum frequency
C=50 pF, 1.62 VVDD2.7 V - 50
MHzC=30 pF, 1.62 VVDD2.7 V - 58
C=10 pF, 1.62 VVDD2.7 V - 66
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 1.62 VVDD2.7 V - 6.6
nsC=30 pF, 1.62 VVDD2.7 V - 4.8
C=10 pF, 1.62 VVDD2.7 V - 3
10
Fmax(3) Maximum frequency
C=50 pF, 1.62 VVDD2.7 V(4) -55
MHzC=30 pF, 1.62 VVDD2.7 V(5) -80
C=10 pF, 1.62 VVDD2.7 V(5) - 133
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 1.62 VVDD2.7 V(5) -5.8
nsC=30 pF, 1.62 VVDD2.7 V(5) -4
C=10 pF, 1.62 VVDD2.7 V(5) -2.4
11
Fmax(3) Maximum frequency
C=50 pF, 1.62 VVDD2.7 V(5) -60
MHzC=30 pF, 1.62 VVDD2.7 V(5) -90
C=10 pF, 1.62 VVDD2.7 V(5) - 175
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 1.62 VVDD2.7 V(5) -5.3
nsC=30 pF, 1.62 VVDD2.7 V(5) -3.6
C=10 pF, 1.62 VVDD2.7 V(5) -1.9
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions:
(tr+tf) 2/3 T
Skew 1/20 T
45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.
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6.3.16 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 60: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 65 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 24: General operating conditions.
Figure 23. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 60. Otherwise the reset is not taken into account by the device.
Table 65. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
RPU(2) Weak pull-up equivalent
resistor(1)
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
VIN = VSS 30 40 50 ㏀
VF(NRST)(2)
2. Guaranteed by design.
NRST Input filtered pulse 1.71 V < VDD < 3.6 V - - 50
ns
VNF(NRST)(2) NRST Input not filtered pulse
1.71 V < VDD < 3.6 V 300 - -
1.62 V < VDD < 3.6 V 1000 - -
ai14132d
STM32
RPU
NRST
(2)
VDD
Filter
Internal Reset
0.1 μF
External
reset circuit (1)
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6.3.17 FMC characteristics
Unless otherwise specified, the parameters given in Table 66 to Table 79 for the FMC
interface are derived from tests performed under the ambient temperature, frcc_c_ck
frequency and VDD supply voltage conditions summarized in Table 24: General operating
conditions, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 24 through Figure 27 represent asynchronous waveforms and Table 66 through
Table 73 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•AddressSetupTime = 0x1
•AddressHoldTime = 0x1
•DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
•BusTurnAroundDuration = 0x0
•Capcitive load CL = 30 pF
In all timing tables, the TKERCK is the fmc_ker_ck clock period.
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Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Data
FMC_NE
FMC_NBL[1:0]
FMC_D[15:0]
t
v(BL_NE)
th(Data_NE)
FMC_NOE
Address
FMC_A[25:0]
t
v(A_NE)
FMC_NWE
tsu(Data_NE)
tw(NE)
MS32753V1
w(NOE)
ttv(NOE_NE) th(NE_NOE)
th(Data_NOE)
th(A_NOE)
th(BL_NOE)
tsu(Data_NOE)
FMC_NADV (1)
tv(NADV_NE)
tw(NADV)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
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Table 66. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 2Tfmc_ker_ck 12 T
fmc_ker_ck +1
ns
tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5
tw(NOE) FMC_NOE low time 2Tfmc_ker_ck 12T
fmc_ker_ck + 1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
th(A_NOE) Address hold time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 -
tsu(Data_NE) Data to FMC_NEx high setup time 11 -
tsu(Data_NOE) Data to FMC_NOEx high setup time 11 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - Tfmc_ker_ck + 1
1. Guaranteed by characterization results.
Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings(1)(2)
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 7Tfmc_ker_ck +1 7Tfmc_ker_ck +1
ns
tw(NOE) FMC_NWE low time 5Tfmc_ker_ck 15T
fmc_ker_ck +1
tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck 0.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 4Tfmc_ker_ck +11 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 3Tfmc_ker_ck+11.5 -
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
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Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
NBL
Data
FMC_NEx
FMC_NBL[1:0]
FMC_D[15:0]
t
v(BL_NE)
th(Data_NWE)
FMC_NOE
Address
FMC_A[25:0]
t
v(A_NE)
tw(NWE)
FMC_NWE
tv(NWE_NE) th(NE_NWE)
th(A_NWE)
th(BL_NWE)
tv(Data_NE)
tw(NE)
MS32754V1
FMC_NADV (1)
tv(NADV_NE)
tw(NADV)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3Tfmc_ker_ck −13T
fmc_ker_ck
ns
tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck Tfmc_ker_ck + 1
tw(NWE) FMC_NWE low time Tfmc_ker_ck −0.5 Tfmc_ker_ck + 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck -
tv(A_NE) FMC_NEx low to FMC_A valid - 2
th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck −0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck −0.5 -
tv(Data_NE) Data to FMC_NEx low to Data valid - Tfmc_ker_ck + 2.5
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck+0.5 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - Tfmc_ker_ck + 1
1. Guaranteed by characterization results.
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Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms
Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1)(2)
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 8Tfmc_ker_ck −1 8T
fmc_ker_ck + 1
ns
tw(NWE) FMC_NWE low time 6Tfmc_ker_ck −1.5 6Tfmc_ker_ck + 0.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Tfmc_ker_ck + 13 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck+ 13 -
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
NBL
Data
FMC_ NBL[1:0]
FMC_ AD[15:0]
t
v(BL_NE)
th(Data_NE)
Address
FMC_ A[25:16]
t
v(A_NE)
FMC_NWE
tv(A_NE)
MS32755V1
Address
FMC_NADV
tv(NADV_NE)
tw(NADV)
tsu(Data_NE)
t
h(AD_NADV)
FMC_ NE
FMC_NOE
tw(NE)
tw(NOE)
tv(NOE_NE) th(NE_NOE)
th(A_NOE)
th(BL_NOE)
tsu(Data_NOE) th(Data_NOE)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
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Table 70. Asynchronous multiplexed PSRAM/NOR read timings(1)
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3Tfmc_ker_ck −13T
fmc_ker_ck + 1
ns
tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Tfmc_ker_ck 2Tfmc_ker_ck + 0.5
ttw(NOE) FMC_NOE low time Tfmc_ker_ck −1T
fmc_ker_ck + 1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time Tfmc_ker_ck −0.5 Tfmc_ker_ck+1
th(AD_NADV)
FMC_AD(address) valid hold time after
FMC_NADV high Tfmc_ker_ck + 0.5 -
th(A_NOE) Address hold time after FMC_NOE high Tfmc_ker_ck −0.5 -
th(BL_NOE) FMC_BL time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck −2 -
tsu(Data_NOE) Data to FMC_NOE high setup time Tfmc_ker_ck −2 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
1. Guaranteed by characterization results.
Table 71. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 8Tfmc_ker_ck −18T
fmc_ker_ck
ns
tw(NOE) FMC_NWE low time 5Tfmc_ker_ck −1.5 5Tfmc_ker_ck + 0.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Tfmc_ker_ck + 3 -
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid 4Tfmc_ker_ck -
1. Guaranteed by characterization results.
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Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms
NBL
Data
FMC_ NEx
FMC_ NBL[1:0]
FMC_ AD[15:0]
t
v(BL_NE)
th(Data_NWE)
FMC_NOE
Address
FMC_ A[25:16]
t
v(A_NE)
tw(NWE)
FMC_NWE
tv(NWE_NE) th(NE_NWE)
th(A_NWE)
th(BL_NWE)
tv(A_NE)
tw(NE)
MS32756V1
Address
FMC_NADV
tv(NADV_NE)
tw(NADV)
tv(Data_NADV)
t
h(AD_NADV)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
Table 72. Asynchronous multiplexed PSRAM/NOR write timings(1)
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 4Tfmc_ker_c −14T
fmc_ker_ck
ns
tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_c −1T
fmc_ker_ck + 0.5
tw(NWE) FMC_NWE low time 2Tfmc_ker_ck− 0.5 2Tfmc_ker_ck+ 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck − 0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time Tfmc_ker_ck Tfmc_ker_ck+ 1
th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck+0.5 -
th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck+0.5 -
th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck −0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tv(Data_NADV) FMC_NADV high to Data valid - Tfmc_ker_ck + 2
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck+0.5 -
1. Guaranteed by characterization results.
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Synchronous waveforms and timings
Figure 28 through Figure 31 represent synchronous waveforms and Table 74 through
Table 77 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•BurstAccessMode = FMC_BurstAccessMode_Enable
•MemoryType = FMC_MemoryType_CRAM
•WriteBurst = FMC_WriteBurst_Enable
•CLKDivision = 1
•DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_CLK maximum values:
•For 2.7 V<VDD<3.6 V, FMC_CLK =100 MHz at 20 pF
•For 1.8 V<VDD<1.9 V, FMC_CLK =100 MHz at 20 pF
•For 1.62 V<VDD<1.8 V, FMC_CLK =100 MHz at 15 pF
Table 73. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 9Tfmc_ker_ck – 1 9Tfmc_ker_ck
ns
tw(NWE) FMC_NWE low time 7Tfmc_ker_ck – 0.5 7Tfmc_ker_ck + 0.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6Tfmc_ker_ck + 3 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck -
1. Guaranteed by characterization results.
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Figure 28. Synchronous multiplexed NOR/PSRAM read timings
FMC_CLK
FMC_NEx
FMC_NADV
FMC_A[25:16]
FMC_NOE
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-AV)
td(CLKL-NADVH)
td(CLKH-AIV)
td(CLKL-NOEL) td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
tsu(ADV-CLKH)
th(CLKH-ADV)
tsu(ADV-CLKH) th(CLKH-ADV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32757V1
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Table 74. Synchronous multiplexed NOR/PSRAM read timings(1)
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2Tfmc_ker_ck − 1 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck + 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2.5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Tfmc_ker_ck -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck −0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 2 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 1 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 -
1. Guaranteed by characterization results.
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Figure 29. Synchronous multiplexed PSRAM write timings
FMC_CLK
FMC_NEx
FMC_NADV
FMC_A[25:16]
FMC_NWE
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-AV)
td(CLKL-NADVH)
td(CLKH-AIV)
td(CLKH-NWEH)
td(CLKL-NWEL)
td(CLKH-NBLH)
td(CLKL-ADV)
td(CLKL-ADIV) td(CLKL-Data)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32758V1
td(CLKL-Data)
FMC_NBL
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Table 75. Synchronous multiplexed PSRAM write timings(1)
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2Tfmc_ker_ck −1 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck + 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Tfmc_ker_ck -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck + 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 2.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 2.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck + 0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 -
1. Guaranteed by characterization results.
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Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings
FMC_CLK
FMC_NEx
FMC_A[25:0]
FMC_NOE
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-AV) td(CLKH-AIV)
td(CLKL-NOEL) td(CLKH-NOEH)
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32759V1
FMC_NADV
td(CLKL-NADVL) td(CLKL-NADVH)
Table 76. Synchronous non-multiplexed NOR/PSRAM read timings(1)
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2Tfmc_ker_ck −1 -
ns
t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck + 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Tfmc_ker_ck -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck + 0.5 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 2 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 1 -
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 -
1. Guaranteed by characterization results.
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Figure 31. Synchronous non-multiplexed PSRAM write timings
MS32760V1
FMC_CLK
FMC_NEx
FMC_A[25:0]
FMC_NWE
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-AV) td(CLKH-AIV)
td(CLKH-NWEH)
td(CLKL-NWEL)
td(CLKL-Data)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
FMC_NADV
td(CLKL-NADVL) td(CLKL-NADVH)
td(CLKL-Data)
FMC_NBL
td(CLKH-NBLH)
Table 77. Synchronous non-multiplexed PSRAM write timings(1)
Symbol Parameter Min Max Unit
t(CLK) FMC_CLK period 2Tfmc_ker_ck −1 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck + 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Tfmc_ker_ck -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck + 1 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck + 1 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 -
1. Guaranteed by characterization results.
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NAND controller waveforms and timings
Figure 32 through Figure 35 represent synchronous waveforms, and Table 78 and Table 79
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration:
•COM.FMC_SetupTime = 0x01
•COM.FMC_WaitSetupTime = 0x03
•COM.FMC_HoldSetupTime = 0x02
•COM.FMC_HiZSetupTime = 0x01
•ATT.FMC_SetupTime = 0x01
•ATT.FMC_WaitSetupTime = 0x03
•ATT.FMC_HoldSetupTime = 0x02
•ATT.FMC_HiZSetupTime = 0x01
•Bank = FMC_Bank_NAND
•MemoryDataWidth = FMC_MemoryDataWidth_16b
•ECC = FMC_ECC_Enable
•ECCPageSize = FMC_ECCPageSize_512Bytes
•TCLRSetupTime = 0
•TARSetupTime = 0
•CL = 30 pF
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Figure 32. NAND controller waveforms for read access
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
tsu(D-NOE) th(NOE-D)
MS32767V1
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(ALE-NOE) th(NOE-ALE)
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Figure 33. NAND controller waveforms for write access
Figure 34. NAND controller waveforms for common memory read access
MS32768V1
th(NWE-D)
tv(NWE-D)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(ALE-NWE) th(NWE-ALE)
MS32769V1
FMC_NWE
FMC_NOE
FMC_D[15:0]
tw(NOE)
tsu(D-NOE) th(NOE-D)
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(ALE-NOE) th(NOE-ALE)
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Figure 35. NAND controller waveforms for common memory write access
MS32770V1
tw(NWE)
th(NWE-D)
tv(NWE-D)
FMC_NWE
FMC_N
OE
FMC_D[15:0]
td(D-NWE)
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(ALE-NOE) th(NOE-ALE)
Table 78. Switching characteristics for NAND Flash read cycles(1)
Symbol Parameter Min Max Unit
tw(N0E) FMC_NOE low width 4Tfmc_ker_ck –0.5 4Tfmc_ker_ck + 0.5
ns
tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 8 -
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 -
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3Tfmc_ker_ck + 1
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4Tfmc_ker_ck −2-
1. Guaranteed by characterization results.
Table 79. Switching characteristics for NAND Flash write cycles(1)
Symbol Parameter Min Max Unit
tw(NWE) FMC_NWE low width 4Tfmc_ker_ck −0.5 4Tfmc_ker_ck + 0.5
ns
tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 -
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2Tfmc_ker_ck −0.5 -
td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5Tfmc_ker_ck −1-
td(ALE-NWE) FMC_ALE valid before FMC_NWE low - 3Tfmc_ker_ck + 0.5
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2Tfmc_ker_ck −1-
1. Guaranteed by characterization results.
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SDRAM waveforms and timings
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
•For 1.8 V<VDD<3.6V: FMC_CLK =100 MHz at 20 pF
•For 1.62 V<DD<1.8 V, FMC_CLK =100 MHz at 30 pF
Figure 36. SDRAM read access waveforms (CL = 1)
Table 80. SDRAM read timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck −12T
fmc_ker_ck + 0.5
ns
tsu(SDCLKH _Data) Data input setup time 2 -
th(SDCLKH_Data) Data input hold time 1 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL- SDNE) Chip select valid time - 1.5
th(SDCLKL_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
MS32751V2
Row n Col1
FMC_SDCLK
FMC_A[12:0]
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
FMC_D[31:0]
FMC_SDNE[1:0]
td(SDCLKL_AddR) td(SDCLKL_AddC)
th(SDCLKL_AddR)
th(SDCLKL_AddC)
td(SDCLKL_SNDE)
tsu(SDCLKH_Data) th(SDCLKH_Data)
Col2 Coli Coln
Data2 Datai DatanData1
th(SDCLKL_SNDE)
td(SDCLKL_NRAS)
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
th(SDCLKL_NRAS)
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Figure 37. SDRAM write access waveforms
Table 81. LPSDR SDRAM read timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck −12T
fmc_ker_ck + 0.5
ns
tsu(SDCLKH_Data) Data input setup time 2 -
th(SDCLKH_Data) Data input hold time 1.5 -
td(SDCLKL_Add) Address valid time - 2.5
td(SDCLKL_SDNE) Chip select valid time - 2.5
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS SDNRAS valid time - 0.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
MS32752V2
Row n Col1
FMC_SDCLK
FMC_A[12:0]
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
FMC_D[31:0]
FMC_SDNE[1:0]
td(SDCLKL_AddR) td(SDCLKL_AddC)
th(SDCLKL_AddR)
th(SDCLKL_AddC)
td(SDCLKL_SNDE)
td(SDCLKL_Data)
th(SDCLKL_Data)
Col2 Coli Coln
Data2 Datai DatanData1
th(SDCLKL_SNDE)
td(SDCLKL_NRAS)
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
th(SDCLKL_NRAS)
td(SDCLKL_NWE) th(SDCLKL_NWE)
FMC_NBL[3:0]
td(SDCLKL_NBL)
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Table 82. SDRAM write timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck −12T
fmc_ker_ck + 0.5
ns
td(SDCLKL _Data) Data output valid time - 3
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL_SDNWE) SDNWE valid time - 1.5
th(SDCLKL_SDNWE) SDNWE hold time 0.5 -
td(SDCLKL_ SDNE) Chip select valid time - 1.5
th(SDCLKL-_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1
td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 -
Table 83. LPSDR SDRAM write timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck −12T
fmc_ker_ck + 0.5
ns
td(SDCLKL _Data) Data output valid time - 2.5
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_Add) Address valid time - 2.5
td(SDCLKL-SDNWE) SDNWE valid time - 2.5
th(SDCLKL-SDNWE) SDNWE hold time 0 -
td(SDCLKL- SDNE) Chip select valid time - 3
th(SDCLKL- SDNE) Chip select hold time 0 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5
td(SDCLKL-SDNCAS) SDNCAS hold time 0 -
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6.3.18 Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 84 and Table 85 for QUADSPI
are derived from tests performed under the ambient temperature, frcc_c_ck frequency and
VDD supply voltage conditions summarized in Table 24: General operating conditions, with
the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Measurement points are done at CMOS levels: 0.5VDD
•I/O compensation cell enabled
•HSLV activated when VDD2.7 V
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 84. QUADSPI characteristics in SDR mode(1)
Symbol Parameter Conditions Min Typ Max Unit
Fck1/TCK QUADSPI clock frequency
2.7 V VDD<3.6 V
CL=20 pF --133
MHz
1.62 V<VDD<3.6 V
CL=15 pF --100
tw(CKH) QUADSPI clock high and low
time -
TCK/2–0.5 - TCK/2
ns
tw(CKL) TCK/2 - TCK/2 + 0.5
ts(IN) Data input setup time
-
1.5 - -
th(IN) Data input hold time 2 - -
tv(OUT) Data output valid time - - 1.5 2
th(OUT) Data output hold time - 0.5 - -
1. Guaranteed by characterization results.
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Figure 38. Quad-SPI timing diagram - SDR mode
Figure 39. Quad-SPI timing diagram - DDR mode
Table 85. QUADSPI characteristics in DDR mode(1)
Symbol Parameter Conditions Min Typ Max Unit
Fck1/t(CK)
QUADSPI clock
frequency
2.7 V<VDD<3.6 V
CL=20 pF --100
MHz
1.62 V<VDD<3.6 V
CL=15 pF --100
tw(CKH) QUADSPI clock high and
low time -
TCK/2 –0.5 - TCK/2
ns
tw(CKL) TCK/2 - TCK/2+0.5
tsr(IN), tsf(IN) Data input setup time - 2 - -
thr(IN), thf(IN) Data input hold time - 2 - -
tvr(OUT),
tvf(OUT) Data output valid time
DHHC=0 - 3.5 4
DHHC=1
Pres=1, 2... -T
CK/4+3.5 TCK/4+4
thr(OUT),
thf(OUT) Data output hold time
DHHC=0 3 - -
DHHC=1
Pres=1, 2... TCK/4+3 - -
1. Guaranteed by characterization results.
MSv36878V1
Data output D0 D1 D2
Clock
Data input D0 D1 D2
t(CK) tw(CKH) tw(CKL)
tr(CK) tf(CK)
ts(IN) th(IN)
tv(OUT) th(OUT)
MSv36879V1
Data output D0 D2 D4
Clock
Data input D0 D2 D4
t(CK) tw(CKH) tw(CKL)
tr(CK) tf(CK)
tsf(IN) thf(IN)
tvf(OUT) thr(OUT)
D1 D3 D5
D1 D3 D5
tvr(OUT) thf(OUT)
tsr(IN) thr(IN)
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6.3.19 Delay block (DLYB) characteristics
Unless otherwise specified, the parameters given in Table 87 for the delay block are derived
from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply
voltage summarized in Table 24: General operating conditions.
6.3.20 16-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 87 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 24: General operating conditions.
Table 86. Dynamics characteristics: Delay Block characteristics(1)
1. Guaranteed by characterization results.
Symbol Parameter Conditions Min Typ Max Unit
tinit Initial delay - 1400 2200 2400
ps
tUnit Delay - 35 40 45
Table 87. ADC characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA Analog power supply - 1.62 - 3.6
VVREF+ Positive reference voltage VDDA ≥2 V 2 - VDDA
VDDA< 2 V VDDA
VREF- Negative reference voltage - VSSA
fADC ADC clock frequency 2 V ≤VDDA ≤3.3 V BOOST = 1 - - 36 MHz
BOOST = 0 - - 20
fS
Sampling rate for Fast
channels, BOOST = 1,
fADC = 36 MHz(2)
16-bit resolution - - 3.60(2)
MSPS
14-bit resolution - - 4.00(2)
12-bit resolution - - 4.50(2)
10-bit resolution - - 5.00(2)
8-bit resolution 6.00(2)
Sampling rate for Fast
channels, BOOST = 0,
fADC = 20 MHz
16-bit resolution - - 2.00(2)
14-bit resolution - - 2.20(2)
12-bit resolution - - 2.50(2)
10-bit resolution - - 2.80(2)
8-bit resolution 3.30(2)
Sampling rate for Slow
channels, BOOST = 0,
fADC = 10 MHz
16-bit resolution - - 1.00
14-bit resolution - - 1.00
12-bit resolution - - 1.00
10-bit resolution - - 1.00
8-bit resolution 1.00
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fTRIG External trigger frequency fADC = 36 MHz - - 3.6 MHz
16-bit resolution - - 10 1/fADC
VAIN(3) Conversion voltage range - 0 - VREF+
V
VCMIV
Common mode input
voltage -VREF/2
10% VREF/2 VREF/2+
10%
RAIN External input impedance - - - 50 ㏀
CADC
Internal sample and hold
capacitor --4-pF
tADCREG_
STUP
ADC LDO startup time - - 5 10 µs
tSTAB ADC power-up time LDO already started 1 conversion
cycle
tCAL
Offset and linearity
calibration time - 165,010
1/fADC
tOFF_CAL Offset calibration time - 1,280
tLATR
Trigger conversion latency
for regular and injected
channels without aborting
the conversion
CKMODE = 00 1.5 2 2.5
CKMODE = 01 - - 2
CKMODE = 10 2.25
CKMODE = 11 2.125
tLATRINJ
Trigger conversion latency
for regular and injected
channels when a regular
conversion is aborted
CKMODE = 00 2.5 3 3.5
CKMODE = 01 - - 3
CKMODE = 10 - - 3.25
CKMODE = 11 - - 3.125
tSSampling time - 1.5 - 640.5
tCONV
Total conversion time
(including sampling time) N-bit resolution
tS + 0.5 + N/2
(9 to 648 cycles in 14-bit
mode)
1. Guaranteed by design.
2. These values are obtained using the following formula: fS = fADC/ tCONV ,
where fADC = 36 MHz and tCONV = 1,5 cycle sampling time + tSAR sampling time.
Refer to the product reference manual for the value of tSAR depending on resolution.
3. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.
Table 87. ADC characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
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Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
Table 88. ADC accuracy(1)(2)(3)
1. Guaranteed by characterization for BGA packages, the values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration.
3. The above table gives the ADC performance in 16-bit mode.
Symbol Parameter Conditions(4)
4. ADC clock frequency ≤36 MHz, 2 V VDDA 3.3 V, 1.6 V VREF VDDA, BOOSTEN (for I/O) = 1.
Min Typ Max Unit
ET
To t a l
unadjusted
error
Single
ended
BOOST = 1 - ±6 -
±LSB
BOOST = 0 - ±8 -
Differential
BOOST = 1 - ±10 -
BOOST = 0 - ±16 -
ED
Differential
linearity
error
Single
ended
BOOST = 1 - 2 -
BOOST = 0 - 1 -
Differential
BOOST = 1 - 8 -
BOOST = 0 - 2 -
EL
Integral
linearity
error
Single
ended
BOOST = 1 - ±6 -
BOOST = 0 - ±4 -
Differential
BOOST = 1 - ±6 -
BOOST = 0 - ±4 -
ENOB(5)
5. ENOB, SINAD, SNR and THD are specified for VDDA = VREF = 3.3 V.
Effective
number of
bits
(2 MSPS)
Single
ended
BOOST = 1 - 11.6 -
bits
BOOST = 0 - 12 -
Differential
BOOST = 1 - 13.3 -
BOOST = 0 - 13.5 -
SINAD(5)
Signal-to-
noise and
distortion
ratio
(2 MSPS)
Single
ended
BOOST = 1 - 71.6 -
dB
BOOST = 0 - 74 -
Differential
BOOST = 1 - 81.83 -
BOOST = 0 - 83 -
SNR(5)
Signal-to-
noise ratio
(2 MSPS)
Single
ended
BOOST = 1 - 72 -
BOOST = 0 - 74 -
Differential
BOOST = 1 - 82 -
BOOST = 0 - 83 -
THD(5)
To t a l
harmonic
distortion
Single
ended
BOOST = 1 - 78 -
BOOST = 0 - 80 -
Differential
BOOST = 1 - 90 -
BOOST = 0 - 95 -
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being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 6.3.14 does not affect the ADC accuracy.
Figure 40. ADC accuracy characteristics (12-bit resolution)
1. Example of an actual transfer curve.
2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
ai14395c
EO
EG
1L SBIDEAL
4095
4094
4093
5
4
3
2
1
0
7
6
1 2 3 456 7 4093 4094 4095 4096
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
VREF+
4096 (or depending on package)]
VDDA
4096
[1LSB IDEAL
=
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Figure 41. Typical connection diagram using the ADC
1. Refer to Table 87 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
ai17534b
STM32
VDD
AINx
IL±1 μA
0.6 V
VT
RAIN(1)
Cparasitic
VAIN
0.6 V
VT
RADC(1)
CADC(1)
12-bit
converter
Sample and hold ADC
converter
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174/357 DS12110 Rev 7
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 42 or Figure 43,
depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 42. Power supply and reference decoupling (VREF+ not connected to VDDA)
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.
Figure 43. Power supply and reference decoupling (VREF+ connected to VDDA)
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.
MSv50648V1
1 μF // 100 nF
1 μF // 100 nF
STM32
VREF+(1)
VSSA/VREF+(1)
VDDA
MSv50649V1
1 μF // 100 nF
STM32
VREF+/VDDA(1)
VREF-/VSSA(1)
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322
6.3.21 DAC electrical characteristics
Table 89. DAC characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA Analog supply voltage - 1.8 3.3 3.6
V
VREF+ Positive reference voltage - 1.80 - VDDA
VREF-
Negative reference
voltage --V
SSA -
RLResistive Load DAC output
buffer ON
connected to
VSSA
5--
㏀
connected to
VDDA
25 - -
RO(2) Output Impedance DAC output buffer OFF 10.3 13 16
RBON
Output impedance sample
and hold mode, output
buffer ON
DAC output
buffer ON
VDD = 2.7 V - - 1.6
㏀
VDD = 2.0 V - - 2.6
RBOFF
Output impedance sample
and hold mode, output
buffer OFF
DAC output
buffer OFF
VDD = 2.7 V - - 17.8
㏀
VDD = 2.0 V - - 18.7
CL(2)
Capacitive Load
DAC output buffer OFF - - 50 pF
CSH(2) Sample and Hold mode - 0.1 1 µF
VDAC_OUT
Voltage on DAC_OUT
output
DAC output buffer ON 0.2 - VREF+
0.2 V
DAC output buffer OFF 0 - VREF+
tSETTLING
Settling time (full scale: for
a 12-bit code transition
between the lowest and
the highest input codes
when DAC_OUT reaches
the final value of ±0.5LSB,
±1LSB, ±2LSB, ±4LSB,
±8LSB)
Normal mode, DAC output buffer
OFF, ±1LSB CL=10 pF -1.7
(2) 2(2) µs
tWAKEUP(3)
Wakeup time from off
state (setting the Enx bit in
the DAC Control register)
until the ±1LSB final value
Normal mode, DAC output buffer
ON, CL ≤ 50 pF, RL = 5 ㏀-57.5µs
Voffset(2) Middle code offset for 1
trim code step
VREF+ = 3.6 V - 850 -
µV
VREF+ = 1.8 V - 425 -
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IDDA(DAC)
DAC quiescent
consumption from VDDA
DAC output
buffer ON
No load, middle
code (0x800) - 360 -
µA
No load, worst
code (0xF1C) - 490 -
DAC output
buffer OFF
No load,
middle/worst
code (0x800)
-20-
Sample and Hold mode,
CSH=100 nF -360*TON/
(TON+TOFF)-
IDDV(DAC) DAC consumption from
VREF+
DAC output
buffer ON
No load, middle
code (0x800) - 170 -
No load, worst
code (0xF1C) - 170 -
DAC output
buffer OFF
No load,
middle/worst
code (0x800)
- 160 -
Sample and Hold mode, Buffer
ON, CSH=100 nF (worst code) -170*TON/
(TON+TOFF)-
Sample and Hold mode, Buffer
OFF, CSH=100 nF (worst code) -160*TON/
(TON+TOFF)-
1. Guaranteed by characterization results.
2. Guaranteed by design.
3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
Table 89. DAC characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 90. DAC accuracy(1)
Symbol Parameter Conditions Min Typ Max Unit
DNL Differential non
linearity(2)
DAC output buffer ON - ±2 -
LSB
DAC output buffer OFF - ±2 -
INL Integral non linearity(3)
DAC output buffer ON, CL≤50 pF,
RL≥5 ㏀-±4-
LSB
DAC output buffer OFF,
CL ≤ 50 pF, no RL
-±4-
Offset Offset error at code
0x800 (3)
DAC output
buffer ON,
CL≤50 pF,
RL ≥5 ㏀
VREF+ = 3.6 V - - ±12
LSBVREF+ = 1.8 V - - ±25
DAC output buffer OFF,
CL ≤ 50 pF, no RL
--±8
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322
Offset1 Offset error at code
0x001(4)
DAC output buffer OFF,
CL ≤ 50 pF, no RL
--±5LSB
OffsetCal
Offset error at code
0x800 after factory
calibration
DAC output
buffer ON,
CL≤50 pF,
RL ≥5 ㏀
VREF+ = 3.6 V - - ±5
LSB
VREF+ = 1.8 V - - ±7
Gain Gain error(5)
DAC output buffer ON,CL≤50 pF,
RL ≥5 ㏀--±1
%
DAC output buffer OFF,
CL ≤ 50 pF, no RL
--±1
TUE Total unadjusted error DAC output buffer OFF,
CL ≤ 50 pF, no RL
--±12LSB
SNR Signal-to-noise ratio(6) DAC output buffer ON,CL≤50 pF,
RL ≥5 ㏀, 1 kHz, BW = 500 KHz - 67.8 - dB
SINAD Signal-to-noise and
distortion ratio(6)
DAC output buffer ON, CL≤50 pF,
RL ≥5 ㏀, 1 kHz - 67.5 - dB
ENOB Effective number of
bits
DAC output buffer ON,
CL≤50 pF, RL ≥5 ㏀, 1 kHz - 10.9 - bits
1. Guaranteed by characterization.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is -0.5dBFS with Fsampling=1 MHz.
Table 90. DAC accuracy(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
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Figure 44. 12-bit buffered /non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
6.3.22 Voltage reference buffer characteristics
RL
CL
Buffered/Non-buffered DAC
DAC_OUTx
Buffer(1)
12-bit
digital to
analog
converter
ai17157V3
Table 91. VREFBUF characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA Analog supply voltage
Normal mode
VSCALE = 000 2.8 3.3 3.6
V
VSCALE = 001 2.4 - 3.6
VSCALE = 010 2.1 - 3.6
VSCALE = 011 1.8 - 3.6
Degraded mode
VSCALE = 000 1.62 - 2.80
VSCALE = 001 1.62 - 2.40
VSCALE = 010 1.62 - 2.10
VSCALE = 011 1.62 - 1.80
VREFBUF
_OUT
Voltage Reference
Buffer Output
Normal mode
VSCALE = 000 - 2.5 -
VSCALE = 001 - 2.048 -
VSCALE = 010 - 1.8 -
VSCALE = 011 - 1.5 -
Degraded mode(2)
VSCALE = 000 VDDA
150 mV -V
DDA
VSCALE = 001 VDDA
150 mV -V
DDA
VSCALE = 010 VDDA
150 mV -V
DDA
VSCALE = 011 VDDA
150 mV -V
DDA
TRIM Trim step resolution - - - ±0.05 ±0.2 %
CLLoad capacitor - - 0.5 1 1.50 uF
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322
6.3.23 Temperature sensor characteristics
esr Equivalent Serial
Resistor of CL
----2
Ω
Iload Static load current - - - - 4 mA
Iline_reg Line regulation 2.8 V VDDA 3.6 V
Iload = 500 µA - 200 -
ppm/V
Iload = 4 mA - 100 -
Iload_reg Load regulation 500 µA ILOAD 4 mA Normal Mode - 50 - ppm/
mA
Tcoeff Temperature coefficient 40 °C < TJ < +125 °C - - -
Tcoeff
xVREFINT
+ 75
ppm/
°C
PSRR Power supply rejection
DC - - 60 -
dB
100KHz - - 40 -
tSTART Start-up time
CL=0.5 µF - - 300 -
µsCL=1 µF - - 500 -
CL=1.5 µF - - 650 -
IINRUSH
Control of maximum
DC current drive on
VREFBUF_OUT during
startup phase(3)
--8-mA
IDDA(VRE
FBUF)
VREFBUF
consumption from
VDDA
ILOAD = 0 µA - - 15 25
µAILOAD = 500 µA - - 16 30
ILOAD = 4 mA - - 32 50
1. Guaranteed by design.
2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDAdrop voltage).
3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.
Table 91. VREFBUF characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 92. Temperature sensor characteristics
Symbol Parameter Min Typ Max Unit
TL(1)
1. Guaranteed by design.
VSENSE linearity with temperature - - 3 °C
Avg_Slope(2) Average slope - 2 - mV/°C
V30(3) Voltage at 30°C ± 5 °C - 0.62 - V
tstart_run(1) Startup time in Run mode (buffer startup) - - 25.2
µs
tS_temp(1) ADC sampling time when reading the temperature 9 - -
Isens(1) Sensor consumption - 0.18 0.31
µA
Isensbuf(1) Sensor buffer consumption - 3.8 6.5
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6.3.24 Temperature and VBAT monitoring
2. Guaranteed by characterization.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1
byte.
Table 93. Temperature sensor calibration values
Symbol Parameter Memory address
TS_CAL1 Temperature sensor raw data acquired value at
30 °C, VDDA=3.3 V 0x1FF1 E820 -0x1FF1 E821
TS_CAL2 Temperature sensor raw data acquired value at
110 °C, VDDA=3.3 V 0x1FF1 E840 - 0x1FF1 E841
Table 94. VBAT monitoring characteristics
Symbol Parameter Min Typ Max Unit
R Resistor bridge for VBAT -26-K
QRatio on VBAT measurement - 4 - -
Er(1)
1. Guaranteed by design.
Error on Q –10 - +10 %
tS_vbat(1) ADC sampling time when reading VBAT input 9 - - µs
VBAThigh High supply monitoring - 3.55 -
V
VBATlow Low supply monitoring - 1.36 -
Table 95. VBAT charging characteristics
Symbol Parameter Condition Min Typ Max Unit
RBC Battery charging resistor
VBRS in PWR_CR3= 0 - 5 -
K
VBRS in PWR_CR3= 1 1.5 -
Table 96. Temperature monitoring characteristics
Symbol Parameter Min Typ Max Unit
TEMPhigh High temperature monitoring - 117 -
°C
TEMPlow Low temperature monitoring - –25 -
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6.3.25 Voltage booster for analog switch
Table 97. Voltage booster for analog switch characteristics(1)
1. Guaranteed by characterization results.
Symbol Parameter Condition Min Typ Max Unit
VDD Supply voltage - 1.62 2-6 3.6 V
tSU(BOOST) Booster startup time - - - 50 µs
IDD(BOOST) Booster consumption
1.62 V VDD 2.7 V - - 125
µA
2.7 V < VDD < 3.6 V - - 250
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6.3.26 Comparator characteristics
Table 98. COMP characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA Analog supply voltage - 1.62 3.3 3.6
VVIN
Comparator input voltage
range -0-V
DDA
VBG(2) Scaler input voltage - Refer to VREFINT
VSC Scaler offset voltage - - ±5 ±10 mV
IDDA(SCALER)
Scaler static consumption
from VDDA
BRG_EN=0 (bridge disable) - 0.2 0.3
µA
BRG_EN=1 (bridge enable) - 0.8 1
tSTART_SCALER Scaler startup time - - 140 250 µs
tSTART
Comparator startup time to
reach propagation delay
specification
High-speed mode - 2 5
µsMedium mode - 5 20
Ultra-low-power mode - 15 80
tD
Propagation delay for
200 mV step with 100 mV
overdrive
High-speed mode - 50 80 ns
Medium mode - 0.5 1.2
µs
Ultra-low-power mode - 2.5 7
Propagation delay for step
> 200 mV with 100 mV
overdrive only on positive
inputs
High-speed mode - 50 120 ns
Medium mode - 0.5 1.2
µs
Ultra-low-power mode - 2.5 7
Voffset Comparator offset error Full common mode range - ±5 ±20 mV
Vhys Comparator hysteresis
No hysteresis - 0 -
mV
Low hysteresis - 10 -
Medium hysteresis - 20 -
High hysteresis - 30 -
IDDA(COMP) Comparator consumption
from VDDA
Ultra-low-
power mode
Static - 400 600
nA
With 50 kHz
±100 mV overdrive
square signal
- 800 -
Medium mode
Static - 5 7
µA
With 50 kHz
±100 mV overdrive
square signal
-6-
High-speed
mode
Static - 70 100
With 50 kHz
±100 mV overdrive
square signal
-75-
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 28: Embedded reference voltage.
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6.3.27 Operational amplifier characteristics
Table 99. OPAMP characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA
Analog supply voltage
Range -23.33.6
V
CMIR Common Mode Input
Range -0-V
DDA
VIOFFSET Input offset voltage
25°C, no load on output - - ±1.5
mV
All voltages and
temperature, no load --±2.5
ΔVIOFFSET Input offset voltage drift - - ±3.0 - V/°C
TRIMOFFSETP
TRIMLPOFFSETP
Offset trim step at low
common input voltage
(0.1*VDDA)
--1.11.5
mV
TRIMOFFSETN
TRIMLPOFFSETN
Offset trim step at high
common input voltage
(0.9*VDDA)
--1.11.5
ILOAD Drive current - - - 500 A
ILOAD_PGA Drive current in PGA mode - - - 270
CLOAD Capacitive load - - - 50 pF
CMRR Common mode rejection
ratio --80-dB
PSRR Power supply rejection
ratio
CLOAD 50pf /
RLOAD 4 k(2) at 1 kHz,
Vcom=VDDA/2
50 66 - dB
GBW Gain bandwidth for high
supply range - 4 7.3 12.3 MHz
SR Slew rate (from 10% and
90% of output voltage)
Normal mode - 3 -
V/µs
High-speed mode - 30 -
AO Open loop gain - 59 90 129 dB
φm Phase margin - - 55 - °
GM Gain margin - - 12 - dB
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VOHSAT High saturation voltage Iload=max or RLOAD=min(2),
Input at VDDA
VDDA
100 mV - -
mV
VOLSAT Low saturation voltage Iload=max or RLOAD=min(2),
Input at 0 V --100
tWAKEUP
Wake up time from OFF
state
Normal
mode
CLOAD 50pf,
RLOAD 4 k(2),
follower
configuration
-0.83.2
µs
High
speed
CLOAD 50pf,
RLOAD 4 k(2),
follower
configuration
-0.92.8
PGA gain
Non inverting gain value
--2--
--4--
--8--
--16--
Inverting gain value
--1--
--3--
--7--
--15 - -
Rnetwork
R2/R1 internal resistance
values in non-inverting
PGA mode(3)
PGA Gain=2 - 10/10 -
k/
k
PGA Gain=4 - 30/10 -
PGA Gain=8 - 70/10 -
PGA Gain=16 - 150/10 -
R2/R1 internal resistance
values in inverting PGA
mode(3)
PGA Gain=-1 - 10/10 -
PGA Gain=-3 - 30/10 -
PGA Gain=-7 - 70/10 -
PGA Gain=-15 - 150/10 -
Delta R Resistance variation (R1 or
R2) -15 - 15 %
PGA BW PGA bandwidth for
different non inverting gain
Gain=2 - GBW/2 -
MHz
Gain=4 - GBW/4 -
Gain=8 - GBW/8 -
Gain=16 - GBW/16 -
Table 99. OPAMP characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
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en Voltage noise density
at
1 KHz output loaded
with 4 k
-140-
nV/
Hz
at
10 KHz -55-
IDDA(OPAMP)
OPAMP consumption from
VDDA
Normal
mode no Load,
quiescent mode,
follower
- 570 1000
µA
High-
speed
mode
- 610 1200
1. Guaranteed by design, unless otherwise specified.
2. RLOAD is the resistive load connected to VSSA or to VDDA.
3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
Table 99. OPAMP characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
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6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 100 for DFSDM are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
summarized in Table 24: General operating conditions, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for
DFSDMx).
Table 100. DFSDM measured timing 1.62-3.6 V(1)
Symbol Parameter Conditions Min Typ Max Unit
fDFSDMCLK DFSDM clock 1.62 V < VDD < 3.6 V - - 133
MHz
fCKIN
(1/TCKIN)
Input clock
frequency
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 V < VDD < 3.6 V
--
20
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
2.7 < VDD < 3.6 V
--
20
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]≠0),
1.62 < VDD < 3.6 V
--
20
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]≠0),
2.7 < VDD < 3.6 V
--
20
(fDFSDMCLK/4)
fCKOUT
Output clock
frequency 1.62 < VDD < 3.6 V - - 20
DuCyCKOUT
Output clock
frequency duty
cycle
1.62 < VDD < 3.6 V 45 50 55 %
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322
twh(CKIN)
twl(CKIN)
Input clock high
and low time
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
TCKIN/2 - 0.5 TCKIN/2 -
ns
tsu
Data input setup
time
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
4--
th
Data input hold
time
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
0.5 - -
TManchester
Manchester data
period (recovered
clock period)
Manchester mode
(SITP[1:0]=2,3),
Internal clock mode
(SPICKSEL[1:0]≠0),
1.62 < VDD < 3.6 V
(CKOUTDIV+1)
* TDFSDMCLK
-(2*CKOUTDIV)
* TDFSDMCLK
1. Guaranteed by characterization results.
Table 100. DFSDM measured timing 1.62-3.6 V(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
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Figure 45. Channel transceiver timing diagrams
MS30766V2
SITP = 0
DFSDM_CKOUT
DFSDM_DATINy
SITP = 1
tsu th
tsu th
tftr
twl twh
SPI timing : SPICKSEL = 1, 2, 3
recovered clock
SITP = 2
DFSDM_DATINy
SITP = 3
Manchester timing
recovered data
11000
SITP = 00
DFSDM_CKINyDFSDM_DATINy
SITP = 01
tsu th
tsu th
tftr
twl twh
SPI timing : SPICKSEL = 0
SPICKSEL=2
SPICKSEL=1
(SPICKSEL=0)
SPICKSEL=3
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6.3.29 Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 101 for DCMI are derived
from tests performed under the ambient temperature, frcc_c_ck frequency and VDD
supply voltage summarized in Table 24: General operating conditions, with the following
configuration:
•DCMI_PIXCLK polarity: falling
•DCMI_VSYNC and DCMI_HSYNC polarity: high
•Data formats: 14 bits
•Capacitive load C=30 pF
•Measurement points are done at CMOS levels: 0.5VDD
Figure 46. DCMI timing diagram
Table 101. DCMI characteristics(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
- Frequency ratio DCMI_PIXCLK/frcc_c_ck -0.4 -
DCMI_PIXCLK Pixel clock input - 80 MHz
DPixel Pixel clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 1 -
ns
th(DATA) Data input hold time 1 -
tsu(HSYNC)
tsu(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input setup time 1.5 -
th(HSYNC)
th(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input hold time 1 -
MS32414V2
DCMI_PIXCLK
tsu(VSYNC)
tsu(HSYNC)
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
1/DCMI_PIXCLK
th(HSYNC)
th(HSYNC)
tsu(DATA) th(DATA)
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6.3.30 LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 102 for LCD-TFT are derived
from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply
voltage summarized in Table 24: General operating conditions, with the following
configuration:
•LCD_CLK polarity: high
•LCD_DE polarity: low
•LCD_VSYNC and LCD_HSYNC polarity: high
•Pixel formats: 24 bits
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load C=30 pF
•Measurement points are done at CMOS levels: 0.5VDD
•I/O compensation cell enabled
Table 102. LTDC characteristics (1)
Symbol Parameter Conditions Min Max Unit
fCLK LTDC clock output frequency
2.7 V < VDD < 3.6 V,
20 pF -150
MHz
2.7 V < VDD < 3.6 V - 133
1.62 V < VDD < 3.6 V - 90
DCLK LTDC clock output duty cycle - 45 55 %
tw(CLKH),
tw(CLKL)
Clock High time, low time tw(CLK)/20.5 tw(CLK)/2+0.5
ns
tv(DATA) Data output valid time - 0.5
th(DATA) Data output hold time 0 -
tv(HSYNC),
tv(VSYNC),
tv(DE)
HSYNC/VSYNC/DE output valid
time -0.5
th(HSYNC),
th(VSYNC),
th(DE)
HSYNC/VSYNC/DE output hold
time 0.5 -
1. Guaranteed by characterization results.
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Figure 47. LCD-TFT horizontal timing diagram
Figure 48. LCD-TFT vertical timing diagram
MS32749V1
LCD_CLK
tv(HSYNC)
LCD_HSYNC
LCD_DE
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
tCLK
LCD_VSYNC
tv(HSYNC)
tv(DE) th(DE)
Pixel
1
Pixel
2
tv(DATA)
th(DATA)
Pixel
N
HSYNC
width
Horizontal
back porch
Active width Horizontal
back porch
One line
MS32750V1
LCD_CLK
tv(VSYNC)
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
tCLK
LCD_VSYNC
tv(VSYNC)
M lines data
VSYNC
width
Vertical
back porch
Active width Vertical
back porch
One frame
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6.3.31 Timer characteristics
The parameters given in Table 103 are guaranteed by design.
Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 103. TIMx characteristics(1)(2)
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Guaranteed by design.
Symbol Parameter Conditions(3)
3. The maximum timer frequency on APB1 or APB2 is up to 200 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
Frcc_pclkx_d2.
Min Max Unit
tres(TIM) Timer resolution time
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK =
200 MHz
1-
tTIMxCLK
AHB/APBx
prescaler>4, fTIMxCLK =
100 MHz
1-
tTIMxCLK
fEXT Timer external clock
frequency on CH1 to CH4 fTIMxCLK = 200 MHz
0fTIMxCLK/2 MHz
ResTIM Timer resolution - 16/32 bit
tMAX_COUNT Maximum possible count
with 32-bit counter --
65536 ×
65536 tTIMxCLK
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6.3.32 Communications interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
•Standard-mode (Sm): with a bit rate up to 100 kbit/s
•Fast-mode (Fm): with a bit rate up to 400 kbit/s.
•Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0433 reference manual) and when the i2c_ker_ck frequency is
greater than the minimum shown in the table below:
The SDA and SCL I/O requirements are met with the following restrictions:
•The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDD is disabled, but still present.
•The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load Cload supported in Fm+, which is given by these formulas:
tr(SDA/SCL)=0.8473xRpxCload
Rp(min)= (VDD-VOL(max))/IOL(max)
Where Rp is the I2C lines pull-up. Refer to Section 6.3.15: I/O port characteristics for
the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 105 for the analog filter
characteristics:
Table 104. Minimum i2c_ker_ck frequency in all I2C modes
Symbol Parameter Condition Min Unit
f(I2CCLK) I2CCLK
frequency
Standard-mode 2
MHz
Fast-mode
Analog filter ON
DNF=0 8
Analog filter OFF
DNF=1 9
Fast-mode Plus
Analog filter ON
DNF=0 17
Analog filter OFF
DNF=1 16
Table 105. I2C analog filter characteristics(1)
1. Guaranteed by design.
Symbol Parameter Min Max Unit
tAF
Maximum pulse width of spikes that
are suppressed by the analog filter 50(2)
2. Spikes with widths below tAF(min) are filtered.
260(3)
3. Spikes with widths above tAF(max) are not filtered.
ns
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SPI interface characteristics
Unless otherwise specified, the parameters given in Table 106 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 24: General operating conditions, with the
following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5VDD
•I/O compensation cell enabled
•HSLV activated when VDD 2.7 V
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 106. SPI dynamic characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
1.62 VVDD3.6 V
--
90
MHz
Master mode
2.7 VVDD3.6 V
SPI1,2,3
133
Master mode
2.7 VVDD3.6 V
SPI4,5,6
100
Slave receiver mode
1.62 VVDD3.6 V
SPI1,2,3
150
Slave receiver mode
1.62 VVDD3.6 V
SPI4,5,6
100
Slave mode transmitter/full
duplex
2.7 VVDD3.6 V
31
Slave mode transmitter/full
duplex
1.62 VVDD3.6 V
25
tsu(NSS) NSS setup time
Slave mode
2--
ns
th(NSS) NSS hold time 1 - -
tw(SCKH),
tw(SCKL)
SCK high and low time Master mode TPLCK - 2 TPLCK TPLCK + 2
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Figure 49. SPI timing diagram - slave mode and CPHA = 0
tsu(MI) Data input setup time
Master mode 1 - -
ns
tsu(SI) Slave mode 2 - -
th(MI) Data input hold time
Master mode 2 - -
th(SI) Slave mode 1 - -
ta(SO) Data output access time Slave mode 9 13 27
tdis(SO) Data output disable time Slave mode 0 1 5
tv(SO) Data output valid time
Slave mode, 2.7 VVDD3.6 V - 11.5 16
Slave mode 1.62 VVDD3.6 V - 13 20
tv(MO) Master mode - 1 3
th(SO) Data output hold time
Slave mode, 1.62 VVDD3.6 V 9 - -
th(MO) Master mode 0 - -
1. Guaranteed by characterization results.
Table 106. SPI dynamic characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
MSv41658V1
NSS input
CPHA=0
CPOL=0
SCK input
CPHA=0
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tc(SCK)
tr(SCK)
th(NSS)
tdis(SO)
tsu(NSS)
ta(SO) tv(SO)
Next bits IN
Last bit OUT
First bit IN
First bit OUT Next bits OUT
th(SO) tf(SCK)
Last bit IN
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Figure 50. SPI timing diagram - slave mode and CPHA = 1(1)
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Figure 51. SPI timing diagram - master mode(1)
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
MSv41659V1
NSS input
CPHA=1
CPOL=0
SCK input
CPHA=1
CPOL=1
MISO output
MOSI input
tsu(SI) th(SI)
tw(SCKL)
tw(SCKH)
tsu(NSS)
tc(SCK)
ta(SO) tv(SO)
First bit OUT Next bits OUT
Next bits IN
Last bit OUT
th(SO) tr(SCK)
tf(SCK) th(NSS)
tdis(SO)
First bit IN Last bit IN
ai14136c
SCK Output
CPHA= 0
MOSI
OUTPUT
MISO
INP UT
CPHA= 0
LSB OUT
LSB IN
CPOL=0
CPOL=1
B IT1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
High
SCK Output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
MSB IN BIT6 IN
MSB OUT
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I2S interface characteristics
Unless otherwise specified, the parameters given in Table 107 for the I2S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 24: General operating conditions, with the
following configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5VDD
•I/O compensation cell enabled
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
Table 107. I2S dynamic characteristics(1)
Symbol Parameter Conditions Min Max Unit
fMCK I2S Main clock output - 256x8K 256FSMHz
fCK I2S clock frequency
Master data - 64FSMHz
Slave data - 64FS
tv(WS) WS valid time Master mode - 3.5
ns
th(WS) WS hold time Master mode 0 -
tsu(WS) WS setup time Slave mode 1 -
th(WS) WS hold time Slave mode 1 -
tsu(SD_MR) Data input setup time
Master receiver 1 -
tsu(SD_SR) Slave receiver 1 -
th(SD_MR) Data input hold time
Master receiver 4 -
th(SD_SR) Slave receiver 2 -
tv(SD_ST) Data output valid time
Slave transmitter (after enable edge) - 20
tv(SD_MT) Master transmitter (after enable edge) - 3
th(SD_ST) Data output hold time
Slave transmitter (after enable edge) 9 -
th(SD_MT) Master transmitter (after enable edge) 0 -
1. Guaranteed by characterization results.
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Figure 52. I2S slave timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 53. I2S master timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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SAI characteristics
Unless otherwise specified, the parameters given in Table 108 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 24: General operating conditions, with the following
configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load C=30 pF
•Measurement points are performed at CMOS levels: 0.5VDD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
Table 108. SAI characteristics(1)
Symbol Parameter Conditions Min Max Unit
fMCK SAI Main clock output - 256 x 8K 256xFs MHz
FCK SAI clock frequency(2)
Master data: 32 bits - 128xFs(3)
MHz
Slave data: 32 bits - 128xFs
tv(FS) FS valid time
Master mode
2.7VDD3.6V -15
ns
Master mode
1.71VDD3.6V -20
tsu(FS) FS setup time Slave mode 7 -
th(FS) FS hold time
Master mode 1 -
Slave mode 1 -
tsu(SD_A_MR) Data input setup time
Master receiver 0.5 -
tsu(SD_B_SR) Slave receiver 1 -
th(SD_A_MR) Data input hold time
Master receiver 3.5 -
th(SD_B_SR) Slave receiver 2 -
tv(SD_B_ST) Data output valid time
Slave transmitter (after enable edge)
2.7VDD3.6V -17
ns
Slave transmitter (after enable edge)
1.62VDD3.6V -20
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 7 -
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge)
2.7VDD3.6V -17
Master transmitter (after enable edge)
1.62VDD3.6V -20
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 7.55 -
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With FS=192 kHz.
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Figure 54. SAI master timing waveforms
Figure 55. SAI slave timing waveforms
MDIO characteristics
The MDIO controller is mapped on APB2 domain. The frequency of the APB bus should at
least 1.5 times the MDC frequency: FPCLK2 1.5 * FMDC.
Table 109. MDIO Slave timing parameters
Symbol Parameter Min Typ Max Unit
FsDC Management data clock - - 40 MHz
td(MDIO) Management data input/output output valid time 7820
nstsu(MDIO) Management data input/output setup time 4--
th(MDIO) Management data input/output hold time 1--
MS32771V1
SAI_SCK_X
SAI_FS_X
(output)
1/fSCK
SAI_SD_X
(transmit)
tv(FS)
Slot n
SAI_SD_X
(receive)
th(FS)
Slot n+2
tv(SD_MT) th(SD_MT)
Slot n
tsu(SD_MR) th(SD_MR)
MS32772V1
SAI_SCK_X
SAI_FS_X
(input)
SAI_SD_X
(transmit)
tsu(FS)
Slot n
SAI_SD_X
(receive)
tw(CKH_X) th(FS)
Slot n+2
tv(SD_ST) th(SD_ST)
Slot n
tsu(SD_SR)
tw(CKL_X)
th(SD_SR)
1/fSCK
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Figure 56. MDIO Slave timing diagram
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 110 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD
supply voltage conditions summarized in Table 24: General operating conditions, with the
following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5VDD
•I/O compensation cell enabled
•HSLV activated when VDD 2.7 V
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
MSv40460V1
tsu(MDIO)
tMDC)
th(MDIO)
td(MDIO)
Table 110. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1)(2)
Symbol Parameter Conditions Min Typ Max Unit
fPP Clock frequency in data transfer mode - 0 - 125 MHz
tW(CKL) Clock low time
fPP =50 MHz
9.5 10.5 -
ns
tW(CKH) Clock high time 8.5 9.5 -
CMD, D inputs (referenced to CK) in MMC and SD HS/SDR/DDR mode
tISU Input setup time HS
fPP ≥50 MHz
2--
nstIH Input hold time HS 1.5 - -
tIDW(3) Input valid window (variable window) 3 - -
CMD, D outputs (referenced to CK) in MMC and SD HS/SDR/DDR mode
tOV Output valid time HS
fPP ≥50 MHz
-3.55
ns
tOH Output hold time HS 2 - -
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CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD
fPP =25 MHz
2--
ns
tIHD Input hold time SD 1.5 - -
CMD, D outputs (referenced to CK) in SD default mode
tOVD Output valid default time SD fPP =25 MHz
-12
ns
tOHD Output hold default time SD 0--
1. Guaranteed by characterization results.
2. Above 100 MHz, CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
Table 110. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1)(2)
Symbol Parameter Conditions Min Typ Max Unit
Table 111. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V(1)(2)
Symbol Parameter Conditions Min Typ Max Unit
fPP Clock frequency in data transfer mode - 0 - 120 MHz
tW(CKL) Clock low time
fPP =50 MHz
9.5 10.5 -
ns
tW(CKH) Clock high time 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC mode
tISU Input setup time HS
fPP ≥50 MHz
1.5 - -
nstIH Input hold time HS 2 - -
tIDW(3) Input valid window (variable window) 3.5 - -
CMD, D outputs (referenced to CK) in eMMC mode
tOV Output valid time HS
fPP ≥50 MHz
-57
ns
tOH Output hold time HS 3 - -
1. Guaranteed by characterization results.
2. CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
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Figure 57. SDIO high-speed mode
Figure 58. SD default mode
Figure 59. DDR mode
CAN (controller area network) interface
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (FDCANx_TX and FDCANx_RX).
ai14888
CK
D, CMD
(output)
tOVD tOHD
MSv36879V1
Data output D0 D2 D4
Clock
Data input D0 D2 D4
t(CK) tw(CKH) tw(CKL)
tr(CK) tf(CK)
tsf(IN) thf(IN)
tvf(OUT) thr(OUT)
D1 D3 D5
D1 D3 D5
tvr(OUT) thf(OUT)
tsr(IN) thr(IN)
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USB OTG_FS characteristics
The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF
certified (for Full-speed device operation).
USB OTG_HS characteristics
Unless otherwise specified, the parameters given in Table 113 for ULPI are derived from
tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage
conditions summarized in Table 24: General operating conditions, with the following
configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load C = 20 pF
•Measurement points are done at CMOS levels: 0.5VDD.
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
Table 112. USB OTG_FS electrical characteristics
Symbol Parameter Condition Min Typ Max Unit
VDD33USB
USB transceiver operating
voltage -3.0
(1)
1. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are
degraded in the 2.7 to 3.0 V voltage range.
-3.6V
RPUI Embedded USB_DP pull-up
value during idle - 900 1250 1600
RPUR
Embedded USB_DP pull-up
value during reception - 1400 2300 3200
ZDRV Output driver impedance(2)
2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
Driver high
and low 28 36 44
Table 113. Dynamic characteristics: USB ULPI(1)
Symbol Parameter Conditions Min Typ Max Unit
tSC Control in (ULPI_DIR, ULPI_NXT) setup time - 0.5 - -
ns
tHC Control in (ULPI_DIR, ULPI_NXT) hold time - 6.5 - -
tSD Data in setup time - 2.5 - -
tHD Data in hold time - 0 - -
tDC/tDD Data/control output delay
2.7 V < VDD < 3.6 V,
CL = 20 pF -6.58.5
--
6.5 13
1.7 V < VDD < 3.6 V,
CL = 15 pF -
1. Guaranteed by characterization results.
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Figure 60. ULPI timing diagram
Ethernet characteristics
Unless otherwise specified, the parameters given in Table 114, Table 115 and Table 116 for
SMI, RMII and MII are derived from tests performed under the ambient temperature,
frcc_c_ck frequency summarized in Table 24: General operating conditions, with the following
configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load C = 20 pF
•Measurement points are done at CMOS levels: 0.5VDD.
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
Table 114 gives the list of Ethernet MAC signals for the SMI and Figure 61 shows the
corresponding timing diagram.
Table 114. Dynamics characteristics: Ethernet MAC signals for SMI(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Typ Max Unit
tMDC MDC cycle time(2.5 MHz) 400 400 403
ns
Td(MDIO) Write data valid time 1 1.5 3
tsu(MDIO) Read data setup time 8 - -
th(MDIO) Read data hold time 0 - -
Clock
Control In
(ULPI_DIR,
ULPI_NXT)
data In
(8-bit)
Control out
(ULPI_STP)
data out
(8-bit)
tDD
tDC
tHD
tSD
tHC
tSC
ai17361c
tDC
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Figure 61. Ethernet SMI timing diagram
Table 115 gives the list of Ethernet MAC signals for the RMII and Figure 62 shows the
corresponding timing diagram.
Figure 62. Ethernet RMII timing diagram
Table 116 gives the list of Ethernet MAC signals for MII and Figure 63 shows the
corresponding timing diagram.
Table 115. Dynamics characteristics: Ethernet MAC signals for RMII(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Typ Max Unit
tsu(RXD) Receive data setup time 2 - -
ns
tih(RXD) Receive data hold time 3 - -
tsu(CRS) Carrier sense setup time 2.5 - -
tih(CRS) Carrier sense hold time 2 - -
td(TXEN) Transmit enable valid delay time 4 4.5 7
td(TXD) Transmit data valid delay time 7 7.5 11.5
MS31384V1
ETH_MDC
ETH_MDIO(O)
ETH_MDIO(I)
tMDC
td(MDIO)
tsu(MDIO) th(MDIO)
ai15667b
RMII_REF_CLK
RMII_TX_EN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRS_DV
td(TXEN)
td(TXD)
tsu(RXD)
tsu(CRS)
tih(RXD)
tih(CRS)
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Figure 63. Ethernet MII timing diagram
6.3.33 JTAG/SWD interface characteristics
Unless otherwise specified, the parameters given in Table 117 and Table 118 for JTAG/SWD
are derived from tests performed under the ambient temperature, frcc_c_ck frequency and
VDD supply voltage summarized in Table 24: General operating conditions, with the
following configuration:
•Output speed is set to OSPEEDRy[1:0] = 0x10
•Capacitive load C=30 pF
•Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
Table 116. Dynamics characteristics: Ethernet MAC signals for MII(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Typ Max Unit
tsu(RXD) Receive data setup time 2 - -
ns
tih(RXD) Receive data hold time 3 - -
tsu(DV) Data valid setup time 1.5 - -
tih(DV) Data valid hold time 1 - -
tsu(ER) Error setup time 1.5 - -
tih(ER) Error hold time 0.5 - -
td(TXEN) Transmit enable valid delay time 4.5 6.5 11
td(TXD) Transmit data valid delay time 7 7.5 15
ai15668b
MII_RX_CLK
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
td(TXEN)
td(TXD)
tsu(RXD)
tsu(ER)
tsu(DV)
tih(RXD)
tih(ER)
tih(DV)
MII_TX_CLK
MII_TX_EN
MII_TXD[3:0]
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Table 117. Dynamics JTAG characteristics(1)
1. Guaranteed by characterization results.
Symbol Parameter Conditions Min Typ Max Unit
Fpp
TCK clock
frequency
2.7 V <VDD< 3.6 V - - 37
MHz
1/tc(TCK) 1.62 V <VDD< 3.6 V - - 27.5
tisu(TMS)
TMS input
setup time -2--
ns
tih(TMS)
TMS input
hold time -1--
tisu(TDI)
TDI input
setup time -1.5--
tih(TDI)
TDI input
hold time -1--
tov (TDO)
TDO output
valid time
2.7 V <VDD< 3.6 V - 8 13.5
1.62 V <VDD< 3.6 V - 8 18
toh(TDO)
TDO output
hold time -7--
Table 118. Dynamics SWD characteristics(1)
1. Guaranteed by characterization results.
Symbol Parameter Conditions Min Typ Max Unit
Fpp
SWCLK
clock
frequency
2.7 V <VDD< 3.6 V - - 71
MHz
1/tc(SWCLK) 1.62 V <VDD< 3.6 V - - 55.5
tisu(SWDIO)
SWDIO input
setup time -2.5--
ns
tih(SWDIO)
SWDIO input
hold time -1--
tov (SWDIO)
SWDIO
output valid
time
2.7 V <VDD< 3.6 V - 8.5 14
1.62 V <VDD< 3.6 V - 8.5 18
toh(SWDIO)
SWDIO
output hold
time
-8--
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STM32H742xI/G STM32H743xI/G Electrical characteristics (rev Y)
322
Figure 64. JTAG timing diagram
Figure 65. SWD timing diagram
MSv40458V1
TDI/TMS
TCK
TDO
t
c(TCK)
t
w(TCKL)
t
w(TCKH)
t
h(TMS/TDI)
t
su(TMS/TDI)
t
ov(TDO)
t
oh(TDO)
MSv40459V1
SWDIO
SWCLK
SWDIO
t
c(SWCLK)
t
wSWCLKL)
t
w(SWCLKH)
t
h(SWDIO)
t
su(SWDIO)
t
ov(SWDIO)
t
oh(SWDIO)
(receive)
(transmit)
Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G
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7 Electrical characteristics (rev V)
7.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
7.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3).
7.1.2 Typical values
Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2).
7.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
7.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 66.
7.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 67.
Figure 66. Pin loading conditions Figure 67. Pin input voltage
MS19011V2
C = 50 pF
MCU pin
MS19010V2
MCU pin
VIN
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STM32H742xI/G STM32H743xI/G Electrical characteristics (rev V)
322
7.1.6 Power supply scheme
Figure 68. Power supply scheme
1. N corresponds to the number of VDD pins available on the package.
2. A tolerance of +/- 20% is acceptable on decoupling capacitors.
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
MSv46116V3
BKUP
IOs
VDD domain
Analog domain
Core domain (VCORE)
Backup domain
D3 domain
(System
logic,
EXTI,
Peripherals,
RAM)
D1 domain
(CPU, peripherals,
RAM)
Level shifter
OPAMP,
Comparator
Voltage
regulator
ADC, DAC
Flash
D2 domain
(peripherals,
RAM)
Power
switch
Power switch
VCAP
VSS
VDDLDO
VBAT
VDDA
VREF+
VREF-
VSSA
Backup
regulator
VDD
Backup
RAM
Power switch
HSI, CSI,
HSI48,
HSE, PLLs
IOs
Power
switch
USB
regulator
VDD50USB
VDD33USB
VSS
VSS
VSS
REF_BUF
VSS
IO
logic
VREF+
USB
IOs
VSS
VSW
LSI, LSE,
RTC, Wakeup
logic, backup
registers,
Reset
IO
logic
VBKP
VBAT
charging
VREF-
VDDA
VBAT
1.2 to 3.6V
2 x 2.2μF
N(1) x 100 nF
+ 1 x 4.7 μF
100 nF
100 nF + 1 x 1 μF
4..7μF
100 nF
VDD
VDDLDO
100 nF + 1 x 1 μF
VREF
VDD33USB VDD50USB
Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G
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device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
7.1.7 Current consumption measurement
Figure 69. Current consumption measurement scheme
7.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 119: Voltage characteristics,
Table 120: Current characteristics, and Table 121: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
ai14126
VBAT
VDD
VDDA
IDD_VBAT
IDD
Table 119. Voltage characteristics (1)
1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
Symbols Ratings Min Max Unit
VDDX - VSS
External main supply voltage (including VDD,
VDDLDO, VDDA, VDD33USB, VBAT)0.3 4.0 V
VIN(2)
2. VIN maximum must always be respected. Refer to Table 156: I/O current injection susceptibility for the
maximum allowed injected current values.
Input voltage on FT_xxx pins VSS0.3
Min(VDD, VDDA,
VDD33USB, VBAT)
+4.0(3)(4)
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
V
Input voltage on TT_xx pins VSS-0.3 4.0 V
Input voltage on BOOT0 pin VSS 9.0 V
Input voltage on any other pins VSS-0.3 4.0 V
|VDDX|Variations between different VDDX power pins
of the same domain -50mV
|VSSx-VSS| Variations between all the different ground pins - 50 mV
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322
Table 120. Current characteristics
Symbols Ratings Max Unit
ΣIVDD Total current into sum of all VDD power lines (source)(1)
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
620
mA
ΣIVSS Total current out of sum of all VSS ground lines (sink)(1) 620
IVDD Maximum current into each VDD power pin (source)(1) 100
IVSS Maximum current out of each VSS ground pin (sink)(1) 100
IIO Output current sunk by any I/O and control pin 20
ΣI(PIN)
Total output current sunk by sum of all I/Os and control pins(2)
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
140
Total output current sourced by sum of all I/Os and control pins(2) 140
IINJ(PIN)(3)(4)
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 119: Voltage characteristics for the maximum allowed input voltage
values.
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
PA5 5/+0
Injected current on PA4, PA5 0/0
ΣIINJ(PIN) Total injected current (sum of all I/Os and control pins)(5)
5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
±25
Table 121. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range −65 to +150
°C
TJMaximum junction temperature 125
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7.3 Operating conditions
7.3.1 General operating conditions
Table 122. General operating conditions
Symbol Parameter Operating
conditions Min Typ Max Unit
VDD Standard operating voltage - 1.62(1) - 3.6 V
VDDLDO
Supply voltage for the internal
regulator VDDLDO VDD 1.62(1) -3.6
VDD33USB
Standard operating voltage, USB
domain
USB used 3.0 - 3.6
V
USB not used 0 - 3.6
VDDA Analog operating voltage
ADC or COMP used 1.62 -
3.6
DAC used 1.8 -
OPAMP used 2.0 -
VREFBUF used 1.8 -
ADC, DAC, OPAMP,
COMP, VREFBUF not
used
0-
VIN I/O Input voltage
TT_xx I/O 0.3 - VDD+0.3
BOOT0 0 - 9
All I/O except BOOT0
and TT_xx 0.3 -
Min(VDD, VDDA,
VDD33USB)
+3.6V <
5.5V(2)(3)
VCORE
Internal regulator ON (LDO)
VOS3 (max frequency
200 MHz) 0.95 1.0 1.26
V
VOS2 (max frequency
300 MHz) 1.05 1.10 1.26
VOS1 (max frequency
400 MHz) 1.15 1.20 1.26
VOS0(4) (max
frequency 480 MHz(5)) 1.26 1.35 1.40
Regulator OFF: external VCORE
voltage must be supplied from external
regulator on two VCAP pins
VOS3 (max frequency
200 MHz) 0.98 1.03 1.26
VOS2 (max frequency
300 MHz) 1.08 1.13 1.26
VOS1 (max frequency
400 MHz) 1.17 1.23 1.26
VOS0 (max frequency
480 MHz(5)) 1.37 1.38 1.40
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322
fCPU Arm® Cortex®-M7 clock frequency
VOS3 - - 200
MHz
VOS2 - - 300
VOS1 - - 400
VOS0 - - 480(5)
fHCLK AHB clock frequency
VOS3 - - 100
VOS2 - - 150
VOS1 - - 200
VOS0 - - 240(5)
fPCLK APB clock frequency
VOS3 - - 50(6)
VOS2 - - 75
VOS1 - - 100
VOS0 - - 120(5)
PD
Power dissipation at
TA = 85 °C for suffix 6(7)
TFBGA240+25 - - 1093
mW
LQFP208 - - 943
LQFP176 - - 930
UFBGA176+25 - - 1070
UFBGA169 - - 1061
LQFP144 - - 915
LQFP100 - - 889
TFBGA100 - - 1018
TA
Ambient temperature for the suffix 6
version
Maximum power dissipation –40 85
°C
Low-power dissipation(8) –40 105
Ambient temperature for the suffix 3
version
Maximum power dissipation –40 125
Low-power dissipation(5) –40 130
TJ Junction temperature range Suffix 6 version –40 125 °C
1. When RESET is released functionality is guaranteed down to VBOR0 min
2. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
3. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must
be disabled.
4. VOS0 is available only when the LDO regulator is ON.
5. TJmax = 105 °C.
6. Maximum APB clock frequency when at least one peripheral is enabled.
7. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 8.9: Thermal characteristics).
8. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 8.9:
Thermal characteristics).
Table 122. General operating conditions (continued)
Symbol Parameter Operating
conditions Min Typ Max Unit
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7.3.2 VCAP external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP pin. CEXT is specified in Table 124. Two external capacitors can be connected to
VCAP pins.
Figure 70. External capacitor CEXT
1. Legend: ESR is the equivalent series resistance.
Table 123. Supply voltage and maximum frequency configuration
Power scale VCORE source Max TJ (°C) Max frequency (MHz) Min VDD (V)
VOS0 LDO 105 480 1.7
VOS1 LDO 125 400 1.62
VOS2 LDO 125 300 1.62
VOS3 LDO 125 200 1.62
SVOS4 LDO 105 N/A 1.62
SVOS5 LDO 105 N/A 1.62
Table 124. VCAP operating conditions(1)
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
Symbol Parameter Conditions
CEXT Capacitance of external capacitor 2.2 µF(2)
2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.
ESR ESR of external capacitor < 100 mΩ
MS19044V2
ESR
R
Leak
C
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322
7.3.3 Operating conditions at power-up / power-down
Subject to general operating conditions for TA.
Table 125. Operating conditions at power-up / power-down (regulator ON)
Symbol Parameter Min Max Unit
tVDD
VDD rise time rate 0 ∞
µs/V
VDD fall time rate 10 ∞
tVDDA
VDDA rise time rate 0 ∞
VDDA fall time rate 10 ∞
tVDDUSB
VDDUSB rise time rate 0 ∞
VDDUSB fall time rate 10 ∞
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7.3.4 Embedded reset and power control block characteristics
The parameters given in Table 126 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 122: General
operating conditions.
Table 126. Reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
tRSTTEMPO(1) Reset temporization
after BOR0 released - - 377 - µs
VBOR0 Brown-out reset threshold 0
Rising edge(1) 1.62 1.67 1.71
V
Falling edge 1.58 1.62 1.68
VBOR1 Brown-out reset threshold 1
Rising edge 2.04 2.10 2.15
Falling edge 1.95 2.00 2.06
VBOR2 Brown-out reset threshold 2
Rising edge 2.34 2.41 2.47
Falling edge 2.25 2.31 2.37
VBOR3 Brown-out reset threshold 3
Rising edge 2.63 2.70 2.78
Falling edge 2.54 2.61 2.68
VPVD0
Programmable Voltage
Detector threshold 0
Rising edge 1.90 1.96 2.01
Falling edge 1.81 1.86 1.91
VPVD1
Programmable Voltage
Detector threshold 1
Rising edge 2.05 2.10 2.16
Falling edge 1.96 2.01 2.06
VPVD2
Programmable Voltage
Detector threshold 2
Rising edge 2.19 2.26 2.32
Falling edge 2.10 2.15 2.21
VPVD3
Programmable Voltage
Detector threshold 3
Rising edge 2.35 2.41 2.47
Falling edge 2.25 2.31 2.37
VPVD4
Programmable Voltage
Detector threshold 4
Rising edge 2.49 2.56 2.62
Falling edge 2.39 2.45 2.51
VPVD5
Programmable Voltage
Detector threshold 5
Rising edge 2.64 2.71 2.78
Falling edge 2.55 2.61 2.68
VPVD6
Programmable Voltage
Detector threshold 6
Rising edge 2.78 2.86 2.94
Falling edge in Run mode 2.69 2.76 2.83
Vhyst_BOR_PVD
Hysteresis voltage of BOR
(unless BOR0) and PVD Hysteresis in Run mode - 100 - mV
IDD_BOR_PVD(1) BOR(2) (unless BOR0) and
PVD consumption from VDD
- - 0.630 µA
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322
7.3.5 Embedded reference voltage
The parameters given in Table 127 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 122: General
operating conditions.
VAVM_0
Analog voltage detector for
VDDA threshold 0
Rising edge 1.66 1.71 1.76
V
Falling edge 1.56 1.61 1.66
VAVM_1
Analog voltage detector for
VDDA threshold 1
Rising edge 2.06 2.12 2.19
Falling edge 1.96 2.02 2.08
VAVM_2
Analog voltage detector for
VDDA threshold 2
Rising edge 2.42 2.50 2.58
Falling edge 2.35 2.42 2.49
VAVM_3
Analog voltage detector for
VDDA threshold 3
Rising edge 2.74 2.83 2.91
Falling edge 2.64 2.72 2.80
Vhyst_VDDA
Hysteresis of VDDA voltage
detector - - 100 - mV
IDD_PVM
PVM consumption from
VDD(1)
---0.25µA
IDD_VDDA
Voltage detector
consumption on VDDA(1) Resistor bridge - - 2.5 µA
1. Guaranteed by design.
2. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to
Section 7.3.6: Supply current characteristics).
Table 126. Reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 127. Embedded reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltages -40°C < TJ < 125 °C,
VDD = 3.3 V 1.180 1.216 1.255 V
tS_vrefint(1)(2)
ADC sampling time when
reading the internal reference
voltage
-4.3--
µs
tS_vbat(1)(2)
VBAT sampling time when
reading the internal VBAT
reference voltage
-9--
Irefbuf(2) Reference Buffer
consumption for ADC VDDA=3.3 V 9 13.5 23 µA
ΔVREFINT(2)
Internal reference voltage
spread over the temperature
range
-40°C < TJ < 125 °C - 5 15 mV
Tcoeff(2) Average temperature
coefficient
Average temperature
coefficient -2070ppm/°C
VDDcoeff(2) Average Voltage coefficient 3.0V < VDD < 3.6V - 10 1370 ppm/V
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7.3.6 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 69: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•All I/O pins are in analog input mode.
•All peripherals are disabled except when explicitly mentioned.
•The Flash memory access time is adjusted with the minimum wait states number,
depending on the fACLK frequency (refer to the table “Number of wait states according to
CPU clock (frcc_c_ck) frequency and VCORE range” available in the reference manual).
•When the peripherals are enabled, the AHB clock frequency is the CPU frequency
divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.
The parameters given in the below tables are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 122: General operating
conditions.
VREFINT_DIV1 1/4 reference voltage - - 25 -
%
VREFINT
VREFINT_DIV2 1/2 reference voltage - - 50 -
VREFINT_DIV3 3/4 reference voltage - - 75 -
1. The shortest sampling time for the application can be determined by multiple iterations.
2. Guaranteed by design.
Table 127. Embedded reference voltage (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 128. Internal reference voltage calibration values
Symbol Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 1FF1E860 - 1FF1E861
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Table 129. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, LDO regulator ON(1)
Symbol Parameter Conditions fHCLK
(MHz) Typ
Max(2)
Unit
Tj=25
°C
Tj=85
°C
Tj=105
°C
Tj=125
°C
IDD
Supply
current in
Run mode
All
peripherals
disabled
VOS0
480 148 226 307 390 -
mA
400125----
VOS1
400 110 168 230 296 384
30084----
VOS2
300 76 114 170 224 297
216 56 88 152 205 278
20053----
VOS3
200 47 71 121 164 223
180 43 64 116 159 218
168 40 63 115 158 217
144 35 55 109 153 212
60 16 36 92 135 194
25 12 24 83 126 185
All
peripherals
enabled
VOS0
480 226 348 439 550 -
400190----
VOS1
400 167 256 327 416 536
300135----
VOS2
300 122 183 248 320 419
20085----
VOS3 200 76 116 174 233 313
1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case.
2. Guaranteed by characterization results, unless otherwise specified.
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Table 130. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON,
LDO regulator ON
Symbol Parameter Conditions fHCLK
(MHz) Typ
Max(1)
Unit
Tj=25
°C
Tj=85
°C
Tj=105
°C
Tj=125
°C
IDD
Supply
current in
Run mode
All
peripherals
disabled
VOS0
480 110 222 304 388 -
mA
40091----
VOS1
400 80 162 228 294 381
30061.5----
VOS2
216 55 111 168 222 294
20038.5----
VOS3 200 34.5 69 120 163 222
All
peripherals
enabled
VOS0
480 220 342 436 546 -
400195----
VOS1
400 175 264 336 424 544
300135----
VOS2
300 120 180 246 318 418
20083----
VOS3 200 75 114 173 232 312
1. Guaranteed by characterization results, unless otherwise specified.
Table 131. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF,
LDO regulator ON
Symbol Parameter Conditions fHCLK
(MHz) Typ
Max(1)
Unit
Tj=25°C Tj=85°C Tj=105
°C
Tj=125
°C
IDD
Supply
current in
Run mode
All
peripherals
disabled
VOS0 480 87 157 259 342 453
mA
VOS1 400 73 123 201 267 355
VOS2 300 52 85 150 204 277
VOS3 200 34 54 109 152 212
All
peripherals
enabled
VOS0 480 168 276 390 504 658
VOS1 400 135 224 308 397 519
VOS2 300 100 154 228 301 401
VOS3 200 70 103 167 226 307
1. Guaranteed by characterization results, unless otherwise specified.
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Table 132. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON
Symbol Parameter Conditions fHCLK
(MHz) Typ
Max(1)
Unit
Tj=25°C Tj=85°C Tj=105
°C
Tj=125
°C
IDD
Supply
current in
batch
acquisition
mode
D1
Standby,
D2
Standby,
D3 Run
VOS3
64 2.7 4.7 12.9 19.0 27.5
mA
81.1----
D1 Stop,
D2 Stop,
D3 Run
VOS3
64 5.4 18.4 83.7 132.6 202.4
83.8----
1. Guaranteed by characterization results, unless otherwise specified.
Table 133. Typical and maximum current consumption in Stop, LDO regulator ON
Symbol Parameter Conditions Typ
Max(1)
Unit
Tj=25°C Tj=85°C Tj=105
°C
Tj=125
°C
IDD (Stop)
D1 Stop,
D2 Stop,
D3 Stop
Flash
memory
OFF, no
IWDG
SVOS5 1.27 6.3 42.5 72.0 -
mA
SVOS4 1.96 9.4 57.4 94.6 -
SVOS3 2.78 13.8 75.9 121.3 183.8
Flash
memory
ON, no
IWDG
SVOS5 1.27 6.3 42.5 72.0 -
SVOS4 2.25 9.8 57.9 95.2 -
SVOS3 3.07 14.1 76.4 122.0 184.8
D1 Stop,
D2 Standby,
D3 Stop
Flash
memory
OFF, no
IWDG
SVOS5 0.91 4.6 30.4 51.2 -
SVOS4 1.42 6.8 41.1 67.3 -
SVOS3 2.02 10.0 54.4 86.6 130.0
Flash
memory
ON, no
IWDG
SVOS5 0.91 4.6 30.4 51.2 -
SVOS4 1.70 7.2 41.5 67.9 -
SVOS3 2.31 10.3 54.9 87.1 130.8
D1 Standby,
D2 Stop,
D3 Stop Flash
memory
OFF, no
IWDG
SVOS5 0.49 2.4 16.5 28.0 -
SVOS4 0.76 3.6 22.2 36.6 -
SVOS3 1.10 5.3 29.3 46.9 71.2
D1 Standby,
D2 Standby,
D3 Stop
SVOS5 0.15 0.7 4.3 7.3 -
SVOS4 0.22 1.0 5.8 9.6 -
SVOS3 0.35 1.5 7.8 12.3 18.6
1. Guaranteed by characterization results, unless otherwise specified.
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Table 134. Typical and maximum current consumption in Sleep mode, LDO regulator
Symbol Parameter Conditions fHCLK
(MHz) Typ
Max(1)
Unit
Tj=25
°C
Tj=85
°C
Tj=105
°C
Tj=125
°C
IDD (Sleep)
Supply
current in
Sleep mode
All
peripherals
disabled
VOS0
480 50.7 96.3 253.4 366.1 -
mA
400 43.4 87.8 245.5 357.9 -
VOS1
400 35.3 66.5 181.3 265.8 379.6
300 27.9 - - - -
VOS2
300 24.6 47.3 139.1 207.3 300.4
200 18.8 - - - -
VOS3 200 16.5 33.6 106.4 160.9 236.1
All
peripherals
enabled
VOS0
480 136.0 194.7 348.5 464.4 -
400 115.0 169.0 325.9 441.7 -
VOS1
400 97.7 138.2 251.3 338.4 456.4
300 74.9 - - - -
VOS2
300 67.3 95.8 187.6 257.9 354.1
200 52.8 - - - -
VOS3 200 47.1 69.3 141.4 197.7 275.1
1. Guaranteed by characterization results, unless otherwise specified.
Table 135. Typical and maximum current consumption in Standby
Symbol Parameter
Conditions
Typ Max(1)
Unit
1.62 V 2.4 V 3 V 3.3 V
3 V
Backup
SRAM
RTC
and
LSE
Tj=25
°C
Tj=85
°C
Tj=105
°C
Tj=125
°C
IDD
(Standby)
Supply
current in
Standby
mode
OFF OFF 1,92 1,95 2,06 2,16 4 18 40 90
µA
ON OFF 3,33 3,44 3,6 3,79 8.2 47 83 141
OFF ON 2,43 2,57 2,77 2,95 - - - -
ON ON 3,82 4,05 4,31 4,55 - - - -
1. Guaranteed by characterization results, unless otherwise specified.
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322
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 157: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
Table 136. Typical and maximum current consumption in VBAT mode
Symbol Parameter
Conditions Typ Max(1)
Unit
Backup
SRAM
RTC
and
LSE
1.2 V 2 V 3 V 3.4 V
3 V
Tj=25
°C
Tj=85
°C
Tj=105
°C
Tj=125
°C
IDD
(VBAT)
Supply
current in
VBAT mode
OFF OFF 0,02 0,02 0,03 0,05 0,5 4,1 10 24
µA
ON OFF 1,33 1,45 1,58 1,7 4,4 22 48 87
OFF ON 0,46 0,57 0,75 0,87 - - - -
ON ON 1,77 2 2,3 2,5 - - - -
1. Guaranteed by characterization results, unless otherwise specified.
Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G
226/357 DS12110 Rev 7
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 137: Peripheral current
consumption in Run mode), the I/Os used by an application also contribute to the current
consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to
supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external)
connected to the pin:
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDx is the MCU supply voltage
fSW is the I/O switching frequency
CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•At startup, all I/O pins are in analog input configuration.
•All peripherals are disabled unless otherwise mentioned.
•The I/O compensation cell is enabled.
•frcc_c_ck is the CPU clock. fPCLK = frcc_c_ck/4, and fHCLK = frcc_c_ck/2.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
–f
rcc_c_ck = 400 MHz (Scale 1), frcc_c_ck = 300 MHz (Scale 2),
frcc_c_ck = 200 MHz (Scale 3)
•The ambient operating temperature is 25 °C and VDD=3.3 V.
ISW VDDx fSW CL
××=
DS12110 Rev 7 227/357
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322
Table 137. Peripheral current consumption in Run mode
Bus Peripheral VOS0 VOS1 VOS2 VOS3 Unit
AHB3
MDMA 4.6 3.8 3.4 3.2
µA/MHz
DMA2D 2.9 2.4 2.1 1.9
JPGDEC 4.1 3.7 3.4 3.1
FLASH 17.0 15.0 14.0 12.0
FMC registers 0.9 1.1 0.9 0.8
FMC kernel 7.0 6.1 5.6 5.0
QUADSPI registers 1.5 1.5 1.4 1.3
QSPI kernel 1.0 0.9 0.8 0.7
SDMMC1 registers 8.2 7.2 6.7 6.0
SDMMC1 kernel 1.3 1.2 0.9 0.9
DTCM1 7.9 6.8 6.0 5.3
DTCM2 8.3 7.2 6.4 5.7
ITCM 7.0 6.3 5.6 5.1
D1SRAM1 13.0 11.0 9.9 8.7
AHB3 bridge 35.0 32.0 29.0 26.0
Total AHB3 120 106 96 86
AHB1
DMA1 54.0 48.0 41.0 37.0
DMA2 55.0 49.0 42.0 37.0
ADC12 registers 4.5 4.1 3.7 3.3
ADC12 kernel 1.0 0.7 0.4 0.6
ART accelerator 4.1 3.7 3.2 2.9
ETH1MAC 17.0 15.0 14.0 12.0
ETH1TX 0.1 0.1 0.1 0.1
ETH1RX 0.1 0.1 0.1 0.1
USB1 OTG registers 23.0 21.0 19.0 17.0
USB1 OTG kernel 8.2 0.5 8.3 8.2
USB1 ULPI 0.1 0.1 0.1 0.1
USB2 OTG registers 21.0 19.0 17.0 15.0
USB2 OTG kernel 8.5 0.4 8.6 8.3
USB2 ULPI 23.0 19.0 20.0 19.0
AHB1 bridge 0.1 0.1 0.1 0.1
Total AHB1 220 181 178 161
Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G
228/357 DS12110 Rev 7
AHB2
DCMI 2.1 1.9 1.8 1.6
µA/MHz
RNG registers 1.7 2.0 1.3 1.2
RNG kernel 11.0 0.1 9.7 9.4
SDMMC2 registers 47.0 41.0 37.0 34.0
SDMMC2 kernel 1.7 1.2 1.1 1.0
D2SRAM1 5.7 4.9 4.4 3.9
D2SRAM2 5.2 4.5 4.0 3.5
D2SRAM3 4.1 3.6 3.2 2.8
AHB2 bridge 0.1 0.1 0.1 0.1
Total AHB2 79 60 63 58
AHB4
GPIOA 1.5 1.3 1.3 1.1
GPIOB 1.2 1.0 1.0 0.9
GPIOC 0.8 0.7 0.7 0.6
GPIOD 1.1 1.0 1.0 0.9
GPIOE 0.7 0.7 0.7 0.6
GPIOF 0.8 0.8 0.7 0.6
GPIOG 0.9 0.8 0.8 0.7
GPIOH 1.1 1.0 1.0 0.9
GPIOI 0.9 0.9 0.8 0.7
GPIOJ 0.8 0.8 0.7 0.7
GPIOK 0.7 0.8 0.7 0.6
CRC 0.4 0.5 0.4 0.3
BDMA 6.6 5.9 5.3 4.8
ADC3 registers 1.7 1.5 1.2 1.2
ADC3 kernel 0.4 0.3 0.5 0.2
BKPRAM 2.3 1.9 1.7 1.5
AHB4 bridge 0.1 0.1 0.1 0.1
Total AHB4 22 20 19 16
APB3
WWDG1 0.7 0.5 0.5 0.2
µA/MHz
LCD-TFT 81.0 36.0 33.0 30.0
APB3 bridge 0.3 0.2 0.1 0.1
Total APB3 87 41 38 34
Table 137. Peripheral current consumption in Run mode (continued)
Bus Peripheral VOS0 VOS1 VOS2 VOS3 Unit
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322
APB1
TIM2 7.7 3.6 3.3 3.0
µA/MHz
TIM3 6.7 3.2 3.0 2.7
TIM4 6.3 3.1 2.8 2.5
TIM5 7.4 3.5 3.2 2.8
TIM6 1.4 0.7 0.8 0.6
TIM7 1.4 0.7 0.7 0.6
TIM12 3.2 1.5 1.5 1.3
TIM13 2.3 1.1 1.1 0.9
TIM14 2.1 1.1 1.1 0.9
LPTIM1 registers 0.7 0.5 0.8 0.7
LPTIM1 kernel 2.4 2.3 1.9 1.7
WWDG2 0.6 0.5 0.5 0.4
SPI2 registers 2.0 1.8 1.7 1.4
SPI2 kernel 0.8 0.6 0.5 0.6
SPI3 registers 1.8 1.6 1.6 1.3
SPI3 kernel 0.7 0.9 0.7 0.7
SPDIFRX1 registers 0.5 0.7 0.7 0.6
SPDIFRX1 kernel 3.5 2.8 2.4 2.2
USART2 registers 1.9 1.7 1.4 1.3
USART2 kernel 4.3 3.9 3.6 3.2
USART3 registers 1.9 1.7 1.4 1.3
USART3 kernel 4.4 3.9 3.5 3.2
UART4 registers 1.7 1.5 1.4 1.4
UART4 kernel 3.9 3.4 3.1 2.8
UART5 registers 1.6 1.4 1.4 1.3
UART5 kernel 3.8 3.4 3.0 2.7
I2C1 registers 1.1 0.8 0.9 0.8
I2C1 kernel 2.5 2.3 2.0 1.9
I2C2 registers 1.0 0.8 0.9 0.8
Table 137. Peripheral current consumption in Run mode (continued)
Bus Peripheral VOS0 VOS1 VOS2 VOS3 Unit
Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G
230/357 DS12110 Rev 7
APB1
(continued)
I2C2 kernel 2.3 2.2 1.9 1.7
µA/MHz
I2C3 registers 0.8 1.0 0.8 0.8
I2C3 kernel 2.4 1.9 1.8 1.6
HDMI-CEC registers 0.7 0.5 0.6 0.5
HDMI-CEC kernel 0.1 0.1 3.2 0.1
DAC12 3.6 1.3 1.2 1.0
USART7 registers 1.8 1.8 1.6 1.4
USART7 kernel 4.0 3.3 3.0 2.8
USART8 registers 2.0 1.6 1.6 1.4
USART8 kernel 3.9 3.4 3.1 2.8
CRS 6.4 5.5 5.0 4.5
SWPMI registers 2.7 2.4 2.3 1.9
SWPMI kernel 0.1 0.1 0.1 0.1
OPAMP 0.2 0.3 0.3 0.2
MDIO 3.3 2.9 2.6 2.3
FDCAN registers 19.0 17.0 15.0 13.0
FDCAN kernel 9.1 7.9 6.9 6.4
APB1 bridge 0.1 0.1 0.1 0.1
Total APB1 142 108 102 88
APB2
TIM1 11.0 5.0 4.5 4.0
TIM8 10.0 4.7 4.3 3.8
USART1 registers 3.6 2.5 2.7 2.9
USART1 kernel 0.1 0.1 0.1 0.1
USART6 registers 4.5 3.0 3.1 3.4
USART6 kernel 0.1 0.1 0.1 0.1
SPI1 registers 2.0 1.7 1.6 1.4
SPI1 kernel 0.9 0.8 0.7 0.6
SPI4 registers 2.1 1.7 1.6 1.5
SPI4 kernel 0.6 0.5 0.5 0.3
TIM15 5.5 2.5 2.3 2.1
TIM16 4.1 2.0 1.8 1.7
TIM17 4.1 1.9 1.8 1.6
SPI5 registers 2.0 1.8 1.6 1.3
SPI5 kernel 0.5 0.4 0.4 0.5
SAI1 registers 1.3 1.1 1.1 1.0
Table 137. Peripheral current consumption in Run mode (continued)
Bus Peripheral VOS0 VOS1 VOS2 VOS3 Unit
DS12110 Rev 7 231/357
STM32H742xI/G STM32H743xI/G Electrical characteristics (rev V)
322
APB2
(continued)
SAI1 kernel 1.4 1.1 1.0 0.8
µA/MHz
SAI2 registers 1.5 1.3 1.2 1.0
SAI2 kernel 1.1 1.0 0.9 0.9
SAI3 registers 1.6 1.3 1.1 1.0
SAI3 kernel 1.1 1.2 1.1 0.9
DFSDM1 registers 6.5 5.8 5.2 4.7
DFSDM1 kernel 0.3 0.2 0.2 0.4
HRTIM 84.0 39.0 35.0 32.0
APB2 bridge 0.2 0.1 0.1 0.2
Total APB2 150 81 74 68
APB4
SYSCFG 0.9 1.0 0.7 0.8
LPUART1 registers 1.1 1.3 1.0 0.8
LPUART1 kernel 2.9 2.2 2.2 2.1
SPI6 registers 1.8 1.6 1.4 1.3
SPI6 kernel 0.4 0.4 0.5 0.3
I2C4 registers 0.9 0.7 0.7 0.4
I2C4 kernel 2.2 2.1 1.9 1.8
LPTIM2 registers 0.8 0.6 0.7 0.5
LPTIM2 kernel 2.3 2.1 1.8 1.4
LPTIM3 registers 0.7 0.7 0.7 0.4
LPTIM3 kernel 2.1 1.7 1.6 1.5
LPTIM4 registers 0.8 0.4 0.6 0.4
LPTIM4 kernel 2.2 2.0 1.7 1.5
LPTIM5 registers 0.5 0.4 0.6 0.4
LPTIM5 kernel 2.0 1.8 1.5 1.2
COMP12 0.6 0.4 0.5 0.2
VREF 0.4 0.2 0.2 0.1
RTC 1.1 0.9 1.0 0.6
SAI4 registers 1.7 1.4 1.3 1.0
SAI4 kernel 2.0 2.0 1.8 1.6
APB4 bridge 0.1 0.1 0.1 0.1
Total APB4 28 24.4 22.4 18.9
Table 137. Peripheral current consumption in Run mode (continued)
Bus Peripheral VOS0 VOS1 VOS2 VOS3 Unit
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7.3.7 Wakeup time from low-power modes
The wakeup times given in Table 138 are measured starting from the wakeup event trigger
up to the first instruction executed by the CPU:
•For Stop or Sleep modes: the wakeup event is WFE.
•WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.
Table 138. Low-power mode wakeup timings
Symbol Parameter Conditions Typ(1) Max(1) Unit
tWUSLEEP(2) Wakeup from Sleep - 9 10
CPU
clock
cycles
tWUSTOP(2) Wakeup from Stop
VOS3, HSI, Flash memory in normal mode 4.4 5.6
µs
VOS3, HSI, Flash memory in low-power
mode 12 15
VOS4, HSI, Flash memory in normal mode 15 20
VOS4, HSI, Flash memory in low-power
mode 23 28
VOS5, HSI, Flash memory in normal mode 39 71
VOS5, HSI, Flash memory in low-power
mode 39 47
VOS3, CSI, Flash memory in normal mode 30 37
VOS3, CSI, Flash memory in low power
mode 36 50
VOS4, CSI, Flash memory in normal mode 38 48
VOS4, CSI, Flash memory in low-power
mode 47 61
VOS5, CSI, Flash memory in normal mode 68 75
VOS5, CSI, Flash memory in low-power
mode 68 77
tWUSTOP_
KERON(2)
Wakeup from Stop,
clock kept running
VOS3, HSI, Flash memory in normal mode 2.6 3.4
VOS3, CSI, Flash memory in normal mode 26 36
tWUSTDBY(2) Wakeup from Standby
mode - 390 500
1. Guaranteed by characterization results.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
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322
7.3.8 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
The external clock signal has to respect the Table 157: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 71.
Figure 71. High-speed external clock source AC timing diagram
Table 139. High-speed external user clock characteristics(1)
1. Guaranteed by design.
Symbol Parameter Min Typ Max Unit
fHSE_ext User external clock source frequency 4 25 50 MHz
VSW
(VHSEH −VHSEL)
OSC_IN amplitude 0.7VDD -V
DD V
VDC OSC_IN input voltage VSS -0.3V
SS
tW(HSE) OSC_IN high or low time 7 - - ns
ai17528b
OSC _I N
External
STM32
clock source
VHSEH
tf(HSE) tW(HSE)
IL
90 %
10 %
THSE
t
tr(HSE) tW(HSE)
fHSE_ext
VHSEL
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234/357 DS12110 Rev 7
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 157: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 72.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 72. Low-speed external clock source AC timing diagram
Table 140. Low-speed external user clock characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext User external clock source frequency - - 32.768 1000 kHz
VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx -V
DDIOx V
VLSEL OSC32_IN input pin low level voltage - VSS -0.3 V
DDIOx
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time - 250 - - ns
1. Guaranteed by design.
ai17529b
OSC32_IN
External
STM32
clock source
VLSEH
tf(LSE) tW(LSE)
IL
90%
10%
TLSE
t
tr(LSE) tW(LSE)
fLSE_ext
VLSEL
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322
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Ta ble 141. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 73). CL1 and CL2 are usually
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Table 141. 4-48 MHz HSE oscillator characteristics(1)
Symbol Parameter Operating
conditions(2) Min Typ Max Unit
F Oscillator frequency - 4 - 48 MHz
RFFeedback resistor - - 200 - k
IDD(HSE) HSE current consumption
During startup(3) -- 4
mA
VDD=3 V, Rm=30
CL=10pF@4MHz -0.35 -
VDD=3 V, Rm=30
CL=10 pF at 8 MHz -0.40 -
VDD=3 V, Rm=30
CL=10 pF at 16 MHz -0.45 -
VDD=3 V, Rm=30
CL=10 pF at 32 MHz -0.65 -
VDD=3 V, Rm=30
CL=10 pF at 48 MHz -0.95 -
Gmcritmax Maximum critical crystal gm Startup - - 1.5 mA/V
tSU(4) Start-up time VDD is stabilized - 2 - ms
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G
236/357 DS12110 Rev 7
Figure 73. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Ta ble 142. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
ai17530b
OSC_OU T
OSC_IN fHSE
CL1
RF
STM32
8 MHz
resonator
Resonator with
integrated capacitors
Bias
controlled
gain
REXT(1)
CL2
Table 142. Low-speed external user clock characteristics(1)
Symbol Parameter Operating conditions(2) Min Typ Max Unit
F Oscillator frequency - - 32.768 - kHz
IDD
LSE current
consumption
LSEDRV[1:0] = 00,
Low drive capability -290 -
nA
LSEDRV[1:0] = 01,
Medium Low drive capability -390 -
LSEDRV[1:0] = 10,
Medium high drive capability -550 -
LSEDRV[1:0] = 11,
High drive capability -900 -
Gmcritmax
Maximum critical crystal
gm
LSEDRV[1:0] = 00,
Low drive capability --0.5
µA/V
LSEDRV[1:0] = 01,
Medium Low drive capability - - 0.75
LSEDRV[1:0] = 10,
Medium high drive capability --1.7
LSEDRV[1:0] = 11,
High drive capability --2.7
tSU(3) Startup time VDD is stabilized - 2 - s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
DS12110 Rev 7 237/357
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322
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 74. Typical application with a 32.768 kHz crystal
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
7.3.9 Internal clock source characteristics
The parameters given in Table 143 to Table 146 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 122: General
operating conditions.
48 MHz high-speed internal RC oscillator (HSI48)
ai17531b
OSC32_OU T
OSC32_IN fLSE
CL1
RF
STM32
32.768 kHz
resonator
Resonator with
integrated capacitors
Bias
controlled
gain
CL2
Table 143. HSI48 oscillator characteristics
Symbol Parameter Conditions Min Typ Max Unit
fHSI48 HSI48 frequency VDD=3.3 V,
TJ=30 °C 47.5(1) 48 48.5(1) MHz
TRIM(2) USER trimming step - - 0.175 - %
USER TRIM
COVERAGE(3) USER TRIMMING Coverage ± 32 steps ±4.79 ±5.60 - %
DuCy(HSI48)(2) Duty Cycle - 45 - 55 %
ACCHSI48_REL(3)(4) Accuracy of the HSI48 oscillator over
temperature (factory calibrated) TJ=-40 to 125 °C –4.5 - 3.5 %
VDD(HSI48)(3) HSI48 oscillator frequency drift with
VDD(5)
VDD=3 to 3.6 V - 0.025 0.05
%
VDD=1.62 V to 3.6 V - 0.05 0.1
tsu(HSI48)(2) HSI48 oscillator start-up time - - 2.1 4.0 µs
IDD(HSI48)(2) HSI48 oscillator power consumption - - 350 400 µA
NT jitter Next transition jitter
Accumulated jitter on 28 cycles(6) - - ± 0.15 - ns
PT jitter Paired transition jitter
Accumulated jitter on 56 cycles(6) - - ± 0.25 - ns
1. Guaranteed by test in production.
2. Guaranteed by design.
3. Guaranteed by characterization.
4. fHSI = ACCHSI48_REL + VDD.
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64 MHz high-speed internal RC oscillator (HSI)
4 MHz low-power internal RC oscillator (CSI)
5. These values are obtained by using the formula: (Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) /
Freq(1.62V).
6. Jitter measurements are performed without clock source activated in parallel.
Table 144. HSI oscillator characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fHSI HSI frequency VDD=3.3 V, TJ=30 °C 63.7(2) 64 64.3(2) MHz
TRIM HSI user trimming step
Trimming is not a multiple
of 32 - 0.24 0.32
%
Trimming is 128, 256 and
384 5.2 1.8 -
Trimming is 64, 192, 320
and 448 1.4 0.8 -
Other trimming are a
multiple of 32 (not
including multiple of 64
and 128)
0.6 0.25 -
DuCy(HSI) Duty Cycle - 45 - 55 %
ΔVDD (HSI)
HSI oscillator frequency drift over
VDD (reference is 3.3 V) VDD=1.62 to 3.6 V 0.12 - 0.03 %
ΔTEMP (HSI)
HSI oscillator frequency drift over
temperature (reference is 64 MHz)
TJ=-20 to 105 °C 1(3) -1
(3) %
TJ=40 to TJmax °C 2(3) -1
(3)
tsu(HSI) HSI oscillator start-up time - - 1.4 2 µs
tstab(HSI) HSI oscillator stabilization time at 1% of target frequency - 4 8 µs
IDD(HSI) HSI oscillator power consumption - - 300 400 µA
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
Table 145. CSI oscillator characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fCSI CSI frequency VDD=3.3 V, TJ=30 °C 3.96(2) 44.04
(2) MHz
TRIM Trimming step - - 0.35 - %
DuCy(CSI) Duty Cycle - 45 - 55 %
TEMP (CSI) CSI oscillator frequency drift over
temperature
TJ = 0 to 85 °C - 3.7(3) 4.5(3)
%
TJ = 40 to 125 °C - 11(3) 7.5(3)
DVDD (CSI) CSI oscillator frequency drift over
VDD
VDD = 1.62 to 3.6 V - 0.06 0.06 %
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Low-speed internal (LSI) RC oscillator
tsu(CSI) CSI oscillator startup time - - 1 2 µs
tstab(CSI)
CSI oscillator stabilization time
(to reach ±3% of fCSI)- - - 4 cycle
IDD(CSI) CSI oscillator power consumption - - 23 30 µA
1. Guaranteed by design.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
Table 145. CSI oscillator characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 146. LSI oscillator characteristics
Symbol Parameter Conditions Min Typ Max Unit
fLSI LSI frequency
VDD = 3.3 V, TJ = 25 °C 31.4(1)
1. Guaranteed by test in production.
32 32.6(1)
kHz
TJ = –40 to 110 °C, VDD = 1.62 to
3.6 V 29.76(2)
2. Guaranteed by characterization results.
- 33.6(2)
TJ = –40 to 125 °C, VDD = 1.62 to
3.6 V 29.4 - 33.6
tsu(LSI)(3)
3. Guaranteed by design.
LSI oscillator
startup time - - 80 130
µs
tstab(LSI)(3)
LSI oscillator
stabilization
time (5% of
final value)
- - 120 170
IDD(LSI)(3)
LSI oscillator
power
consumption
- - 130 280 nA
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7.3.10 PLL characteristics
The parameters given in Table 147 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 122: General operating conditions.
Table 147. PLL characteristics (wide VCO frequency range)(1)
Symbol Parameter Conditions Min Typ Max Unit
fPLL_IN
PLL input clock - 2 - 16 MHz
PLL input clock duty cycle - 10 - 90 %
fPLL_P_OUT PLL multiplier output clock P
VOS0 1.5 - 480(2)
MHz
VOS1 1.5 - 400(2)
VOS2 1.5 - 300(2)
VOS3 1.5 - 200(2)
fVCO_OUT PLL VCO output - 192 - 960
tLOCK PLL lock time
Normal mode - 50(3) 150(3)
µs
Sigma-delta mode
(CKIN ≥ 8 MHz) -58
(3) 166(3)
Jitter
Cycle-to-cycle jitter(4) -
VCO =
192 MHz -134 -
±ps
VCO =
200 MHz -134 -
VCO =
400 MHz -76 -
VCO =
800 MHz -39 -
Long term jitter
Normal mode VCO =
800 MHz -±0.7 -
%
Sigma-delta
mode (CKIN =
16 MHz)
VCO =
800 MHz -±0.8 -
IDD(PLL)(3) PLL power consumption on VDD
VCO freq =
836 MHz
VDDA - 590 1500
µA
VCORE -720 -
VCO freq =
192 MHz
VDDA -180600
VCORE -280 -
1. Guaranteed by design unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation (480 MHz for VOS0, 400 MHz for VOS1,
300 MHz for VOS2, 200 MHz for VOS3).
3. Guaranteed by characterization results.
4. Integer mode only.
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Table 148. PLL characteristics (medium VCO frequency range)(1)
Symbol Parameter Conditions Min Typ Max Unit
fPLL_IN
PLL input clock - 1 - 2 MHz
PLL input clock duty cycle - 10 - 90 %
fPLL_OUT
PLL multiplier output clock P, Q,
R
VOS1 1.17 - 210
MHz
VOS2 1.17 - 210
VOS3 1.17 - 200
fVCO_OUT PLL VCO output - 150 - 420
tLOCK PLL lock time
Normal mode - 60(2) 100(2)
µs
Sigma-delta mode forbidden
Jitter
Cycle-to-cycle jitter(3) -
VCO =
150 MHz -145-
±ps
VCO =
300 MHz -91-
VCO =
400 MHz -64-
VCO =
420 MHz -63-
Period jitter fPLL_OUT =
50 MHz
VCO =
150 MHz -55-
±-ps
VCO =
400 MHz -30-
Long term jitter Normal mode VCO =
400 MHz -±0.3-%
I(PLL)(2) PLL power consumption on VDD
VCO freq =
420MHz
VDD - 440 1150
µA
VCORE - 530 -
VCO freq =
150MHz
VDD - 180 500
VCORE - 200 -
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by characterization results.
3. Integer mode only.
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7.3.11 Memory characteristics
Flash memory
The characteristics are given at TJ = –40 to 125 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 149. Flash memory characteristics
Symbol Parameter Conditions Min Typ Max Unit
IDD Supply current
Write / Erase 8-bit mode - 6.5 -
mA
Write / Erase 16-bit mode - 11.5 -
Write / Erase 32-bit mode - 20 -
Write / Erase 64-bit mode - 35 -
Table 150. Flash memory programming (single bank configuration nDBANK=1)
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
tprog
Word (266 bits) programming
time
Program/erase parallelism x 8 - 290 580(2)
µs
Program/erase parallelism x 16 - 180 360
Program/erase parallelism x 32 - 130 260
Program/erase parallelism x 64 - 100 200
tERASE128KB Sector (128 KB) erase time
Program/erase parallelism x 8 - 2 4
s
Program/erase parallelism x 16 - 1.8 3.6
Program/erase parallelism x 32 -
tME Mass erase time
Program/erase parallelism x 8 - 13 26
Program/erase parallelism x 16 - 8 16
Program/erase parallelism x 32 - 6 12
Program/erase parallelism x 64 - 5 10
Vprog Programming voltage
Program parallelism x 8
1.62 - 3.6
V
Program parallelism x 16
Program parallelism x 32
Program parallelism x 64 1.8 - 3.6
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 10K erase operations.
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7.3.12 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 152. They are based on the EMS levels and classes
defined in application note AN1709.
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
Table 151. Flash memory endurance and data retention
Symbol Parameter Conditions
Value
Unit
Min(1)
NEND Endurance TJ = –40 to +125 °C (6 suffix versions) 10 kcycles
tRET
Data retention 1 kcycle at TA = 85 °C 30
Years
10 kcycles at TA = 55 °C 20
1. Guaranteed by characterization results.
Table 152. EMS characteristics
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on any I/O pin to induce
a functional disturbance VDD = 3.3 V, TA = +25 °C,
UFBGA240, frcc_c_ck =
400 MHz, conforms to
IEC 61000-4-2
3B
VFTB
Fast transient voltage burst limits to be applied
through 100 pF on VDD and VSS pins to induce a
functional disturbance
5A
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Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•Corrupted program counter
•Unexpected reset
•Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 153. EMI characteristics
Symbol Parameter Conditions Monitored
frequency band
Max vs.
[fHSE/fCPU]Unit
8/400 MHz
SEMI Peak level VDD = 3.6 V, TA = 25 °C, UFBGA240 package,
conforming to IEC61967-2
0.1 to 30 MHz 11
dBµV
30 to 130 MHz 6
130 MHz to 1 GHz 12
1 GHz to 2 GHz 7
EMI Level 2.5 -
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7.3.13 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•A supply overvoltage is applied to each power supply pin
•A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 154. ESD absolute maximum ratings
Symbol Ratings Conditions Packages Class Maximum
value(1) Unit
VESD(HBM)
Electrostatic discharge
voltage (human body
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS-
001
All 1C 1000
V
VESD(CDM)
Electrostatic discharge
voltage (charge device
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS-
002
All C1 250
1. Guaranteed by characterization results.
Table 155. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latchup class TA = +25 °C conforming to JESD78 II level A
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7.3.14 I/O current injection characteristics
As a general rule, a current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
Table 156. I/O current injection susceptibility(1)
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
IINJ
PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15,
PJ12, PB4 50
mA
PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11 0 NA
PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4,
PA5, PH4, PH5, BOOT0 00
All other I/Os 5 NA
1. Guaranteed by characterization.
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7.3.15 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 157: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 122: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
Table 157. I/O static characteristics
Symbol Parameter Condition Min Typ Max Unit
VIL
I/O input low level voltage except
BOOT0
1.62 V<VDDIOx<3.6 V
--0.3V
DD(1)
V
I/O input low level voltage except
BOOT0 --
0.4VDD0.
1(2)
BOOT0 I/O input low level voltage - - 0.19VDD+
0.1(2)
VIH
I/O input high level voltage except
BOOT0
1.62 V<VDDIOx<3.6 V
0.7VDD(1) --
V
I/O input high level voltage except
BOOT0(3)
0.47VDD+0.
25(2) --
BOOT0 I/O input high level
voltage(3)
0.17VDD+0.
6(2) --
VHYS(2)
TT_xx, FT_xxx and NRST I/O
input hysteresis 1.62 V< VDDIOx <3.6 V
- 250 -
mV
BOOT0 I/O input hysteresis - 200 -
Ileak(4)
FT_xx Input leakage current(2)
0< VIN Max(VDDXXX)(9) --+/-250
nA
Max(VDDXXX) < VIN 5.5 V
(5)(6)(9) - - 1500
FT_u IO
0< VIN Max(VDDXXX)(9) --+/- 350
Max(VDDXXX) < VIN 5.5 V
(5)(6)(9) - - 5000(7)
TT_xx Input leakage current 0< VIN Max(VDDXXX) (9) --+/-250
VPP (BOOT0 alternate function)
0< VIN VDDIOX --15
VDDIOX < VIN 9 V 35
RPU
Weak pull-up equivalent
resistor(8) VIN=VSS 30 40 50
k
RPD
Weak pull-down equivalent
resistor(8) VIN=VDD(9) 30 40 50
CIO I/O pin capacitance - - 5 - pF
1. Compliant with CMOS requirements.
2. Guaranteed by design.
3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 A + [number of I/Os where VIN is applied on the pad] Ilkg(Max).
5. All FT_xx IO except FT_lu, FT_u and PC3.
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All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 75.
Figure 75. VIL/VIH for all I/Os except BOOT0
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 7.2. In particular:
•The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 120).
•The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 120).
6. VIN must be less than Max(VDDXXX) + 3.6 V.
7. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be
disabled.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
9. Max(VDDXXX) is the maximum value of all the I/O supplies.
MSv46121V3
0
0.5
1
1.5
2
2.5
3
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Voltage
TLL requirement: VIHmin = 2 V
TLL requirement: VILmin = 0.8 V
CMOS requirement: V
IHmin
=0.7V
DD
CMOS requirement: V
ILmax
=0.3V
DD
Based on simulation V
IHmin
=0.47V
DD
+0.25
Based on simulation V
ILmax
=0.4V
DD
-0.1
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Output voltage levels
Unless otherwise specified, the parameters given in Table 158: Output voltage
characteristics for all I/Os except PC13, PC14, PC15 and PI8 and Ta ble 159: Output voltage
characteristics for PC13, PC14, PC15 and PI8 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 122: General
operating conditions. All I/Os are CMOS and TTL compliant.
Table 158. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8(1)
Symbol Parameter Conditions(3) Min Max Unit
VOL Output low level voltage
CMOS port(2)
IIO=8 mA
2.7 V VDD 3.6 V
-0.4
V
VOH Output high level voltage
CMOS port(2)
IIO=-8 mA
2.7 V VDD 3.6 V
VDD0.4 -
VOL(3) Output low level voltage
TTL port(2)
IIO=8 mA
2.7 V VDD 3.6 V
-0.4
VOH(3) Output high level voltage
TTL port(2)
IIO=-8 mA
2.7 V VDD 3.6 V
2.4 -
VOL(3) Output low level voltage IIO=20 mA
2.7 V VDD 3.6 V -1.3
VOH(3) Output high level voltage IIO=-20 mA
2.7 V VDD 3.6 V VDD1.3 -
VOL(3) Output low level voltage IIO=4 mA
1.62 V VDD 3.6 V -0.4
VOH (3) Output high level voltage IIO=-4 mA
1.62 VVDD<3.6 V VDD-0.4 -
VOLFM+(3) Output low level voltage for an FTf
I/O pin in FM+ mode
IIO= 20 mA
2.3 V VDD3.6 V -0.4
IIO= 10 mA
1.62 V VDD 3.6 V -0.4
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 119:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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Table 159. Output voltage characteristics for PC13, PC14, PC15 and PI8(1)
Symbol Parameter Conditions(3) Min Max Unit
VOL Output low level voltage
CMOS port(2)
IIO=3 mA
2.7 V VDD 3.6 V
-0.4
V
VOH Output high level voltage
CMOS port(2)
IIO=-3 mA
2.7 V VDD 3.6 V
VDD0.4 -
VOL(3) Output low level voltage
TTL port(2)
IIO=3 mA
2.7 V VDD 3.6 V
-0.4
VOH(2) Output high level voltage
TTL port(2)
IIO=-3 mA
2.7 V VDD 3.6 V
2.4 -
VOL(2) Output low level voltage IIO=1.5 mA
1.62 V VDD 3.6 V -0.4
VOH(2) Output high level voltage IIO=-1.5 mA
1.62 V VDD 3.6 V VDD0.4 -
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 119:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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Output buffer timing characteristics (HSLV option disabled)
The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the
product voltage is below 2.7 V.
Table 160. Output timing characteristics (HSLV OFF)(1)(2)
Speed Symbol Parameter conditions Min Max Unit
00
Fmax(3) Maximum frequency
C=50 pF, 2.7 V VDD3.6 V - 12
MHz
C=50 pF, 1.62 VVDD2.7 V - 3
C=30 pF, 2.7 VVDD3.6 V - 12
C=30 pF, 1.62 VVDD2.7 V - 3
C=10 pF, 2.7 VVDD3.6 V - 16
C=10 pF, 1.62 VVDD2.7 V - 4
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 2.7 V VDD3.6 V - 16.6
ns
C=50 pF, 1.62 VVDD2.7 V - 33.3
C=30 pF, 2.7 VVDD3.6 V - 13.3
C=30 pF, 1.62 VVDD2.7 V - 25
C=10 pF, 2.7 VVDD3.6 V - 10
C=10 pF, 1.62 VVDD2.7 V - 20
01
Fmax(3) Maximum frequency
C=50 pF, 2.7 V VDD3.6 V - 60
MHz
C=50 pF, 1.62 VVDD2.7 V - 15
C=30 pF, 2.7 VVDD3.6 V - 80
C=30 pF, 1.62 VVDD2.7 V - 15
C=10 pF, 2.7 VVDD3.6 V - 110
C=10 pF, 1.62 VVDD2.7 V - 20
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 2.7 V VDD3.6 V - 5.2
ns
C=50 pF, 1.62 VVDD2.7 V - 10
C=30 pF, 2.7 VVDD3.6 V - 4.2
C=30 pF, 1.62 VVDD2.7 V - 7.5
C=10 pF, 2.7 VVDD3.6 V - 2.8
C=10 pF, 1.62 VVDD2.7 V - 5.2
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Fmax(3) Maximum frequency
C=50 pF, 2.7 VVDD3.6 V(5) -85
MHz
C=50 pF, 1.62 VVDD2.7 V(5) -35
C=30 pF, 2.7 VVDD3.6 V(5) -110
C=30 pF, 1.62 VVDD2.7 V(5) -40
C=10 pF, 2.7 VVDD3.6 V(5) - 166
C=10 pF, 1.62 VVDD2.7 V(5) - 100
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 2.7 VVDD3.6 V(5) -3.8
ns
C=50 pF, 1.62 VVDD2.7 V(5) -6.9
C=30 pF, 2.7 VVDD3.6 V(5) -2.8
C=30 pF, 1.62 VVDD2.7 V(5) -5.2
C=10 pF, 2.7 VVDD3.6 V(5) -1.8
C=10 pF, 1.62 VVDD2.7 Vv-3.3
11
Fmax(3) Maximum frequency
C=50 pF, 2.7 VVDD3.6 Vv- 100
MHz
C=50 pF, 1.62 VVDD2.7 V(5) -50
C=30 pF, 2.7 VVDD3.6 Vv- 133
C=30 pF, 1.62 VVDD2.7 V(5) -66
C=10 pF, 2.7 VVDD3.6 V(5) - 220
C=10 pF, 1.62 VVDD2.7 V(5) -85
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 2.7 VVDD3.6 V(5) -3.3
ns
C=50 pF, 1.62 VVDD2.7 V(5) -6.6
C=30 pF, 2.7 VVDD3.6 V(5) -2.4
C=30 pF, 1.62 VVDD2.7 V(5) -4.5
C=10 pF, 2.7 VVDD3.6 V(5) -1.5
C=10 pF, 1.62 VVDD2.7 V(5) -2.7
1. Guaranteed by design.
2. The frequency of the GPIOs that can be supplied in VBAT mode (PC13, PC14, PC15 and PI8) is limited to 2 MHz
3. The maximum frequency is defined with the following conditions:
(tr+tf) 2/3 T
Skew 1/20 T
45%<Duty cycle<55%
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
5. Compensation system enabled.
Table 160. Output timing characteristics (HSLV OFF)(1)(2) (continued)
Speed Symbol Parameter conditions Min Max Unit
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Output buffer timing characteristics (HSLV option enabled)
Table 161. Output timing characteristics (HSLV ON)(1)
Speed Symbol Parameter conditions Min Max Unit
00
Fmax(2) Maximum frequency
C=50 pF, 1.62 VVDD2.7 V - 10
MHzC=30 pF, 1.62 VVDD2.7 V - 10
C=10 pF, 1.62 VVDD2.7 V - 10
tr/tf(3)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 1.62 VVDD2.7 V - 11
nsC=30 pF, 1.62 VVDD2.7 V - 9
C=10 pF, 1.62 VVDD2.7 V - 6.6
01
Fmax(2) Maximum frequency
C=50 pF, 1.62 VVDD2.7 V - 50
MHzC=30 pF, 1.62 VVDD2.7 V - 58
C=10 pF, 1.62 VVDD2.7 V - 66
tr/tf(3)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 1.62 VVDD2.7 V - 6.6
nsC=30 pF, 1.62 VVDD2.7 V - 4.8
C=10 pF, 1.62 VVDD2.7 V - 3
10
Fmax(2) Maximum frequency
C=50 pF, 1.62 VVDD2.7 V(4) -55
MHzC=30 pF, 1.62 VVDD2.7 V(4) -80
C=10 pF, 1.62 VVDD2.7 V(4) - 133
tr/tf(3)
Output high to low level
fall time and output low
to high level rise time
C=30 pF, 1.62 VVDD2.7 V(4) -5.8
nsC=30 pF, 1.62 VVDD2.7 V(4) -4
C=30 pF, 1.62 VVDD2.7 V(4) -2.4
11
Fmax(2) Maximum frequency
C=30 pF, 1.62 VVDD2.7 V(4) -60
MHzC=30 pF, 1.62 VVDD2.7 V(4) -90
C=30 pF, 1.62 VVDD2.7 V(4) - 175
tr/tf(3)
Output high to low level
fall time and output low
to high level rise time
C=30 pF, 1.62 VVDD2.7 V(4) -5.3
nsC=30 pF, 1.62 VVDD2.7 V(4) -3.6
C=30 pF, 1.62 VVDD2.7 V(4) -1.9
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions:
(tr+tf) 2/3 T
Skew 1/20 T
45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.
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7.3.16 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 157: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 162 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 122: General operating conditions.
Figure 76. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 157. Otherwise the reset is not taken into account by the device.
7.3.17 FMC characteristics
Unless otherwise specified, the parameters given in Table 163 to Table 176 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 122: General operating conditions,
with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Measurement points are done at CMOS levels: 0.5VDD
•IO Compensation cell activated.
•HSLV activated when VDD 2.7 V
•VOS level set to VOS1.
Table 162. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
RPU(2) Weak pull-up equivalent
resistor(1)
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
VIN = VSS 30 40 50 ㏀
VF(NRST)(2)
2. Guaranteed by design.
NRST Input filtered pulse 1.71 V < VDD < 3.6 V - - 50
ns
VNF(NRST)(2) NRST Input not filtered pulse
1.71 V < VDD < 3.6 V 300 - -
1.62 V < VDD < 3.6 V 1000 - -
ai14132d
STM32
RPU
NRST
(2)
VDD
Filter
Internal Reset
0.1 μF
External
reset circuit (1)
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Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
Asynchronous waveforms and timings
Figure 77 through Figure 79 represent asynchronous waveforms and Table 163 through
Table 170 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•AddressSetupTime = 0x1
•AddressHoldTime = 0x1
•DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
•BusTurnAroundDuration = 0x0
•Capacitive load CL = 30 pF
In all timing tables, the TKERCK is the fmc_ker_ck clock period.
Figure 77. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Data
FMC_NE
FMC_NBL[1:0]
FMC_D[15:0]
t
v(BL_NE)
th(Data_NE)
FMC_NOE
Address
FMC_A[25:0]
t
v(A_NE)
FMC_NWE
tsu(Data_NE)
tw(NE)
MS32753V1
w(NOE)
ttv(NOE_NE) th(NE_NOE)
th(Data_NOE)
th(A_NOE)
th(BL_NOE)
tsu(Data_NOE)
FMC_NADV (1)
tv(NADV_NE)
tw(NADV)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
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Table 163. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3Tfmc_ker_ck–1 3Tfmc_ker_ck+1
ns
tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5
tw(NOE) FMC_NOE low time 2Tfmc_ker_ck –1 2Tfmc_ker_ck+1
th(NE_NOE)
FMC_NOE high to FMC_NE high
hold time 0-
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
th(A_NOE)
Address hold time after
FMC_NOE high 0-
tsu(Data_NE)
Data to FMC_NEx high setup
time 11 -
tsu(Data_NOE)
Data to FMC_NOEx high setup
time 11 -
th(Data_NOE)
Data hold time after FMC_NOE
high 0-
th(Data_NE)
Data hold time after FMC_NEx
high 0-
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - Tfmc_ker_ck+1
Table 164. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT
timings(1)(2)
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 7Tfmc_ker_ck+1 7Tfmc_ker_ck+1
ns
tw(NOE) FMC_NOE low time 5Tfmc_ker_ck–1 5Tfmc_ker_ck +1
tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck– 0.5 -
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx
high 4Tfmc_ker_ck +11 -
th(NE_NWAIT)
FMC_NEx hold time after
FMC_NWAIT invalid 3Tfmc_ker_ck+11.5 -
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Figure 78. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
NBL
Data
FMC_NEx
FMC_NBL[1:0]
FMC_D[15:0]
t
v(BL_NE)
th(Data_NWE)
FMC_NOE
Address
FMC_A[25:0]
t
v(A_NE)
tw(NWE)
FMC_NWE
tv(NWE_NE) th(NE_NWE)
th(A_NWE)
th(BL_NWE)
tv(Data_NE)
tw(NE)
MS32754V1
FMC_NADV (1)
tv(NADV_NE)
tw(NADV)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
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Table 165. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3Tfmc_ker_ck –1 3Tfmc_ker_ck
ns
tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck Tfmc_ker_ck+1
tw(NWE) FMC_NWE low time Tfmc_ker_ck –0.5 Tfmc_ker_ck+0.5
th(NE_NWE)
FMC_NWE high to FMC_NE high
hold time Tfmc_ker_ck -
tv(A_NE) FMC_NEx low to FMC_A valid - 2
th(A_NWE)
Address hold time after FMC_NWE
high Tfmc_ker_ck –0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
th(BL_NWE)
FMC_BL hold time after FMC_NWE
high Tfmc_ker_ck –0.5 -
tv(Data_NE) Data to FMC_NEx low to Data valid - Tfmc_ker_ck+ 2.5
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck+0.5 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - Tfmc_ker_ck+ 1
Table 166. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT
timings(1)(2)
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 8Tfmc_ker_ck –1 8Tfmc_ker_ck+1
ns
tw(NWE) FMC_NWE low time 6Tfmc_ker_ck –1.5 6Tfmc_ker_ck+0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx
high 5Tfmc_ker_ck+13 -
th(NE_NWAIT)
FMC_NEx hold time after
FMC_NWAIT invalid 4Tfmc_ker_ck+13 -
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Figure 79. Asynchronous multiplexed PSRAM/NOR read waveforms
NBL
Data
FMC_ NBL[1:0]
FMC_ AD[15:0]
t
v(BL_NE)
th(Data_NE)
Address
FMC_ A[25:16]
t
v(A_NE)
FMC_NWE
tv(A_NE)
MS32755V1
Address
FMC_NADV
tv(NADV_NE)
tw(NADV)
tsu(Data_NE)
t
h(AD_NADV)
FMC_ NE
FMC_NOE
tw(NE)
tw(NOE)
tv(NOE_NE) th(NE_NOE)
th(A_NOE)
th(BL_NOE)
tsu(Data_NOE) th(Data_NOE)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
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Table 167. Asynchronous multiplexed PSRAM/NOR read timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 4Tfmc_ker_ck –1 4Tfmc_ker_ck +1
ns
tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Tfmc_ker_ck
2Tfmc_ker_ck
+0.5
ttw(NOE) FMC_NOE low time Tfmc_ker_ck –1 Tfmc_ker_ck +1
th(NE_NOE)
FMC_NOE high to FMC_NE high hold
time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time Tfmc_ker_ck –0.5 Tfmc_ker_ck +1
th(AD_NADV)
FMC_AD(address) valid hold time
after FMC_NADV high) Tfmc_ker_ck +0.5 -
th(A_NOE)
Address hold time after FMC_NOE
high Tfmc_ker_ck –0.5 -
tsu(Data_NE) Data to FMC_NEx high setup time 11 -
tsu(Data_NOE) Data to FMC_NOE high setup time 11 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
Table 168. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2)
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 8Tfmc_ker_ck –1 8Tfmc_ker_ck
ns
tw(NOE) FMC_NWE low time 5Tfmc_ker_ck –1.5 5Tfmc_ker_ck +0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before
FMC_NEx high 4Tfmc_ker_ck +11 -
th(NE_NWAIT)
FMC_NEx hold time after
FMC_NWAIT invalid 3Tfmc_ker_ck +11.5 -
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Synchronous waveforms and timings
Figure 80 through Figure 83 represent synchronous waveforms and Table 171 through
Table 174 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•BurstAccessMode = FMC_BurstAccessMode_Enable
•MemoryType = FMC_MemoryType_CRAM
•WriteBurst = FMC_WriteBurst_Enable
•CLKDivision = 1
•DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Table 169. Asynchronous multiplexed PSRAM/NOR write timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 4Tfmc_ker_ck –1 4Tfmc_ker_ck
ns
tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck –1 Tfmc_ker_ck +0.5
tw(NWE) FMC_NWE low time 2Tfmc_ker_ck –0.5 2Tfmc_ker_ck +0.5
th(NE_NWE)
FMC_NWE high to FMC_NE high hold
time Tfmc_ker_ck –0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time Tfmc_ker_ck Tfmc_ker_ck + 1
th(AD_NADV)
FMC_AD(adress) valid hold time after
FMC_NADV high) Tfmc_ker_ck +0.5 -
th(A_NWE)
Address hold time after FMC_NWE
high Tfmc_ker_ck +0.5 -
th(BL_NWE)
FMC_BL hold time after FMC_NWE
high Tfmc_ker_ck – 0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tv(Data_NADV) FMC_NADV high to Data valid - Tfmc_ker_ck +2
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck +0.5 -
Table 170. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 9Tfmc_ker_ck –1 9Tfmc_ker_ck
ns
tw(NWE) FMC_NWE low time 7Tfmc_ker_ck –0.5 7Tfmc_ker_ck +0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx
high 5Tfmc_ker_ck +11 -
th(NE_NWAIT)
FMC_NEx hold time after
FMC_NWAIT invalid 4Tfmc_ker_ck +11.5 -
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In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_CLK maximum values:
•For 2.7 V<VDD<3.6 V, FMC_CLK = 125 MHz at 20 pF
•For 1.8 V<VDD<1.9 V, FMC_CLK = 100 MHz at 20 pF
•For 1.62 V<VDD<1.8 V, FMC_CLK = 100 MHz at 15 pF
Figure 80. Synchronous multiplexed NOR/PSRAM read timings
FMC_CLK
FMC_NEx
FMC_NADV
FMC_A[25:16]
FMC_NOE
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-AV)
td(CLKL-NADVH)
td(CLKH-AIV)
td(CLKL-NOEL) td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
tsu(ADV-CLKH)
th(CLKH-ADV)
tsu(ADV-CLKH) th(CLKH-ADV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32757V1
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Table 171. Synchronous multiplexed NOR/PSRAM read timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2Tfmc_ker_ck –1 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck+0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2.5
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x=16…25) Tfmc_ker_ck -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck –0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
tsu(ADV-CLKH)
FMC_A/D[15:0] valid data before FMC_CLK
high 2 -
th(CLKH-ADV)
FMC_A/D[15:0] valid data after FMC_CLK
high 1 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 -
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Figure 81. Synchronous multiplexed PSRAM write timings
FMC_CLK
FMC_NEx
FMC_NADV
FMC_A[25:16]
FMC_NWE
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-AV)
td(CLKL-NADVH)
td(CLKH-AIV)
td(CLKH-NWEH)
td(CLKL-NWEL)
td(CLKH-NBLH)
td(CLKL-ADV)
td(CLKL-ADIV) td(CLKL-Data)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32758V1
td(CLKL-Data)
FMC_NBL
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Table 172. Synchronous multiplexed PSRAM write timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period, VDD = 2.7 to 3.6 V 2Tfmc_ker_ck –1
1 -
Ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x =0..2) - 1
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high
(x = 0…2) Tfmc_ker_ck +0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid
(x =16…25) -2
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x =16…25) Tfmc_ker_ck -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck +0.5 -
td(CLKL-ADV) FMC_CLK low to to FMC_AD[15:0] valid - 2.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
td(CLKL-DATA)
FMC_A/D[15:0] valid data after FMC_CLK
low -2.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck +0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 -
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Figure 82. Synchronous non-multiplexed NOR/PSRAM read timings
FMC_CLK
FMC_NEx
FMC_A[25:0]
FMC_NOE
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-AV) td(CLKH-AIV)
td(CLKL-NOEL) td(CLKH-NOEH)
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32759V1
FMC_NADV
td(CLKL-NADVL) td(CLKL-NADVH)
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Table 173. Synchronous non-multiplexed NOR/PSRAM read timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2Tfmc_ker_ck –1 -
ns
t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high
(x= 0…2) 2Tfmc_ker_ck+0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid
(x=16…25) - 2
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x=16…25) 2Tfmc_ker_ck -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high 2Tfmc_ker_ck-0.5 -
tsu(DV-CLKH)
FMC_D[15:0] valid data before FMC_CLK
high 2 -
th(CLKH-DV)
FMC_D[15:0] valid data after FMC_CLK
high 1 -
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 -
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Figure 83. Synchronous non-multiplexed PSRAM write timings
MS32760V1
FMC_CLK
FMC_NEx
FMC_A[25:0]
FMC_NWE
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-AV) td(CLKH-AIV)
td(CLKH-NWEH)
td(CLKL-NWEL)
td(CLKL-Data)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
FMC_NADV
td(CLKL-NADVL) td(CLKL-NADVH)
td(CLKL-Data)
FMC_NBL
td(CLKH-NBLH)
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Table 174. Synchronous non-multiplexed PSRAM write timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
t(CLK) FMC_CLK period 2Tfmc_ker_ck –1 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
t(CLKH-NExH)
FMC_CLK high to FMC_NEx high
(x= 0…2) Tfmc_ker_ck+0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid
(x=16…25) - 2.
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x=16…25) Tfmc_ker_ck -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck+1 -
td(CLKL-Data)
FMC_D[15:0] valid data after FMC_CLK
low -3.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck+1 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 -
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NAND controller waveforms and timings
Figure 84 through Figure 87 represent synchronous waveforms, and Table 175 and
Table 176 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
•COM.FMC_SetupTime = 0x01
•COM.FMC_WaitSetupTime = 0x03
•COM.FMC_HoldSetupTime = 0x02
•COM.FMC_HiZSetupTime = 0x01
•ATT.FMC_SetupTime = 0x01
•ATT.FMC_WaitSetupTime = 0x03
•ATT.FMC_HoldSetupTime = 0x02
•ATT.FMC_HiZSetupTime = 0x01
•Bank = FMC_Bank_NAND
•MemoryDataWidth = FMC_MemoryDataWidth_16b
•ECC = FMC_ECC_Enable
•ECCPageSize = FMC_ECCPageSize_512Bytes
•TCLRSetupTime = 0
•TARSetupTime = 0
•Capacitive load CL = 30 pF
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Figure 84. NAND controller waveforms for read access
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
tsu(D-NOE) th(NOE-D)
MS32767V1
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(ALE-NOE) th(NOE-ALE)
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Figure 85. NAND controller waveforms for write access
Figure 86. NAND controller waveforms for common memory read access
MS32768V1
th(NWE-D)
tv(NWE-D)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(ALE-NWE) th(NWE-ALE)
MS32769V1
FMC_NWE
FMC_NOE
FMC_D[15:0]
tw(NOE)
tsu(D-NOE) th(NOE-D)
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(ALE-NOE) th(NOE-ALE)
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Figure 87. NAND controller waveforms for common memory write access
Table 175. Switching characteristics for NAND Flash read cycles(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(N0E) FMC_NOE low width 4Tfmc_ker_ck – 0.5 4Tfmc_ker_ck+0.5
ns
tsu(D-NOE)
FMC_D[15-0] valid data before
FMC_NOE high 8-
th(NOE-D)
FMC_D[15-0] valid data after
FMC_NOE high 0-
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3Tfmc_ker_ck +1
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4Tfmc_ker_ck –2 -
Table 176. Switching characteristics for NAND Flash write cycles(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NWE) FMC_NWE low width 4Tfmc_ker_ck – 0.5 4Tfmc_ker_ck +0.5
ns
tv(NWE-D)
FMC_NWE low to FMC_D[15-0]
valid 0-
th(NWE-D)
FMC_NWE high to FMC_D[15-0]
invalid 2Tfmc_ker_ck – 0.5 -
td(D-NWE)
FMC_D[15-0] valid before
FMC_NWE high 5Tfmc_ker_ck – 1 -
td(ALE-NWE)
FMC_ALE valid before FMC_NWE
low -3T
fmc_ker_ck +0.5
th(NWE-ALE)
FMC_NWE high to FMC_ALE
invalid 2Tfmc_ker_ck – 1 -
MS32770V1
tw(NWE)
th(NWE-D)
tv(NWE-D)
FMC_NWE
FMC_N
OE
FMC_D[15:0]
td(D-NWE)
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(ALE-NOE) th(NOE-ALE)
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SDRAM waveforms and timings
In all timing tables, the TKERCK is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
•For 2.7 V<VDD<3.6 V: FMC_CLK =110 MHz at 20 pF
•For 1.8 V<VDD<1.9 V: FMC_CLK =100 MHz at 20 pF
•For 1.62 V<DD<1.8 V, FMC_CLK =100 MHz at 15 pF
Figure 88. SDRAM read access waveforms (CL = 1)
MS32751V2
Row n Col1
FMC_SDCLK
FMC_A[12:0]
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
FMC_D[31:0]
FMC_SDNE[1:0]
td(SDCLKL_AddR) td(SDCLKL_AddC)
th(SDCLKL_AddR)
th(SDCLKL_AddC)
td(SDCLKL_SNDE)
tsu(SDCLKH_Data) th(SDCLKH_Data)
Col2 Coli Coln
Data2 Datai DatanData1
th(SDCLKL_SNDE)
td(SDCLKL_NRAS)
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
th(SDCLKL_NRAS)
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Table 177. SDRAM read timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 1 2Tfmc_ker_ck
+0.5
ns
tsu(SDCLKH _Data) Data input setup time 2 -
th(SDCLKH_Data) Data input hold time 1 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL- SDNE) Chip select valid time - 1.5
th(SDCLKL_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
Table 178. LPSDR SDRAM read timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
ns
tsu(SDCLKH_Data) Data input setup time 2 -
th(SDCLKH_Data) Data input hold time 1.5 -
td(SDCLKL_Add) Address valid time - 2.5
td(SDCLKL_SDNE) Chip select valid time - 2.5
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS SDNRAS valid time - 0.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
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Figure 89. SDRAM write access waveforms
Table 179. SDRAM Write timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
ns
td(SDCLKL _Data) Data output valid time - 1
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL_SDNWE) SDNWE valid time - 1.5
th(SDCLKL_SDNWE) SDNWE hold time 0.5 -
td(SDCLKL_ SDNE) Chip select valid time - 1.5
th(SDCLKL-_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1
td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 -
MS32752V2
Row n Col1
FMC_SDCLK
FMC_A[12:0]
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
FMC_D[31:0]
FMC_SDNE[1:0]
td(SDCLKL_AddR) td(SDCLKL_AddC)
th(SDCLKL_AddR)
th(SDCLKL_AddC)
td(SDCLKL_SNDE)
td(SDCLKL_Data)
th(SDCLKL_Data)
Col2 Coli Coln
Data2 Datai DatanData1
th(SDCLKL_SNDE)
td(SDCLKL_NRAS)
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
th(SDCLKL_NRAS)
td(SDCLKL_NWE) th(SDCLKL_NWE)
FMC_NBL[3:0]
td(SDCLKL_NBL)
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7.3.18 Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 181 and Table 182 for QUADSPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 122: General operating conditions, with the
following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Measurement points are done at CMOS levels: 0.5VDD
•IO Compensation cell activated.
•HSLV activated when VDD 2.7 V
•VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
The following table summarizes the parameters measured in SDR mode.
Table 180. LPSDR SDRAM Write timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
ns
td(SDCLKL _Data) Data output valid time - 2.5
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_Add) Address valid time - 2.5
td(SDCLKL-SDNWE) SDNWE valid time - 2.5
th(SDCLKL-SDNWE) SDNWE hold time 0 -
td(SDCLKL- SDNE) Chip select valid time - 3
th(SDCLKL- SDNE) Chip select hold time 0 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5
td(SDCLKL-SDNCAS) SDNCAS hold time 0 -
Table 181. QUADSPI characteristics in SDR mode(1)
Symbol Parameter Conditions Min Typ Max Unit
Fck11/TCK
QUADSPI clock
frequency
2.7<VDD<3.6 V
CL = 20 pF --133
MHz
1.62<VDD<3.6 V
CL = 15 pF --100
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The following table summarizes the parameters measured in DDR mode.
tw(CKH) QUADSPI clock high
and low time Even
division
PRESCALER[7:0] =
n = 0,1,3,5...
TCK/2–0.5 - TCK/2
ns
tw(CKL) TCK/2 - TCK/2+0.5
ts(IN) QUADSPI clock high
and low time Odd
division
PRESCALER[7:0] =
n = 2,4,6,8...
(n/2)*TCK/(n+1)-0.5 - (n/2)*TCK/ (n+1)
th(IN) (n/2+1)*TCK/(n+1) - (n/2+1)*TCK/
(n+1)+0.5
tv(OUT) Data input setup time
-
1--
th(OUT) Data input hold time 3.5 - -
tw(CKH) Data output valid time - - 1 2
tw(CKL) Data output hold time - 0 - -
1. Guaranteed by characterization results.
Table 181. QUADSPI characteristics in SDR mode(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 182. QUADSPI characteristics in DDR mode(1)
Symbol Parameter Conditions Min Typ Max Unit
Fck11/TCK QUADSPI clock frequency
2.7<VDD<3.6 V
CL = 20 pF --100
MHz
1.62<VDD<3.6 V
CL = 15 pF --100
tw(CKH) QUADSPI clock high and
low time Even division
PRESCALER[7:0] =
n = 0,1,3,5...
TCK/2–0.5 - TCK/2
ns
tw(CKL) TCK/2 - TCK/2+0.5
tw(CKH) QUADSPI clock high and
low time Odd division
PRESCALER[7:0] =
n = 2,4,6,8...
(n/2)*TCK/
(n+1)-0.5 -(n/2)*TCK/
(n+1)
tw(CKL)
(n/2+1)*TCK/
(n+1) -(n/2+1)*TCK /
(n+1)+0.5
tsr(IN), tsf(IN) Data input setup time - 1.5 - -
thr(IN),thf(IN) Data input hold time - 3.5 - -
tvr(OUT),
tvf(OUT)
Data output valid time
DHHC=0 - 5 6
DHHC=1
PRESCALER[7:0] =
1,2…
-T
CK/4+1 TCK/4+2
thr(OUT),
thf(OUT)
Data output hold time
DHHC=0 3 - -
DHHC=1
PRESCALER[7:0]=1
,2…
TCK/4 - -
1. Guaranteed by characterization results.
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Figure 90. Quad-SPI timing diagram - SDR mode
Figure 91. Quad-SPI timing diagram - DDR mode
7.3.19 Delay block (DLYB) characteristics
Unless otherwise specified, the parameters given in Table 183 for Delay Block are derived
from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply
voltage summarized in Table 122: General operating conditions, with the following
configuration:
MSv36878V1
Data output D0 D1 D2
Clock
Data input D0 D1 D2
t(CK) tw(CKH) tw(CKL)
tr(CK) tf(CK)
ts(IN) th(IN)
tv(OUT) th(OUT)
MSv36879V1
Data output D0 D2 D4
Clock
Data input D0 D2 D4
t(CK) tw(CKH) tw(CKL)
tr(CK) tf(CK)
tsf(IN) thf(IN)
tvf(OUT) thr(OUT)
D1 D3 D5
D1 D3 D5
tvr(OUT) thf(OUT)
tsr(IN) thr(IN)
Table 183. Delay Block characteristics
Symbol Parameter Conditions Min Typ Max Unit
tinit Initial delay - 1400 2200 2400 ps
tUnit Delay - 35 40 45 -
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7.3.20 16-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 184 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 122: General operating conditions.
Table 184. ADC characteristics(1)(2)
Symbol Parameter Conditions Min Typ Max Unit
VDDA
Analog supply
voltage for ADC
ON
-1.62-3.6V
VREF+
Positive reference
voltage -1.62-V
DDA V
VREF-
Negative
reference voltage -V
SSA V
fADC
ADC clock
frequency 1.62 V VDDA 3.6 V
BOOST = 11 0.12 - 50
MHz
BOOST = 10 0.12 - 25
BOOST = 01 0.12 - 12.5
BOOST = 00 - - 6.25
fs(3)
Sampling rate for
Direct channels(4)
Resolution = 16 bits,
VDDA >2.5 V TJ = 90 °C
fADC=36 MHz SMP = 1.5 - - 3.60
MSps
Resolution = 16 bits fADC=37 MHz SMP = 2.5 - - 3.35
Resolution = 14 bits
TJ = 125 °C
fADC = 50 MHz SMP = 2.5 - - 5.00
Resolution = 12 bits fADC = 50 MHz SMP = 2.5 - - 5.50
Resolution = 10 bits fADC = 50 MHz SMP = 1.5 - - 7.10
Resolution = 8 bits fADC = 50 MHz SMP = 1.5 - - 8.30
Sampling rate for
Fast channels
Resolution = 16 bits,
VDDA >2.5 V TJ = 90 °C
fADC=32 MHz SMP = 2.5 - - 2.90
Resolution = 16 bits fADC=31 MHz SMP = 2.5 - - 2.80
Resolution = 14 bits
TJ = 125 °C
fADC = 33 MHz SMP = 2.5 - - 3.30
Resolution = 12 bits fADC = 39 MHz SMP = 2.5 - - 4.30
Resolution = 10 bits fADC = 48 MHz SMP = 2.5 - - 6.00
Resolution = 8 bits fADC = 50 MHz SMP = 2.5 - - 7.10
Sampling rate for
Slow channels
Resolution = 16 bits TJ = 90 °C
fADC = 10 MHz SMP = 1.5
--
1.00
resolution = 14 bits
TJ = 125 °C
--
resolution = 12 bits - -
resolution = 10 bits - -
resolution = 8 bits - -
tTRIG
External trigger
period Resolution = 16 bits - - 10 1/
fADC
VAIN(5) Conversion
voltage range -0-V
REF+ V
VCMIV
Common mode
input voltage -VREF/2
10%
VREF/
2
VREF/2
+ 10% V
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RAIN(6) External input
impedance
Resolution = 16 bits, TJ = 125 °C - - - - 170
Resolution = 14 bits, TJ = 125 °C - - - - 435
Resolution = 12 bits, TJ =125 °C - - - - 1150
Resolution = 10 bits, TJ = 125 °C - - - - 5650
Resolution = 8 bits, TJ = 125 °C - - - - 26500
CADC
Internal sample
and hold
capacitor
--4-pF
tADCVREG
_STUP
ADC LDO startup
time --510us
tSTAB
ADC Power-up
time LDO already started 1 - -
conver
sion
cycle
tCAL
Offset and
linearity
calibration time
- 165010 - - 1/fADC
tOFF_
CAL
Offset calibration
time -1280--1/f
ADC
tLATR
Trigger
conversion
latency regular
and injected
channels without
conversion abort
CKMODE = 00 1.5 2 2.5
1/fADC
CKMODE = 01 - - 2.5
CKMODE = 10 - - 2.5
CKMODE = 11 - - 2.25
tLATRINJ
Trigger
conversion
latency regular
injected channels
aborting a regular
conversion
CKMODE = 00 2.5 3 3.5
1/fADC
CKMODE = 01 - - 3.5
CKMODE = 10 - - 3.5
CKMODE = 11 - - 3.25
tSSampling time - 1.5 - 810.5 1/fADC
tCONV
Total conversion
time (including
sampling time)
Resolution = N bits ts + 0.5
+ N/2 --1/f
ADC
Table 184. ADC characteristics(1)(2) (continued)
Symbol Parameter Conditions Min Typ Max Unit
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IDDA_D
(ADC)
ADC consumption
on VDDA,
BOOST=11,
Differential mode
Resolution = 16 bits, fADC=25 MHz - - - 1440 -
µA
Resolution = 14 bits, fADC=30 MHz - - - 1350 -
Resolution = 12 bits, fADC=40 MHz - - - 990 -
ADC consumption
on VDDA
BOOST=10,
Differential mode
fADC=25 MHz
Resolution = 16 bits - - - 1080 -
Resolution = 14 bits - - - 810 -
Resolution = 12 bits - - - 585 -
ADC consumption
on VDDA
BOOST=01,
Differential mode
fADC=12.5 MHz
Resolution = 16 bits - - - 630 -
Resolution = 14 bits - - - 432 -
Resolution = 12 bits - - - 315 -
ADC consumption
on VDDA
BOOST=00,
Differential mode
fADC=6.25 MHz
Resolution = 16 bits - - - 360 -
Resolution = 14 bits - - - 270 -
Resolution = 12 bits - - - 225 -
IDDA_SE(
ADC)
ADC consumption
on VDDA
BOOST=11,
Single-ended
mode
Resolution = 16 bits, fADC=25 MHz - - - 720 -
Resolution = 14 bits, fADC=30 MHz - - - 675 -
Resolution = 12 bits, fADC=40 MHz - - - 495 -
ADC consumption
on VDDA
BOOST=10,
Singl-ended mode
fADC=25 MHz
Resolution = 16 bits - - - 540 -
Resolution = 14 bits - - - 405 -
Resolution = 12 bits - - - 292.5 -
ADC consumption
on VDDA
BOOST=01,
Single-ended
mode
fADC=12.5 MHz
Resolution = 16 bits - - - 315 -
Resolution = 14 bits - - - 216 -
Resolution = 12 bits - - - 157.5 -
ADC consumption
on VDDA
BOOST=00,
Single-ended
mode
fADC=6.25 MHz
Resolution = 16 bits - - - 180 -
Resolution = 14 bits - - - 135 -
Resolution = 12 bits - - - 112.5 -
IDD
(ADC)
ADC consumption
on VDD
BOOST=11
fADC=50 MHz - - - 400 -
fADC=25 MHz - - - 220 -
fADC=12.5 MHz - - - 180 -
fADC=6.25 MHz - - - 120 -
fADC=3.125 MHz - - - 80 -
1. Guaranteed by design.
2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
3. These values are valid for UFBGA169 and one ADC. The values for other packages and multiple ADCs may be different.
4. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
5. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.
6. The tolerance is 10 LSBs for 16-bit resolution, 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions.
Table 184. ADC characteristics(1)(2) (continued)
Symbol Parameter Conditions Min Typ Max Unit
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Table 185. Minimum sampling time vs RAIN(1)(2)
Resolution RAIN (Ω)
Minimum sampling time (s)
Direct
channels(3) Fast channels(4) Slow channels(5)
16 bits 47 7.37E-08 1.14E-07 1.72E-07
14 bits
47 6.29E-08 9.74E-08 1.55E-07
68 6.84E-08 1.02E-07 1.58E-07
100 7.80E-08 1.12E-07 1.62E-07
150 9.86E-08 1.32E-07 1.80E-07
220 1.32E-07 1.61E-07 2.01E-07
12 bits
47 5.32E-08 8.00E-08 1.29E-07
68 5.74E-08 8.50E-08 1.32E-07
100 6.58E-08 9.31E-08 1.40E-07
150 8.37E-08 1.10E-07 1.51E-07
220 1.11E-07 1.34E-07 1.73E-07
330 1.56E-07 1.78E-07 2.14E-07
470 2.16E-07 2.39E-07 2.68E-07
680 3.01E-07 3.29E-07 3.54E-07
10 bits
47 4.34E-08 6.51E-08 1.08E-07
68 4.68E-08 6.89E-08 1.11E-07
100 5.35E-08 7.55E-08 1.16E-07
150 6.68E-08 8.77E-08 1.26E-07
220 8.80E-08 1.08E-07 1.40E-07
330 1.24E-07 1.43E-07 1.71E-07
470 1.69E-07 1.89E-07 2.13E-07
680 2.38E-07 2.60E-07 2.80E-07
1000 3.45E-07 3.66E-07 3.84E-07
1500 5.15E-07 5.35E-07 5.48E-07
2200 7.42E-07 7.75E-07 7.78E-07
3300 1.10E-06 1.14E-06 1.14E-06
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8 bits
47 3.32E-08 5.10E-08 8.61E-08
68 3.59E-08 5.35E-08 8.83E-08
100 4.10E-08 5.83E-08 9.22E-08
150 5.06E-08 6.76E-08 9.95E-08
220 6.61E-08 8.22E-08 1.11E-07
330 9.17E-08 1.08E-07 1.32E-07
470 1.24E-07 1.40E-07 1.63E-07
680 1.74E-07 1.91E-07 2.12E-07
1000 2.53E-07 2.70E-07 2.85E-07
1500 3.73E-07 3.93E-07 4.05E-07
2200 5.39E-07 5.67E-07 5.75E-07
3300 8.02E-07 8.36E-07 8.38E-07
4700 1.13E-06 1.18E-06 1.18E-06
6800 1.62E-06 1.69E-06 1.68E-06
10000 2.36E-06 2.47E-06 2.45E-06
15000 3.50E-06 3.69E-06 3.65E-06
1. Guaranteed by design.
2. Data valid at up to 125 °C, with a 47 pF PCB capacitor, and VDDA=1.6 V.
3. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
4. Fast channels correspond to PC0, PC1, PC2, PC3, PA0, and PA1.
5. Slow channels correspond to all ADC inputs except for the Fast channels.
Table 185. Minimum sampling time vs RAIN(1)(2) (continued)
Resolution RAIN (Ω)
Minimum sampling time (s)
Direct
channels(3) Fast channels(4) Slow channels(5)
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Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 7.3.14 does not affect the ADC accuracy.
Table 186. ADC accuracy(1)(2)
Symbol Parameter Conditions(3) Min Typ Max Unit
ET Total undadjusted error
Direct
channel
Single ended - +10/–20 -
LSB
Differential - ±15 -
Fast channel
Single ended - +10/–20 -
Differential - ±15 -
Slow
channel
Single ended - ±10 -
Differential ±10 -
EO Offset error - - ±10 -
EG Gain error - - ±15 -
ED Differential linearity error
Single ended - +3/–1 -
Differential - +4.5/–1 -
EL Integral linearity error
Direct
channel
Single ended - ±11 -
Differential - ±7 -
Fast channel
Single ended - ±13 -
Differential - ±7 -
Slow
channel
Single ended - ±10 -
Differential - ±6 -
ENOB Effective number of bits
Single ended - 12.2 -
Bits
Differential - 13.2 -
SINAD Signal-to-noise and
distortion ratio
Single ended - 75.2 -
dB
Differential - 81.2 -
SNR Signal-to-noise ratio
Single ended - 77.0 -
Differential - 81.0 -
THD Total harmonic distortion
Single ended - 87 -
Differential - 90 -
1. Data guaranteed by characterization for BGA packages. The values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC clock frequency = 25 MHz, ADC resolution = 16 bits, VDDA=VREF+=3.3 V and BOOST=11.
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Figure 92. ADC accuracy characteristics (12-bit resolution)
1. Example of an actual transfer curve.
2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 93. Typical connection diagram using the ADC
1. Refer to Table 184 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
ai14395c
EO
EG
1L SBIDEAL
4095
4094
4093
5
4
3
2
1
0
7
6
1 2 3 456 7 4093 4094 4095 4096
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
VREF+
4096 (or depending on package)]
VDDA
4096
[1LSB IDEAL
=
ai17534b
STM32
VDD
AINx
IL±1 μA
0.6 V
VT
RAIN(1)
Cparasitic
VAIN
0.6 V
VT
RADC(1)
CADC(1)
12-bit
converter
Sample and hold ADC
converter
Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G
286/357 DS12110 Rev 7
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 94 or Figure 95,
depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 94. Power supply and reference decoupling (VREF+ not connected to VDDA)
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.
Figure 95. Power supply and reference decoupling (VREF+ connected to VDDA)
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.
MSv50648V1
1 μF // 100 nF
1 μF // 100 nF
STM32
VREF+(1)
VSSA/VREF+(1)
VDDA
MSv50649V1
1 μF // 100 nF
STM32
VREF+/VDDA(1)
VREF-/VSSA(1)
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7.3.21 DAC characteristics
Table 187. DAC characteristics(1)(2)
Symbol Parameter Conditions Min Typ Max Unit
VDDA Analog supply voltage - 1.8 3.3 3.6
V
VREF+ Positive reference voltage - 1.80 - VDDA
VREF-
Negative reference
voltage --V
SSA -
RLResistive Load DAC output buffer
ON
connected
to VSSA
5--
kconnected
to VDDA
25 - -
ROOutput Impedance DAC output buffer OFF 10.3 13 16
RBON
Output impedance
sample and hold mode,
output buffer ON
DAC output buffer
ON
VDD =
2.7 V --1.6
k
VDD =
2.0 V --2.6
RBOFF
Output impedance
sample and hold mode,
output buffer OFF
DAC output buffer
OFF
VDD =
2.7 V --17.8
k
VDD =
2.0 V --18.7
CLCapacitive Load
DAC output buffer OFF - - 50 pF
CSH Sample and Hold mode - 0.1 1 µF
VDAC_OUT
Voltage on DAC_OUT
output
DAC output buffer ON 0.2 - VDDA
0.2 V
DAC output buffer OFF 0 - VREF+
tSETTLING
Settling time (full scale:
for a 12-bit code transition
between the lowest and
the highest input codes
when DAC_OUT reaches
the final value of ±0.5LSB,
±1LSB, ±2LSB, ±4LSB,
±8LSB)
Normal mode, DAC
output buffer ON,
CL ≤ 50 pF,
RL 5 ㏀
±0.5 LSB - 2.05 -
µs
±1 LSB - 1.97 -
±2 LSB - 1.67 -
±4 LSB - 1.66 -
±8 LSB - 1.65 -
Normal mode, DAC output buffer
OFF, ±1LSB CL=10 pF -1.72
tWAKEUP(3)
Wakeup time from off
state (setting the ENx bit
in the DAC Control
register) until the final
value of ±1LSB is reached
Normal mode, DAC output buffer
ON, CL ≤ 50 pF, RL = 5 ㏀-57.5
µs
Normal mode, DAC output buffer
OFF, CL ≤ 10 pF 25
PSRR DC VDDA supply rejection
ratio
Normal mode, DAC output buffer
ON, CL ≤ 50 pF, RL = 5 ㏀-80 28 dB
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288/357 DS12110 Rev 7
tSAMP
Sampling time in Sample
and Hold mode
CL=100 nF
(code transition between
the lowest input code and
the highest input code
when DAC_OUT reaches
the ±1LSB final value)
MODE<2:0>_V12=100/101
(BUFFER ON) -0.72.6
ms
MODE<2:0>_V12=110
(BUFFER OFF) -11.518.7
MODE<2:0>_V12=111
(INTERNAL BUFFER OFF) -0.30.6µs
CIint
Internal sample and hold
capacitor -1.82.22.6pF
tTRIM
Middle code offset trim
time
Minimum time to verify the each
code 50 - - µs
Voffset
Middle code offset for 1
trim code step
VREF+ = 3.6 V - 850 -
µV
VREF+ = 1.8 V - 425 -
IDDA(DAC)
DAC quiescent
consumption from VDDA
DAC output buffer
ON
No load,
middle
code
(0x800)
- 360 -
µA
No load,
worst code
(0xF1C)
- 490 -
DAC output buffer
OFF
No load,
middle/wor
st code
(0x800)
-20-
Sample and Hold mode,
CSH=100 nF -
360*TON/
(TON+TOFF)
(4)
-
IDDV(DAC) DAC consumption from
VREF+
DAC output buffer
ON
No load,
middle
code
(0x800)
- 170 -
No load,
worst code
(0xF1C)
- 170 -
DAC output buffer
OFF
No load,
middle/wor
st code
(0x800)
- 160 -
Sample and Hold mode, Buffer
ON, CSH=100 nF (worst code) -
170*TON/
(TON+TOFF)
(4)
-
Sample and Hold mode, Buffer
OFF, CSH=100 nF (worst code) -
160*TON/
(TON+TOFF)
(4)
-
1. Guaranteed by design unless otherwise specified.
Table 187. DAC characteristics(1)(2) (continued)
Symbol Parameter Conditions Min Typ Max Unit
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322
2. TBD stands for “to be defined”.
3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
4. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more
details.
Table 188. DAC accuracy(1)
Symbol Parameter Conditions Min Typ Max Unit
DNL Differential non
linearity(2)
DAC output buffer ON 2- 2
LSB
DAC output buffer OFF 2- 2
- Monotonicity 10 bits - - - -
INL Integral non linearity(3)
DAC output buffer ON, CL≤50 pF,
RL≥5 ㏀4- 4
LSB
DAC output buffer OFF,
CL ≤ 50 pF, no RL
4- 4
Offset Offset error at code
0x800 (3)
DAC output
buffer ON,
CL≤50 pF,
RL ≥5 ㏀
VREF+ = 3.6 V - - ±15
LSB
VREF+ = 1.8 V - - ±30
DAC output buffer OFF,
CL ≤ 50 pF, no RL
--±8
Offset1 Offset error at code
0x001(4)
DAC output buffer OFF,
CL ≤ 50 pF, no RL
--±5LSB
OffsetCal
Offset error at code
0x800 after factory
calibration
DAC output
buffer ON,
CL≤50 pF,
RL ≥5 ㏀
VREF+ = 3.6 V - - ±6
LSB
VREF+ = 1.8 V - - ±7
Gain Gain error(5)
DAC output buffer ON,CL≤50 pF,
RL ≥5 ㏀--±1
%
DAC output buffer OFF,
CL ≤ 50 pF, no RL
--±1
SNR Signal-to-noise ratio(6)
DAC output buffer ON,CL≤50 pF,
RL ≥5 ㏀, 1 kHz, BW = 500 KHz - 67.8 -
dB
DAC output buffer OFF,
CL ≤ 50 pF, no RL,1 kHz, BW =
500 KHz
- 67.8 -
THD Total harmonic
distortion(6)
DAC output buffer ON, CL≤50 pF,
RL ≥5 ㏀, 1 kHz -78.6 -
dB
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz -78.6 -
SINAD Signal-to-noise and
distortion ratio(6)
DAC output buffer ON, CL≤50 pF,
RL ≥5 ㏀, 1 kHz - 67.5 -
dB
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz - 67.5 -
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290/357 DS12110 Rev 7
Figure 96. 12-bit buffered /non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
ENOB Effective number of
bits
DAC output buffer ON,
CL≤50 pF, RL ≥5 ㏀, 1 kHz - 10.9 -
bits
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz - 10.9 -
1. Guaranteed by characterization.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is 0.5dBFS with Fsampling=1 MHz.
Table 188. DAC accuracy(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
RL
CL
Buffered/Non-buffered DAC
DAC_OUTx
Buffer(1)
12-bit
digital to
analog
converter
ai17157V3
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7.3.22 Voltage reference buffer characteristics
Table 189. VREFBUF characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA Analog supply voltage
Normal mode
VSCALE = 000 2.8 3.3 3.6
V
VSCALE = 001 2.4 - 3.6
VSCALE = 010 2.1 - 3.6
VSCALE = 011 1.8 - 3.6
Degraded mode
VSCALE = 000 1.62 - 2.80
VSCALE = 001 1.62 - 2.40
VSCALE = 010 1.62 - 2.10
VSCALE = 011 1.62 - 1.80
VREFBUF
_OUT
Voltage Reference
Buffer Output, at 30 °C,
Iload= 100 µA
Normal mode
VSCALE = 000 2.498 2.5 2.5035
VSCALE = 001 2.046 2.049 2.052
VSCALE = 010 1.801 1.804 1.806
VSCALE = 011 1.4995 1.5015 1.504
Degraded mode(2)
VSCALE = 000 VDDA
150 mV -V
DDA
VSCALE = 001 VDDA
150 mV -V
DDA
VSCALE = 010 VDDA
150 mV -V
DDA
VSCALE = 011 VDDA
150 mV -V
DDA
TRIM Trim step resolution - - - ±0.05 ±0.1 %
CLLoad capacitor - - 0.5 1 1.50 uF
esr Equivalent Serial
Resistor of CL
----2
Ω
Iload Static load current - - - - 4 mA
Iline_reg Line regulation 2.8 V VDDA 3.6 V
Iload = 500 µA - 200 -
ppm/V
Iload = 4 mA - 100 -
Iload_reg Load regulation 500 µA ILOAD 4 mA Normal Mode - 50 - ppm/
mA
Tcoeff Temperature coefficient 40 °C < TJ < +125 °C - -
Tcoeff
VREFINT
+ 100
ppm/
°C
PSRR Power supply rejection
DC - - 60 -
dB
100KHz - - 40 -
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7.3.23 Temperature sensor characteristics
tSTART Start-up time
CL=0.5 µF - - 300 -
µsCL=1 µF - - 500 -
CL=1.5 µF - - 650 -
IINRUSH
Control of maximum
DC current drive on
VREFBUF_OUT during
startup phase(3)
--8-mA
IDDA(VRE
FBUF)
VREFBUF
consumption from
VDDA
ILOAD = 0 µA - - 15 25
µAILOAD = 500 µA - - 16 30
ILOAD = 4 mA - - 32 50
1. Guaranteed by design.
2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDAdrop voltage).
3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.
Table 189. VREFBUF characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 190. Temperature sensor characteristics
Symbol Parameter Min Typ Max Unit
TL(1)
1. Guaranteed by design.
VSENSE linearity with temperature - - 3 °C
Avg_Slope(2)
2. Guaranteed by characterization.
Average slope - 2 - mV/°C
V30(3)
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1
byte.
Voltage at 30°C ± 5 °C - 0.62 - V
tstart_run Startup time in Run mode (buffer startup) - - 25.2
µs
tS_temp(1) ADC sampling time when reading the temperature 9 - -
Isens(1) Sensor consumption - 0.18 0.31
µA
Isensbuf(1) Sensor buffer consumption - 3.8 6.5
Table 191. Temperature sensor calibration values
Symbol Parameter Memory address
TS_CAL1 Temperature sensor raw data acquired value at
30 °C, VDDA=3.3 V 0x1FF1 E820 -0x1FF1 E821
TS_CAL2 Temperature sensor raw data acquired value at
110 °C, VDDA=3.3 V 0x1FF1 E840 - 0x1FF1 E841
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322
7.3.24 Temperature and VBAT monitoring
7.3.25 Voltage booster for analog switch
Table 192. VBAT monitoring characteristics
Symbol Parameter Min Typ Max Unit
R Resistor bridge for VBAT -26-K
QRatio on VBAT measurement - 4 - -
Er(1)
1. Guaranteed by design.
Error on Q –10 - +10 %
tS_vbat(1) ADC sampling time when reading VBAT input 9 - - µs
VBAThigh High supply monitoring - 3.55 -
V
VBATlow Low supply monitoring - 1.36 -
Table 193. VBAT charging characteristics
Symbol Parameter Condition Min Typ Max Unit
RBC Battery charging resistor
VBRS in PWR_CR3= 0 - 5 -
K
VBRS in PWR_CR3= 1 1.5 -
Table 194. Temperature monitoring characteristics
Symbol Parameter Min Typ Max Unit
TEMPhigh High temperature monitoring - 117 -
°C
TEMPlow Low temperature monitoring - –25 -
Table 195. Voltage booster for analog switch characteristics(1)
1. Guaranteed by characterization results.
Symbol Parameter Condition Min Typ Max Unit
VDD Supply voltage - 1.62 2.6 3.6 V
tSU(BOOST) Booster startup time - - - 50 µs
IDD(BOOST) Booster consumption
1.62 V VDD 2.7 V - - 125
µA
2.7 V < VDD < 3.6 V - - 250
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294/357 DS12110 Rev 7
7.3.26 Comparator characteristics
Table 196. COMP characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDDA Analog supply voltage - 1.62 3.3 3.6
VVIN
Comparator input voltage
range -0-V
DDA
VBG Scaler input voltage - (2)
VSC Scaler offset voltage - - ±5 ±10 mV
IDDA(SCALER)
Scaler static consumption
from VDDA
BRG_EN=0 (bridge disable) - 0.2 0.3
µA
BRG_EN=1 (bridge enable) - 0.8 1
tSTART_SCALER Scaler startup time - - 140 250 µs
tSTART
Comparator startup time to
reach propagation delay
specification
High-speed mode - 2 5
µsMedium mode - 5 20
Ultra-low-power mode - 15 80
tD(3)
Propagation delay for
200 mV step with 100 mV
overdrive
High-speed mode - 50 80 ns
Medium mode - 0.5 1.2
µs
Ultra-low-power mode - 2.5 7
Propagation delay for step
> 200 mV with 100 mV
overdrive only on positive
inputs
High-speed mode - 50 120 ns
Medium mode - 0.5 1.2
µs
Ultra-low-power mode - 2.5 7
Voffset Comparator offset error Full common mode range - ±5 ±20 mV
Vhys Comparator hysteresis
No hysteresis - 0 -
mV
Low hysteresis 5 10 22
Medium hysteresis 8 20 37
High hysteresis 16 30 52
IDDA(COMP) Comparator consumption
from VDDA
Ultra-low-
power mode
Static - 400 600
nA
With 50 kHz
±100 mV overdrive
square signal
- 800 -
Medium mode
Static - 5 7
µA
With 50 kHz
±100 mV overdrive
square signal
-6-
High-speed
mode
Static - 70 100
With 50 kHz
±100 mV overdrive
square signal
-75-
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 127: Embedded reference voltage.
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322
7.3.27 Operational amplifier characteristics
3. Guaranteed by characterization results.
Table 197. Operational amplifier characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDA
Analog supply voltage
Range -23.33.6
V
CMIR Common Mode Input
Range -0-V
DDA
VIOFFSET Input offset voltage
25°C, no load on output - - ±1.5
mV
All voltages and
temperature, no load --±2.5
ΔVIOFFSET Input offset voltage drift - - ±3.0 - V/°C
TRIMOFFSETP
TRIMLPOFFSETP
Offset trim step at low
common input voltage
(0.1*VDDA)
--1.11.5
mV
TRIMOFFSETN
TRIMLPOFFSETN
Offset trim step at high
common input voltage
(0.9*VDDA)
--1.11.5
ILOAD Drive current - - - 500 A
ILOAD_PGA Drive current in PGA mode - - - 270
CLOAD Capacitive load - - - 50 pF
CMRR Common mode rejection
ratio --80-dB
PSRR Power supply rejection
ratio
CLOAD 50pf /
RLOAD 4 k(1) at 1 kHz,
Vcom=VDDA/2
50 66 - dB
GBW Gain bandwidth for high
supply range
200 mV Output dynamic
range VDDA - 200 mV 47.312.3MHz
SR Slew rate (from 10% and
90% of output voltage)
Normal mode - 3 -
V/µs
High-speed mode - 30 -
AO Open loop gain 200 mV Output dynamic
range VDDA - 200 mV 59 90 129 dB
φm Phase margin - - 55 - °
GM Gain margin - - 12 - dB
VOHSAT High saturation voltage Iload=max or RLOAD=min,
Input at VDDA
VDDA
100 mV - -
mV
VOLSAT Low saturation voltage Iload=max or RLOAD=min,
Input at 0 V - - 100
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tWAKEUP
Wake up time from OFF
state
Normal
mode
CLOAD 50pf,
RLOAD 4 k,
follower
configuration
-0.83.2
µs
High
speed
mode
CLOAD 50pf,
RLOAD 4 k,
follower
configuration
-0.92.8
PGA gain
Non inverting gain error
value
PGA gain = 2 1-1
%
PGA gain = 4 2-2
PGA gain = 8 2.5 - 2.5
PGA gain = 16 3-3
Inverting gain error value
PGA gain = 2 1-1
PGA gain = 4 1-1
PGA gain = 8 2-2
PGA gain = 16 3-3
External non-inverting gain
error value
PGA gain = 2 1-1
PGA gain = 4 3-3
PGA gain = 8 3.5 - 3.5
PGA gain = 16 4-4
Rnetwork
R2/R1 internal resistance
values in non-inverting
PGA mode(2)
PGA Gain=2 - 10/10 -
k/
k
PGA Gain=4 - 30/10 -
PGA Gain=8 - 70/10 -
PGA Gain=16 - 150/10 -
R2/R1 internal resistance
values in inverting PGA
mode(2)
PGA Gain = -1 - 10/10 -
PGA Gain = -3 - 30/10 -
PGA Gain = -7 - 70/10 -
PGA Gain = -15 - 150/10 -
Delta R Resistance variation (R1
or R2) -15 - 15 %
Table 197. Operational amplifier characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
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7.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 198 for DFSDM are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 122: General operating conditions.
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load CL = 30 pF
•Measurement points are done at CMOS levels: 0.5VDD
•VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (DìFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM).
PGA BW
PGA bandwidth for
different non inverting gain
Gain=2 - GBW/2 -
MHz
Gain=4 - GBW/4 -
Gain=8 - GBW/8 -
Gain=16 - GBW/16 -
PGA bandwidth for
different inverting gain
Gain = -1 - 5.00 -
MHz
Gain = -3 - 3.00 -
Gain = -7 - 1.50 -
Gain = -15 - 0.80 -
en Voltage noise density
at
1 KHz output loaded
with 4 k
-140-
nV/
Hz
at
10 KHz -55-
IDDA(OPAMP)
OPAMP consumption from
VDDA
Normal
mode no Load,
quiescent mode,
follower
- 570 1000
µA
High-
speed
mode
- 610 1200
1. RLOAD is the resistive load connected to VSSA or to VDDA.
2. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
Table 197. Operational amplifier characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
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Table 198. DFSDM measured timing 1.62-3.6 V
Symbol Parameter Conditions Min Typ Max Unit
fDFSDMCLK
DFSDM
clock 1.62 < VDD < 3.6 V - - 133
MH
z
fCKIN
(1/TCKIN)
Input clock
frequency
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
--20
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
2.7 < VDD < 3.6 V
--20
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]¹0),
1.62 < VDD < 3.6 V
--20
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]¹0),
2.7 < VDD < 3.6 V
--20
fCKOUT
Output clock
frequency 1.62 < VDD < 3.6 V - - 20
DuCyCKOU
T
Output clock
frequency
duty cycle
1.62 < VDD < 3.6 V 45 50 55 %
twh(CKIN)
twl(CKIN)
Input clock
high and low
time
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
TCKIN/2-0.5 TCKIN/2 -
ns
tsu
Data input
setup time
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
1.5 - -
th
Data input
hold time
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
0.5 - -
TManchester
Manchester
data period
(recovered
clock period)
Manchester mode (SITP[1:0]=2,3),
Internal clock mode
(SPICKSEL[1:0]¹0),
1.62 < VDD < 3.6 V
(CKOUTDIV+1)
* TDFSDMCLK
-(2*CKOUTDIV)
* TDFSDMCLK
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Figure 97. Channel transceiver timing diagrams
MS30766V2
SITP = 0
DFSDM_CKOUT
DFSDM_DATINy
SITP = 1
tsu th
tsu th
tftr
twl twh
SPI timing : SPICKSEL = 1, 2, 3
recovered clock
SITP = 2
DFSDM_DATINy
SITP = 3
Manchester timing
recovered data
11000
SITP = 00
DFSDM_CKINyDFSDM_DATINy
SITP = 01
tsu th
tsu th
tftr
twl twh
SPI timing : SPICKSEL = 0
SPICKSEL=2
SPICKSEL=1
(SPICKSEL=0)
SPICKSEL=3
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7.3.29 Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 199 for DCMI are derived from
tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 122: General operating conditions, with the following configuration:
•DCMI_PIXCLK polarity: falling
•DCMI_VSYNC and DCMI_HSYNC polarity: high
•Data formats: 14 bits
•Capacitive load CL=30 pF
•Measurement points are done at CMOS levels: 0.5VDD
•VOS level set to VOS1
Figure 98. DCMI timing diagram
Table 199. DCMI characteristics(1)
Symbol Parameter Min Max Unit
- Frequency ratio DCMI_PIXCLK/fHCLK -0.4 -
DCMI_PIXCLK Pixel Clock input - 80 MHz
Dpixel Pixel Clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 3 -
-
th(DATA) Data hold time 1 -
tsu(HSYNC),
tsu(VSYNC) DCMI_HSYNC/ DCMI_VSYNC input setup time 2 - ns
th(HSYNC),
th(VSYNC) DCMI_HSYNC/ DCMI_VSYNC input hold time 1 - -
1. Guaranteed by characterization results.
MS32414V2
DCMI_PIXCLK
tsu(VSYNC)
tsu(HSYNC)
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
1/DCMI_PIXCLK
th(HSYNC)
th(HSYNC)
tsu(DATA) th(DATA)
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7.3.30 LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 200 for LCD-TFT are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 122: General operating conditions, with the following
configuration:
•LCD_CLK polarity: high
•LCD_DE polarity: low
•LCD_VSYNC and LCD_HSYNC polarity: high
•Pixel formats: 24 bits
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load CL=30 pF
•Measurement points are done at CMOS levels: 0.5VDD
•IO Compensation cell activated.
•HSLV activated when VDD 2.7 V
•VOS level set to VOS1
Table 200. LTDC characteristics(1)
Symbol Parameter Min Max Unit
fCLK
LTDC clock
output
frequency
2.7<VDD<3.6 V
20pF
-
150
MHz
2.7<VDD<3.6 V 133
1.62<VDD<3.6 V 90
DCLK LTDC clock output duty cycle 45 55 %
tw(CLKH),
tw(CLKL)
Clock High time, low time tw(CLK)//2-0.5 tw(CLK)//2+0.5
-
tv(DATA) Data output valid time
2.7<VDD<3.6 V
-
0.5
th(DATA) 1.62<VDD<3.6 V 5
tv(DATA) Data output hold time 0 -
tv(HSYNC),
tv(VSYNC),
tv(DE)
HSYNC/VSYNC/DE output
valid time
2.7<VDD<3.6 V - 0.5
1.62<VDD<3.6 V - 5
th(HSYNC),
th(VSYNC),
th(DE)
HSYNC/VSYNC/DE output hold time 0 -
1. Guaranteed by characterization results.
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Figure 99. LCD-TFT horizontal timing diagram
Figure 100. LCD-TFT vertical timing diagram
MS32749V1
LCD_CLK
tv(HSYNC)
LCD_HSYNC
LCD_DE
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
tCLK
LCD_VSYNC
tv(HSYNC)
tv(DE) th(DE)
Pixel
1
Pixel
2
tv(DATA)
th(DATA)
Pixel
N
HSYNC
width
Horizontal
back porch
Active width Horizontal
back porch
One line
MS32750V1
LCD_CLK
tv(VSYNC)
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
tCLK
LCD_VSYNC
tv(VSYNC)
M lines data
VSYNC
width
Vertical
back porch
Active width Vertical
back porch
One frame
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7.3.31 Timer characteristics
The parameters given in Table 201 are guaranteed by design.
Refer to Section 7.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
7.3.32 Communication interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0399 reference manual) and when the i2c_ker_ck frequency is
greater than the minimum shown in the table below:
Table 201. TIMx characteristics(1)(2)
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Guaranteed by design.
Symbol Parameter Conditions(3)
3. The maximum timer frequency on APB1 or APB2 is up to 240 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
Frcc_pclkx_d2.
Min Max Unit
tres(TIM) Timer resolution time
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK =
240 MHz
1-
tTIMxCLK
AHB/APBx
prescaler>4, fTIMxCLK =
120 MHz
1-
tTIMxCLK
fEXT Timer external clock
frequency on CH1 to CH4 fTIMxCLK = 240 MHz
0fTIMxCLK/2 MHz
ResTIM Timer resolution - 16/32 bit
tMAX_COUNT Maximum possible count
with 32-bit counter --
65536 ×
65536 tTIMxCLK
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The SDA and SCL I/O requirements are met with the following restrictions:
•The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDDIOx is disabled, but still present.
•The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load CLoad supported in Fm+, which is given by these formulas:
tr(SDA/SCL)=0.8473xRPxCLoad
RP(min)= (VDD-VOL(max))/IOL(max)
Where RP is the I2C lines pull-up. Refer to Section 7.3.15: I/O port characteristics
for
the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog fil-
ter characteristics:
USART interface characteristics
Unless otherwise specified, the parameters given in Table 204 for USART are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 122: General operating conditions, with the following
configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load CL = 30 pF
•Measurement points are done at CMOS levels: 0.5VDD
•IO Compensation cell activated.
•VOS level set to VOS1
Table 202. Minimum i2c_ker_ck frequency in all I2C modes
Symbol Parameter Condition Min Unit
f(I2CCLK) I2CCLK
frequency
Standard-mode - 2
MHz
Fast-mode
Analog Filtre ON
DNF=0 8
Analog Filtre OFF
DNF=1 9
Fast-mode Plus
Analog Filtre ON
DNF=0 17
Analog Filtre OFF
DNF=1 16 -
Table 203. I2C analog filter characteristics(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tAF
Maximum pulse width of spikes
that are suppressed by analog
filter
50(2)
2. Spikes with widths below tAF(min) are filtered.
80(3)
3. Spikes with widths above tAF(max) are not filtered.
ns
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Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).
Table 204. USART characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fCK USART clock frequency
Master mode
--
12.5
MHz
Slave mode 25
tsu(NSS) NSS setup time Slave mode tker+1 - -
-
th(NSS) NSS hold time Slave mode 2 - -
tw(SCKH),
tw(SCKL)
CK high and low time Master mode 1/fCK/2-2 1/fCK/2 1/fCK/2+2
tsu(RX) Data input setup time
Master mode tker+6 - -
ns
Slave mode 1.5 - -
th(RX) Data input hold time
Master mode 0 - -
Slave mode 1.5 - -
tv(TX) Data output valid time
Slave mode - 12 20
Master mode - 0.5 1
th(TX) Data output hold time
Slave mode 9 - -
Master mode 0 - -
1. Guaranteed by characterization results.
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Figure 101. USART timing diagram in Master mode
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Figure 102. USART timing diagram in Slave mode
ai14136c
SCK Output
CPHA= 0
MOSI
OUTPUT
MISO
INP UT
CPHA= 0
LSB OUT
LSB IN
CPOL=0
CPOL=1
B I T1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
High
SCK Output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
MSB IN BIT6 IN
MSB OUT
MSv41658V1
NSS input
CPHA=0
CPOL=0
SCK input
CPHA=0
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tc(SCK)
tr(SCK)
th(NSS)
tdis(SO)
tsu(NSS)
ta(SO) tv(SO)
Next bits IN
Last bit OUT
First bit IN
First bit OUT Next bits OUT
th(SO) tf(SCK)
Last bit IN
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SPI interface characteristics
Unless otherwise specified, the parameters given in Table 205 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 122: General operating conditions, with the following
configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load CL = 30 pF
•Measurement points are done at CMOS levels: 0.5VDD
•IO Compensation cell activated.
•HSLV activated when VDD 2.7 V
•VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 205. SPI characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fSCK SPI clock frequency
Master mode
1.62<VDD<3.6 V
SPI1, 2, 3
--
80
MHz
Master mode
2.7<VDD<3.6 V
SPI1, 2, 3
100
Master mode
1.62<VDD<3.6 V
SPI4, 5, 6
50
Slave receiver mode
1.62<VDD<3.6 V 100
Slave mode transmitter/full duplex
2.7<VDD<3.6 V 31
Slave mode transmitter/full duplex
1.62 <VDD<3.6 V 29
tsu(NSS) NSS setup time Slave mode 2 - -
-
th(NSS) NSS hold time Slave mode 1 - -
tw(SCKH),
tw(SCKL)
SCK high and low time Master mode TPCLK-2 TPCLK TPCLK+2
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Figure 103. SPI timing diagram - slave mode and CPHA = 0
tsu(MI) Data input setup time
Master mode 1 - -
ns
tsu(SI) Slave mode 1 - -
th(MI) Data input hold time
Master mode 4 - -
th(SI) Slave mode 2 - -
ta(SO) Data output access time Slave mode 9 13 27
tdis(SO) Data output disable time Slave mode 0 1 5
tv(SO) Data output valid time
Slave mode
2.7<VDD<3.6 V -12.516
Slave mode
1.62<VDD<3.6 V -12.517
tv(MO) Master mode - 1 3
th(SO) Data output hold time
Slave mode
1.62<VDD<3.6 V 10 - -
th(MO) Master mode 0 - -
1. Guaranteed by characterization results.
Table 205. SPI characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
MSv41658V1
NSS input
CPHA=0
CPOL=0
SCK input
CPHA=0
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tc(SCK)
tr(SCK)
th(NSS)
tdis(SO)
tsu(NSS)
ta(SO) tv(SO)
Next bits IN
Last bit OUT
First bit IN
First bit OUT Next bits OUT
th(SO) tf(SCK)
Last bit IN
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Figure 104. SPI timing diagram - slave mode and CPHA = 1(1)
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Figure 105. SPI timing diagram - master mode(1)
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
MSv41659V1
NSS input
CPHA=1
CPOL=0
SCK input
CPHA=1
CPOL=1
MISO output
MOSI input
tsu(SI) th(SI)
tw(SCKL)
tw(SCKH)
tsu(NSS)
tc(SCK)
ta(SO) tv(SO)
First bit OUT Next bits OUT
Next bits IN
Last bit OUT
th(SO) tr(SCK)
tf(SCK) th(NSS)
tdis(SO)
First bit IN Last bit IN
ai14136c
SCK Output
CPHA= 0
MOSI
OUTPUT
MISO
INP UT
CPHA= 0
LSB OUT
LSB IN
CPOL=0
CPOL=1
B IT1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
High
SCK Output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
MSB IN BIT6 IN
MSB OUT
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I2S Interface characteristics
Unless otherwise specified, the parameters given in Table 206 for I2S are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 122: General operating conditions, with the following
configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load CL = 30 pF
•Measurement points are done at CMOS levels: 0.5VDD
•IO Compensation cell activated.
•HSLV activated when VDD 2.7 V
•VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,WS).
Table 206. I2S dynamic characteristics(1)
1. Guaranteed by characterization results.
Symbol Parameter Conditions Min Max Unit
fMCK I2S main clock output - 256x8K 256FSMHz
fCK I2S clock frequency
Master data - 64FSMHz
Slave data - 64FS
tv(WS) WS valid time Master mode - 3
ns
th(WS) WS hold time Master mode 0 -
tsu(WS) WS setup time Slave mode 1 -
th(WS) WS hold time Slave mode 1 -
tsu(SD_MR) Data input setup time
Master receiver 1 -
tsu(SD_SR) Slave receiver 1 -
th(SD_MR) Data input hold time
Master receiver 4 -
th(SD_SR) Slave receiver 2 -
tv(SD_ST)
Data output valid time
Slave transmitter (after enable
edge) -17
tv(SD_MT)
Master transmitter (after
enable edge) -3
th(SD_ST)
Data output hold time
Slave transmitter (after enable
edge) 9-
th(SD_MT)
Master transmitter (after
enable edge) 0-
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Figure 106. I2S slave timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 107. I2S master timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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SAI characteristics
Unless otherwise specified, the parameters given in Table 207 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 122: General operating conditions, with the following
configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load CL = 30 pF
•IO Compensation cell activated.
•Measurement points are done at CMOS levels: 0.5VDD
•VOS level set to VOS1.
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
alternate function characteristics (SCK,SD,WS).
Table 207. SAI characteristics(1)
Symbol Parameter Conditions Min Max Unit
fMCK SAI Main clock output - 256x8K 256xFS
MHz
fCK
SAI clock
frequency(2)
Master Data: 32 bits - 128xFS(3)
Slave Data: 32 bits - 128xFS(3)
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tv(FS) FS valid time
Master mode
2.7VDD3.6 -13
ns
Master mode
1.62VDD3.6 -20
tsu(FS) FS hold time Master mode 8 -
th(FS)
FS setup time Slave mode 1 -
FS hold time Slave mode 1 -
tsu(SD_A_MR) Data input setup time
Master receiver 0.5 -
tsu(SD_B_SR) Slave receiver 1 -
th(SD_A_MR) Data input hold time
Master receiver 3.5 -
th(SD_B_SR) Slave receiver 2 -
tv(SD_B_ST) Data output valid time
Slave transmitter (after enable
edge)
2.7VDD3.6
-14
Slave transmitter (after enable
edge)
1.62VDD3.6
-20
th(SD_B_ST) Data output hold time Slave transmitter (after enable
edge) 9-
tv(SD_A_MT) Data output valid time
Master transmitter (after enable
edge)
2.7VDD3.6
-12
Master transmitter (after enable
edge)
1.62VDD3.6
-19
th(SD_A_MT) Data output hold time Master transmitter (after enable
edge) 7.5 -
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With FS=192 kHz.
Table 207. SAI characteristics(1) (continued)
Symbol Parameter Conditions Min Max Unit
Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G
314/357 DS12110 Rev 7
Figure 108. SAI master timing waveforms
Figure 109. SAI slave timing waveforms
MDIO characteristics
Table 208. MDIO Slave timing parameters
Symbol Parameter Min Typ Max Unit
FMDC Management Data Clock - - 30 MHz
td(MDIO) Management Data Iput/output output valid time 8 10 19
nstsu(MDIO) Management Data Iput/output setup time 1 - -
th(MDIO) Management Data Iput/output hold time 1 - -
MS32771V1
SAI_SCK_X
SAI_FS_X
(output)
1/fSCK
SAI_SD_X
(transmit)
tv(FS)
Slot n
SAI_SD_X
(receive)
th(FS)
Slot n+2
tv(SD_MT) th(SD_MT)
Slot n
tsu(SD_MR) th(SD_MR)
MS32772V1
SAI_SCK_X
SAI_FS_X
(input)
SAI_SD_X
(transmit)
tsu(FS)
Slot n
SAI_SD_X
(receive)
tw(CKH_X) th(FS)
Slot n+2
tv(SD_ST) th(SD_ST)
Slot n
tsu(SD_SR)
tw(CKL_X)
th(SD_SR)
1/fSCK
DS12110 Rev 7 315/357
STM32H742xI/G STM32H743xI/G Electrical characteristics (rev V)
322
Figure 110. MDIO Slave timing diagram
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 209 and Table 210 for SDIO are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage summarized in Table 122: General operating conditions, with the following
configuration:
•Output speed is set to OSPEEDRy[1:0] = 0x11
•Capacitive load CL=30 pF
•Measurement points are done at CMOS levels: 0.5VDD
•IO Compensation cell activated.
•HSLV activated when VDD 2.7 V
•VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
characteristics.
MSv40460V1
tsu(MDIO)
tMDC)
th(MDIO)
td(MDIO)
Table 209. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V(1)(2)
Symbol Parameter Conditions Min Typ Max Unit
fPP Clock frequency in data transfer mode - 0 - 133 MHz
- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fPP =52MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP =52MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(3)/DDR(3) mode
tISU Input setup time HS - 1.5 - -
ns
tIH Input hold time HS - 1.5 - -
tIDW(4) Input valid window (variable window) - 3 - - -
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR(3) mode
tOV Output valid time HS - - 3.5 5
ns
tOH Output hold time HS - 2 - -
Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G
316/357 DS12110 Rev 7
CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD - 1.5 -
ns
tIHD Input hold time SD - 1.5 -
CMD, D outputs (referenced to CK) in SD default mode
tOVD Output valid default time SD - - 0.5 2
ns
tOHD Output hold default time SD - 0 - -
1. Guaranteed by characterization results.
2. Above 100 MHz, CL = 20 pF.
3. An external voltage converter is required to support SD 1.8 V.
4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
Table 209. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V(1)(2) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 210. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V(1)(2)
1. Guaranteed by characterization results.
2. CL = 20 pF.
Symbol Parameter Conditions Min Typ Max Unit
fPP
Clock frequency in data transfer
mode -0-120MHz
- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fPP =52 MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP =52 MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC mode
tISU Input setup time HS - 1 - -
ns
tIH Input hold time HS - 2.5 - -
tIDW(3)
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
Input valid window (variable
window) -3.5- -
CMD, D outputs (referenced to CK) in eMMC mode
tOVD Output valid time HS - - 5 7
ns
tOHD Output hold time HS - 3 - -
DS12110 Rev 7 317/357
STM32H742xI/G STM32H743xI/G Electrical characteristics (rev V)
322
Figure 111. SDIO high-speed mode
Figure 112. SD default mode
Figure 113. DDR mode
ai14888
CK
D, CMD
(output)
tOVD tOHD
MSv36879V1
Data output D0 D2 D4
Clock
Data input D0 D2 D4
t(CK) tw(CKH) tw(CKL)
tr(CK) tf(CK)
tsf(IN) thf(IN)
tvf(OUT) thr(OUT)
D1 D3 D5
D1 D3 D5
tvr(OUT) thf(OUT)
tsr(IN) thr(IN)
Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G
318/357 DS12110 Rev 7
USB OTG_HS characteristics
Unless otherwise specified, the parameters given in Table 211 for ULPI are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
summarized in Table 122: General operating conditions, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load CL=20 pF
•Measurement points are done at CMOS levels: 0.5VDD
•IO Compensation cell activated.
•VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
characteristics.
Figure 114. ULPI timing diagram
Table 211. Dynamics characteristics: USB ULPI(1)
1. Guaranteed by characterization results.
Symbol Parameter Condition Min Typ Max Unit
tSC
Control in (ULPI_DIR , ULPI_NXT) setup
time -2.5--
ns
tHC
Control in (ULPI_DIR, ULPI_NXT) hold
time -2--
tSD Data in setup time - 2.5 - -
tHD Data in hold time - 0 - -
tDC/tDD Control/Datal output delay
2.7<VDD<3.6 V
CL=20 pF -99.5
1.71<VDD<3.6 V
CL=15 pF -914
Clock
Control In
(ULPI_DIR,
ULPI_NXT)
data In
(8-bit)
Control out
(ULPI_STP)
data out
(8-bit)
tDD
tDC
tHD
tSD
tHC
tSC
ai17361c
tDC
DS12110 Rev 7 319/357
STM32H742xI/G STM32H743xI/G Electrical characteristics (rev V)
322
Ethernet interface characteristics
Unless otherwise specified, the parameters given in Tabl e 212, Table 213 and Table 214 for
SMI, RMII and MII are derived from tests performed under the ambient temperature,
frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 122: General
operating conditions, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load CL=20 pF
•Measurement points are done at CMOS levels: 0.5VDD
•IO Compensation cell activated.
•HSLV activated when VDD 2.7 V
•VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
characteristics:
Figure 115. Ethernet SMI timing diagram
Table 212. Dynamics characteristics: Ethernet MAC signals for SMI (1)
1. Guaranteed by characterization results.
Symbol Parameter Min Typ Max Unit
tMDC MDC cycle time( 2.5 MHz) 400 400 403
ns
Td(MDIO) Write data valid time 0.5 1.5 4
tsu(MDIO) Read data setup time 12.5 - -
th(MDIO) Read data hold time 0 - -
MS31384V1
ETH_MDC
ETH_MDIO(O)
ETH_MDIO(I)
tMDC
td(MDIO)
tsu(MDIO) th(MDIO)
Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G
320/357 DS12110 Rev 7
Figure 116. Ethernet RMII timing diagram
Table 213. Dynamics characteristics: Ethernet MAC signals for RMII (1)
1. Guaranteed by characterization results.
Symbol Parameter Min Typ Max Unit
tsu(RXD) Receive data setup time 2 - -
ns
tih(RXD) Receive data hold time 2 - -
tsu(CRS) Carrier sense setup time 1.5 - -
tih(CRS) Carrier sense hold time 1.5 - -
td(TXEN) Transmit enable valid delay time 7 8 9.5
td(TXD) Transmit data valid delay time 8 9 11
Table 214. Dynamics characteristics: Ethernet MAC signals for MII (1)
1. Guaranteed by characterization results.
Symbol Parameter Min Typ Max Unit
tsu(RXD) Receive data setup time 2 - -
ns
tih(RXD) Receive data hold time 2 - -
tsu(DV) Data valid setup time 1.5 - -
tih(DV) Data valid hold time 1.5 - -
tsu(ER) Error setup time 1.5 - -
tih(ER) Error hold time 0.5 - -
td(TXEN) Transmit enable valid delay time 9 10 11
td(TXD) Transmit data valid delay time 8.5 9.5 12.5
ai15667b
RMII_REF_CLK
RMII_TX_EN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRS_DV
td(TXEN)
td(TXD)
tsu(RXD)
tsu(CRS)
tih(RXD)
tih(CRS)
DS12110 Rev 7 321/357
STM32H742xI/G STM32H743xI/G Electrical characteristics (rev V)
322
Figure 117. Ethernet MII timing diagram
JTAG/SWD interface characteristics
Unless otherwise specified, the parameters given in Table 215 and Table 216 for
JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck
frequency and VDD supply voltage summarized in Table 122: General operating conditions,
with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 0x10
•Capacitive load CL=30 pF
•Measurement points are done at CMOS levels: 0.5VDD
•VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
characteristics:
Table 215. Dynamics JTAG characteristics
Symbol Parameter Conditions Min Typ Max Unit
Fpp TCK clock frequency
2.7V <VDD< 3.6 V - - 37
MHz
1/tc(TCK) 1.62 <VDD< 3.6 V - - 27.5
tisu(TMS) TMS input setup time - 2.5 - -
tih(TMS) TMS input hold time - 1 - -
tisu(TDI) TDI input setup time - 1.5 - - -
tih(TDI) TDI input hold time - 1 - - -
tov(TDO) TDO output valid time
2.7V <VDD< 3.6 V - 8 13.5 -
1.62 <VDD< 3.6 V - 8 18 -
toh(TDO) TDO output hold time - 7 - - -
ai15668b
MII_RX_CLK
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
td(TXEN)
td(TXD)
tsu(RXD)
tsu(ER)
tsu(DV)
tih(RXD)
tih(ER)
tih(DV)
MII_TX_CLK
MII_TX_EN
MII_TXD[3:0]
Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G
322/357 DS12110 Rev 7
Figure 118. JTAG timing diagram
Figure 119. SWD timing diagram
Table 216. Dynamics SWD characteristics:
Symbol Parameter Conditions Min Typ Max Unit
Fpp SWCLK clock frequency
2.7V <VDD< 3.6 V - - 71
MHz
1/tc(SWCLK) 1.62 <VDD< 3.6 V - - 52.5
tisu(SWDIO) SWDIO input setup time - 2.5 - - -
tih(SWDIO) SWDIO input hold time - 1 - - -
tov(SWDIO) SWDIO output valid time
2.7V <VDD< 3.6 V - 8.5 14 -
1.62 <VDD< 3.6 V -8.519 -
toh(SWDIO) SWDIO output hold time - 8 - - -
MSv40458V1
TDI/TMS
TCK
TDO
t
c(TCK)
t
w(TCKL)
t
w(TCKH)
t
h(TMS/TDI)
t
su(TMS/TDI)
t
ov(TDO)
t
oh(TDO)
MSv40459V1
SWDIO
SWCLK
SWDIO
t
c(SWCLK)
t
wSWCLKL)
t
w(SWCLKH)
t
h(SWDIO)
t
su(SWDIO)
t
ov(SWDIO)
t
oh(SWDIO)
(receive)
(transmit)
DS12110 Rev 7 323/357
STM32H742xI/G STM32H743xI/G Package information
352
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at www.st.com.
ECOPACK® is an ST trademark.
8.1 LQFP100 package information
LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.
Figure 120. LQFP100 package outline
1. Drawing is not to scale.
e
IDENTIFICATION
PIN 1
GAUGE PLANE
0.25 mm
SEATING PLANE
D
D1
D3
E3
E1
E
K
ccc C
C
125
26
100
76
75 51
50
1L_ME_V5
A2
A
A1
L1
L
c
b
A1
Package information STM32H742xI/G STM32H743xI/G
324/357 DS12110 Rev 7
Table 217. LQPF100 package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc - - 0.080 - - 0.0031
Package information STM32H742xI/G STM32H743xI/G
326/357 DS12110 Rev 7
Device marking for LQFP100
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 122. LQFP100 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
MSv46104V1
ES32H743VIT6
R
WW
Revision code
Product identification(1)
Date code
Pin 1
indentifier
Y
DS12110 Rev 7 327/357
STM32H742xI/G STM32H743xI/G Package information
352
8.2 TFBGA100 package information
TFBGA100 is a 100-ball, 8 x 8 mm, 0.8 mm pitch, thin fine-pitch ball grid array package.
Figure 123. TFBGA100 package outline
1. Drawing is not to scale.
Table 218. TFBGA100 package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.100 - - 0.0433
A1 0.150 - - 0.0059 - -
A2 - 0.760 - - 0.0299 -
b 0.350 0.400 0.450 0.0138 0.0157 0.0177
D 7.850 8.000 8.150 0.3091 0.3150 0.3209
SEATING
PLANE
12345678910
K
J
H
G
F
E
D
C
B
A
A2
A1
A
C
ddd C
(100 BALLS)
b
eee
fff
CAB
C
D
E
F
e
B
Ge
A1 ball
identifier
A1 ball
index
area
A
A08Q_ME_V1
D1
E1
BOTTOM VIEW TOP VIEW
Package information STM32H742xI/G STM32H743xI/G
328/357 DS12110 Rev 7
Figure 124. TFBGA100 package recommended footprint
1. Dimensions are expressed in millimeters.
D1 - 7.200 - 0.2835 -
E 7.850 8.000 8.150 0.3091 0.3150 0.3209
E1 - 7.200 - - 0.2835 -
e - 0.800 - - 0.0315 -
F - 0.400 - - 0.0157 -
G - 0.400 - - 0.0157 -
ddd - - 0.100 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 219. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA)
Dimension Recommended values
Pitch 0.8
Dpad 0.400 mm
Dsm 0.470 mm typ (depends on the soldermask
registration tolerance)
Table 218. TFBGA100 package mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
Dpad
Dsm
DS12110 Rev 7 329/357
STM32H742xI/G STM32H743xI/G Package information
352
Device marking for TFBGA100
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 125. TFBGA100 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
Stencil opening 0.400 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm
Table 219. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA) (contin-
Dimension Recommended values
MSv46178V1
Revision code
Ball
A1identifier
STM32H743
VHI6
Y WW
Product
identification(1)
Date code
R
Package information STM32H742xI/G STM32H743xI/G
330/357 DS12110 Rev 7
8.3 LQFP144 package information
LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package.
Figure 126. LQFP144 package outline
1. Drawing is not to scale.
e
IDENTIFICATION
PIN 1
GAUGE PLANE
0.25 mm
SEATING
PLANE
D
D1
D3
E3
E1
E
K
ccc C
C
136
37
144
109
108 73
72
1A_ME_V4
A2
A
A1
L1
L
c
b
A1
DS12110 Rev 7 331/357
STM32H742xI/G STM32H743xI/G Package information
352
Table 220. LQFP144 package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.8740
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 - 17.500 - - 0.6890 -
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 - 17.500 - - 0.6890 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.080 - - 0.0031
DS12110 Rev 7 333/357
STM32H742xI/G STM32H743xI/G Package information
352
Device marking for LQFP144
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 128. LQFP144 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
MSv46106V2
Date code
Pin 1 identifier
ES32H743ZIT6
Y WW
Product identification(1)
Revision code
R
Package information STM32H742xI/G STM32H743xI/G
334/357 DS12110 Rev 7
8.4 UFBGA169 package information
UFBGA169 is a 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Figure 129. UFBGA169 package outline
1. Drawing is not in scale.
Table 221. UFBGA169 package mechanical data
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
A 0.460 0.530 0.600 0.0181 0.0209 0.0236
A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.230 0.280 0.330 0.0091 0.0110 0.0130
D 6.950 7.000 7.050 0.2736 0.2756 0.2776
D1 5.950 6.000 6.050 0.2343 0.2362 0.2382
E 6.950 7.000 7.050 0.2736 0.2756 0.2776
E1 5.950 6.000 6.050 0.2343 0.2362 0.2382
e - 0.500 - - 0.0197 -
F 0.450 0.500 0.550 0.0177 0.0197 0.0217
A0YV_ME_V2
Seating plane
A2
A1
A
eF
F
e
N
A
BOTTOM VIEW
E
D
TOP VIEW
Øb (169 balls)
Y
X
YeeeØM
fffØM
Z
Z
X
A1 ball
identifier
A1 ball
index area
b
D1
E1
A4
A3
13 1
Z
Z
ddd
SIDE VIEW
DS12110 Rev 7 335/357
STM32H742xI/G STM32H743xI/G Package information
352
Device marking for UFBGA169
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 130. UFBGA169 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
ddd - - 0.100 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 221. UFBGA169 package mechanical data (continued)
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
MSv61382V1
Revision code
Ball A1
identifier
Product identification(1)
Date code
ES32H743
AII6
WWY
R
Package information STM32H742xI/G STM32H743xI/G
336/357 DS12110 Rev 7
8.5 LQFP176 package information
LQFP176 is a 176-pin, 24 x 24 mm low profile quad flat package.
Figure 131. LQFP176 package outline
1. Drawing is not to scale.
1T_ME_V2
A2
A
e
EHE
D
HD
ZD
ZE
b
0.25 mm
gauge plane
A1 L
L1
k
c
IDENTIFICATION
PIN 1
Seating plane
C
A1
Table 222. LQFP176 package mechanical data
Ref.
Dimensions
Millimeters Inches(1)
Min. Typ. Max. Min. Typ. Max.
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 - 1.450 0.0531 - 0.0571
b 0.170 - 0.270 0.0067 - 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
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D 23.900 - 24.100 0.9409 - 0.9488
HD 25.900 - 26.100 1.0197 - 1.0276
ZD - 1.250 - - 0.0492 -
E 23.900 - 24.100 0.9409 - 0.9488
HE 25.900 - 26.100 1.0197 - 1.0276
ZE - 1.250 - - 0.0492 -
e - 0.500 - - 0.0197 -
L(2) 0.450 - 0.750 0.0177 - 0.0295
L1 - 1.000 - - 0.0394 -
k 0° - 7° 0° - 7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. L dimension is measured at gauge plane at 0.25 mm above the seating plane.
Table 222. LQFP176 package mechanical data (continued)
Ref.
Dimensions
Millimeters Inches(1)
Min. Typ. Max. Min. Typ. Max.
DS12110 Rev 7 339/357
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352
Device marking for LQFP176
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 133. LQFP176 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
MSv46108V2
Pin 1identifier
ES32H743IIT6
YWW
R
Date code
Product identification(1)
Revision code
Package information STM32H742xI/G STM32H743xI/G
340/357 DS12110 Rev 7
8.6 LQFP208 package information
LQFP208 is a 208-pin, 28 x 28 mm low-profile quad flat package.
Figure 134. LQFP208 package outline
1. Drawing is not to scale.
D
D1
D3
E3
E1
E
e
L1
GAUGE PLANE
0.25 mm
b
C
SEATING
PLANE
ccc C
IDENTIFICATION
PIN 1
152
53
104
105
156
157
208
c
L
A1
A1
A
A2
UH_ME_V2
K
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352
Table 223. LQFP208 package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 29.800 30.000 30.200 1.1811 1.1732 1.1890
D1 27.800 28.000 28.200 1.1024 1.0945 1.1102
D3 - 25.500 - - 1.0039 -
E 29.800 30.000 30.200 1.1811 1.1732 1.1890
E1 27.800 28.000 28.200 1.1024 1.0945 1.1102
E3 - 25.500 - - 1.0039 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.080 - - 0.0031
DS12110 Rev 7 343/357
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352
Device marking for LQFP208
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 136. LQFP208 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
MSv46110V2
Date code
Pin 1 identifier
ES32H743BIT6
Y WW
Product identification(1)
Revision code
R
Package information STM32H742xI/G STM32H743xI/G
344/357 DS12110 Rev 7
8.7 UFBGA176+25 package information
UFBGA176+25 is a 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array
package.
Figure 137. UFBGA176+25 package outline
1. Drawing is not to scale.
Table 224. UFBGA176+25 package mechanical data
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
A - - 0.600 - - 0.0236
A1 - - 0.110 - - 0.0043
A2 - 0.130 - - 0.0051 -
A3 - 0.450 - - 0.0177 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 9.850 10.000 10.150 0.3878 0.3937 0.3996
D1 - 9.100 - - 0.3583 -
E 9.850 10.000 10.150 0.3878 0.3937 0.3996
E1 - 9.100 - - 0.3583 -
e - 0.650 - - 0.0256 -
Z - 0.450 - - 0.0177 -
ddd - - 0.080 - - 0.0031
A0E7_ME_V8
D1
Seating plane
A3
Cddd
A1 A
eZ
Z
e
R
A
15 1
BOTTOM VIEW
E
D
TOP VIEW
Øb (176 + 25 balls)
B
A
B
eeeØ M
fffØM
C
C
A
C
A1 ball
identifier
A1 ball
index
area
b
A4
E1
A2
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352
Figure 138. UFBGA176+25 package recommended footprint
eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 225. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
Dimension Recommended values
Pitch 0.65 mm
Dpad 0.300 mm
Dsm 0.400 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening 0.300 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
Table 224. UFBGA176+25 package mechanical data (continued)
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
A0E7_FP_V1
Dpad
Dsm
Package information STM32H742xI/G STM32H743xI/G
346/357 DS12110 Rev 7
Device marking for UFBGA176+25
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 139. UFBGA176+25 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
MSv46112V1
Revision code
Ball
A1identifier
ES32H743II
Y WW
R
Product identification(1)
Date code
DS12110 Rev 7 347/357
STM32H742xI/G STM32H743xI/G Package information
352
8.8 TFBGA240+25 package information
TFBGA240+25 is a 265 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array
package.
Figure 140. TFBGA240+25 package outline
1. Dimensions are expressed in millimeters.
C
SEATING
PLANE
ddd C
A
A1
A2
D1
F
E1
E
D
G
e
A
S
17 1
b (240 + 25 balls)
BOTTOM VIEW
e
A1 ball identifier
TOP VIEW
A07U_ME_V1
Package information STM32H742xI/G STM32H743xI/G
348/357 DS12110 Rev 7
Figure 141. TFBGA240+25 package recommended footprint
1. Dimensions are expressed in millimeters.
Table 226. TFBG240+25 ball package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.100 - - 0.0433
A1 0.150 - - 0.0059 - -
A2 - 0.760 - - 0.0299 -
b 0.350 0.400 0.450 0.0138 0.0157 0.0177
D 13.850 14.000 14.150 0.5453 0.5512 0.5571
D1 - 12.800 - - 0.5039 -
E 13.850 14.000 14.150 0.5453 0.5512 0.5571
E1 - 12.800 - - 0.5039 -
e - 0.800 - - 0.0315 -
F - 0.600 - - 0.0236 -
G - 0.600 - - 0.0236 -
ddd - - 0.100 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0031
A07U_FP_V2
Dpad
Dsm
DS12110 Rev 7 349/357
STM32H742xI/G STM32H743xI/G Package information
352
Device marking for TFBGA240+25
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 142. TFBGA240+25 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
Table 227. TFBGA240+25 recommended PCB design rules (0.8 mm pitch)
Dimension Recommended values
Pitch 0.8 mm
Dpad 0.225 mm
Dsm 0.290 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.100 mm
MSv46114V1
Revision code
Ball
A1identifier
STM32H743XIH6
Y WW
Product
identification(1)
Date code
R
Package information STM32H742xI/G STM32H743xI/G
350/357 DS12110 Rev 7
8.9 Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × Θ
JA)
Where:
•TA max is the maximum ambient temperature in °C,
•Θ
JA is the package junction-to-ambient thermal resistance, in °C/W,
•PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 228. Thermal characteristics(1)
Symbol Definition Parameter Value Unit
Θ
JA
Thermal resistance
junction-ambient
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm /0.5 mm pitch 45.0
°C/W
Thermal resistance junction-ambient
TFBGA100 - 8 x 8 mm /0.8 mm pitch 39.3
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm /0.5 mm pitch 43.7
Thermal resistance junction-ambient
UFBGA169 - 7 x 7 mm /0.5 mm pitch 37.7
Thermal resistance junction-ambient
LQFP176 - 24 x 24 mm /0.5 mm pitch 43.0
Thermal resistance junction-ambient
LQFP208 - 28 x 28 mm /0.5 mm pitch 42.4
Thermal resistance junction-ambient
UFBGA176+25 - 10 x 10 mm /0.65 mm pitch 37.4
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch 36.6
DS12110 Rev 7 351/357
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8.9.1 Reference document
•JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
•For information on thermal management, refer to application note “Thermal
management guidelines for STM32 32-bit Arm Cortex MCUs applications” (AN5036)
available from www.st.com.
Θ
JC
Thermal resistance
junction-case
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm /0.5 mm pitch 11.5
°C/W
Thermal resistance junction-ambient
TFBGA100 - 8 x 8 mm /0.8 mm pitch 17.1
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm /0.5 mm pitch 11.3
Thermal resistance junction-ambient
UFBGA169 - 7 x 7 mm /0.5 mm pitch TBD
Thermal resistance junction-ambient
LQFP176 - 24 x 24 mm /0.5 mm pitch 11.2
Thermal resistance junction-ambient
LQFP208 - 28 x 28 mm /0.5 mm pitch 11.1
Thermal resistance junction-ambient
UFBGA176+25 - 10 x 10 mm /0.65 mm pitch 23.9
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch 7.4
Θ
JB
Thermal resistance
junction-board
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm /0.5 mm pitch 36.3
°C/W
Thermal resistance junction-ambient
TFBGA100 - 8 x 8 mm /0.8 mm pitch 21.1
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm /0.5 mm pitch 38.3
Thermal resistance junction-ambient
UFBGA169 - 7 x 7 mm /0.5 mm pitch TBD
Thermal resistance junction-ambient
LQFP176 - 24 x 24 mm /0.5 mm pitch 39.4
Thermal resistance junction-ambient
LQFP208 - 28 x 28 mm /0.5 mm pitch 40.3
Thermal resistance junction-ambient
UFBGA176+25 - 10 x 10 mm /0.65 mm pitch 19.3
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch 24.3
1. TBD stands for “to be defined”.
Table 228. Thermal characteristics(1) (continued)
Symbol Definition Parameter Value Unit
Ordering information STM32H742xI/G STM32H743xI/G
352/357 DS12110 Rev 7
9 Ordering information
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Example: STM32 H 743 X I T 6 TR
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
H = High performance
Device subfamily
743 = STM32H7x3
742 = STM32H7x2
Pin count
V = 100 pins
Z = 144 pins
A = 169 pins
I = 176 pins/balls
B = 208 pins
X = 240 balls
Flash memory size
G = 1 Mbytes
I = 2 Mbytes
Package
T = LQFP ECOPACK®2
K = UFBGA pitch 0.65 mm ECOPACK®2
I = UFBGA pitch 0.5 mm ECOPACK®2
H = TFBGA ECOPACK®2
Temperature range
6 = Industrial temperature range, –40 to 85 °C
Packing
TR = tape and reel
No character = tray or tube
DS12110 Rev 7 353/357
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10 Revision history
Table 229. Document revision history
Date Revision Changes
22-Jun-2017 1 Initial release.
27-Sep-2017 2
Updated list of features. Changed datasheet status to “production data”.
Added UFBGA169 and TFBGA100 packages and well as notes related their status on
cover page and in Table 2: STM32H742xI/G and STM32H743xI/G features and
peripheral counts. Differentiated number of GPIOs for each package in Table 2:
STM32H742xI/G and STM32H743xI/G features and peripheral counts.
Updated Error code correction (ECC) in Section 3.3.2: Embedded SRAM. Change
PWR_CR3 into PWR_D3CR in Section 3.5.1: Power supply scheme. Updated
Section 3.12: Nested vectored interrupt controller (NVIC).
Added ADC sampling rate values in Section 3.17: Analog-to-digital converters (ADCs).
Added Table 4: DFSDM implementation in Section 3.23: Digital filter for sigma-delta
modulators (DFSDM)
Changed PC2/3 to PC2/3_C and VDD33USB to VDD in Figure 5: LQFP100 pinout.
Changed PC2/3 to PC2/3_C in Figure 7: LQFP144 pinout. Changed PC2/3 to
PC2/3_C in Figure 9: LQFP176 pinout. Changed PC2/3 to PC2/3_C in Figure 11:
LQFP208 pinout.
Table 9: Pin/ball definition:
– Modified PA7, PC4, PC5, PB1, PG1, PE7, PE8 and PE9 I/O structure
– TFBGA240 +25: removed duplicate occurrence of F1, F2 and P17 pin; added notes
related to F1, F2, G2 pin connection; added note on E1, L16, L17, M16, M17, K16,
K17, N17.
– UFBGA176+25: changed G10 pin name to VSS.
– Added note to VREF+ pin.
Added current consumption corresponding to 125 °C ambient temperature in
Section 6.3.6: Supply current characteristics. Removed CRYP peripheral from
Table 39: Peripheral current consumption in Run mode.
Replaced FMC_CLK by FMC_SDCLK in Section : SDRAM waveforms and timings.
Changed description of the last five fS values and updated tLATRINJin Table 87: ADC
characteristics.
For TFBGA100, TFBGA240+25 and UFBGA169, updated thermal resistance power-
junction in Table 228: Thermal characteristics as well as power dissipation in Table 24:
General operating conditions.
23-Oct-2017 3
Features:
– Removed secure firmware upgrade support.
– Total current consumption changed to 4
µA minimum
.
Updated Figure 8: UFBGA169 ballout.
Updated dpad and dsm in Table 227: TFBGA240+25 recommended PCB design rules
(0.8 mm pitch).
Revision history STM32H742xI/G STM32H743xI/G
354/357 DS12110 Rev 7
18-May-2018 4
Updated LSI clock frequency and ADC on cover page. Removed note related to
UFBGA169 package.
Updated USB OTG interfaces to add crystal-less capability.
Updated ADC features on cover page and in Table 2: STM32H742xI/G and
STM32H743xI/G features and peripheral counts.
Added Arm trademark notice in Section 1: Introduction.
Updated Figure 1: STM32H743xI/G block diagram.
Updated GPIO default mode in Section 3.8: General-purpose input/outputs (GPIOs).
Added ADC sampling rate values in Section 3.17: Analog-to-digital converters (ADCs).
Updated Section 3.18: Temperature sensor.
Updated LCD-TFT FIFO Size in Section 3.25: LCD-TFT controller.
Section 3.33: Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S):
changed maximum SPI frequency to 150 Mbits/s.
Modified number of bidirectional endpoints in Section 3.40: Universal serial bus on-the-
go high-speed (OTG_HS).
Table 9: Pin/ball definition: updated PC14 and PC15 function after reset; changed
CAN1_TX/RX to FDCAN1_TX/RX and CAN1_TXFD/RXFD to
FDCAN1_TXFD_MODE/RXFD_MODE; changed CAN2_TX/RX to FDCAN2_TX/RX
and CAN2_TXFD/RXFD to FDCAN2_TXFD_MODE/RXFD_MODE and replaced
VCAP1/2/3 and VDDLDO1/2/3 by VCAP and VDDLDO, respectively.
Updated PA0, PA13, PA14, PC14 and PC15 pin/ball signals in pinout/ballout
schematics.
Replaced fACLK by frcc_c_ck in Section : Typical and maximum current consumption.
Replaced system clock by CPU clock and fACLK by frcc_c_ck in Section : On-chip
peripheral current consumption.
Updated Note 2. in Table 27: Reset and power control block characteristics, Table 28:
Embedded reference voltage, Table 30: Typical and maximum current consumption in
Run mode, code with data processing running from ITCM, regulator ON, Table 31:
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON, regulator ON, Table 36: Typical and maximum
current consumption in Stop mode, regulator ON, Table 37: Typical and maximum
current consumption in Standby mode and Table 38: Typical and maximum current
consumption in VBAT mode.
Added note to fLSI in Table 49: LSI oscillator characteristics.
Updated Figure 22: VIL/VIH for all I/Os except BOOT0.
Added note in Table 84: QUADSPI characteristics in SDR mode, Table 85: QUADSPI
characteristics in DDR mode and Table 86: Dynamics characteristics: Delay Block
characteristics.
Section 6.3.20: 16-bit ADC characteristics: updated THD conditions in Table 88: ADC
accuracy; removed formula to compute RAIN.
Changed decoupling capacitor value to 100 nF in Section : General PCB design
guidelines.
Added note in Table 89: DAC characteristics, Table 97: Voltage booster for analog
switch characteristics, Table 100: DFSDM measured timing 1.62-3.6 V, Table 117:
Dynamics JTAG characteristics and Table 118: Dynamics SWD characteristics.
Updated Figure 128: LQFP144 marking example (package top view), Figure 133:
LQFP176 marking example (package top view) and Figure 136: LQFP208 marking
example (package top view).
Updated TFBGA240+25 package information to final mechanical data.
Table 229. Document revision history
Date Revision Changes
DS12110 Rev 7 355/357
STM32H742xI/G STM32H743xI/G Revision history
356
13-Jul-2018 5
Added description of power-up and power-down phases in Section 3.5.1: Power
supply scheme.
Removed ETH_TX_ER from Table 9: Pin/ball definition and Table 10: Port A alternate
functions to Table 20: Port K alternate functions.
Added note related to decoupling capacitor tolerance below Figure 15: Power supply
scheme. Added note 2. related to CEXT in Table 25: VCAP operating conditions.
Updated Table 46: HSI48 oscillator characteristics, Table 47: HSI oscillator
characteristics and Table 48: CSI oscillator characteristics. Renamed Table 50 into
“PLL characteristics (wide VCO frequency range)” and updated note 2.. Added
Table 51: PLL characteristics (medium VCO frequency range).
Updated Tcoeff in Table 91: VREFBUF characteristics and tS_vbat in Table 94: VBAT
monitoring characteristics. Updated Table 99: OPAMP characteristics.
05-Apr-2019 6
Added STM32H743xG part numbers corresponding to 1 Mbyte of Flash memory as
well as STM32H742xI/G part numbers.
Changed maximum Arm Core-M7 frequency to 480 MHz.
Features:
– Changed operational amplifier bandwidth to 7.3 MHz
– Updated high-resolution timer to 2.1 ns
– Updated low-power consumption feature.
– Updated Figure 2: STM32H743xI/G block diagram.
Updated voltage scaling in Section 3.5.1: Power supply scheme. Added VOS0 in
Section 3.5.3: Voltage regulator. Updated HSE clock in Section 3.7.1: Clock
management.
Changed FMC NOR/NAND maximum clock frequency to 100 MHz in Features and
Synchronous waveforms and timings.
Added note related to VDDLDO in Table 9: Pin/ball definition.
Updated Section 6: Electrical characteristics (rev Y):
– Added note 2. related to CEXT in Table 25: VCAP operating conditions.
– Updated fHSI48 in Table 46: HSI48 oscillator characteristics.
– Updated tstab in Table 47: HSI oscillator characteristics.
– Updated Table 60: I/O static characteristics and Figure 22: VIL/VIH for all I/Os
except BOOT0.
– Added Table 62: Output voltage characteristics for PC13, PC14, PC15 and PI8.
– Added note related to PC13, PC14, PC15 an PI8 limited frequency in Table 63:
Output timing characteristics (HSLV OFF).
– Updated note 2 below Figure 23: Recommended NRST pin protection.
–Table 87: ADC characteristics: updated fS and added note related to fS formula;
updated tCAL.
– Renamed Section 6.3.24 into Temperature and VBAT monitoring and content
updated.
– Updated fDFSDMCLK in Table 100: DFSDM measured timing 1.62-3.6 V.
Added Section 7: Electrical characteristics (rev V).
Updated paragraph introducing all package marking schematics to add the new
sentence “The printed markings may differ depending on the supply chain”. Updated
Table 228: Thermal characteristics. Added note related to ECOPACK®2 compliance in
Section 9: Ordering information.
Table 229. Document revision history
Date Revision Changes
Revision history STM32H742xI/G STM32H743xI/G
356/357 DS12110 Rev 7
25-Apr-2019 7
Updated Figure 1: STM32H742xI/G block diagram
Updated Figure 2: STM32H743xI/G block diagram
Updated Table 9: Pin/ball definition.
Updated Table 10 to Table 20 (alternate functions).
Updated Table 39: Peripheral current consumption in Run mode.
Updated Table 137: Peripheral current consumption in Run mode.
Updated Table 184: ADC characteristics.
Updated Table 185: Minimum sampling time vs RAIN.
Updated Table 186: ADC accuracy.
Table 229. Document revision history
Date Revision Changes
DS12110 Rev 7 357/357
STM32H742xI/G STM32H743xI/G
357
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