CMR3000-D01 Data Sheet CMR3000-D01 3-AXIS LOW POWER GYRO WITH DIGITAL SPI AND I2C INTERFACE Features * * * * * * * * * * Applications CMR3000-D01 is targeted to battery operated devices. Typical but not limited applications are 2.5 V - 3.6 V supply voltage, 1.6 V - 3.6 V digital I/O voltage Low 5 mA current consumption 2000 /s measurement range 20 Hz and 80 Hz user selectable bandwidths SPI and I2C digital interface Interrupt signal triggered by data ready Size 3.1x4.1x0.83 mm3 Proven capacitive 3D-MEMS technology High shock durability RoHS compliant / lead free soldering Sens X Sens Y Sens Z Sens P Drive Bias CSA & Highpass Filter PLL & Drive Phase Detection Calibration & Low-pass Filter * * * Gaming input devices Computer peripherals and remote controllers Mobile Phones Low-pass Filter ADC Low-pass Filter SCK/SCL SPI & I2C i/f Oscillator Reference NonVolatile Memory MOSI/SDA CSB Low-pass Filter Bias MISO Control & INT INT Figure 1 CMR3000-D01 Block Diagram VTI Technologies Oy Myllykivenkuja 6 P.O. Box 27 FI-01621 Vantaa www.vti.fi PRELIMINARY - Subject to changes Doc. Nr. 82106500.A.02 1/4 Rev. 02 CMR3000-D01 Target Performance Characteristics 1) Parameter Vdd Digital I/O Vdd Operating temperature ** Current consumption * Measurement range ** Offset calibration error * 3) Offset temperature error ** 4) Sensitivity * 5) Sensitivity calibration error * Sensitivity temperature error ** Condition Vdd Digital I/O Vdd Measurement Stand-By Power down FS=2000 /s Typical supply range 2.5 - 3.0 V Min Nom 2) Max 2.8 1.8 / 2.8 3.0 3.0 - 3.3 3.3 - V V -40 -2000 -200 5 1.3 <10 1 1.33 0.02 85 -40 - 5 1.3 <10 2000 200 1 1.33 7 0.02 85 - - C mA mA nA /s /s /s/C Count//s % %/C 1 2000 20 80 0.9 250 12 - - % FS Hz Hz 400 500 /s ms ms kHz kHz -40 ... +85 C -40 ... +85 C Non-Linearity ** 7) Output Data Rate, ODR ** Bandwidth ** 8) -1000<<1000 /s - Integrated noise stdev** Turn on time PD to meas** 9) Turn on time SB to meas** 10) I2C clock rate ** SPI clock rate ** 20 Hz BW 20 Hz BW 80 Hz BW - * ** 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) Units 2.5 1.6 -7 - 6) Extended supply range 3.0 - 3.6 V Min Nom 2) Max 1 2000 20 80 0.9 250 12 - 2000 200 +7 - 400 500 - 100% tested in production. Qualified during product validation. The product is factory calibrated at 2.8 V in room temperature. Typical values are not guaranteed. Offset when the device is not rotated Offset temperature error = {Count(0 /s)-Offset} / Sensitivity [/s]. Sensitivity = Calibrated sensitivity. Offset= Calibrated offset. Sensitivity = {Count(+500/s) - Count(-500/s)}/2 [Count//s]. Sensitivity temperature error = {[Count(+500/s)-Count(-500/s)]/2 - Sensitivity} / Sensitivity x 100% [%]. Sensitivity = Calibrated sensitivity. Best fit straight line -1000<<1000 /s. Frequency responses with 1st order roll off From Power-Down to measurement mode. Settling error less than 1% of FS. From Stand-By to measurement mode. Settling error less than 1% of FS. VTI Technologies Oy Myllykivenkuja 6 P.O. Box 27 FI-01621 Vantaa www.vti.fi PRELIMINARY - Subject to changes Doc. Nr. 82106500.A.02 2/4 Rev. A.02 CMR3000-D01 Figure 2 Package dimensions in mm I2C SPI 1 INT MOSI CSB 2 3 4 5 DVSS INT MOSI_SDA CSB AVSS DVDD DVIO MISO SCK_SCL AVDD 10 1 VDD 9 INT DVIO 8 MISO 7 SDA SCK 2 3 4 5 6 100n 100n 100n DVSS INT MOSI_SDA CSB AVSS DVDD DVIO MISO SCK_SCL AVDD 10 VDD 9 DVIO 8 ADDR[0] 7 SCL 6 100n 100n 100n Figure 3 Application schematics for I2C and SPI bus VTI Technologies Oy Myllykivenkuja 6 P.O. Box 27 FI-01621 Vantaa www.vti.fi PRELIMINARY - Subject to changes Doc. Nr. 82106500.A.02 3/4 Rev. A.02 CMR3000-D01 Figure 4 Recommended layout pattern (not actual size, for reference only) Table 1 Pin descriptions (top view) Pin # 1 2 3 4 5 6 7 8 9 10 Name DVSS INT MOSI_SDA CSB AVSS AVDD SCK_SCL MISO DVIO DVDD Function Digital ground Interrupt SPI Serial Data Input (MOSI) / I2C Serial Data (SDA) Chip select / I2C enable Analog ground Analog supply voltage SPI Serial Clock (SCK) / I2C Serial Clock (SCL) SPI Serial Data Output (MISO) / I2C slave address LSB ADDR[0] I/O Supply Digital supply voltage Document Change Control Rev. 0.1 0.2 0.3 0.4 0.5 0.6 A.01 A.02 Date 04-May-09 04-Sep-09 01-Oct-10 09-Apr-10 20-May-10 01-Oct-10 03-Nov-10 25-Mar-11 VTI Technologies Oy Myllykivenkuja 6 P.O. Box 27 FI-01621 Vantaa www.vti.fi Change Description 1st version Block diagram, package dimensions & layout pattern added Package dimensions updated Target Performance Characteristics updated Target Performance Characteristics, Table 1, Figure 3 updated Target Performance Characteristics updated Fig.2 updated, Target Performance Characteristics updated Target Performance Characteristics updated PRELIMINARY - Subject to changes Doc. Nr. 82106500.A.02 4/4 Rev. A.02