SL74HCT574
System Logic
Semiconductor
SLS
Octal 3-State Noninverting D Flip-Flop
High-Performance Silicon-Gate CMOS
The SL74HCT574 is identical in pinout to the LS/ALS574. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High-Speed CMOS inputs.
Data meeting the setup time is clocked to the outputs with the
rising edge of the Clock. The Output Enable input does not affect the
states of the flip-flops, but when Output Enable is high, all device
outputs are forced to the high-impedance state; thus, data may be
stored even when the outputs are not enabled.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
SL74HCT574N Plastic
SL74HCT574D SOIC
TA = -55° to 125° C for all packages
FUNCTION TABLE
Inputs Output
Output
Enable Clock D Q
L H H
L L L
L L,H, X no
change
H X X Z
X = don’t care
Z = high impedance
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
PIN ASSIGNMENT
SL74HCT574
System Logic
Semiconductor
SLS
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±35 mA
ICC DC Supply Current, VCC and GND Pins ±75 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC).
Unused outputs must be left open.
SL74HCT574
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
≤85
°C ≤125
°C Unit
VIH Minimum High-Level
Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT≤ 20 µA 4.5
5.5 2.0
2.0 2.0
2.0 2.0
2.0 V
VIL Maximum Low -Level
Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA 4.5
5.5 0.8
0.8 0.8
0.8 0.8
0.8 V
VOH Minimum High-Level
Output Voltage VIN=VIH or VIL
IOUT ≤ 20 µA 4.5
5.5 4.4
5.4 4.4
5.4 4.4
5.4 V
VIN=VIH or VIL
IOUT ≤ 6.0 mA
4.5
3.98
3.84
3.7
VOL Maximum Low-Level
Output Voltage VIN= VIL or VIH
IOUT ≤ 20 µA 4.5
5.5 0.1
0.1 0.1
0.1 0.1
0.1 V
VIN= VIL or VIH
IOUT ≤ 6.0 mA
4.5
0.26
0.33
0.4
IIN Maximum Input
Leakage Current VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA
IOZ Maximum Three State
Leakage Current Output in High-Impedance
State
VIN =VIH or VIL
VOUT= VCC or GND
5.5 ±0.5 ±5.0 ±10 µA
ICC Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA 5.5 4.0 40 160 µA
∆ICC Additional Quiescent
Supply Current VIN=2.4 V, Any One Input
VIN=VCC or GND,
Other Inputs
≥-55°C 25°C to
125°C mA
IOUT=0µA 5.5 2.9 2.4
SL74HCT574
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
Symbol Parameter 25 °C to
-55°C ≤85°C ≤125°C Unit
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4) 30 24 20 MHz
tPLH, tPHL Maximum Propagation Delay, Clock to Q (Figures
1 and 4) 30 38 45 ns
tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5) 28 35 42 ns
tPZH, tPZL Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5) 28 35 42 ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4) 12 15 18 ns
CIN Maximum Input Capacitance 10 10 10 pF
COUT Maximum Three-State Output Capacitance
(Output in High-Impedance State) 15 15 15 pF
Power Dissipation Capacitance (Per Flip-Flop) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
58 pF
TIMING REQUIREMENTS (VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
Symbol Parameter 25 °C to
-55°C ≤85°C ≤125°C Unit
tSU Minimum Setup Time, Data to
Clock (Figure 3) 10 13 15 ns
th Minimum Hold Time, Clock to
Data (Figure 3) 5 5 5 ns
tw Minimum Pulse Width, Clock
(Figure 1) 15 19 22 ns
tr, tf Maximum Input Rise and Fall
Times (Figure 1) 500 500 500 ns
SL74HCT574
System Logic
Semiconductor
SLS
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit Figure 5. Test Circuit
EXPANDED LOGIC DIAGRAM
SL74HCT574
System Logic
Semiconductor
SLS
