Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
http://www.cirrus.com
101 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
Advanced Multi-bit Delta-Sigma Architecture
24-bit Conversion
Supports All Audio Sample Rates Including
192 kHz
101 dB Dynamic Range at 5 V
-94 dB THD+N
90 mW Power Consumption
High-Pass Filter to Remove DC Offsets
Analog/Digital Core Supplies from 3.3 V to 5 V
Supports Logic Levels between 1.8 V and 5 V
Auto-detect Mode Selection in Slave Mode
Auto-Detect MCLK Divider
Pin Compatible with CS5341
General Description
The CS5340 is a complete analog-to-digital converter
for digital au dio sy stem s. It pe rfor ms sa mpling, analo g-
to-digital conversion, and anti-alias filtering, generating
24-bit values for both left and right inputs in serial form
at sample rates up to 200 kHz per channel.
The CS5340 uses a 5th-order, multi-bit Delta-Sigma
modulator followed by digital filtering and decimation,
which removes the need for an externa l anti-alias filter.
The CS5340 is available in a 16-pin TSSOP package
for Commercial (- 10° to +70° C) and Automotive grades
(-40° to +85° C). The CDB5340 Customer Demonstra-
tion Board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
Information” on page 22 for complete ordering
information.
The CS5340 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as set-top boxes, DVD-karaoke players, DVD record-
ers, A/V receivers, and automotive applications.
High-Pass
Filter
Low-Latency
Digital Filters
High-Pass
Filter
Serial Port
VA
3.3 V to 5 V
Internal
Reference
Voltages
Switch-Cap
ADC
VD
3.3 V to 5 V VL
1.8 V to 5 V
Auto-detect
MCLK D iv ider
Slave Mode
Auto-detect
Master Clock
Reset
Single-Ended
Analog Input
Low-Latency
Digital Filters
Switch-Cap
ADC
Mode
Configuration
Single-Ended
Analog Input
SCLK
LRCK
SDOUT
M0
M1
FILT+
VQ
AINR
AINL
March '08
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2DS601F2
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3/11/08
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4
SPECIFIED OPERATING CONDITIONS ............................................................................................... 4
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 4
ANALOG CHARACTERISTICS - COMMERCIAL GRADE .................................................................... 5
ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE ..................................................................... 6
DIGITAL FILTER CHARACTERISTICS .................................................................................................7
DC ELECTRICAL CHARA CTERISTIC S ....... .... ... ... ... .... ... ... ... .... ... ... ................... .... ... ... ... ................... 10
DIGITAL CHARACTERISTICS ............................................................................................................. 10
SWITCHING CHARAC TE RISTIC S - SERIA L AUDI O PORT ............... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 11
2. PIN DESCRIPTION .............................................................................................................................. 13
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 14
4. APPLICATIONS ................................................................................................................................... 15
4.1 Single-, Double-, and Quad-Speed Modes .....................................................................................15
4.2 Operation as Either a Clock Master or Slave ................................................................................. 15
4.2.1 Operation as a Clock Master ........................... ................... ... ... .................... ... ... ................... 16
4.2.2 Operation as a Clock Slave with Auto-Detect ....... ... .... ... ... ... .................... ... ... ... ... .... ... ... ... ... 16
4.2.3 Master Clock ......... ... ... ... .... ... ... ............................................................................................. 17
4.3 Serial Audio Interface ..................................................................................................................... 17
4.4 Power-Up Sequence ...................................................................................................................... 18
4.5 Analog Connections ....................................................................................................................... 18
4.6 Grounding and Power Supply Decoupling ................ ... ... ... .... ................... ... ... .... ... ................... ... ...18
4.7 Synchronization of Multiple Devices ............................................................................................... 18
4.8 Capacitor Size on the Reference Pin (FILT+) ................................................................................19
5. PARAMETER DEFINITIONS ................................................................................................................ 20
6. PACKAGE DIMENSIONS ................................................................................................................... 21
THERMAL CHARACTERISTICS .......................................................................................................... 21
7. ORDERING INFORMATION ................................................................................................................ 22
8. REVISION HISTORY ............................................................................................................................ 22
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LIST OF FIGURES
Figure 1.Single-Speed Mode Stopband Rejection ................. ... ................... .................... ................... ........ 8
Figure 2.Single-Speed Mode Stopband Rejection ................. ... ................... .................... ................... ........ 8
Figure 3.Single-Speed Mode Transition Band (Detail) ................................................................................ 8
Figure 4.Single-Speed Mode Passband Ripple .......................................................................................... 8
Figure 5.Double-Speed Mode Stopband Rejection ..................................................................................... 8
Figure 6.Double-Speed Mode Stopband Rejection ..................................................................................... 8
Figure 7.Double-Speed Mode Transition Band (Detail) .............................................................................. 9
Figure 8.Double-Speed Mode Passband Ripple ......................................................................................... 9
Figure 9.Quad-Speed Mode Stopband Rejection ....................................................................................... 9
Figure 10.Quad-Speed Mode Stopband Rejection ..................................................................................... 9
Figure 11.Quad-Speed Mode Transition Band (Detail) ............................................................................... 9
Figure 12.Quad-Speed Mode Passband Ripple ....... ... ... .... ... ... ... .... ... ... ... ... .................... ... ... ... .... .............. 9
Figure 13.Master Mode, Left-Justified SAI ................................................................................................ 12
Figure 14.Slave Mode, Left-Justified SAI .................................................................................................. 12
Figure 15.Master Mode, I²S SAI ................................................................................................................ 12
Figure 16.Slave Mode, I²S SAI .................................................................................................................. 12
Figure 17.Typical Connection Diagram ..................................................................................................... 14
Figure 18.CS5340 Master Mode Clocking ................................................................................................ 16
Figure 19.I²S Serial Audio Interface .......................................................................................................... 17
Figure 20.Left-Justified Serial Audio Interface .......................................................................................... 17
Figure 21.CS5340 Recommended Analog Input Buffer ............................................................................ 18
Figure 22.CS5340 THD+N versus Frequency .......................................................................................... 19
LIST OF TABLES
Table 1. Speed Modes and the Associated Output Sample Rat es (Fs) ........... ... ... ... .................... ............ 15
Table 2. CS5340 Mode Control ................................................................................................................. 15
Table 3. Master Clock (MCLK) Ratios ....................................................................................................... 17
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates ...................................... 17
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1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristic s an d spe cif icat ion s ar e derived from measurements taken at typical supply voltages
and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V.)
Notes: 1. This part is spec ified a t typica l anal og voltag es of 3.3 V a nd 5. 0 V. See A nalog Char acte ristics - Com-
mercial Grade and Analog Characterist ics - Automotive Grade, below, for details.
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 2)
2. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SRC latch-up.
4. The maximum over/under voltage is limited by the input current.
Parameter Symbol Min Typ Max Unit
Power Supplies Analog
Digital
Logic
VA
VD
VL
3.1
3.1
1.7
(Note 1)
3.3
3.3
5.25
5.25
5.25
V
V
V
Ambient Operating Temperature Commercial
Automotive TAC
TAC
-10
-40 -
-70
85 °C
°C
Parameter Symbol Min Max Units
DC Power Supplies: Analog
Logic
Digital
VA
VL
VD
-0.3
-0.3
-0.3
+6.0
+6.0
+6.0
V
V
V
Input Current (Note 3) Iin -10 +10 mA
Analog Input Voltage (Note 4) VIN GND-0.7 VA+0.7 V
Digital Input Voltage (Note 4) VIND -0.7 VL+0.7 V
Ambient Operating Temperature (Power Applied) TA-50 +95 °C
Storage Temperature Tstg -65 +150 °C
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ANALOG CHARACTERISTICS - COMMERCIAL GRADE
Test Conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is
10 Hz to 20 kHz.
5. Referred to the typical full-scale input voltage
Dynamic Performance for Commercial Grade VA = 5 V VA = 3.3 V
Single-Speed Mode Fs = 48 kHz Symbol Min Typ Max Min Typ Max Unit
Dynamic Range A-weighted
unweighted 95
92 101
98 -
-92
89 98
95 -
-dB
dB
Total Harmonic Distortion + Noise (Note 5)
-1 dB
-20 dB
-60 dB
THD+N -
-
-
-94
-78
-38
-88
-
-
-
-
-
-91
-75
-35
-85
-
-
dB
dB
dB
Double-Speed Mode Fs = 96 kHz Symbol Min Typ Max Min Typ Max Unit
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
95
92
-
101
98
95
-
-
-
92
89
-
98
95
92
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Note 5)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth -1 dB
THD+N -
-
-
-
-94
-78
-38
-91
-88
-
-
-
-
-
-
-
-91
-75
-35
-85
-85
-
-
-
dB
dB
dB
dB
Quad-Speed Mode Fs = 192 kHz Symbol Min Typ Max Min Typ Max Unit
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
95
92
-
101
98
95
-
-
-
92
89
-
98
95
92
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Note 5)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth -1 dB
THD+N -
-
-
-
-94
-78
-38
-91
-88
-
-
-
-
-
-
-
-91
-75
-35
-85
-85
-
-
-
dB
dB
dB
dB
Dynamic Performance All Modes Min Typ Max Unit
Interchannel Isolation - 90 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Gain Error -5 - +5 %
Gain Drift - ±100 - ppm/°C
Analog Input Characteristics
Full-Scale Input Vo ltage 0.53*VA 0.56*VA 0.59*VA Vpp
Input Impedance - 25 - kΩ
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ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE
Test Conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is
10 Hz to 20 kHz.
6. Referred to the typical full-scale input voltage
Dynamic Performance for Automotive Grade VA = 5 V VA = 3.3 V
Single-Speed Mode Fs = 48 kHz Symbol Min Typ Max Min Typ Max Unit
Dynamic Range A-weighted
unweighted 93
90 101
98 -
-90
87 98
95 -
-dB
dB
Total Harmonic Distortion + Noise (Note 5)
-1 dB
-20 dB
-60 dB
THD+N -
-
-
-94
-78
-38
-86
-
-
-
-
-
-91
-75
-35
-83
-
-
dB
dB
dB
Double-Speed Mode Fs = 96 kHz Symbol Min Typ Max Min Typ Max Unit
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
93
90
-
101
98
95
-
-
-
90
87
-
98
95
92
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Note 5)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth -1 dB
THD+N -
-
-
-
-94
-78
-38
-91
-86
-
-
-
-
-
-
-
-91
-75
-35
-85
-83
-
-
-
dB
dB
dB
dB
Quad-Speed Mode Fs = 192 kHz Symbol Min Typ Max Min Typ Max Unit
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
93
90
-
101
98
95
-
-
-
90
87
-
98
95
92
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Note 5)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth -1 dB
THD+N -
-
-
-
-94
-78
-38
-91
-86
-
-
-
-
-
-
-
-91
-75
-35
-85
-83
-
-
-
dB
dB
dB
dB
Dynamic Performance All Modes Min Typ Max Unit
Interchannel Isolation - 90 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Gain Error -10 - +10 %
Gain Drift - ±100 - ppm/°C
Analog Input Characteristics
Full-Scale Input Voltage 0.50*VA 0.56*VA 0.62*VA Vpp
Input Impedance - 25 - kΩ
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DIGITAL FILTER CHARACTERISTICS
7. Filter characteristics sca le precisely with Fs
8. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
Parameter Symbol Min Typ Max Unit
Single-Speed Mode
Passband (-0.1 dB) (Note 7) 0 - 0.4895 Fs
Passband Ripple -0.035 - 0.035 dB
Stopband (Note 7) 0.5687 - - Fs
Stopband Attenuation 70 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -12/Fs - s
Double-Speed Mode
Passband (-0.1 dB) (Note 7) 0 - 0.4895 Fs
Passband Ripple -0.025 - 0.025 dB
Stopband (Note 7) 0.5604 - - Fs
Stopband Attenuation 69 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -9/Fs - s
Quad-Speed Mode
Passband (-0.1 dB) (Note 7) 0 - 0.2604 Fs
Passband Ripple -0.025 - 0.025 dB
Stopband (Note 7) 0.5 - - Fs
Stopband Attenuation 60 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -5/Fs - s
High-Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 8) -1
20 -
-Hz
Hz
Phase Devia ti o n @ 20 Hz (Note 8) -10 -Deg
Passband Ripple -- 0dB
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Figure 1. Single-Speed Mode Stopband Rejection Figure 2. Single-Speed Mode Stopband Rejection
Figure 3. Single-Speed Mode Transition Band (Detail) Figure 4. Single-Speed Mode Passband Ripple
Figure 5. Double-Speed Mode Stopband Rejection Figure 6. Double-Speed Mode Stopband Rejection
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Amplitude (dB)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Amplitude (dB)
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Figure 7. Double-Speed Mode Transition Band (Detail) Figure 8. Double-Spe ed Mode Passband Ripple
Figure 9. Quad-Speed Mode Stopband Rejection Figure 10. Quad-Speed Mode Stopband Rejection
Figure 11. Quad-Speed Mode Transition Ban d (Detail) Figure 12. Quad-Speed Mode Passband Ripple
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.46 0.47 0.48 0.49 0.50 0.51 0.52
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Frequency (normalized to Fs)
Amplitude (dB)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (normalized to Fs)
Amplitude (dB)
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DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to 0 V. MCLK=12.288 MHz; Master Mode)
9. P ower Down Mode is defined as RST = Low, with all clocks and data lines held static at a valid logic
levels.
10. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram, Figure 17 on page 14.
DIGITAL CHARACTERISTICS
Parameter Symbol Min Typ Max Unit
DC Power Supplies: Positive Analog
Positive Digital
Positive Logic
VA
VD
VL
3.1
3.1
1.7
-
-
-
5.25
5.25
5.25
V
V
V
Power Supply Current VA = 5 V
(Normal Operation) VA = 3.3 V
VL,VD = 5 V
VL,VD = 3.3 V
IA
IA
ID
ID
-
-
-
-
21
18.2
15
9
25.5
22.5
18.5
10
mA
mA
mA
mA
Power Supply Current VA = 5 V
(Power-Down Mode) (Note 9) VL,VD=5 V IA
ID
-
-1.5
0.4 -
-mA
mA
Power Consumption VL, VD, VA = 5 V
(Normal Operation) VL, VD, VA = 3.3 V
(Power-Down Mode)
-
-
-
-
-
-
180
90
9.5
220
107.2
-
mW
mW
mW
Power Supply Rejection Ratio (1 kHz) (Note 10) PSRR - 65 - dB
VQ Nominal Voltage
Output Impedance -
-VA÷2
25 -
-V
kΩ
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
VA
36
0.01
-
-
-
V
kΩ
mA
Parameter Symbol Min Typ Max Units
High-Level Input Voltage (% of VL) VIH 70% - - V
Low-Level Input Voltage (% of VL) VIL --30%V
High-Level Output Voltage at Io = 100 µA(% of VL)
VOH 70% - - V
Low-Level Output Voltage at Io =100 µA(% of VL)
VOL --15%V
Input Leakage Current Iin -10 - +10 µA
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SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF)
11. For a description of speed modes, please refer to Table on page 15.
Parameter Symbol Min Typ Max Unit
MCLK Spec ifi ca ti o ns
MCLK Period tclkw 39 - 45 ns
78 - 1953 ns
MCLK Pulse Duty Cycle 40 - 60 %
Master Mode
SCLK falling to LRCK Single-Speed tmslr -20 - 20 ns
Double-Speed -20 - 20 ns
Quad-Speed -8 - 8 ns
SCLK falling to SDOUT valid. tsdo - - 32 ns
SCLK Duty Cycle. Single-Speed - 50 - %
Double-Speed -50-%
Quad-Speed -33-%
Slave Mode
Single-Spe e d (Not e 11 )
LRCK Duty Cycle 40 50 60 %
SCLK Period tsclkw 156 - - ns
SCLK Duty Cycle 45 50 55 %
SDOUT valid before SCLK rising tstp 10 - - ns
SDOUT valid after SCLK rising thld 5--ns
SCLK falling to LRCK edge tslrd -20 - 20 ns
Double-Speed (Note 11)
LRCK Duty Cycle 40 50 60 %
SCLK Period tsclkw 156 - - ns
SCLK Duty Cycle 45 50 55 %
SDOUT valid before SCLK rising tstp 10 - - ns
SDOUT valid after SCLK rising thld 5--ns
SCLK falling to LRCK edge. tslrd -20 - 20 ns
Quad-Speed (N ote 11)
LRCK Duty Cycle 40 50 60 %
SCLK Period tsclkw 78 - - ns
SCLK Duty Cycle 29.7 33 50 %
SDOUT valid before SCLK rising tstp 10 - - ns
SDOUT valid after SCLK rising thld 5--ns
SCLK falling to LRCK edge. tslrd -8 - 8 ns
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SCLK output
tmslr
SDOUT
tsdo
LRCK output
MSB MSB-1
Figure 13. Master Mode, Left-Justified SAI Figure 14. Slave Mode, Left-Justified SAI
LRCK input
SCLK input
SDOUT MSB
tstp thld
tsclkw
MSB-1
tslrd
Figure 15. Master Mode, I²S SA I Figure 16. Slave Mode, I²S SAI
SCLK output
tmslr
tsdo
LRCK output
MSB
SDOUT
LRCK input
SCLK input
SDOUT
tstp thld
tsclkw
MSB
tslrd
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2. PIN DESCRIPTION
Pin Name # Pin Description
M0
M1 1
16 Mode Selection (Input) - Determines the operational mode of the device.
MCLK 2 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VL 3 Logic Power (Input) - Positive power for the digital input/output.
SDOUT 4 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
GND 5,14 Ground (Input) - Ground reference. Must be connected to analog ground.
VD 6 Digital Power (Input) - Positive power suppl y for the digital section.
SCLK 7 Serial Clock (Input/Output) - Serial clock for the serial audio interfa c e.
LRCK 8 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently
active on the serial audio data line.
RST 9Reset (Input) - The device enters a low power mode when low.
AINL
AINR 10
12 Analog Input (Input) - The full-scale ana log input level is specified in the Analog Charac -
teristics specification table.
VQ 11 Quiescent Voltage (Output) - Filter connection for the internal quiescent
reference voltage.
VA 13 Analog Power (Input) - Positive power supply for the analog section.
FILT+ 15 Positive Voltage Reference (Output) - Positive reference voltage for the internal
sampling circuits.
M0 M1
MCLK FILT+
VL REF_GND
SDOUT VA
GND AINR
VD VQ
SCLK AINL
LRCK RST
1
2
3
4
5
6
7
8
5
1
2
6
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
5
1
2
6
16
15
14
13
12
11
10
9
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3. TYPICAL CONNECTION DIAGRAM
FILT+ V
0.1 µF
A/D CONVERTER
SCLK
CS5340
MCLK
VQ
1µF+
RST
VA L
1µF1.8 V to 5V
1µF
+
+
SDOUT
GND
LRCK
Power Down
and Mode
Settings
Audio Data
Processor
Timing Logic
and Clock
0.1 µF
0.1 µF
0.1 µF
REFGND
1µF
+
AINL
AINR
3.3V to 5V
1µF
+0.1 µF
3.3V to 5V
Ω
5.1
VD
0.1 µF
Ω
10k
VL or GND
* Pull-up to VL for I2S
Pull-down to GND for LJ
*
M0
M1
Analog Input Buffer
Figure 21
**
** Resistor may only be
used if VD is derived from
VA. If used, do not drive
any other logic from VD
***
*** C a p a c ito r v a lu e af fe c ts
low frequency distortion
performance as described
in Section 4.8
DS601F2 15
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4. APPLICATIONS
4.1 Single-, Double-, and Quad-Speed Modes
The CS5340 can sup port ou tput samp le rate s from 2 kHz to 200 kHz. The prop er speed m ode ca n be de-
termined by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1.
Table 1. Speed Modes and the Associated Output Sample Rates (Fs)
4.2 Operation as Either a Clock Master or Slave
The CS5340 supports operation as either a clock master or slave. As a clock master, the LRCK an d SCLK
pins are outputs with the left/right and serial clocks synchronously gene rate d on -chi p. As a clock slave, th e
LRCK and SCLK pins are inputs and require the left/right and serial clocks to be externally generated. The
selection of clock master or slave is made via the Mod e pins as shown in Table 2.
Speed Mode MCLK/LRCK
Ratio Output Sample Rate Range (kHz)
Single-Speed Mode 512x 43 - 50
256x 2 - 50
Double-Speed Mode 256x 86 - 100
128x 4 - 100
Quad-Speed Mode 128x 172 - 200
64x* 100 - 200
* Quad-Speed Mode, 64x onl y available in Master Mode.
M1 (Pin 16) M0 (Pin 1) MODE
00
Clock Master, Single-Speed Mode
01
Clock Master, Double-Speed Mode
10
Clock Master, Quad-Speed Mode
11
Clock Slave, All Speed Modes
Table 2. CS5340 Mode Control
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4.2.1 Operation as a Clock Master
As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally de-
rived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as
shown in Figure 18.
4.2.2 Operation as a Clock Slave with Auto-Detect
LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be
synchronously derived from the master cloc k and must be equal to Fs. It is also re commended that the
serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system
performance.
A unique feature of the CS5340 is the automatic selection of either Single-, Double- or Quad-Speed mode
when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode
pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio
sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are
not supported when operating with a fast MCLK (512x, 256x, 128x for Sing le-, Double-, a nd Quad-Speed
Modes, respectively). Please refer to Table for supported sample rate ranges.
÷ 128
÷ 256
÷ 64
M0M1
LRCK Output
(Equal to Fs)
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 2
÷ 4
÷ 1
SCLK Output
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 2
÷ 1 0
1
MCLK
Auto-Select
Figure 18. CS5340 Master Mode Clocking
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4.2.3 Master Clock
The CS5340 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters.
There is also an internal MCLK divider which is automatically activated based on the speed mode and
frequency of the MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required.
Table 4 lists some common audio output sample rates and the required MCLK frequency. Please note
that not all of the listed sample rates are supported when operating with a fast MCLK (512x, 256x, 128x
for Single-, Double-, and Quad-Speed Modes, respective ly).
4.3 Serial Audio Interface
The CS5340 supports both I²S and Left-Justified serial audio formats. Upon start-up, the CS5340 will detect
the logic level on SDOUT (pin 4). A 10 kΩ pull-up to VL is needed to select I²S format, and a 10 kΩ pull-
down to GND is needed to select Left-Justified format. Figures 19 an d 20 illustrate the I²S and Left-Justified
audio formats. Please see Figures 13 through 16, for more information on the required timing for the two
serial audio in terface format s. Also see Applica tion Note AN282 for a detailed discussion of the serial audio
interface formats.
Single-Speed Mode Double-Speed Mode Quad-Speed Mode
MCLK/LRCK Ratio 256x, 512x 128x, 256x 64x*,128x
* Quad Speed, 64x only available in Master Mode.
Table 3. Master Clock (MCLK) Ratios
SAMPLE RATE (kHz) MCLK (MHz)
32 8.192
44.1 11.2896
22.5792
48 12.288
24.576
64 8.192
88.2 11.2896
22.5792
96 12.288
24.576
192 12.288
24.576
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates
SDATA 23 22 8 723 22
SCLK
LRCK
23 2265432108765432109 9
Left Channel Right Channel
Figure 19. I²S Serial Audio Interface
SDATA 23 22 7 623 22
SCLK
LRCK
23 2254321087654321089 9
Left Channel Right Channel
Figure 20. Left-Justified Serial Audio Interface
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4.4 Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies
drop below the minimum specified operating voltages to prevent power-glitch-related issues.
4.5 Analog Connections
The analog modulato r samples the input at half of the MCLK frequency, or nominally 6.144 MHz. The digital
filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which
are multiples of the input sampling frequency (n ×6.144 MHz), where n=0,1,2,... Refer to Figure 21 which
shows the suggested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the
optimum source impedan ce for the modulators. The use of capacitors which have a large voltage coefficient
(such as gen er al pu rp os e ce ra mic s ) m ust be av oided since these can degrade signal linearity.
4.6 Grounding and Power Supply Decoupling
As with any high-resolution converter, achie ving optimal performa nce from the CS5340 requires care ful at-
tention to power supply and grounding arrangements. Figure 17 shows the recommended power arrange-
ments, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run fr om the
system logic supply or may be powered from the analog supply via a resistor. In this case, no additional
devices should be powe red from VD. Decoupling cap acitors should be as near to the ADC as possible, with
the low-value ceramic capacito r being the near est. All signals, especially clocks, should be kept away from
the FILT+ and VQ pin s in or der to avoid unwanted coupling into the modu lators. The FILT+ and VQ decou-
pling capacitors, particularly the 0 .01 µF, must be positioned to mini mize the electrical p ath from FILT+ and
REF_GND. Furthermore, all ground pins on CS5340 should be referenced to the same ground reference.
The CDB5340 evaluation board demonstrates the optimum layout and power supply arrangements. To min-
imize digital noise, connect the ADC digital outputs only to CMOS inputs.
4.7 Synchronization of Multiple Devices
In systems where multiple ADCs are required, the user can achieve simultaneous sampling if the MCLK and
LRCK signals are the same for all o f the CS5340’s in the system. If only one master clock source is needed,
one solution is to place o ne CS5340 in Master mode, and slave a ll of the other CS5340’s to the one master.
If multiple master clock sources are needed , a possible solution would be to supply all clocks from the same
external source and time the CS5340 reset with the inactive (falling) edge of MCLK. This will ensure that all
converters begin sampling on the same clock edge.
Figure 21. CS5340 Recommended Analog Input Buffer
100 kΩ
100 kΩ
VA
4.7 µF
470 pF
C0G
634 Ω
91 Ω
2700 pF
CS53 40 A INx
AINx
DS601F2 19
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4.8 Capacitor Size on the Reference Pin (FILT+)
The CS5340 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this
decoupling capacitor will affect the low frequency distortion performance as shown in Figure 22, with larger
capacitor values used to optimize low frequency distortion performance. This plot was taken using the
CDB5340 evaluation platform, with the device running in Single-Speed Mode and VA=VD=VL=5 V.
Figure 22. CS5340 THD+N versus Frequency
47 uF
100 uF
22 uF
10 uF
6.8 uF
4.7 uF
3.3 uF
2.2 uF
1 uF
5.6 uF
20 DS601F2
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5. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms va lue of the signa l to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Ra nge is a signal- to-noise ratio measurement over the specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the measure-
ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expres sed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms va lue of the signa l to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of th e am p litu de r es po ns e varia tio n f ro m 1 0 Hz to 20 kHz r ela tiv e to th e amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci-
bels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog input for a full-scale digital output.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid- scale transition (111...111 to 000...000) from the ideal. Units in mV.
DS601F2 21
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6. PACKAGE DIMENSIONS
1. “D” and “E1” are reference datums and do not included mold flash or protrusion s, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar in trusion shall not re-
duce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
THERMAL CHARACTERISTICS
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A -- -- 0.043 -- -- 1.10
A1 0.002 0.004 0.006 0.05 -- 0.15
A2 0.03346 0.0354 0.037 0.85 0.90 0.95
b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3
D 0.193 0.1969 0.201 4.90 5.00 5.10 1
E 0.248 0.2519 0.256 6.30 6.40 6.50
E1 0.169 0.1732 0.177 4.30 4.40 4.50 1
e -- 0.026 BSC -- -- 0.65 BSC --
L 0.020 0.024 0.028 0.50 0.60 0.70
µ0° 4° 8° 0° 4° 8°
JEDEC #: MO-153
Controlling Dimension is Millimeters
Parameter Symbol Min Typ Max Unit
Allowable Junction Temperature - - 135 °C
Junction to Ambient Thermal Impedance θJA -75-
°C/W
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
E
N
123
eb2A1
A2 A
D
SEATING
PLANE
E11
L
SIDE VIEW
END VIEW
TOP VIEW
∝
22 DS601F2
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7. ORDERING INFORMATION
8. REVISION HISTORY
Product Description Package Pb-Free Grade Temp Range Container Order #
CS5340 101 dB, 192 kHz, Multi-Bit
Audio A/D Converter 16-TSSOP YES Commercial -10° to +70° C Bulk CS5340-CZZ
Tape & Reel CS5340-CZZR
CS5340 101 dB, 192 kHz, Multi-Bit
Audio A/D Converter 16-TSSOP YES Automotive -40° to +85° C Bulk CS5340-DZZ
Tape & Reel CS5340-DZZR
CDB5340 CS5340 Evaluation Board - - - - - CDB5340
Release Changes
PP3
Remove CS5340-CZ from Ordering Information
Redefine Serial Audio Port Switching Cha ra c teristics
Correct dimension “e” under Package Dimensions
Update Output Sample Rate Range
F1 Update maximum current and power specifications
Update Filt+ output impedance specification
F2 Reduced minimum sample rate to 4 kHz for Double-Speed Mode 128x in Table 1 on page 15
Updated Legal Text
Contacting Cirrus Logic Support
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To find the one nearest to you, go to www.cirrus.com.
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