Revision 2.0
April 2002
1
R0201-BS616LV2018
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
• Very low operation voltage : 2.4 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 16mA (Max.) operating current
I -grade: 20mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV2018 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
The BS616LV2018 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2018 is available in DICE form, JEDEC standard 48-pin
TSOP Type I package and 48-ball BGA package.
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor Inc.reserves the right to modify document contents without notice.
Row
Decoder
Memory Array
1024 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A3 A2 A1
Data
Buffer
Input
Control
Gnd
Vcc
OE
WE
CE
DQ15
DQ0
A16
A5
A6
A7
A15
A13
16
16
16
16
14
128
2048
1024
20
A14
A12
A9
A4
A0
A11
A8
Address
Input
Buffer
A10
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
BS616LV2018
G
H
F
E
D
C
A9A8
D15
D14
VSS
D9
D13
A12
A14
D12
D11
D10 A5
B
A
D8
LB
1
UB
OE
A3
A0
23
A11A10
A13
A15
WE
D5
A16
A7
A6
D4
D3
D1
D7
D6
D2
A4
A1 A2
45
D0
6
N.C.
VCC VSS
VCC
N.C.
CE
N.C.
N.C.
N.C.
N.C.
48-ball BGA top view
BSI
POWER DISSIPATION
SPEED
(ns) STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE Vcc=
3.0V Vcc=3.0V Vcc=3.0V
PKG TYPE
BS616LV2018DC DICE
BS616LV2018TC TSOP1-48
BS616LV2018AC
0 O C to +70 O C700.7 uA
16 mA
BGA-48-0608
BS616LV2018DI DICE
BS616LV2018TI TSOP1-48
BS616LV2018AI
-40 O C to +85 O C
2.4V ~3.6V
70 1.5 uA 20 mA
BGA-48-0608
Revision 2.0
April 2002
2
R0201-BS616LV2018
Name Function
A0-A16 Address Input These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE Chip Enable Input CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins.
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc Power Supply
Gnd Ground
TRUTH TABLE
PIN DESCRIPTIONS
BSI BS616LV2018
MODE CE WE OE LB UB DQ0~DQ7 DQ8~DQ15 Vcc CURRENT
Not selected
(Power Down B1
)HXXXX High Z High Z I
CCSB, ICCS
Output Disabled L H H X X High Z High Z ICC
L L Dout Dout ICC
H L High Z Dout ICC
Read L H L
L H Dout High Z ICC
LL Din Din I
CC
HL X Din I
CC
Write L L X
LH Din X I
CC
Revision 2.0
April 2002
3
PARAMETER
NAME PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS
VIL Guaranteed Input Low
Voltage(2) Vcc=3.0V -0.5 -- 0.8 V
VIH Guaranteed Input High
Voltage(2) Vcc=3.0V 2.0 -- Vcc+0.2 V
IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA
IOL Output Leakage Current Vcc = Max, CE = VIH, or OE = VIH,
VI/O = 0V to Vcc -- -- 1 uA
VOL Output Low Voltage Vcc = Max, IOL = 2mA Vcc=3.0V -- -- 0.4 V
VOH Output High Voltage Vcc = Min, IOH = -1mA Vcc=3.0V 2.4 -- -- V
ICC Operating Power Supply
Current CE = VIL, IDQ = 0mA, F = Fmax(3) Vcc=3.0V -- -- 16 mA
ICCSB Standby Current-TTL CE = VIH, IDQ = 0mA Vcc=3.0V -- -- 1 mA
ICCSB1 Standby Current-CMOS
CE Њ Vcc-0.2V,
VIN Њ Vcc - 0.2V or VIN Љ 0.2V Vcc=3.0V -- 0.1 0.7 uA
R0201-BS616LV2018
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS
VDR Vcc for Data Retention CE Њ Vcc - 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V 1.5 -- -- V
ICCDR Data Retention Current CE Њ Vcc - 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V -- 0.05 0.5 uA
tCDR
Chip Deselect to Data
Retention Time 0 -- -- ns
tROperation Recovery Time
See Retention Waveform
TRC
(2) -- -- ns
SYMBOL PARAMETER CONDITIONS MAX. UNIT
CIN Input
Capacitance VIN=0V 6 pF
CDQ Input/Output
Capacitance VI/O=0V 8 pF
RANGE AMBIENT
TEMPERATURE Vcc
Commercial 0 OC to +70 OC2.4V ~ 3.6V
Industrial -40 OC to +85 OC2.4V ~ 3.6V
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
1. Vcc = 1.5V, TA= + 25OC
2. tRC = Read Cycle Time
ABSOLUTE MAXIMUM RATINGS(1) OPERATING RANGE
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL PARAMETER RATING UNITS
VTERM Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5 V
TBIAS Temperature Under Bias C-40 to +125 O
TSTG Storage Temperature C-60 to +150 O
PTPower Dissipation 1.0 W
IOUT DC Output Current 20 mA
BSI BS616LV2018
Revision 2.0
April 2002
4
R0201-BS616LV2018
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CAR
ANY CHANG
PERMITTED
E: CHANGE :
E STATE
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
CE
Data Retention Mode
Vcc
tCDR
Vcc
tR
VIHVIH
Vcc VDR 1.5V
≥
CE Vcc - 0.2V
≥
BSI BS616LV2018
Ω667
THEVENIN EQUIVALENT
ALL INPUT PULSES
→
10%
←
90%
Vcc
GND
→←5ns
90% 10%
1.73V
OUTPUT
FIGURE 2
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
1269
Ω
1404
5PF
FIGURE 1B
Ω
3.3V
INCLUDING
JIG AND
SCOPE
1269
Ω
100PF
FIGURE 1A
Ω
1404
OUTPUT
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME DESCRIPTION BS616LV2018-70
MIN. TYP. MAX.
tAVAX tRC Read Cycle Time 70 -- --
tAVQV tAA Address Access Time -- -- 70
tELQV tACS Chip Select Access Time (CE) -- -- 70
tBA Data Byte Control Access Time (LB,UB) -- -- 35
tBA
tGLQV tOE Output Enable to Output Valid -- -- 35
tE1LQX tCLZ Chip Select to Output Low Z (CE) 10 -- --
tBE tBE Data Byte Control to Output Low Z (LB,UB) 10 -- --
tGLQX tOLZ Output Enable to Output in Low Z 10 -- --
tEHQZ tCHZ Chip Deselect to Output in High Z (CE) 0 -- 35
tBDO tBDO Data Byte Control to Output High Z (LB,UB) 0 -- 35
tGHQZ tOHZ Output Disable to Output in High Z 0--30
tAXOX tOH Output Disable to Address Change 10 -- --
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. tBA is 35ns (@speed=70ns) with address toggle. ; .tBA is 70ns (@speed=70ns) without address toggle.
NOTE :
(1)
Revision 2.0
April 2002
5
R0201-BS616LV2018
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. Transition is measured 500mV from steady state with CL= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
±
BSI BS616LV2018
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
tRC
tOH
tAA
DOUT
ADDRESS
tOH
tOH
READ CYCLE3 (1,4)
tRC
tOE
DOUT
LB,UB
CE
OE
ADDRESS
tCLZ
(5) tACS
tCHZ
(1,5)
tOHZ (5)
tOLZ
tAA
READ CYCLE2 (1,3,4)
tCLZ
tCHZ
(5)
DOUT
LB,UB
CE
(5)
tBA
tACS
tBE tBDO
tBDO
tBA
tBE
Revision 2.0
April 2002
6
R0201-BS616LV2018
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
WRITE CYCLE
BSI BS616LV2018
tWR
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
tWC
(3)
tCW
(11)
tBW
(2)
tWP
tAW
tOHZ
(4,10)
tAS
(3)
tDH
tDW
DIN
DOUT
WE
LB,UB
CE
OE
ADDRESS
(5)
JEDEC
PARAMETER
NAME
PARAMETER
NAME DESCRIPTION BS616LV2018-70
MIN. TYP. MAX.
tAVAX Write Cycle Time
tWC 70 -- --
tE1LWH tCW Chip Select to End of Write 70 -- --
tAVWL tAS Address Setup Time 0----
tAVWH tAW Address Valid to End of Write 70 -- --
tWLWH tWP Write Pulse Width 35 -- --
tWHAX tWR Write recovery Time (CE,WE) 0 -- --
tBW tBW Date Byte Control to End of Write (LB,UB) 30 -- --
tWLQZ tWHZ Write to Output in High Z 0--30
tDVWH tDW Data to Write Time Overlap 30 -- --
tWHDX tDH Data Hold from Write Time 0----
tGHQZ tOHZ Output Disable to Output in High Z 0--30
tWHOX tOW End of Write to Output Active 5----
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. tBW is 30ns (@speed=70ns) with address toggle. ; tBW is 70ns (@speed=70ns) without address toggle.
(1)
NOTE :
Revision 2.0
April 2002
7
R0201-BS616LV2018
BSI BS616LV2018
WRITE CYCLE2 (1,6)
tWC
tCW
(11)
(2)
tWP
tAW
tWHZ
(4,10)
tAS
tWR
(3)
tDH
tDW
DIN
DOUT
WE
CE
ADDRESS
(5)
tDH
(7) (8)
(8,9)
tBW
LB,UB
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
±
Revision 2.0
April 2002
8
R0201-BS616LV2018
PACKAGE
T: TSOP 1 - 48 PIN
A: BGA - 48 PIN (6x8mm)
D: DICE
ORDERING INFORMATION
BSI
BS616LV2018 X X -- Y Y
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
SPEED
70: 70ns
BS616LV2018
Revision 2.0
April 2002
9
R0201-BS616LV2018
BSI BS616LV2018
PACKAGE DIMENSIONS
1
24
24
D
1
C
L
HD
48
SECTION A-A
BASE METAL
WITH PLATING
cc1
b1
b
0.02360.006
0.0200.004
0.004 ~ 0.006
0.004 ~ 0.008
0.0080.001
0.0090.002
0.04330.004
0~ 8
0.004 Max.
0.03150.004
0.7080.008
0.4720.004
0.6450.004
0.0390.002
0.0040.002
25
"A"
25 Seating Plane
48
12(2X)
E
be12(2X)
D
y
Ӱ
L1
y
L
HD
e
E
SYMBOL
UNIT
b
c1
b1
c
A2
A1
A
16.400.10
0.500.10
0.800.10
0.600.15
18.000.20
12.000.10
0~ 8
0.1 Max.
0.10 ~ 0.16
0.10 ~ 0.21
0.200.03
0.220.05
1.000.05
0.100.05
1.100.10
MMINCH
12(2x)
"A" DETAIL VIEW L1
GAUGE PLANE
A1
A
A2
SEATING PLANE
12(2x) L
A
A
0
0.254
TSOP1-48PIN
24 25
148
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
/WE
CE2
NC
/UB
/LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
9
10
13
16
17
A16
NC
VSS
IO15
IO7
IO14
IO6
IO13
IO5
IO12
IO4
VCC
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
/OE
VSS
/CE
A0
47
48TSOP(I)-12x18mm
Pkg Type :
37
27
46
Revision 2.0
April 2002
10
R0201-BS616LV2018
BSI BS616LV2018
48 mini-BGA (6 x 8)
D1
VIEW A
1.4 Max.
e
E1
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
8.0 6.0
EN
48 3.75
E1D1
5.25
NOTES:
PACKAGE DIMENSIONS (continued)
Revision 2.0
April 2002
11
BSI
REVISION HISTORY
Revision Description Date Note
1.0 Data Sheet release Jan. 30, 2001
2.0 Modify some AC parameters April,12,2002
BS616LV2018
R0201-BS616LV2018
