© Semiconductor Components Industries, LLC, 2014
October, 2016 − Rev. 24 1Publication Order Number:
NCP1010/D
NCP1010, NCP1011,
NCP1012, NCP1013,
NCP1014
Self-Supplied Monolithic
Switcher for Low Standby-
Power Offline SMPS
The NCP101X series integrates a fixed−frequency current−mode
controller and a 700 V MOSFET. Housed in a PDIP−7 or SOT−223
package, the NCP101X offers everything needed to build a rugged and
low−cost power supply, including soft−start, frequency jittering,
short−circuit protection, skip−cycle, a maximum peak current setpoint
and a Dynamic Self−Supply (no need for an auxiliary winding).
Unlike other monolithic solutions, the NCP101X is quiet by nature:
during nominal load operation, the part switches at one of the available
frequencies (65 − 100 − 130 kHz). When the current setpoint falls
below a given value, e.g. the output power demand diminishes, the IC
automatically enters the so−called skip−cycle mode and provides
excellent ef ficiency at light loads. Because this occurs at typically 1/4
of the maximum peak value, no acoustic noise takes place. As a result,
standby power is reduced to the minimum without acoustic noise
generation.
Short−circuit detection takes place when the feedback signal fades
away, e.g. in true short−circuit conditions or in broken Optocoupler
cases. External disabling is easily done either simply by pulling the
feedback pin down or latching it to ground through an inexpensive
SCR for complete latched−off. Finally soft−start and frequency
jittering further ease the designer task to quickly develop low−cost and
robust offline power supplies.
For improved standby performance, the connection of an auxiliary
winding stops the DSS operation and helps to consume less than
100 mW at high line. In this mode, a built−in latched overvoltage
protection prevents from lethal voltage runaways in case the
Optocoupler would brake. These devices are available in economical
8−pin dual−in−line and 4−pin SOT−223 packages.
Features
•Built−in 700 V MOSFET with Typical RDSon of 11 W
and 22 W
•Large Creepage Distance Between High−Voltage Pins
•Current−Mode Fixed Frequency Operation:
65 kHz – 100 kHz − 130 kHz
•Skip−Cycle Operation at Low Peak Currents Only:
No Acoustic Noise!
•Dynamic Self−Supply, No Need for an Auxiliary
Winding
•Internal 1.0 ms Soft−Start
•Latched Overvoltage Protection with Auxiliary
Winding Operation
•Frequency Jittering for Better EMI Signature
•Auto−Recovery Internal Output Short−Circuit
Protection
•Below 100 mW Standby Power if Auxiliary Winding
is Used
•Internal Temperature Shutdown
•Direct Optocoupler Connection
•SPICE Models Available for TRANsient Analysis
•These are Pb−Free and Halide−Free Devices
Typical Applications
•Low Power AC/DC Adapters for Chargers
•Auxiliary Power Supplies (USB, Appliances,TVs, etc.)
PDIP−7
CASE 626A
AP SUFFIX
1
8
MARKING
DIAGRAMS
P101xAPyy
AWL
YYWWG
1
See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.
ORDERING INFORMATION
SOT−223
CASE 318E
ST SUFFIX
1
4AYW
101xy G
G
1
4
x = Current Limit (0, 1, 2, 3, 4)
y = Oscillator Frequency
A (65 kHz), B (100 kHz), C (130 kHz)
yy = 06 (65 kHz), 10 (100 kHz), 13 (130 kHz)
A = Assembly Location
WL = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
www.onsemi.com
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
2
1
VCC 8GND
2
NC
3
GND
4
FB
7GND
5DRAIN
(Top View)
PIN CONNECTIONS
PDIP−7 SOT−223
(Top View)
1
2
3
4
VCC
FB
DRAIN
GND
Indicative Maximum Output Power from NCP1014
RDSon − Ip 230 Vac 100 − 250 Vac
11 W − 450 mA DSS 14 W 6.0 W
11 W − 450 mA Auxiliary Winding 19 W 8.0 W
1. Informative values only, with: Tamb = 50°C, Fswitching = 65 kHz, circuit mounted on minimum copper area as recommended.
Figure 1. Typical Application Example
27
3
45
18
100−250 Vac
+
+
NCP101X
Vout
+
GND
Quick Selection Table
NCP1010 NCP1011 NCP1012 NCP1013 NCP1014
RDSon [W]22 11
Ipeak [mA] 100 250 250 350 450
Freq [kHz] 65 100 130 65 100 130 65 100 130 65 100 130 65 100
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
3
PIN FUNCTION DESCRIPTION
Pin No.
(SOT−223) Pin No.
(PDIP−7) Pin Name Function Description
1 1 VCC Powers the Internal Circuitry This pin is connected to an external capacitor of typic-
ally 10 mF. The natural ripple superimposed on the
VCC participates to the frequency jittering. For im-
proved standby performance, an auxiliary VCC can be
connected to Pin 1. The VCC also includes an active
shunt which serves as an opto fail−safe protection.
− 2 NC − −
− 3 GND The IC Ground −
2 4 FB Feedback Signal Input By connecting an optocoupler to this pin, the peak
current setpoint is adjusted accordingly to the output
power demand.
3 5 Drain Drain Connection The internal drain MOSFET connection.
− − − − −
− 7 GND The IC Ground −
4 8 GND The IC Ground −
65, 100 or
130 kHz
Clock
Overload?
UVLO
Management
G
ND
NC
VCC
FB Dra
in
GN
D
GN
D
Figure 2. Simplified Internal Circuit Architecture
2
1
3
4
IVCC I?
Vclamp*
4 V
18 k
Error flag armed?
EMI Jittering
VCC Startup Source Drain
Flip−Flop
DCmax = 65%
Reset
Reset
High when VCC t 3 V
Driver
S
Q
R
−
+
Iref = 7.4 mA
IVCC
Set Q
VCC
8
Rsense
250 ns
L.E.B.
7
5
−
+
+
-
Soft−Start Startup Sequence
Overload
−
+
0.5 V
Drain
*Vclamp = VCCOFF + 200 mV (8.7 V Typical)
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
4
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MAXIMUM RATINGS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Rating
ÁÁÁÁÁ
ÁÁÁÁÁ
Symbol
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Value
ÁÁÁÁ
ÁÁÁÁ
Unit
Power Supply Voltage on all pins, except Pin 5 (Drain) VCC −0.3 to 10 V
Drain Voltage −−0.3 to 700 V
Drain Current Peak during Transformer Saturation NCP1010/11
NCP1012/13/14 IDS(pk) 550
1.0 mA
A
Maximum Current into Pin 1 when Activating the 8.7 V Active Clamp I_VCC 15 mA
Thermal Characteristics
P Suffix, Case 626A
Junction−to−Lead
Junction−to−Air, 2.0 oz (70 mm) Printed Circuit Copper Clad
0.36 Sq. Inch (2.32 Sq. Cm)
1.0 Sq. Inch (6.45 Sq. Cm)
ST Suffix, Plastic Package Case 318E
Junction−to−Lead
Junction−to−Air, 2.0 oz (70 mm) Printed Circuit Copper Clad
0.36 Sq. Inch (2.32 Sq. Cm)
1.0 Sq. Inch (6.45 Sq. Cm)
RqJL
RqJA
RqJL
RqJA
9.0
77
60
14
74
55
°C/W
Maximum Junction Temperature TJmax 150 °C
Storage Temperature Range −−60 to +150 °C
ESD Capability, Human Body Model (All pins except HV) − 2.0 kV
ESD Capability, Machine Model − 200 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C,
VCC = 8.0 V unless otherwise noted.)
Rating Pin Symbol Min Typ Max Unit
SUPPLY SECTION AND VCC MANAGEMENT
VCC Increasing Level at which the Current Source Turns−off 1 VCCOFF 7.9 8.5 9.1 V
VCC Decreasing Level at which the Current Source Turns−on 1 VCCON 6.9 7.5 8.1 V
Hysteresis between VCCOFF and VCCON 1 − − 1.0 − V
VCC Decreasing Level at which the Latch−off Phase Ends 1 VCClatch 4.4 4.7 5.1 V
VCC Decreasing Level at which the Internal Latch is Released 1 VCCreset − 3.0 − V
Internal IC Consumption, MOSFET Switching at 65 kHz (Note 2) 1 ICC1 − 0.92 1.1 mA
Internal IC Consumption, MOSFET Switching at 100 kHz (Note 2) 1 ICC1 − 0.95 1.15 mA
Internal IC Consumption, MOSFET Switching at 130 kHz (Note 2) 1 ICC1 − 0.98 1.2 mA
Internal IC Consumption, Latch−off Phase, VCC = 6.0 V 1 ICC2 − 290 − mA
Active Zener Voltage Positive Offset to VCCOFF 1 Vclamp 140 200 300 mV
Latch−off Current
NCP1012/13/14 0°C < TJ < 125°C
−40°C < TJ < 125°C
NCP1010/11 0°C < TJ < 125°C
−40°C < TJ < 125°C
1 ILatch 6.3
5.8
5.8
5.3
7.4
7.4
7.3
7.3
9.2
9.2
9.0
9.0
mA
POWER SWITCH CIRCUIT
Power Switch Circuit On−state Resistance
NCP1012/13/14 (Id = 50 mA) TJ = 25°C
TJ = 125°C
NCP1010/11 (Id = 50 mA) TJ = 25°C
TJ = 125°C
5 RDSon −11
19
22
38
16
24
35
50
W
2. See characterization curves for temperature evolution.
3. Adjust di/dt to reach Ipeak in 3.2 msec.
4. See characterization curves for temperature evolution.
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
5
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C,
VCC = 8.0 V unless otherwise noted.)
Rating UnitMaxTypMinSymbolPin
POWER SWITCH CIRCUIT
Power Switch Circuit and Startup Breakdown Voltage
(ID(off) = 120 mA, TJ = 25°C) 5 BVdss 700 − − V
Power Switch and Startup Breakdown Voltage Off−state Leakage Current
TJ = −40°C (Vds = 650 V)
TJ = 25°C (Vds = 700 V)
TJ = 125°C (Vds = 700 V)
5
5
5
IDS(OFF)−
−
−
70
50
30
120
−
−
mA
Switching Characteristics (RL = 50 W, Vds Set for Idrain = 0.7 x Ilim)
T urn−on Time (90%−10%)
T urn−off Time (10%−90%) 5
5ton
toff −
−20
10 −
−
ns
INTERNAL STARTUP CURRENT SOURCE
High−voltage Current Source, VCC = 8.0 V
NCP1012/13/14 0°C < TJ < 125°C
−40°C < TJ < 125°C
NCP1010/11 0°C < TJ < 125°C
−40°C < TJ < 125°C
1 IC1 5.0
5.0
5.0
5.0
8.0
8.0
8.0
8.0
10
11
10.3
11.5
mA
High−voltage Current Source, VCC = 0 1 IC2 − 10 − mA
Minimum Start−up Drain Voltage (Istart = 0.5 mA, Vcc = Vcc(on) − 0.2 V) 5 Vstart(min) − 15 − V
CURRENT COMPARATOR TJ = 25°C (Note 2)
Maximum Internal Current Setpoint, NCP1010 (Note 3) 5Ipeak (22) 90 100 110 mA
Maximum Internal Current Setpoint, NCP1011 (Note 3) 5Ipeak (22) 225 250 275 mA
Maximum Internal Current Setpoint, NCP1012 (Note 3) 5Ipeak (11) 225 250 275 mA
Maximum Internal Current Setpoint, NCP1013 (Note 3) 5Ipeak (11) 315 350 385 mA
Maximum Internal Current Setpoint, NCP1014 (Note 3) 5Ipeak (11) 405 450 495 mA
Default Internal Current Setpoint for Skip−Cycle Operation, Percentage of
Max Ip − ILskip − 25 − %
Propagation Delay from Current Detection to Drain OFF State − TDEL − 125 − ns
Leading Edge Blanking Duration − TLEB − 250 − ns
INTERNAL OSCILLATOR
Oscillation Frequency, 65 kHz Version, TJ = 25°C (Note 4) − fOSC 59 65 71 kHz
Oscillation Frequency, 100 kHz Version, TJ = 25°C (Note 4) − fOSC 90 100 110 kHz
Oscillation Frequency, 130 kHz Version, TJ = 25°C (Note 4) − fOSC 117 130 143 kHz
Frequency Dithering Compared to Switching Frequency
(with active DSS) − fdither −"3.3 − %
Maximum Duty−cycle − Dmax 62 67 72 %
FEEDBACK SECTION
Internal Pull−up Resistor 4 Rup − 18 − kW
Internal Soft−Start (Guaranteed by Design) −Tss − 1.0 − ms
SKIP−CYCLE GENERATION
Default Skip Mode Level on FB Pin 4 Vskip − 0.5 − V
TEMPERATURE MANAGEMENT
Temperature Shutdown − TSD 140 150 160 °C
Hysteresis in Shutdown − − − 50 − °C
2. See characterization curves for temperature evolution.
3. Adjust di/dt to reach Ipeak in 3.2 msec.
4. See characterization curves for temperature evolution.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
6
TYPICAL CHARACTERISTICS
Figure 3. IC1 @ VCC = 8.0 V, FB = 1.5 V
vs. Temperature
−12
−9
−8
−7
−6
−5
−4
−3
−2
−20 0 20 40 60 100 120
TEMPERATURE (°C)
IC1 ( mA)
Figure 4. ICC1 @ VCC = 8.0 V, FB = 1.5 V
vs. Temperature
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
−20 0 20 40 60 100 120
TEMPERATURE (°C)
ICC1 (mA)
Figure 5. ICC2 @ VCC = 6.0 V, FB = Open
vs. Temperature
0.20
0.22
0.24
0.26
0.28
0.30
0.32
0.34
0.36
0.38
0.40
−40 0 20406080 120
TEMPERATURE (°C)
ICC2 (mA)
Figure 6. VCC OFF, FB = 1.5 V vs. Temperature
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9.0
−40 0 20 40 60 100 120
TEMPERATURE (°C)
VCC−OFF ( V )
−40 80
−10
−11
−40 80
−20 100 −20 80
Figure 7. VCC ON, FB = 3.5 V vs. Temperature
7.0
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8.0
−20 0 20 40 60 100 120
TEMPERATURE (°C)
VCC−ON ( V)
Figure 8. Duty Cycle vs. Temperature
66
67
68
69
−40 0 20 40 60 100 120
TEMPERATURE (°C)
DUTY CYCLE (%)
−40 80 80−20
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
7
TYPICAL CHARACTERISTICS
Figure 9. ILatch, FB = 1.5 V vs. Temperature
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
9.0
−40 0 20 40 80 100 120
TEMPERATURE (°C)
I_Latch (mA)
Figure 10. Ipeak−RR, VCC = 8.0 V, FB = 3.5 V
vs. Temperature
350
400
450
500
550
600
−40 0 20 40 60 100 120
TEMPERATURE (°C)
Ipeak (mA)
Figure 11. Frequency vs. Temperature
50
60
70
80
90
100
110
−20 0 20 40 60 100 120
TEMPERATURE (°C)
100 kHz
65 kHz
Figure 12. ON Resistance vs. Temperature,
NCP1012/1013
0
5
10
15
20
25
−40 0 20 40 80 100 120
TEMPERATURE (°C)
RDSon (W)
fOSC (kHz)
NCP1014
−20 60 −20 80
−40 80 60−20
Figure 13. Rup vs. Temperature
16
17
18
19
20
21
22
−20 0 20 40 60 100 120
TEMPERATURE (°C)
NCP1014
Figure 14. Minimum Start−up Drain Voltage vs.
Temperature
13.75
14.00
14.25
14.50
14.75
15.25
−40 0 20 40 80 100 120
TEMPERATURE (°C)
MINIMUM START−UP RAIN VOLTAGE (V)
INTERNAL PULL−UP RESISTOR
RESISTANCE (kW)
−40 80 60−20
15.00
NCP1012
NCP1010
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
8
APPLICATION INFORMATION
Introduction
The NCP101X offers a complete current−mode control
solution (actually an enhanced NCP1200 controller section)
together with a high−voltage power MOSFET in a
monolithic structure. The component integrates everything
needed t o build a rugged and low−cost Switch−Mode Power
Supply (SMPS) featuring low standby power. The Quick
Selection Table on Page 2, details the differences between
references, mainly peak current setpoints and operating
frequency.
No need for an auxiliary winding: ON Semiconductor
Very High Voltage Integrated Circuit technology lets you
supply the IC directly from the high−voltage DC rail. We call
it Dynamic Self−Supply (DSS). This solution simplifies the
transformer design and ensures a better control of the SMPS
in difficult output conditions, e.g. constant current
operations. However, for improved standby performance,
an auxiliary winding can be connected to the VCC pin to
disable the DSS operation.
Short−circuit protection: By permanently monitoring the
feedback line activity, the IC is able to detect the presence of
a short−circuit, immediately reducing the output power for
a total system protection. Once the short has disappeared, the
controller resumes and goes back to normal operation.
Fail−safe optocoupler and OVP: When an auxiliary
winding is connected to the VCC pin, the device stops its
internal Dynamic Self−Supply and takes its operating power
from the auxiliary winding. A 8.7 V active clamp is
connected between VCC and ground. In case the current
injected in this clamp exceeds a level of 7.4 mA (typical),
the controller immediately latches off and stays in this
position until VCC cycles down to 3.0 V (e.g. unplugging t h e
converter from the wall). By adjusting a limiting resistor in
series with the VCC terminal, it becomes possible to
implement an overvoltage protection function, latching off
the circuit in case of broken optocoupler or feedback loop
problems.
Low standby−power: If SMPS naturally exhibits a good
efficiency a t nominal load, it begins to be less ef ficient when
the output power demand diminishes. By skipping unneeded
switching cycles, the NCP101X drastically reduces the
power wasted during light load conditions. An auxiliary
winding can further help decreasing the standby power to
extremely low levels by invalidating the DSS operation.
Typical measurements show results below 80 mW @
230 Vac for a typical 7.0 W universal power supply.
No acoustic noise while operating: Instead of skipping
cycles at high peak currents, the NCP101X waits until the
peak current demand falls below a fixed 1/4 of the maximum
limit. As a result, cycle skipping can take place without
having a singing transformer … You can thus select cheap
magnetic components free of noise problems.
SPICE model: A dedicated model to run transient
cycle−by−cycle simulations is available but also an
averaged version to help close the loop. Ready−to−use
templates can be downloaded in OrCAD’s PSpice, and
INTUSOFT’s IsSpice4 from ON Semiconductor web site,
NCP101X related section.
Dynamic Self−Supply
When the power supply is first powered from the mains
outlet, the internal current source (typically 8.0 mA) is
biased and charges up the VCC capacitor from the drain pin.
Once the voltage on this VCC capacitor reaches the VCCOFF
level (typically 8.5 V), the current source turns off and
pulses are delivered by the output stage: the circuit is awake
and activates the power MOSFET. Figure 15 details the
internal circuitry.
Figure 15. The Current Source Regulates VCC
by Introducing a Ripple
Vref OFF = 8.5 V
Vref ON = 7.5 V
Vref Latch = 4.7 V*
-
+
Internal Supply
+
Vref VCCOFF
+200 mV
(8.7 V Typ.)
VCC
+CVCC
Startup Source
Drain
*In fault condition
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
9
Figure 16. The Charge/Discharge Cycle Over a 10 mF VCC Capacitor
Vcc
8.5 V
7.5 V
Device
Internally
Pulses
Startup Period
8.00
6.00
4.00
2.00
0
The protection burst duty−cycle can easily be computed
through the various timing events as portrayed by Figure 18.
Being loaded by the circuit consumption, the voltage on
the VCC capacitor goes down. When the DSS controller
detects that VCC has reached 7.5 V (VCCON), it activates the
internal current source to bring VCC toward 8.5 V and stops
again: a cycle takes place whose low frequency depends on
the VCC capacitor and the IC consumption. A 1.0 V ripple
takes place on the VCC pin whose average value equals
(VCCOFF + VCCON)/2. Figure 16 portrays a typical
operation of the DSS.
As one can see, the VCC capacitor shall be dimensioned to
offer an adequate startup time, i.e. ensure regulation is
reached before VCC crosses 7.5 V (otherwise the part enters
the fault condition mode). If we know that DV = 1.0 V
and ICC1 (max) is 1.1 mA (for instance we selected an 1 1 W
device switching at 65 kHz), then the VCC capacitor can
be calculated using: CwICC1 · tstartup
DV(eq. 1) . Let’s
suppose that the SMPS needs 10 ms to startup, then we will
calculate C to offer a 15 ms period. As a result, C should be
greater than 20 mF thus the selection of a 33 mF/16 V
capacitor is appropriate.
Short Circuit Protection
The internal protection circuitry involves a patented
arrangement that permanently monitors the assertion of an
internal error flag. This error flag is, in fact, a signal that
instructs the controller that the internal maximum peak
current limit is reached. This naturally occurs during the
startup period (Vout is not stabilized to the target value) or
when the optocoupler LED is no longer biased, e.g. in a
short−circuit condition or when the feedback network is
broken. When the DSS normally operates, the logic checks
for the presence of the error flag every time VCC crosses
VCCON. If the error flag is low (peak limit not active) then
the IC works normally. If the error signal is active, then the
NCP101X immediately stops the output pulses, reduces its
internal current consumption and does not allow the startup
source to activate: VCC drops toward ground until it reaches
the so−called latch−off level, where the current source
activates again to attempt a new restart. When the error is
gone, the IC automatically resumes its operation. If the
default is still there, the IC pulses during 8.5 V down to 7.5 V
and enters a new latch−off phase. The resulting burst
operation guarantees a low average power dissipation and
lets the SMPS sustain a permanent short−circuit. Figure 17
shows the corresponding diagram.
Figure 17. Simplified NCP101X Short−Circuit
Detection Circuitry
−
+
4 V
FB Division
Max
Ip
Flag
VCC VCCON
Signal
To
Latch
Rese
t
Current Sense
Information
Clamp
Active?
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
10
Figure 18. NCP101X Facing a Fault Condition (Vin = 150 Vdc)
Tstart
Tsw
TLatch
1 V Ripple
Latch−off
Level
The rising slope from the latch−off level up to 8.5 V
is expressed by: Tstart +DV1 · C
IC1 . The time during which
the IC actually pulses is given by tsw +DV2 · C
ICC1 .
Finally, the latch−off time can be derived
using the same formula topology: TLatch +DV3 · C
ICC2 .
From these three definitions, the burst duty−cycle
can be computed: dc +Tsw
Tstart )Tsw )TLatch (eq. 2) .
dc +DV2
ICC1 · ǒDV2
ICC1 )DV1
IC1 )DV3
ICC2Ǔ(eq. 3) . Feeding the
equation with values extracted from the parameter section
gives a typical duty−cycle of 13%, precluding any lethal
thermal runaway while in a fault condition.
DSS Internal Dissipation
The Dynamic Self−Supplied pulls energy out from the
drain pin. In Flyback−based converters, this drain level can
easily g o a bove 6 00 V p eak a nd t hus i ncrease t he s tress o n t he
DSS startup source. H owever , the d rain voltage evolves w ith
time and its period is small compared to that of the DSS. As
a r esult, the averaged d issipation, e xcluding capacitive l osses,
can be derived by: PDSS +ICC1 · tVds(t) u.(eq. 4) .
Figure 19 portrays a typical drain−ground waveshape where
leakage ef fects have been removed.
Figure 19. A typical drain−ground waveshape
where leakage effects are not accounted for.
Vds(t)
Vin Vr
toff
dt
ton t
Tsw
By looking at Figure 19, the average result can easily be
derived by additive square area calculation:
tVds(t) u+ Vin · (1 *d) )Vr · toff
Tsw (eq. 5)
By developing Equation 5, we obtain:
tVds(t) u+ Vin *Vin · ton
Tsw )Vr · toff
Tsw (eq. 6)
toff can be expressed by: toff +Ip · Lp
Vr (eq. 7) where ton
can be evaluated by: ton +Ip · Lp
Vin (eq. 8) .
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
11
Plugging Equations 7 and 8 into Equation 6 leads to
tVds(t) u+ Vin and thus, PDSS +Vin ICC1 (eq. 9) .
The worse case occurs at high line, when Vin equals
370 Vdc. With ICC1 = 1.1 mA (65 kHz version), we can
expect a DSS dissipation around 407 mW. If you select a
higher switching frequency version, the ICC1 increases and
it is likely that the DSS consumption exceeds that number.
In that case, we recommend to add an auxiliary winding in
order t o o f fer more dissipation room to the power MOSFET.
Please read application note AND8125/D, “Evaluating
the Power Capability of the NCP101X Members” to help in
selecting the right part/configuration for your application.
Lowering the Standby Power with an Auxiliary Winding
The DSS operation can bother the designer when its
dissipation is too high and extremely low standby power is
a must. In both cases, one can connect an auxiliary winding
to disable the self−supply. The current source then ensures
the startup sequence only and stays in the off state as long as
VCC does not drop below VCCON or 7.5 V. Figure 20 shows
that the insertion of a resistor (Rlimit) between the auxiliary
DC level and the VCC pin is mandatory to not damage the
internal 8.7 V active Zener diode during an overshoot for
instance (absolute maximum current is 15 mA) and to
implement the fail−safe optocoupler protection as offered by
the active clamp. Please note that there cannot be bad
interaction between the clamping voltage of the internal
Zener and VCCOFF since this clamping voltage is actually
built on top of VCCOFF with a fixed amount of offset
(200 mV typical).
Self−supplying controllers in extremely low standby
applications often puzzles the designer. Actually, if a SMPS
operated at nominal load can deliver an auxiliary voltage of
an arbitrary 16 V (Vnom), this voltage can drop to below
10 V (Vstby) when entering standby. This is because the
recurrence of the switching pulses expands so much that the
low frequency refueling rate of the VCC capacitor is not
enough to keep a constant auxiliary voltage. Figure 21
portrays a typical scope shot of a SMPS entering deep
standby (output unloaded). So care must be taken when
calculating Rlimit 1) to not trigger the VCC over current
latch [by injecting 6.3 mA (min. value) into the active
clamp] in normal operation but 2) not to drop too much
voltage over Rlimit when entering standby. Otherwise the
DSS could reactivate and the standby performance would
degrade. We are thus able to bound Rlimit between two
equations:
Vnom *Vclamp
Itrip vRlimit vVstby *VCCON
ICC1 (eq. 10)
Where:
Vnom is the auxiliary voltage at nominal load.
Vstdby is the auxiliary voltage when standby is entered.
Itrip is the current corresponding to the nominal operation.
It must be selected to avoid false tripping in overshoot
conditions.
ICC1 is the controller consumption. This number slightly
decreases compared to ICC1 from the spec since the part in
standby almost does not switch.
VCCON is the level above which Vaux must be maintained
to keep the DSS in the OFF mode. It is good to shoot around
8.0 V in order to of fer an adequate design mar gin, e.g. to not
reactivate the startup source (which is not a problem in itself
if low standby power does not matter).
Since Rlimit shall not bother the controller in standby, e.g.
keep Vaux to around 8.0 V (as selected above), we purposely
select a Vnom well above this value. As explained before,
experience shows that a 40% decrease can be seen on
auxiliary windings from nominal operation down to standby
mode. Let’s select a nominal auxiliary winding of 20 V to
offer sufficient margin regarding 8.0 V when in standby
(Rlimit also drops voltage in standby…). Plugging the
values in Equation 10 gives the limits within which Rlimit
shall be selected:
20
*
8.7
6.3 m vRlimit v
12
*
8
1.1 m (eq. 11
)
1.8 k tRlimit t3.6 k
, that is to say:
If w e design a power supply delivering 12 V, then the ratio
between auxiliary and power must be: 12/20 = 0.6. The OV P
latch will activate when the clamp current exceeds 6.3 mA.
This will occur when Vaux increases to: 8.7 V + 1.8 k x
(6.4m + 1.1m) = 22.2 V for the first boundary or 8.7 V +
3.6 k x (6.4m +1.1m) = 35.7 V for second boundary. On the
power output, it will respectively give 22.2 x 0.6 = 13.3 V
and 35.7 x 0.6 = 21.4 V. As one can see, tweaking the Rlimit
value will allow the selection of a given overvoltage output
level. Theoretically predicting the auxiliary drop from
nominal to standby is an almost impossible exercise since
many parameters are involved, including the converter time
constants. Fine tuning of Rlimit thus requires a few
iterations and experiments on a breadboard to check Vaux
variations but also output voltage excursion in fault. Once
properly adjusted, the fail−safe protection will preclude any
lethal voltage runaways in case a problem would occur in the
feedback loop.
When an OVP occurs, all switching pulses are
permanently disabled, the output voltage thus drops to zero.
The VCC cycles up and down between 8.5–4.7 V and stays
in this state until the user unplugs the power supply and
forces VCC to drop below 3.0 V (VCCreset). Below this
value, the internal OVP latch is reset and when the high
voltage is reapplied, a new startup sequence can take place
in an attempt to restart the converter.
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
12
Figure 20. A more detailed view of the NCP101X offers better insight on how to
properly wire an auxiliary winding.
Startup Source
Drain
+
-
−
+
VCCON = 8.5 V
VCCOFF = 7.5 V
+
VCC Rlimit
+
-+I > 7.4m
(Typ.)
+ +
CVcc Caux Laux
Ground
+
Vclamp = 8.7 V typ.
Permanent
Latch
D1
Figure 21. The burst frequency becomes so low that it is difficult to keep
an adequate level on the auxiliary VCC . . .
u30 ms
Lowering the Standby Power with Skip−Cycle
Skip−cycle o f fers an e f ficient way t o reduce t he s tandby
power by skipping unwanted cycles at light loads.
However, the recurrent frequency in skip often enters the
audible r ange a nd a h igh peak c urrent obviously g enerates
acoustic n oise i n t he t ransformer . T he noise t akes i ts o rigins
in the resonance of the transformer mechanical structure
which is excited by the skipping pulses. A possible
solution, s uccessfully i mplemented i n t he N CP1200 series,
also authorizes skip−cycle but only when the power
demand has dropped below a given l evel. At this time, the
peak current is reduced and no noise can be heard.
Figure 22 pictures the peak current evolution of the
NCP101X entering standby.
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
13
Figure 22. Low Peak Current Skip−Cycle Guarantees Noise−Free Operation
100% Peak current
at nominal power
25%
Skip−cycle
current limit
Full power operation involves the nominal switching
frequency and thus avoids any noise when running.
Experiments carried on a 5.0 W universal mains board
unveiled a standby power of 300 mW @ 230 Vac with the
DSS activated and dropped to less than 100 mW when an
auxiliary winding is connected.
Frequency Jittering for Improved EMI Signature
By sweeping the switching frequency around its nominal
value, it spreads the energy content on adjacent frequencies
rather than keeping it centered in one single ray. This offers
the benefit to artificially reduce the measurement noise on
a standard EMI receiver and pass the tests more easily. The
EMI sweep is implemented by routing the VCC ripple
(induced by the DSS activity) to the internal oscillator. As a
result, the switching frequency moves up and down to the
DSS rhythm. Typical deviation is "3.3% of the nominal
frequency. With a 1.0 V peak−to−peak ripple, the frequency
will equal 65 kHz in the middle of the ripple and will
increase as VCC rises or decrease as VCC ramps down.
Figure 23 portrays the behavior we have adopted.
Figure 23. The VCC ripple is used to introduce a frequency jittering on the internal oscillator sawtooth.
Here, a 65 kHz version was selected.
VCC Ripple VCCOFF 67.15 kHz
65 kHz
62.85 kHz
VCCON Internal Sawtooth
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
14
Soft−Start
The NCP101X features an internal 1.0 ms soft−start
activated during the power on sequence (PON). As soon as
VCC reaches VCCOFF, the peak current is gradually
increased from nearly zero up to the maximum internal
clamping level (e.g. 350 mA). This situation lasts 1.0 ms
and further to that time period, the peak current limit is
blocked to the maximum until the supply enters regulation.
The soft−start is also activated during the over current burst
(OCP) sequence. Every restart attempt is followed by a
soft−start activation. Generally speaking, the soft−start will
be activated when VCC ramps up either from zero (fresh
power−on sequence) or 4.7 V, the latch−off voltage
occurring during OCP. Figure 24 portrays the soft−start
behavior. The time scales are purposely shifted to offer a
better zoom portion.
Figure 24. Soft−Start is activated during a startup sequence or an OCP condition.
0 V (Fresh PON)
or
4.7 V (Overload)
VCC 8.5 V
Current
Sense Max Ip
1.0 ms
Non−Latching Shutdown
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the internal skip level
(Vskip), the output pulses are disabled. As soon as FB is
relaxed, the IC resumes its operation. Figure 25 depicts t h e
application example.
Figure 25. A non−latching shutdown where pulses are stopped as long as the NPN is biased.
ON/OFF
27
3
45
18
Drain
+CVcc
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
15
Full Latching Shutdown
Other a pplications require a full l atching s hutdown, e.g.
when an abnormal situation is detected (overtemperature
or overvoltage). This feature can easily be implemented
through two external transistors wired as a discrete SCR.
When the OVP level exceeds the Zener breakdown
voltage, the NPN biases the PNP and fires the equivalent
SCR, permanently bringing down the FB pin. The
switching pulses are disabled until the user unplugs the
power supply.
Figure 26. Two Bipolars Ensure a Total Latch−Off of the SMPS in Presence of an OVP
27
3
45
18
Drain
+CVcc
BAT54
10 k
10 k
OVP Rhold
12 k
Rhold ensures that the SCR stays on when fired. The bias
current flowing through Rhold should be small enough to l et
the VCC ramp up (8.5 V) and down (7.5 V) when the SCR
is fired. The NPN base can also receive a signal from a
temperature sensor. Typical bipolars can be MMBT2222
and MMBT2907 for the discrete latch. The MMBT3946
features two bipolars NPN+PNP in the same package and
could also be used.
Power Dissipation and Heatsinking
The NCP101X welcomes two dissipating terms, the DSS
current−source (when active) and the MOSFET. Thus,
Ptot = PDSS + PMOSFET. When the PDIP−7 package is
surrounded by copper, it becomes possible to drop its
thermal resistance junction−to−ambient, RqJA down
to 75°C/W and thus dissipate more power. The
maximum power the device can thus evacuate is:
Pmax +TJmax *Tambmax
RqJA (eq. 12) which gives around
1.0 W for an ambient of 50°C. The losses inherent to the
MOSFET RDSon can be evaluated using the following
formula: Pmos +1
3·Ip
2·d·R
DSon (eq. 13) , where Ip
is the worse case peak current (at the lowest line input), d is
the converter operating duty−cycle and RDSon, the
MOSFET resistance for TJ = 100°C. This formula is only
valid for Discontinuous Conduction Mode (DCM)
operation where the turn−on losses are null (the primary
current is zero when you restart the MOSFET). Figure 27
gives a possible layout to help drop the thermal resistance.
When measured on a 35 mm (1 oz) copper thickness PCB,
we obtained a thermal resistance of 75°C/W.
Figure 27. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
16
Design Procedure
The design of an SMPS around a monolithic device does
not differ from that of a standard circuit using a controller and a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices:
Figure 28. The Drain−Source Wave Shall Always be Positive . . .
1.004M 1.011M 1.018M 1.025M 1.032M
−50.0
50.0
150
250
350
> 0 !!
1. In any case, the lateral MOSFET body−diode shall
never be forward biased, either during startup
(because of a large leakage inductance) or in
normal operation as shown by Figure 28.
As a result, the Flyback voltage which is reflected on the
drain at the switch opening cannot be larger than the input
voltage. When selecting components, you thus must adopt
a turn ratio which adheres to the following equation:
N · (Vout )Vf) tVinmin (eq. 14) . For instance, if
operating from a 120 V DC rail, with a delivery of 12 V, w e
can select a reflected voltage of 100 Vdc maximum:
120–100 > 0. Therefore, the turn ratio Np:Ns must be
smaller than 100/(12 + 1) = 7.7 or Np:Ns < 7.7. We will see
later on how it affects the calculation.
2. A current−mode architecture is, by definition,
sensitive to subharmonic oscillations.
Subharmonic oscillations only occur when the
SMPS is operating in Continuous Conduction
Mode (CCM) together with a duty−cycle greater
than 50%. As a result, we recommend to operate
the device in DCM only, whatever duty−cycle it
implies (max = 65%). However, CCM operation
with duty−cycles below 40% is possible.
3. Lateral MOSFETs have a poorly dopped
body−diode which naturally limits their ability to
sustain the avalanche. A traditional RCD clamping
network shall thus be installed to protect the
MOSFET. In some low power applications,
a simple capacitor can also be used since
Vdrain max +Vin )N · (Vout )Vf) )Ip · Lf
Ctot
Ǹ
(eq. 15) , where Lf is the leakage inductance,
Ctot is the total capacitance at the drain node
(which is increased by the capacitor wired between
drain and source), N the Np:Ns turn ratio, Vout the
output voltage, Vf the secondary diode forward
drop and finally, Ip the maximum peak current.
Worse case occurs when the SMPS is very close to
regulation, e.g. the Vout target is almost reached
and Ip is still pushed to the maximum.
Taking into account all previous remarks, it becomes
possible to calculate the maximum power that can be
transferred at low line.
When the switch closes, Vin is applied across the primary
inductance L p until the current reaches the level imposed by
the feedback loop. The duration of this event is called the ON
time and can be defined by:
ton +Lp · Ip
Vin (eq. 16)
At the switch opening, the primary energy is transferred
to the secondary and the flyback voltage appears across
Lp, resetting the transformer core with a slope of
N · (Vout )Vf)
Lp . toff, the OFF time is thus:
toff +Lp · Ip
N · (Vout )Vf) (eq. 17)
If one wants to keep DCM only, but still need to pass the
maximum power, we will not allow a dead−time after the
core is reset, but rather immediately restart. The switching
time can be expressed by:
Tsw +toff )ton +Lp · Ip · ǒ1
Vin )1
N · (Vout )Vf)Ǔ
(eq. 18)
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
17
The Flyback transfer formula dictates that:
Pout
h+1
2·Lp·Ip
2·Fsw (eq. 19) which, by extracting
Ip and plugging into Equation 19, leads to:
T
sw +Lp 2 · Pout
h·Fsw·Lp
Ǹ·ǒ1
Vin )1
N · (Vout )Vf)Ǔ
(eq. 20
)
Extracting Lp from Equation 20 gives:
Lpcritical +(Vin · Vr)2·h
2·Fsw·[Pout·(Vr
2)2·Vr·Vin)Vin2)]
(eq. 21) , with Vr = N . (Vout + Vf) and h the efficiency.
If Lp critical gives the inductance value above which
DCM operation is lost, there is another expression we can
write to connect Lp, the primary peak current bounded by
the NCP101X and the maximum duty−cycle that needs to
stay below 50%:
Lpmax +DCmax · Vinmin · Tsw
Ipmax (eq. 22) where Vinmin
corresponds to the lowest rectified bulk voltage, hence the
longest ton duration or largest duty−cycle. Ip max is the
available peak current from the considered part, e.g. 350 mA
typical for the NCP1013 (however, the minimum value of
this parameter shall be considered for reliable evaluation).
Combining Equations 21 and 22 gives the maximum
theoretical power you can pass respecting the peak current
capability of the NCP101X, the maximum duty−cycle and
the discontinuous mode operation:
Pmax :+Tsw2· Vinmin2·Vr
2·h·
(eq. 23)
Fsw
(2 · Lpmax · Vr2)4 · Lpmax · Vr · Vinmin
)2 · Lpmax · Vinmin2)
From Equation 22 we obtain the operating duty−cycle
d+Ip · Lp
Vin · Tsw (eq. 24) which lets us calculate the RMS
current circulating in the MOSFET:
IdRMS +Ip · d
3
Ǹ(eq. 25) . From this equation, we
obtain the average dissipation in the MOSFET:
Pavg +1
3·Ip
2·d·R
DSon (eq. 26) to which switching
losses shall be added.
If we stick to Equation 23, compute Lp and follow the
above calculations, we will discover that a power supply
built with the NCP101X and operating from a 100 Vac line
minimum will not be able to deliver more than 7.0 W
continuous, regardless of the selected switching frequency
(however the transformer core size will go down as
Fswitching is increased). This number increases
significantly when operated from a single European mains
(18 W). Application note AND8125/D, “Evaluating the
Power Capability of the NCP101X Members” details how
to assess the available power budget from all the NCP101X
series.
Example 1. A 12 V 7.0 W SMPS operating on a large
mains with NCP101X:
Vin = 100 Vac to 250 Vac or 140 Vdc to 350 Vdc once
rectified, assuming a low bulk ripple
Efficiency = 80%
Vout = 12 V, Iout = 580 mA
Fswitching = 65 kHz
Ip max = 350 mA – 10% = 315 mA
Applying the above equations leads to:
Selected maximum reflected voltage = 120 V
with Vout = 12 V, secondary drop = 0.5 V → Np:Ns = 1:0.1
Lp critical = 3.2 mH
Ip = 292 mA
Duty−cycle worse case = 50%
Idrain RMS = 119 mA
PMOSFET = 354 mW at RDSon = 24 W (TJ > 100°C)
PDSS = 1.1 mA x 350 V = 385 mW, if DSS is used
Secondary diode voltage stress = (350 x 0.1) + 12 = 47 V
(e.g. a MBRS360T3, 3.0 A/60 V would fit)
Example 2. A 12 V 16 W SMPS operating on narrow
European mains with NCP101X:
Vin = 230 Vac " 15%, 276 Vdc for Vin min to 370 Vdc
once rectified
Efficiency = 80%
Vout = 12 V, Iout = 1.25 A
Fswitching = 65 kHz
Ip max = 350 mA – 10% = 315 mA
Applying the equations leads to:
Selected maximum reflected voltage = 250 V
with Vout = 12 V, secondary drop = 0.5 V → Np:Ns = 1:0.05
Lp = 6.6 mH
Ip = 0.305 mA
Duty−cycle worse case = 0.47
Idrain RMS = 121 mA
PMOSFET = 368 mW at RDSon = 24 W (TJ > 100°C)
PDSS = 1.1 mA x 370 V = 407 mW, if DSS is used below an
ambient of 50°C.
Secondary diode voltage stress = (370 x 0.05) + 12 = 30.5 V
(e.g. a MBRS340T3, 3.0 A/40 V)
Please note that these calculations assume a flat DC rail
whereas a 10 ms ripple naturally affects the final voltage
available o n the transformer e nd. Once the B ulk capacitor has
been selected, one should check that the resulting ripple (min
Vbulk?) i s s till c ompatible w ith the above calculations. As a n
example, to b enefit from t he l argest o perating r ange, a 7 .0 W
board was built with a 47 mF bulk capacitor which ensured
discontinuous operation even in the ripple minimum waves.
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
18
MOSFET Protection
As in any Flyback design, it is important to limit the
drain excursion to a safe value, e.g. below the MOSFET BVDSS which is 700 V. Figure 29 presents possible
implementations:
Figure 29. Different Options to Clamp the Leakage Spike
+
NCP101X
C
Vcc
HV
1 8
2
3
4
7
5+
CVcc
HV
Rclamp Cclamp
D
1 8
2
3
4
7
5+
CVcc
HV
D
1 8
2
3
4
7
5
+
C
Dz
ABC
NCP101X NCP101X
Figure 29A: The simple capacitor limits the voltage
according to Equation 15. This option is only valid for low
power applications, e.g. below 5.0 W, otherwise chances
exist to destroy the MOSFET. After evaluating the leakage
inductance, you can compute C with Equation 15. Typical
values are between 100 pF and up to 470 pF. Large
capacitors increase capacitive losses.
Figure 29B: This diagram illustrates the most standard
circuitry called the RCD network. Rclamp and Cclamp are
calculated using the following formulas:
Rclamp +2 · Vclamp · (Vclamp *(Vout )Vf sec) · N)
Lleak · Ip2·Fsw (eq. 27)
Cclamp +Vclamp
Vripple · Fsw · Rclamp (eq. 28)
Vclamp is usually selected 50−80 V above the reflected
value N x (Vout + Vf). The diode needs to be a fast one and
a MUR160 represents a good choice. One major drawback
of the RCD network lies in its dependency upon the peak
current. Worse case occurs when Ip and Vin are maximum
and Vout is close to reach the steady−state value.
Figure 29C: This option is probably the most expensive of
all three but it offers the best protection degree. If you need
a very precise clamping level, you must implement a Zener
diode or a TVS. There are little technology differences
behind a standard Zener diode and a TVS. However, the die
area is far bigger for a transient suppressor than that of Zener.
A 5.0 W Zener diode like the 1N5388B will accept 180 W
peak power if it lasts less than 8.3 ms. If the peak current in
the worse case (e.g. when the PWM circuit maximum
current limit works) multiplied by the nominal Zener
voltage exceeds these 180 W, then the diode will be
destroyed when the supply experiences overloads. A
transient suppressor like the P6KE200 still dissipates 5.0 W
of continuous power but is able to accept surges up to 600 W
@ 1.0 ms. Select the Zener or TVS clamping level between
40 to 80 V above the reflected output voltage when the
supply is heavily loaded.
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
19
Typical Application Examples
A 6.5 W NCP1012−Based Flyback Converter
Figure 30 shows a converter built with a NCP1012
delivering 6.5 W from a universal input. The board uses the
Dynamic Self−Supply and a simplified Zener−type
feedback. This configuration was selected for cost reasons
and a more precise circuitry can be used, e.g. based on a
TL431:
Figure 30. An NCP1012−Based Flyback Converter Delivering 6.5 W
1
2
J1
CEE7.5/2
D1 D2
E1
10 m/400 V
E2
10 m/16 V
2
3
7
2
1
GND
GND
GND
VCC HV
FB
GND
IC1
NCP1012
R2
150 k D5
U160
5
4
4
8
C2
2n2/Y
4
8
7
6
5
TR1
1
E3
470 m/25 V
D6
B150
R3
100 R R4
180 R
2
1
ZD1
11 V J2
CZM5/2
IC2
PC817
C1
2.2 nF
1N4007 1N4007
R1
47 R
D3 D4
1N4007 1N4007
The converter built according to Figure 31 layouts, gave
the following results:
•Efficiency at Vin = 100 Vac and Pout = 6.5 W = 75.7%
•Efficiency at Vin = 230 Vac and Pout = 6.5 W = 76.5%
Figure 31. The NCP1012−Based PCB Layout . . . and its Associated Component Placement
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
20
A 7.0 W NCP1013−based Flyback Converter
Featuring Low Standby Power
Figure 32 depicts another typical application showing a
NCP1013−65 kHz operating in a 7.0 W converter up to
70°C of ambient temperature. We can increase the output
power since an auxiliary winding is used, the DSS is
disabled, and thus offering more room for the MOSFET. In
this application, the feedback is made via a TLV431 whose
low bias current (100 mA min) helps to lower the no−load
standby power.
Figure 32. A Typical Converter Delivering 7.0 W from a Universal Mains
1 8
2
3
4
7
5
VCC
NC
GND
FB
GND
D
Vbulk
C2
47 mF/
450 V
+
1N4148
D4
R2
3.3 k
+C10
33 mF/25 V
R4 22
NCP1013P06
+100 mF/10 V
C3 C9
1 nF
C8
10 nF
400 V
R7
100 k/
1 W
D3
MUR160
T1
12 V @
0.6 A
GND
D2
MBRS360T3
+ + 100 mF/16 V
C7
+
C6 C8
470 mF/16 V
R5
39 k
R3
1 k
IC1
SFH6156−2
C4
100 nF
IC2
TLV431 R6
4.3 k
C5
2.2 nF
Y1 Type
T1
Aux
L2
22 mH
GND
Measurements have been taken from a demonstration
board implementing the diagram in Figure 32 and the
following results were achieved, with either the auxiliary
winding in place or through the Dynamic Self−Supply:
Vin = 230 Vac, auxiliary winding, Pout = 0, Pin = 60 mW
Vin = 100 Vac, auxiliary winding, Pout = 0, Pin = 42 mW
Vin = 230 Vac, Dynamic Self−Supply, Pout = 0,
Pin = 300 mW
Vin = 100 Vac, Dynamic Self−Supply, Pout = 0,
Pin = 130 mW
Pout = 7.0 W, h = 81% @ 230 Vac, with auxiliary winding
Pout = 7.0 W, h = 81.3 @ 100 Vac, with auxiliary winding
For a quick evaluation of Figure 32 application example,
the following transformers are available from Coilcraft:
A9619−C, Lp = 3.0 mH, Np:Ns = 1:0.1, 7.0 W
application o n universal mains, including auxiliary winding,
NCP1013−65kHz.
A0032−A, Lp = 6.0 mH, Np:Ns = 1:0.055, 10 W
application on European mains, DSS operation only,
NCP1013−65 kHz.
Coilcraft
1102 Silver Lake Road
CARY IL 60013
Email: info@coilcraft.com
Tel.: 847−639−6400
Fax.: 847−639−1469
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
21
ORDERING INFORMATION
Device Order Number Frequency
(kHz) Package Type Shipping†RDSon
(W)Ipk (mA)
NCP1010AP065G 65 PDIP−7
(Pb−Free) 50 Units / Rail
23 100
NCP1010AP100G 100 23 100
NCP1010AP130G 130 23 100
NCP1010ST65T3G 65 SOT−223
(Pb−Free) 4000 / Tape & Reel
23 100
NCP1010ST100T3G 100 23 100
NCP1010ST130T3G 130 23 100
NCP1011AP065G 65 PDIP−7
(Pb−Free)
50 Units / Rail 23 250
NCP1011AP100G 100 50 Units / Rail 23 250
NCP1011AP130G 130 23 250
NCP1011ST65T3G 65 SOT−223
(Pb−Free) 4000 / Tape & Reel
23 250
NCP1011ST100T3G 100 23 250
NCP1011ST130T3G 130 23 250
NCP1012AP065G 65 PDIP−7
(Pb−Free)
50 Units / Rail 11 250
NCP1012AP100G 100 50 Units / Rail 11 250
NCP1012AP133G 130 50 Units / Rail 11 250
NCP1012ST65T3G 65 SOT−223
(Pb−Free) 4000 / Tape & Reel 11 250
NCP1012ST100T3G 100 11 250
NCP1012ST130T3G 130 4000 / Tape & Reel 11 250
NCP1013AP065G 65 PDIP−7
(Pb−Free) 50 Units / Rail
11 350
NCP1013AP100G 100 11 350
NCP1013AP133G 130 11 350
NCP1013ST65T3G 65 SOT−223
(Pb−Free) 4000 / Tape & Reel
11 350
NCP1013ST100T3G 100 11 350
NCP1013ST130T3G 130 11 350
NCP1014AP065G 65 PDIP−7
(Pb−Free) 50 Units / Rail 11 450
NCP1014AP100G 100 50 Units / Rail 11 450
NCP1014ST65T3G 65 SOT−223
(Pb−Free) 4000 / Tape & Reel 11 450
NCP1014ST100T3G 100 11 450
† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
22
PACKAGE DIMENSIONS
PDIP−7
AP SUFFIX
CASE 626A
ISSUE B
14
58
b2
NOTE 8
D
b
L
A1
A
eB
E
A
TOP VIEW
C
SEATING
PLANE
0.010 CA
SIDE VIEW
END VIEW
END VIEW
WITH LEADS CONSTRAINED
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
E1
M
8X
c
D1
B
H
NOTE 5
e
e/2 A2
NOTE 3
MBMNOTE 6
M
DIM MIN MAX
INCHES
A−−−− 0.210
A1 0.015 −−−−
b0.014 0.022
C0.008 0.014
D0.355 0.400
D1 0.005 −−−−
e0.100 BSC
E0.300 0.325
M−−−− 10
−−− 5.33
0.38 −−−
0.35 0.56
0.20 0.36
9.02 10.16
0.13 −−−
2.54 BSC
7.62 8.26
−−− 10
MIN MAX
MILLIMETERS
E1 0.240 0.280 6.10 7.11
b2
eB −−−− 0.430 −−− 10.92
0.060 TYP 1.52 TYP
A2 0.115 0.195 2.92 4.95
L0.115 0.150 2.92 3.81
°°
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
www.onsemi.com
23
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE N
A1
b1
D
E
b
e
e1
4
123
0.08 (0003)
A
L1
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
1.5
0.059 ǒmm
inchesǓ
SCALE 6:1
3.8
0.15
2.0
0.079
6.3
0.248
2.3
0.091 2.3
0.091
2.0
0.079
SOLDERING FOOTPRINT*
HEDIM
AMIN NOM MAX MIN
MILLIMETERS
1.50 1.63 1.75 0.060
INCHES
A1 0.02 0.06 0.10 0.001
b0.60 0.75 0.89 0.024
b1 2.90 3.06 3.20 0.115
c0.24 0.29 0.35 0.009
D6.30 6.50 6.70 0.249
E3.30 3.50 3.70 0.130
e2.20 2.30 2.40 0.087
0.85 0.94 1.05 0.033
0.064 0.068
0.002 0.004
0.030 0.035
0.121 0.126
0.012 0.014
0.256 0.263
0.138 0.145
0.091 0.094
0.037 0.041
NOM MAX
L1 1.50 1.75 2.00 0.060
6.70 7.00 7.30 0.264 0.069 0.078
0.276 0.287
HE− −
e1
0°10°0°10°
q
q
L
L0.20 −−− −−− 0.008 −−− −−−
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer ’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body . Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NCP1010/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loc
al
Sales Representative
◊
