128-Macrocell MAX® EPLD
CY7C342B
Cypress Semiconductor Corporation •3901 North First Street •San Jose •CA 95134 •408-943-2600
Document #: 38-030 14 Rev. *A Revised April 8, 2002
Features
• 128 macrocells in eight logic array blocks (LABs)
• Eight dedicated inputs, 52 bidirectional I/O pins
• Programmable interconnect array
• Advanced 0.65-micron CMOS technology to increase
performance
• Available in 68-pin HLCC, PLCC, and PGA packages
Functional Description
The CY7C342B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX® architecture is
100% user-configurable, allowing the device to accommodate
a variety of independent logic functions.
The 128 macrocells in the CY7C342B are divided into eight
LABs, 1 6 per LAB. The re a re 256 e xpander pro duct t erms, 3 2
per LAB, to b e used and shared by the macro cells with in each
LAB.
Each LAB is interconnected with a programmable interconnect
array, allowing all signals to be routed throughout the chip.
The speed and density of the C Y7C342B allo ws it to be u sed in a
wide range of a pplications, from repla cement of large amount s of
7400-series TTL logic, to complex controllers and multifunction
chips. Wit h greater than 25 tim es the functional ity of 20-pin PLD s,
the CY7C342B allows the replacement of over 50 TTL devices. By
repl acing lar ge amounts of logic, the CY7 C342B reduces board
space, part c ount, and i ncreases system reliabili ty.
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
LogicBlockDiagram
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 37
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
MACROCELL 7
MACROCELL 8MACROCELL 121–128
MACROCELL 102–112
MACROCELL 86–96MACROCELL 38–48
MACROCELL 22–32
MACROCELL 9–16
SYSTEM CLOCK
P
I
A
INPUT (A7) 68
INPUT (A8) 66
INPUT (L6) 36
INPUT (K6) 35
(B8) 65
(A9) 64
(B9) 63
(A10) 62
(B10) 61
(B11) 60
(C11) 59
(C10) 58
(D11) 57
(D10) 56
(E11) 55
(F11) 53
(F10) 52
(G11) 51
(H11) 49
(H10) 48
(J11) 47
(J10) 46
(K11) 45
(K10) 44
(L10) 43
(L9) 42
(K9) 41
(L8) 40
(K8) 39
(L7) 38
4(A5)
5(B4)
6(A4)
7(B3)
8(A3)
9(A2)
10 (B2)
11 (B1)
12 (C2)
13 (C1)
14 (D2)
15 (D1)
17(E1)
18 (F2)
19 (F1)
21 (G1)
22 (H2)
23 (H1)
24 (J2)
25 (J1)
26 (K1)
27 (K2)
28(L2)
29 (K3)
30(L3)
31 (K4)
LABH
LABG
LABF
LABE
LABA
LABB
LABC
LABD
3, 20, 37, 54 (B5, G2,K7, E10)
16, 33, 50, 67 (E2,K5, G10,B7)
VCC
GND
() –PERTAIN TO 68-PIN PGA PACKAGE
1 (B6) INPUT/CLK
2 (A6) INPUT
32 (L4) INPUT
34 (L5) INPUT
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
MACROCELL 73–80
MACROCELL 72
MACROCELL 71
MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELL 67
MACROCELL 66
MACROCELL 65
MACROCELL 57–64
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55
MACROCELL 56
CY7C342B
Document #: 38-03014 Rev. *A Page 2 of 14
Selection Guide
7C342B-15 7C342B-20 7C342B-25 7C342B-30 7C342B-35 Unit
Maxi mu m A cc es s Ti me 15 20 25 30 35 ns
Pin Configurations
I/O
Top View
HLCC, PLCC
76 453
11
12
10
98
4342 44
45
46
21
22
24
23
25
13
14
4140
21
26 27
18
19
17
16
15
20
28 29 3130 32 33 3635 37 38 3934
52
51
49
50
48
47
VCC
53
54
55
60
58
59
57
56
66 65 6364 62
68 67 61
I/O
INPUT
INPUT/CLK
INPUT
GND
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
VCC
INPUT
INPUT
GND
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
VCC
I/O
INPUT/
CLK
INPUT
GND
I/O I/O
I/O I/O
VCC I/O
I/O I/O
GND I/O
I/O I/O
I/O I/O
I/OI/O
I/O
I/O
I/O
I/O
I/O
VCC
INPUT
INPUT
GND
INPUT
I/O
INPUT
I/O
I/O
I/O
I/O
I/OI/O
I/OI/O
VCC
I/O
I/OI/O
GNDI/O
I/O
I/O
I/O
I/O
I/O
I/O
PGA
Bottom View
I/O
INPUT INPUT I/O I/O
I/O I/O I/O I/O
L
K
J
H
G
F
E
D
C
B
A
1234567891011
7C342B
7C342B
CY7C342B
Document #: 38-03014 Rev. *A Page 3 of 14
Logic Array Blocks
There are eight logic array blocks in the CY7C342B. Each LAB
consists of a macrocell array containing 16 macrocells, an
expand er produc t term a rray contain ing 32 expanders , and a n
I/O block. The LAB is fed by the programmable interconnect
array an d the d edica ted input bus. All ma croce ll feed back s go
to the macrocell array, the expander array, and the program-
mable interconnect a rray . Exp anders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable
interconnect array so that they may be accessed by macrocells
in other LABs as well as the macrocells in the LAB in which
they are situated.
Externally, the CY7C342B provides eight dedicated inputs,
one of which may be used as a system clock. There are 52 I/O
pins that may be individually configured for input, output, or
bidirectional data flow.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves inter-
connec t limitations by routin g only the sig nals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on rou ting, the PIA has a fixed delay.
This el iminates undesired skews among l ogic signals t hat may
cause glitches in internal or external logic. The fixed delay,
regardless of programmable interconnect array configuration,
simplifies design by assuring that internal signal skews or
races are avoided. The result is ease of design implemen-
tation, of ten in a sig nal pass, without the m ultiple in ternal logi c
placem ent and rou ting ite rations require d for a program mabl e
gate array to achieve design timing objectives.
Timing Delays
T iming delays within the CY7C342B may be easily determined
using Warp®, Warp Professional™, or Warp Enterprise™
softwa re by the mo del show n in Figure 1. The CY 7C342B has
fixed internal delays, allowing the user to determine the
worst-case timing delays for any design.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational se ctions of
this da t as he et is no t i mp lie d. E x posu r e to abs o lu t e m ax i mum
ratings conditions for extended periods of time may affect
device reliability. The CY7C342B contains circuitry to protect
device pins from high static voltages or electric fields, but
normal precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages.
For proper operation, input and output pins must be
constrained to the range GND < (VIN or VOUT) < VCC. Unused
inputs must always be tied to an appropriate logic level
(either VCC or GND). Each set of VCC and GND pins must
be connected together directly at the device. Power supply
decoupling capacitors of at least 0.2 µF must be c onn e ct ed
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled to GND
directly at the device. Decoupling capacitors should have
good frequency response, such as mo nolithic cerami c types
have.
LOGIC ARRAY
CONTROLDELAY
tLAC
EXPANDER
DELAY
tEXP
CLOCK
DELAY
tIC
tRD
tCOMB
tLATCH
INPUT
DELAY
tIN
REGISTER
OUTPUT
DELAY
tOD
tXZ
tZX
LOGIC ARRAY
DELAY
tLAD
FEEDBACK
DELAY
tFD
OUTPUT
INPUT
SYSTEM CLOCK DELAY tICS
tRH
tRSU
tPRE
tCLR
PIA
DELAY
tPIA
I/O DELAY
tIO
Figure 1. CY7C342B Internal Timing Model
CY7C342B
Document #: 38-03014 Rev. *A Page 4 of 14
Design Security
The CY7C342B contains a programmable design security
feature that controls the access to the data programmed into
the devi ce. I f this program mabl e feature is use d, a propri etary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
obtained since programmed data within EPROM cells is
invisi ble. The bi t that control s this fun ction, along w ith all oth er
program data, may be reset simply by erasing the entire
device.
The CY7C342B is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100%
programming yield.
The erasable nature of these devices allows test programs to
be used and erased d uring early s tages of the production fl ow .
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expande r delay tEXP to the overall delay. Simila rly , there i s an
additional tPIA delay for an input from an I/O pin when
compared to a signal from straight input pin.
When calculating synchronous frequencies, use tSU if all
inputs are on dedicated input pins. When expander logic is
used in the data path, add the appropriate ma ximum expand er
delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1,
or 1/(tEXP + tS1) is the lowest frequency. The lowest of these
frequencies is the maximum data path frequency for the
synchronous configuration.
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on the dedicated input pins.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, tEXP to tAS1. Determine
which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequenc y for the asy nc hronou s con f ig-
uration.
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same
synchronous clock. If tOH is greater than the minimum
required input hold time of the subsequent synchronous
logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case
environmental and supply voltage conditions.
Typical ICC vs. fMAX
400
300
200
100
1 kHz 10 kHz 100 kHz 1 MHz
I
CC
MAXIMUM FREQUENCY
10 MHz
050 MHz100 Hz
ACTIVE (mA) Typ.
VCC = 5.0V
Room Temp.
Output Drive Current
01 2 3 4
I OUTPUT CURRENT (mA) TYPICAL
VOOUTPUTVOLT AG E (V )
250
200
150
100
50
5
O
IOH
IOL
VCC = 5.0V
Room Temp.
CY7C342B
Document #: 38-03014 Rev. *A Page 5 of 14
Maximum Ratings
(Above w hi ch the useful life may be impaired. For user g uid e-
lines, not tes ted .)
Storage Temperature ................................ –65°C to +135°C
Ambient Temperature with
Power Applied............................................ –65°C to +135°C
Maximum Junction Temperat ure
(under bias)..................................................................150°C
Supply Voltage to Ground Potential............–2.0V to +7.0V[1]
DC Output Current per Pin[1]................... –25 mA to +25 mA
DC Input Voltage[1].........................................–2.0V to +7.0V
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 5V ± 5%
Industrial –40°C to +85°C 5V ± 10%
Electrical Characteristics Ov er the Op erating Range
Parameter Description Test Conditions Min. Max. Unit
VCC Supply Voltage Maximum VCC rise time is 10 ms 4.75(4.5) 5.25(5.5) V
VOH Output HIGH Voltage IOH = –4 mA DC[2] 2.4 V
VOL Output LOW Voltage IOL = 8 mA DC[2] 0.45 V
VIH Input HIGH Voltage 2.0 VCC + 0.3 V
VIL Input LOW Voltage –0.3 0.8 V
IIX Input Current VI = VCC or ground –10 +10 µA
IOZ Output Leakage Current VO = VCC or ground –40 +40 µA
tRRecom mended Inpu t Rise T ime 100 ns
tFRecommended Input Fall Time 100 ns
Capacitance
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance VIN = 0V, f = 1.0 MHz 10 pF
COUT Output Capacitance VOUT = 0V, f = 1.0 MHz 20 pF
AC Test Loads and W aveforms
Notes:
1. Minimum DC in put i s –0.3V . During transactions, input may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter
than 20 ns.
2. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
3.0V
5V
OUTPUT
R1 464Ω
R2
250Ω
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
≤6ns ≤6ns
5V
OUTPUT
R1 464Ω
R2
250Ω
5pF
INCLUDING
JIG AN D
SCOPE
(a) (b)
OUTPUT 1.75V
Equivalent to: THÉ VENIN EQUIVALENT (commercial/military)
ALL INPUT PULSES
163Ω
CY7C342B
Document #: 38-03014 Rev. *A Page 6 of 14
Commercial and Industrial External Synchronous Switching Charact eristics Over Operating Range
Parameter Description
7C342B-15 7C342B-20
UnitMin. Max. Min. Max.
tPD1 Dedicated Input to Combinatorial Output Delay[3] 15 20 ns
tPD2 I/O Input to Combinatorial Output Delay[3] 25 33 ns
tSU Global Clock Set-Up time 10 13 ns
tCO1 Synchronous Clock Input to Output Delay[3] 8 9 ns
tHInput Hold Time from Synchronous Clock Input 0 0 ns
tWH Synchronous Clock Input HIGH Time 5 7 ns
tWL Synchronous Clock Input LOW Time 5 7 ns
fMAX Maximum Register Toggle Frequency [4] 100 71.4 MHz
tCNT Minimum Global Clock Period 12 15 ns
fCNT Maximum Internal Global Clock Frequency[5] 83.3 66.7 MHZ
Commercial and Industrial External Synchronous Switching Charact eristics Over Operating Range
Parameter Description
7C342B-25 7C342B-30 7C342B-35
UnitMin. Max. Min. Max. Min. Max.
tPD1 Dedicated Input to Combinatorial Output Delay[3] 25 30 35 ns
tPD2 I/O Input to Combinatorial Output Delay[3] 40 45 55 ns
tSU Global Clock Se t-Up time 15 20 25 ns
tCO1 Synchronous Clock Input to Output Delay[3] 14 16 20 ns
tHInput Hold Time from Synchronous Clock Input 0 0 0 ns
tWH Synchronous Clock Input HIGH Time 810 12.5 ns
tWL Synchronous Clock Input LOW Time 810 12.5 ns
fMAX Maximum Register Toggle Frequency[4] 62.5 50 40 MHz
tCNT Minimum Gl obal Clock Pe riod 20 25 30 ns
tODH Output Data Hold Ti me After clock 2 2 2 ns
fCNT Maximum Internal Global Clock Frequency[5] 50 40 33.3 MHz
Commercial and Industrial External Asynchronous Switching Characteristics
Over Operating Range
Parameter Description 7C342B-15 7C342B–20 UnitMin. Max. Min. Max.
tACO1 Asynchronous Clock Input to Output Delay[3] 15 20 ns
tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[6] 5 6 ns
tAH Input Hold Time from Asynchronous Clock Input 5 6 ns
tAWH Asynchronous Cl ock Input HIGH Time[6] 5 7 ns
tAWL Asynchronous Clock Input LOW Time[6] 5 7 ns
tACNT Minimum Internal Array Clock Frequency 12 15 ns
fACNT Maximum Internal Array Clock Frequency[5] 83.3 66.7 MHz
tACO1 Asynchronous Clock Input to Output Delay[3] 25 30
tAS1 Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[5] 5 6 10
tAH Input Hold Time from Asynchronous Clock Input 6 8 10
Notes:
3. C1 = 35 pF.
4. The fMAX values represent the highest frequency for pipeline data.
5. This parameter is measured with a 16-bit counter programmed into each LAB
6. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped.
CY7C342B
Document #: 38-03014 Rev. *A Page 7 of 14
tAWH Asynchronous Cl ock Input HIGH Time[5] 11 14 16
tAWL Asynchronous Clock Input LOW Time[5] 911 14
tACNT Minimum Internal Array Clock Frequency 20 25
fACNT Maximum Internal Array Clock Frequency[5] 50 40 33.3
Commercial and Industrial External Asynchronous Switching Characteristics
Over Operating Range (continued)
Parameter Description 7C342B-15 7C342B–20 UnitMin. Max. Min. Max.
Commercial and Industrial Typical Internal Switching Charact eristics Over Operating Range
Parameter Description
7C342B-15 7C342B-20
UnitMin. Max. Min. Max.
tIN Dedicated Input Pad and Buffer Delay 3 4 ns
tIO I/O Input Pad and Buffer Delay 3 4 ns
tEXP Expander Array Delay 810 ns
tLAD Logic Array Data Delay 812 ns
tLAC Logic Array Control Delay 5 5 ns
tOD Output Buffer and Pad Delay[3] 3 3 ns
tZX[8] Output Buf fer Enab le De la y [3] 5 5 ns
tXZ Output Buffer Disable Delay[7] 5 5 ns
tRSU Register Set-Up Time Relative to Clock Signal at Register 2 1 ns
tRH Register Hold Time Relative to Clock Signal at Register 710 ns
tLATCH Flow Through Latch Delay 1 1 ns
tRD Register Delay 1 1 ns
tCOMB[9] Transparent Mode Delay 1 1 ns
tIC Asynchronous Clock Logic Delay 6 8 ns
tICS Synchronous C loc k Dela y 0 0 ns
tFD Feedback Delay 1 1 ns
tPRE Asynchronous Register Preset Time 3 3 ns
tCLR Asynchronous Register Clear Time 3 3 ns
tPIA Programmab le Inte rco nnect Array Delay Time 10 13 ns
tIN Dedicated Input Pad and Buffer Delay 5 7
tIO I/O Input Pad and Buffer Delay 6 6
tEXP Expander Array Delay 12 14
tLAD Logic Array Data Delay 12 14
tLAC Logic Array Control Delay 10 12
tOD Output Buffer and Pad Delay[3] 5 5
tZX[8] Output Buf fer Enab le De la y [3] 10 11
tXZ Output Buffer Disable Delay[7] 10 11
tRSU Register Set-Up Time Relative to Clock Signal at Register 6 8 10
tRH Register Hold Time Relative to Clock Signal at Register 468
tLATCH Flow Through Latch Delay 3 4
tRD Register Delay 1 2
Notes:
7. C1 = 5 pF.
8. Sample tested only for an output change of 500 mV.
CY7C342B
Document #: 38-03014 Rev. *A Page 8 of 14
Commercial and Industrial Typical Internal Switching Charact eristics Over Operating Range (continued)
Parameter Description
7C342B-25 7C342B-30 7C342B-35
UnitMin. Max. Min. Max. Min. Max.
tCOMB[9] Transparent Mode Delay 3 4 4 ns
tIC Asynchronous Clock Logic Delay 14 16 16 ns
tICS Synchronous Clock Delay 3 2 1 ns
tFD Feedback Delay 1 1 2 ns
tPRE Asynchronous Register Preset Time 5 6 7 ns
tCLR Asynchronous Register Clear Time 5 6 7 ns
tPIA Programmable Interconnect Array Delay Time 14 16 20 ns
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
COMBINATORIAL
OUTPUT
tPD1/tPD2
tWL
tSU tH
LOGIC ARRAY
tWH
External Synchronou s
CLOCK AT R EGISTER
SYNCHRONOUS
SYNCHRONOUS
LOGIC ARRAY
DATA FROM
REGISTERED
CLOCK PIN
OUTPUTS
tCO1
External Asynchro nous
t
AH
t
AS1
t
AWH
t
AWL
DEDICATED INPUTS OR
REGI STE R ED FE ED B AC K
ASYNCHRONOUS
CLOCK INPUT
Note:
9. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combina-
torial operation.
CY7C342B
Document #: 38-03014 Rev. *A Page 9 of 14
Switching Waveforms (continued)
tIN
IO
tEXP
tLAC,t
LAD
tCOMB tOD
INPUT PI N
I/O PIN
LOGIC ARRAY
LOGIC ARRAY
OUTPUT
INPUT
ARRAY DELAY
EXPANDER
OUTPUT
PIN
t
Internal Combinatorial
Internal Synchronous
tXZ tZX
tOD
HIGH IMPEDANCE
CLOCK FROM
LOGIC ARRAY
LOGIC ARRAY
DATA FROM
OUTPUT PIN
tRD
STATE
Internal Asynchronous
tIO tAWH tAWL tF
tIN
tIC
tRSU tRH
tRD,tLATCH tFD tCLR,tPRE tFD
CLOCK PI N
LOGIC ARRAY
LOGIC ARRAY
CLOCK FROM
DATA FROM
CLOCK INTO
LOGIC ARRAY
REGISTER OUTPUT
TO ANOTHER LAB
tPIA
TO LOCAL LAB
REGISTER OUTPUT
LOGIC ARRAY
tR
CY7C342B
Document #: 38-03014 Rev. *A Page 10 of 14
Switching Waveforms (continued)
tIN tICS
tRSU tRH
SYSTEM CLOCK
AT REGISTER
DATA FROM
LOGIC ARRAY
Internal Synchronous
SYSTEM CLOCK PIN
Ordering Information
Speed (ns) Ordering Code Package Name Package Type Operating Range
15 CY7C342B-15JC/JI J81 68-lead Plastic Leaded Chip Carrier Commercial/
Industrial
20 CY7C342B-20JC/JI J81 68-lead Plastic Leaded Chip Carrier Commercial/
Industrial
25 CY7C342B-25HC/HI H81 68-pin Windowed Leaded Chip Carrier Commercial/
Industrial
CY7C342B-25JC/JI J81 68-lead Plastic Leaded Chip Carrier
CY7C342B-25RC/RI R68 68-pin Windowed Ceramic Pin Grid Array
30 CY7C342B-30JC/JI J81 68-lead Plastic Leaded Chip Carrier Commercial/
Industrial
35 CY7C342B-35JC/JI J81 68-lead Plastic Leaded Chip Carrier Commercial/
Industrial
CY7C342B-35RJ/RI R68 68-pin Windowed Ceramic Pin Grid Array
CY7C342B
Document #: 38-03014 Rev. *A Page 11 of 14
Package Diagrams
68-pin Windowed Leaded Chip Carrier H81
51-80080
CY7C342B
Document #: 38-03014 Rev. *A Page 12 of 14
Package Diagrams (continued)
68-lead Plastic Leaded Chip Carrier J81
51-85005-A
CY7C342B
Document #: 38-03014 Rev. *A Page 13 of 14
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
MAX and Warp are registered trademarks and Warp Professional and Warp Enterprise are trademarks of Cypress Semiconductor
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams (continued)
68-Pin Windowed PGA Ceramic R68
51-80099-*A
CY7C342B
Document #: 38-03014 Rev. *A Page 14 of 14
Document T itl e: CY7C3 42B 128 -Ma croce ll MAX® EPLD
Document Numbe r: 38-030 14
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 106314 04/25/01 SZV Change from Spec number: 38-00119 to 38-03014
*A 113612 04/11/02 OOR PGA package diagram dimensions were updated
