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FEATURES APPLICATIONS
PACKAGE AND PIN-OUT
SN65MLVD2DRB
SN65MLVD3DRB
SON-8
VCC
RE
R
GND
VCC
B
A
GND
1
2
3
4
8
7
6
5
DESCRIPTION
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
SINGLE M-LVDS RECEIVERS
•Parallel Multipoint Data and Clock•Low-Voltage Differential 30- Ωto 55- ΩLine
Transmission via Backplanes and CablesReceivers for Signaling Rates
(1)
up to
•Cellular Base Stations250Mbps; Clock Frequencies up to 125MHz
•Central Office Switches•SN65MLVD2 Type-1 Receiver Incorporates 25
•Network Switches and RoutersmV of Input Threshold Hysteresis•SN65MLVD3 Type-2 Receiver Provides 100mV Offset Threshold to Detect Open-Circuitand Idle-Bus Conditions•Wide Receiver Input Common-Mode VoltageRange, –1 V to 3.4 V, Allows 2 V of GroundNoise
•Improved V
IT
(35 mV)•Meets or Exceeds the M-LVDS StandardTIA/EIA-899 for Multipoint Topology•High Input Impedance with Low SupplyVoltage
•Bus-Pin HBM ESD Protection Exceeds 9 kV•Packaged in 8-Pin SON (DRB) 70% SmallerThan 8-Pin SOIC(1)
The signaling rate of a line is the number of voltagetransitions that are made per second, expressed in the unitsbps (bits per second).
The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in fullcompliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to250 Mbps. Each receiver channel is controlled by a receive enable ( RE). When RE = low, the correspondingchannel is enabled; when RE = high, the corresponding channel is disabled.
The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers(SN65MLVD2) have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations withloss of input; Type-2 receivers (SN65MLVD3) implement a failsafe by using an offset threshold. Receiveroutputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges.
The devices are characterized for operation from –40 °C to 85 °C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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M-LVDS
Receivers
M-LVDS
Receivers
M-LVDS
Receivers
M-LVDS
Receivers
M-LVDS
Receivers
M-LVDS
Receivers
M-LVDS
Transceiver
M-LVDS
Transceiver
M-LVDS
Transceiver
(SystemClock-Secondary)
8KHz 19.44MHz
Userdefinedfrequency
<100MHz
80 RT
80 RT
80 RT
80 RT
80 RT
80 RT
80 RT
80 RT
80 RT
80 RT
80 RT
80 RT
CLK1A (8KHz)
CLK1B(8KHz)
CLK2A (19.44MHz)
CLK2B(19.44MHz)
CLK3A (userdefinedfrequency)
CLK3B(userdefinedfrequency)
CLK1A
8KHz
CLK1B
8KHz
CLK3A CLK3B
Userdefinedfrequency
LineCard1-N
AdvancedTCA Backplane-SynchronizedSystemClock
M-LVDS
Transceiver
M-LVDS
Transceiver
M-LVDS
Transceiver
(SystemClock-Primary)
8KHz 19.44MHz
Userdefinedfrequency
<100MHz
CLK2A
19.44MHz
CLK2B
19.44MHz
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
TYPICAL APPLICATION
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ABSOLUTE MAXIMUM RATINGS
PACKAGE DISSIPATION RATINGS
(1)
THERMAL CHARACTERISTICS
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
PART NUMBER FUNCTION PART MARKING PACKAGE / CARRIER
SN65MLVD2DRBT M-LVDS Type 1 Receiver MF2 8-Pin SON / Small Tape and ReelSN65MLVD2DRBR M-LVDS Type 1 Receiver MF2 8-Pin SON / Tape and ReelSN65MLVD3DRBT M-LVDS Type 2 Receiver MF3 8-Pin SON / Small Tape and ReelSN65MLVD3DRBR M-LVDS Type 2 Receiver MF3 8-Pin SON / Tape and Reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
V
CC
Supply voltage range
(2)
–0.5 to 4 VRE –0.5 to 4 VInput voltage range
A or B –1.8 to 4 VOutput voltage range R –0.3 to 4 VHuman-body model
(3)
All other pins ±7
kVA, B ±9Electrostatic discharge
Machine model
(4)
All pins ±200 VField-induced-charged-device model
(5)
All pins ±2 kVContinuous power dissipation See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A. Bus pin stressed with respect to a common connection of GNDand V
CC
.(4) Tested in accordance with JEDEC Standard 22 Test Method A115-A.(5) Tested in accordance with EIA-JEDEC JESD22-C101C.
T
A
≤25 °C DERATING FACTOR
(2)
T
A
= 85 °CPACKAGE PCB TYPE
POWER RATING ABOVE T
A
= 25 °C POWER RATING
Low-K 280 mW 2.80 mW/ °C 112 mW8-SON DRB
High-K 662 mW 6.62 mW/ °C 264 mW
(1) The thermal dissipations are in the consideration of soldering down the powerPAD without via on each type of boards.(2) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
θ
JB
Junction-to-board thermal resistance 89 °C/Wθ
JC
Junction-to-case thermal resistance 98 °C/WP
D
Device power dissipation RE at 0 V, C
L
= 15 pF, V
ID
= 400 mV, 125 MHz 90 mW
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RECOMMENDED OPERATING CONDITIONS
DEVICE ELECTRICAL CHARACTERISTICS
RECEIVER ELECTRICAL CHARACTERISTICS
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VV
IH
High-level input voltage 2 V
CC
VV
IL
Low-level input voltage GND 0.8 VV
A
or V
B
Voltage at any bus terminal –1.4 3.8 V|V
ID
| Magnitude of differential input voltage 0.035 V
CC
VV
IC
Differential common-mode input voltage –1 3.4 VR
L
Differential load resistance 30 50 Ω1/t
UI
Signaling rate 250 MbpsT
A
Operating free-air temperature –40 85 °C
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
I
CC
Supply current RE at 0 V, C
L
= 15 pF, V
ID
= 400 mV, 125 MHz 25 mA
(1) All typical values are at 25 °C and with a 3.3-V supply voltage.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT+
Positive-going differential input voltage Type 1 35
mVthreshold
Type 2 135V
IT–
Negative-going differential input voltage Type 1 –35See Figure 1 ,Table 1 and Table 2 mVthreshold
Type 2 65V
HYS
Differential input voltage hysteresis Type 1 25
mV(V
IT+
– V
IT–
)
Type 2 0V
OH
High-level output voltage I
OH
= –8 mA 2.4 VV
OL
Low-level output voltage I
OL
= 8 mA 0.4 VI
IH
High-level input current V
IH
= 2 V to V
CC
–10 µAI
IL
Low-level input current V
IL
= GND to 0.8 V –10 µAI
OZ
High-impedance output current V
O
= 0 V or V
CC
–10 15 µAI
A
or I
B
Receiver input current One input (V
A
or V
B
) = –1.4 V or 3.8 V, –20 20 µAOther input = 1.2 VI
AB
Receiver differential input current (I
A
– I
B
) V
A
= V
B
= –1.4 V or 3.8 V –4 4 µAI
A(OFF)
or One input (V
A
or V
B
) = –1.4 V or 3.8 V,I
B(OFF)
Receiver input current Other input = 1.2 V, V
CC
= GND or 1.5 –20 20 µAVI
AB(OFF)
Receiver power-off differential input current (I
A
– I
B
) V
A
= V
B
= –1.4 V or 3.8 V, V
CC
= GND –4 4 µAor 1.5 VC
A
or C
B
Input capacitance V
I
= 0.4sin(30E6 πt) + 0.5V,
(2)
3 pFOther input at 1.2 VC
AB
Differential input capacitance V
AB
= 0.4sin(30E6 πt) + 0.5 V
(2)
2.5 pFC
A/B
Input capacitance balance, (C
A
/C
B
) 0.99 1.01
(1) All typical values are at 25 °C and with a 3.3-V supply voltage.(2) HP4194A impedance analyzer (or equivalent)
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RECEIVER SWITCHING CHARACTERISTICS
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 2 6 nst
PHL
Propagation delay time, high-to-low-level output 2 6 nst
r
Output signal rise time 1 2.3t
f
Output signal fall time C
L
= 15 pF, See Figure 2 1 2.3 nsType 1 90 210t
sk(p)
Pulse skew (|t
PHL
– t
PLH
|) psType 2 45 250t
sk(pp)
Part-to-part skew 1 nst
jit(per)
Period jitter, rms (1 standard deviation)
(2)
125 MHz clock input 10 pst
jit(c-c)
Cycle-to-cycle jitter, rms
(3)
125 MHz clock input
(4)
8 psType 1 500 pst
jit(det)
Deterministic jitter
(2)
250 Mbps 2
15
-1 PRBS input
(5)Type 2 450 psType 1 8 pst
jit(ran)
Random jitter
(2)
250 Mbps 2
15
-1 PRBS input
(5)Type 2 8 pst
PZH
Enable time, high-impedance-to-high-level output C
L
= 15 pF, See Figure 3 15 nst
PZL
Enable time, high-impedance-to-low-level output C
L
= 15 pF, See Figure 3 15 nst
PHZ
Disable time, high-level-to-high-impedance output C
L
= 15 pF, See Figure 3 10 nst
PLZ
Disable time, low-level-to-high-impedance output C
L
= 15 pF, See Figure 3 10 ns
(1) All typical values are at 25 °C and with a 3.3-V supply voltage.(2) Jitter measured by triggering off of the input source to track out the associated input jitter.(3) Stimulus jitter has been subtracted from the numbers.(4) Measured over 75K samples(5) Measured over BER = 10
–6
.
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
A 6 I M-LVDS Non-inverting inputB 7 I M-LVDS Inverting inputR 3 O Data output from receiversRE 2 I Receiver enable, active low, enables all receiversGND 4, 5 Circuit groundV
CC
1, 8 Supply voltage
DEVICE FUNCTION TABLES
TYPE-1 RECEIVER (SN65MLVD2) TYPE-2 RECEIVER (SN65MLVD3)
INPUTS
(1)
OUTPUT
(1)
INPUTS
(1)
OUTPUT
(1)
V
ID
= V
A
– V
B
RE R V
ID
= V
A
– V
B
RE RV
ID
≥35 mV L H V
ID
≥135 mV L H–35 mV ≤V
ID
≤35 mV L ? 65 mV ≤V
ID
≤135 mV L ?V
ID
≤– 35 mV L L V
ID
≤65 mV L LX H Z X H ZX Open Z X Open ZOpen Circuit L ? Open Circuit L L
(1) H=high level, L=low level, Z=high impedance, X=Don’t care, ?=indeterminate
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
200kW
250kW
100kW
AB
ReceiverInput
7V
10 W
R
ReceiverOutput
7V
400 W
VCC
RE
ReceiverEnable
360kW
VCC
100kW
250kW
200kW
10 W
VCC
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
6
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PARAMETER MEASUREMENT INFORMATION
(V A+V B)/2
VA
VB
VO
VCM
VID
R
A
B
IA
IB
IO
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
Figure 1. Receiver Voltage and Current Definitions
Table 1. Type-1 Receiver Input Threshold Test Voltages
RESULTINGRESULTING DIFFERENTIALAPPLIED VOLTAGES COMMON-MODE INPUT
RECEIVERINPUT VOLTAGE
VOLTAGE
OUTPUT
(1)
V
IA
V
IB
V
ID
V
IC
2.400 0.000 2.400 1.200 H0.000 2.400 – 2.400 1.200 L3.400 3.365 0.035 3.3825 H3.365 3.400 – 0.035 3.3825 L–0.965 –1 0.035 –0.9825 H–1 –0.965 – 0.035 –0.9825 L
(1) H= high level, L = low level, output state assumes receiver is enabled ( RE = L)
Table 2. Type-2 Receiver Input Threshold Test Voltages
RESULTINGRESULTING DIFFERENTIALAPPLIED VOLTAGES COMMON-MODE INPUT
RECEIVERINPUT VOLTAGE
VOLTAGE
OUTPUT
(1)
V
IA
V
IB
V
ID
V
IC
2.400 0.000 2.400 1.200 H0.000 2.400 – 2.400 1.200 L3.400 3.265 0.135 3.3325 H3.4000 3.335 0.065 3.3675 L–0.865 –1 0.135 –0.9325 H–0.935 –1 0.065 –0.9675 L
(1) H= high level, L = low level, output state assumes receiver is enabled ( RE = L)
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VA
VB
VID
C
15pF
LVO
0V
90%
10%
0.8V
1.2V
VA
VB
VID
VO
tPHL tPLH
tftr
0.4V
-0.4V
VOL
VCC
VOH
2
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, Frequency = 1 MHz,duty cycle = 50 ±5%. C
L
is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixturecapacitance within 2 cm of the D.U.T.B. The measurement is made on test equipment with a –3dB bandwidth of at least 1 GHz.
Figure 2. Receiver Timing Test Circuit and Waveforms
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B
A
1.2V
Inputs
RE
C
15pF
LVO
R
499
L
W
VTEST
tPZL tPLZ
VTEST
A
RE
VO
VTEST
A
RE
VO
VCC
0.8V
VCC
0V
V +0.5V
OL
VOL
VCC
1.6V
0V
0V
VCC
VOH
VOH
0V
tPZH
tPHZ
VCC
2
VCC
2
VCC
2
VCC
2
0.5V
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, frequency = 1 MHz,duty cycle = 50 ±5%.B. R
L
is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.TC. C
L
is the instrumentation and fixture capacitance within 2 cm of the D.U.T. and ±20%. The measurement is made ontest equipment with a –3dB bandwidth of at least 1GHz.
Figure 3. Receiver Enable/Disable Time Test Circuit and Waveforms
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SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
A. All input pulses are supplied by the Agilent 81250 Parallel BERT Stimulus System with plug-in E4832A.B. The cycle-to-cycle jitter measurement is made on a TEK TDS6604 running TDSJIT3 application softwareC. Period jitter is measured using a 125-MHz 50 ±1% duty cycle clock input.D. Deterministic jitter and random jitter are measured using a 250-Mbps 2
15-1
PRBS input
Figure 4. Receiver Jitter Measurement Waveforms
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TYPICAL CHARACTERISTICS
0
2
4
6
8
10
12
25 50 75 100 125
f-Frequency-MHz
I -SupplyCurrent-mA
CC
MLVD3(Type2)
MLVD2(Type1)
V =3.3V,
T =25 C,
V =400mV,
V =1V
CC
A
ID
IC
º
2
2.5
3
3.5
4
4.5
5
5.5
6
-40 -8.75 22.5 53.75 85
T -Free-AirTemperature- C
A
º
P -PropagationDelayTime-ns
D
tPHL
tPLH
V =3.3V,
f=1MHz,
C =15pF
CC
L
2
2.5
3
3.5
4
4.5
5
5.5
6
-40 -8.75 22.5 53.75 85
T -Free-AirTemperature- C
A
º
P -PropagationDelayTime-ns
D
V =3.3V,
f=1MHz,
C =15pF
CC
L
tPHL
tPLH
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
-40 -8.75 22.5 53.75 85
t/t -Rising/FallingTransitionTime-ns
rf
tr
tf
T -Free-AirTemperature- C
A
º
V =3.3V,
f=1MHz,
C =15pF
CC
L
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
SUPPLY CURRENT RECEIVER (TYPE-1) PROPAGATION DELAY TIMEvs vsFREQUENCY FREE-AIR TEMPERATURE
Figure 5. Figure 6.
RECEIVER (TYPE-2) PROPAGATION DELAY TIME RECEIVER (TYPE-1) TRANSITION TIMEvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 7. Figure 8.
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1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
-40 -8.75 22.5 53.75 85
t /t -Rising/FallingTransitionTime-ns
r f
tr
tf
T -Free-AirTemperature- C
A
º
V =3.3V,
f=1MHz,
C =15pF
CC
L
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
5 7.5 11 13 15
t/t -Rising/FallingTransitionTime-ns
r f
C -OutputLoadCapacitor-pF
L
tr
tf
V =3.3V,
f=1MHz,
C =15pF
CC
L
100
150
200
250
300
350
400
450
500
50 100 150 200 250
SignalingRate-Mbps
t -Peak-to-PeakJitter-ps
jit(pp)
MLVD2(Type1)
MLVD3(Type2)
V =3.3V,T =25 C,
2 -1PRBSNRZ,
SeeFigure4
CC A
15
º
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
5 7.5 11 13 15
t/t -Rising/FallingTransitionTime-ns
r f
C -OutputLoadCapacitor-pF
L
tr
tf
V =3.3V,
f=1MHz,
C =15pF
CC
L
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
RECEIVER (TYPE-2) TRANSITION TIME RECEIVER (TYPE-1) TRANSITION TIMEvs vsFREE-AIR TEMPERATURE OUTPUT LOAD CAPACITOR
Figure 9. Figure 10.
RECEIVER (TYPE-2) TRANSITION TIME ADDED RECEIVER PEAK-TO-PEAK JITTERvs vsOUTPUT LOAD CAPACITOR SIGNALING RATE
Figure 11. Figure 12.
12
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0
1
2
3
4
5
25 50 75 100 125
f -ClockFrequency-MHz
CLK
t rms-Cycle-to-CycleJitter-ps
jit(c-c)
MLVD2(Type1)
MLVD3(Type2)
V =3.3V,T =25 C,
SeeFigure4
CC A
º
0
1
2
3
4
5
25 50 75 100 125
f -ClockFrequency-MHz
CLK
t rms-PeriodJitter-ps
jit(per)
MLVD3(Type2)
MLVD2(Type1)
V =3.3V,T =25 C,
SeeFigure4
CC A
º
EYE PATTERNS
666.9ps/div
33.5mV/div
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
ADDED RECEIVER PERIOD JITTER ADDED RECEIVER CYCLE-TO-CYCLE JITTERvs vsCLOCK FREQUENCY CLOCK FREQUENCY
Figure 13. Figure 14.
Figure 15. SN65MLVD2 Output (V
CC
= 3.3 V, C
L
= 15 pF) 250 Mbps 2
15
–1 PRBS
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666.9ps/div
33.5mV/div
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
Figure 16. SN65MLVD3 Output (V
CC
= 3.3 V, C
L
= 15 pF) 250 Mbps 2
15
–1 PRBS
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65MLVD2DRBR ACTIVE SON DRB 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65MLVD2DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65MLVD2DRBT ACTIVE SON DRB 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65MLVD2DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65MLVD3DRBR ACTIVE SON DRB 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65MLVD3DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65MLVD3DRBT ACTIVE SON DRB 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65MLVD3DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Dec-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65MLVD2DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
SN65MLVD2DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
SN65MLVD3DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
SN65MLVD3DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65MLVD2DRBR SON DRB 8 3000 367.0 367.0 35.0
SN65MLVD2DRBT SON DRB 8 250 210.0 185.0 35.0
SN65MLVD3DRBR SON DRB 8 3000 367.0 367.0 35.0
SN65MLVD3DRBT SON DRB 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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