INTEL CORPORATION ORDER NUMBER: 245103-003
MO BILE PENTIUM
II PROCESSOR IN
Micro-PGA AND BGA PACKAGES AT 400 M Hz, 366 MHz,
333 MHz, 300PE MHz, AND 266PE MHz
Available at 400 MHz, 366 MHz, 333 MHz,
300PE M Hz, and 266PE MHz
Supports the Intel Architecture with
Dynamic Execution
Integrated prim ary 16-Kbyte instructio n
cache and 16-Kbyte write back data cache
Integrated second level cache (256-Kbyte)
Micro-P GA and BGA packaging
technologies
— Supports thin form factor notebook
designs
— Exposed die enables more efficient heat
dissipation
Fully compatible with previous Intel
microprocessors
— Binary compatible with all applications
— Support for MM X ™ technology
Power Managem ent Features
— Quick Start and Deep Sleep m odes
provide extremely low power
dissipation
Low-Pow er GTL+ processor system bus
interface
Integrated math co-processor
Integrated thermal diode
The Intel
Mobile Pentium
II processor introduces a higher level of performanc e for today’s mobile
computing environment, including multimedia enhancements and improved Internet and communications
capabilities. It provides an improved performance1 available for applications running on advanced operating
systems such as Windows* 98. On top of its built-in power management capabilities, the Pentium II
processor takes advantage of software designed for Intel’s MMX
technology to unleash enhanced color,
sm oot her graphi cs and other multimedia and comm uni cations enhancement s.
The Mobile Pentium
II processor may contain design defects or errors know as errata that may cause the
product to devi ate from publ i shed specificati ons. Current characterized errata are avai l abl e upon request.
1. Refer to the
Mobile Pentium
II Processor Performance Brief
.
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
ii INTEL CORPORATION
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in
Intel's terms and conditions of sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or
implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions m ark ed “reserved” or “undefi ned.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.
The Mobile Pentium® II processor may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be
obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com
Copyright © Intel Corporation, 1999.
*Third-party brands and names are the property of their res pective owners.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION iii
CONTENTS
PAGE PAGE
1. INTRODUCTION..............................................1
1.1 Overview....................................................2
1.2 Terminology...............................................2
1.3 References ................................................2
2. MOBI L E PENTIUM® II PROCESSOR
FEATURES......................................................4
2.1 F eature Differences between the Mobile
Pentium® II Processor at 400 MHz and
Mobile Pentium® II P rocessor at 366 MHz
and
below ........................................................4
2.2 Power Management...................................4
2.2.1 Clock Control Architecture................4
2.2.2 Normal State ....................................6
2.2.3 Auto Halt State .................................6
2.2.4 STOP GRANT State.........................6
2.2.5 QUICK START State........................6
2.2.6 HALT/GRANT SNOOP State............7
2.2.7 SLEEP State ....................................8
2.2.8 Deep Sleep State .............................8
2.2.9 Operating Syst em Implications of
Quick Start and Sleep States............8
2.3 Low Power GTL+.......................................8
2.3.1 GTL+ Signals....................................9
2.4 Mobil e P entium® II Processor CPUID.........9
3. ELECTRICAL SPECIFICATIONS ..................11
3.1 Processor System Signals.......................11
3.1.1 P ower Sequenc i ng Requi rements... 12
3.1.2 T est Access P ort (TAP) Connect i on13
3.1.3 Catastrophic Thermal Protection ....13
3.1.4 Unused Signals ..............................13
3.1.5 S i gnal State in Low Power Stat es... 13
3.2 Power Supply Requirements.................... 14
3.2.1 Decoupling Recomm endations....... 14
3.2.2 Voltage Planes ...............................14
3.3 Syst em Bus Cl ock and Processor Cl ocking15
3.4 Maximum Ratings ....................................16
3.5 DC Specifications.....................................18
3.6 AC Specifications.....................................23
3.6.1 System Bus, Clock, APIC, TAP,
CMOS and Open-Drain AC
Specifications .................................23
4. SYSTEM SIGNAL SIMULATIONS.................37
4.1 Syst em Bus Cl ock (BCLK ) Signal Quality
Specifications...........................................37
4.2 Low Power GTL+ Signal Qual i ty
Specifications...........................................38
4.3 Non-Low Power GTL+ Signal Qual i t y
Specifications...........................................41
4.3.1 Overshoot and Undershoot Gui del i nes42
4.3.1 Ringback Specification....................43
4.3.2 Settling Limit Guideline...................43
5. MECHANICAL SPECIFICATIONS .................44
5.1 Di mensions of the Micro-PGA Package ...44
5.2 Dimensions of the BGA Package.............46
5.3 Signal Listings..........................................49
6. THERMAL SPECIFICATIONS........................62
6.1 Thermal Diode..........................................63
6.2 Case Temperature...................................64
7. PROCESSOR INITIALIZATION AND
CONFIGURATION..........................................65
7.1 Description...............................................65
7.1.1 Quick Start Enable..........................65
7.1.2 System Bus Frequency...................65
7.1.3 APIC Disable..................................65
7.2 Clock Frequencies and Ratios ..................65
8. PROCESSOR INTERFACE............................66
8.1 Alphabetical Signal Reference .................66
8.2 Signal Summaries....................................72
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
iv INTEL CORPORATION
LIST OF FIGURES
PAGE
Figure 1.1 Signal Groups of a Mobile Pent i um® II
Processor-Based System ....................1
Figure 2.1 Clock Control States.............................5
Figure 3.1 Ramp Rate Requirement..................... 13
Figure 3.2 PLL LC Filter ......................................14
Figure 3.3 Generic Clock W aveform.................... 30
Figure 3.4 Valid Delay Timings............................31
Figure 3.5 Setup and Hold Timings ..................... 31
Figure 3.6 Reset and Configuration Timings........32
Figure 3.7 Power-On Reset Timings.................... 33
Figure 3.8 Test Timings (Boundary Scan) ...........34
Figure 3.9 Test Reset Timings.............................34
Figure 3.10 Quick Start/Deep Sleep Timing......... 35
Figure 3.11 St op Grant/Sleep/ Deep Sleep Tim i ng36
Figure 4.1 BCLK Generic Clock W aveform .........38
Figure 4.2 GTL+ Receiver Ringback Tolerance....39
Figure 4.3 Maximum Acceptabl e GTL+
Overshoot/Undershoot Waveform for
the Mobile Pent i um® II Process or at
400 MHz............................................ 41
Figure 4.4 Non-GTL+ Signal Ri ngback and Set tling
Limit...................................................42
Figure 5.1 Micro-P GA Package-Top and Side
View...................................................45
Figure 5.2 Micro-PGA Package - Bottom View.... 46
Figure 5.3 Surf ace-Mount BGA P ackage - Top and
Side View...........................................48
Figure 5.4 Surf ace-Mount BGA P ackage - Bottom
View...................................................49
Figure 5.5 Pin/Ball Map - Top View ..................... 50
Figure 6.1 Techni que f or Meas uri ng Case
Temperature...................................... 64
Figure 8.1 PWRGOOD Relat ionship at Power-On70
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION v
LIST OF TABLES
PAGE PAGE
Table 2.1 VTOL, CMOS and Open Drain Signal
Characteristics.....................................4
Table 2.2 Clock State Characteristics....................7
Table 2.3 Mobile Pentium
II Processor CPUID....9
Table 2.4 Mobile Pentium
II Processor CPUID
Cache and TLB Descriptors.................9
Table 3.1 System Signal Groups......................... 11
Table 3.2 Recomm ended Resistors for Open Drain
Signals...............................................12
Table 3.3 LC Filter Specifications........................15
Table 3.4 Core Frequency t o System Bus Rat i o
Configuration .....................................15
Table 3.5 Abs ol ute Maximum Rat i ngs for Mobile
Pentium
II Processor at 400 MHz .... 16
Table 3.6 Abs ol ute Maximum Rat i ngs for Mobile
Pentium
II P rocessor at 366 MHz and
Below.................................................17
Table 3.7 Power Speci ficati ons for Mobile
Pentium® II Processor at 400 MHz.... 18
Table 3.8 Power Speci ficati ons for Mobile
Pentium® II P rocessor at 366 MHz and
Below.................................................19
Table 3.9 Power Speci ficati ons for Low Voltage
Pentium® II Processor.......................20
Table 3.10 Low Power GTL+ Signal Group DC
Specifications ....................................21
Table 3.11. Low Power GTL+ Bus DC
Specifications ....................................21
Table 3.12 Cloc k, APIC, TAP, CMOS and Open-
Drain Signal Group DC S pecific ations
for the Mobile P ent i um® II P rocessor at
400 MHz............................................ 22
Table 3.13 Cloc k, APIC, TAP, CMOS and Open-
Drain Signal Group DC S pecific ations
for the Mobile P ent i um® II P rocessor at
366 MHz and Below........................... 23
Table 3.14 Sys t em Bus Cl ock AC Specific ations.24
Table 3.15 Vali d Mobil e Pentium
II Processor
Frequencies.......................................25
Table 3.16 Low Power GTL+ Signal Groups A C
Specifications ....................................25
Table 3.17 CMOS and Open-Drain S i gnal Groups
AC Specifications .............................. 26
Table 3.18 Reset Configuration A C S pecific ations27
Table 3.19 TAP Signal AC Specifications............28
Table 3.20 Quic k Start/Deep Sleep AC
Specifications.....................................29
Table 3.21 St op Grant/Sleep/ Deep Sleep AC
Specifications.....................................29
Table 4.1 BCLK Signal Quality Specifications......37
Table 4.2 Low Power GTL+ Signal Group Ringback
Specif i cation for the Mobile Pentium® II
Processor ..........................................39
Table 4.3. GTL+ Si gnal Group
Overshoot/Undershoot Tolerance at the
Proces sor Core for the Mobile
Pentium® II P rocessor at
400 MHz............................................40
Table 4.4 Signal Ri ngback Spec i ficati ons for Non-
GTL+ Signals f or the Mobile Pentium®
II Processor at 400 MHz.....................43
Table 4.5 Signal Ri ngback Spec i ficati ons for Non-
GTL+ Signals f or the Mobile Pentium®
II Processor at 366 MHz and Bel ow.. .43
Table 5.1 Micro-P GA Package Mec hani cal
Specifications.....................................44
Table 5.2 Surf ace-Mount BGA P ackage
Specifications.....................................47
Table 5.3 Signal Li sting in Order by P i n/Ball
Number..............................................51
Table 5.4 Signal Li sting in Order by S i gnal Name 57
Table 5.5 Voltage and No-Connect B al l / Pin
Locations...........................................61
Table 6.1 Mobile Pentium
II Processor (0.18
m)
Power Specifications ..........................62
Table 6.2 Thermal Diode Interface.......................63
Table 6.3. Thermal Diode Specifications .............63
Table 8.1 Input Signals........................................73
Table 8.2 Output Signals.....................................74
Table 8.3 Input/Output Signals (Single Driver).....74
Table 8.4 Input /Output S i gnal s (Multiple Driver).. .75
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 1
1. INTRODUCTION
The Mobile Pentium ® II process or is now offered at
400 MHz, 366 MHz, 333 MHz, 300PE MHz, and
266PE MHz, with a system bus speed of 66 MHz.
The Mobile Pentium® II processor at 400 MHz in
Micro-PGA and BGA packages are the first mobile
processors manufactured in 0.18
m technology.
Processors at frequencies 366 MHz and below are
manufactured in 0.25
m processing technology.
The Mobile Pentium® II processor consists of a
processor core with an integrated L2 cache and a
64-bit high performanc e system bus. The integrated
L2 cache is designed to help improve performance;
it complements the system bus by providing critical
data faster and reducing total system power
consumption. The Mobile Pent i um® II processor’s
64-bit wide Low Power Gunning Transceiver Logic
(GTL+) system bus is compatible with the 440BX
AGPSet and provides a glue-less, point-to-point
interface for an I/O bridge/memory controller.
Figure 1.1 shows the various parts of a Mobile
Pentium II processor-based system and how the
Mobile Pentium II processor c onnects to them.
Mobile
Pentium® II
Processor
443BX
North Bri d ge
PIIX4E/M
South Bridge
PCI
ISA/EIO
TAP
CMOS/
Open Dr ain
DRAM
System
Bus
Thermal
Sensor
SMBus
System
Controller
V0000-05
OR
Figure 1.1 Signal Groups of a Mobile Pentium® II Processor-Based System
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
2INTEL CORPORATION
1.1 Overview
• Performance improved over existing mobile
processors
• Support s the Intel Architecture with Dynam i c
Execution
• Support s the Intel Architecture MMX
technology
• Int egrated Intel Fl oat i ng-Point Unit
compat ible with the I EEE 754 standard
• Integrated pri mary (L1) instruction and data
caches
• 4-way set associ at ive, 32-byte li ne size,
1 line per sec tor
• 16-Kbyte instruction c ache and 16-Kbyte
writeback data cache
• Cacheable range programm abl e by
process or programm abl e regi sters
• Integrated second level (L2) c ache
• 4-way set associ at ive, 32-byte li ne size, 1
line per sec tor
• Operates at full c ore speed
• 256-Kbyte, ECC prot ected cac he data array
• 4 Gbyte c acheable range
• Low Power GTL+ system bus interface
• 64-bit data bus, 66-MHz operation
• Uniprocessor, t wo loads onl y (processor and
I/O bri dge/ memory control l er)
• Short trace length and l ow capac i t ance
allows for si ngl e ended termination
• Voltage reduc tion technol ogy
• Advanced processor cl oc k control
• Quic k Start for low power, low exit latenc y
clock “throttl i ng”
• Deep Sleep mode for extrem el y l ow power
dissipation
• Thermal di ode f or measuri ng proc essor
temperature
1.2 Terminology
In this document a ‘#’ symbol following a signal
name indicates that the signal is active low. This
means that when the signal is asserted (based on
the nam e of the signal) it is in an electri cal low state.
Otherwise, signals are driven in an electrical high
state when they are asserted. In state machine
diagrams , a signal nam e in a condi tion indic ates t he
condition of that signal being asserted. If the signal
name is preceded by a ‘!’ symbol, then it indicates
the condition of that signal not being asserted. For
example, the condition ‘!STPCLK# and HS’ is
equivalent to ‘the active low signal STPCLK# is
unasserted (i.e., it is at 1.5V for the 400 MHz, and
2.5V for the 366 MHz and below)
and
the HS
condition is true.’ The symbols ‘L’ and ‘H’ refer
respectively to electrical low and electrical high
signal levels. The symbols ‘0’ and ‘1’ refer
respectively to logical low and logical high signal
levels. For example, BD[3:0] = ‘1010’ = ‘HLHL’
refers to a hexadecimal ‘A’, and D[3:0]# = ‘1010’ =
‘LHLH’ also refers to a hexadecimal ‘A’ .
1.3 References
Pentium
®
II Processor at 233 M Hz, 266 MHz, 300
MHz and 333 MHz
(Order Number 243335)
Pentium
®
II Processor Dev el oper’s Manual
(Order Number 243502)
CKDM66-M Cl ock Driv er Specifi cation
(Contact your Intel Field Sales Representative)
CK97 Clock Driver S pecification
(Contact your Intel Field Sales Representative)
Intel A rchitecture Software Developer’s Manual
(Order Number 243193)
Volume I: Basic Architecture
(Order Number 243190)
Volume II: Instruction Set Reference
(Order Number 243191)
Volume III: System Programming Guide
(Order Number 243192)
Mobile Pentium II Processor (0. 18
m)I/O Buffer
Models, IBIS Format
(Available i n el ectronic f orm;
contac t your Intel Field Sales Representative)
Mobile Pentium
®
II Processor S ystem Bus Layout
Guideline
(Order Number 243672-001)
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 3
Mobile Pentium
®
II Processor M ec hani cal and
Thermal Design Guide
(Order Number 243671-001)
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
4INTEL CORPORATION
2. MOBILE PENTIUM® II PROCESSOR
FEATURES
2.1 Feature Differences between the
Mobile Pentium® II Processor at
400 MHz and Mobile Pentium® II
Processor at 366 MHz and below
Power specifications
CPUID
CMOS/Open Drain si gnal vol tage tolerance
Pull-up/pull-down recommendation for almost
all signal s
CMOS signal DC s pecific ations
CMOS signal A C s pecific ations
VTOL pin impedance
Core voltages, VCC and VCCP
Table 2.1 VTOL, CMOS and Open Drai n S i gnal Characteristics
Mobile Pentium® II
Processor VTOL Pin CMOS/Open Drain Signal
Voltage Tolerance (VCMOS)CMOS/Open Drain Signal
Trip Voltage (VTRIP)
400 MHz Short to Vss 1.5V 0.75V
366 MHz and below High Impedance 2.5V 1.25V
2.2 Power Management
2.2.1 Clock Control Architecture
The Mobile Pentium
II processor clock control
architecture (Figure 2.1) has been optimized for
leading edge “Deep Green” desktop and mobile
com put er designs.
The Auto Halt state provides a low power clock st ate
that can be controlled through the software
execution of the HLT instruction. The Quick Start
state provides a very low power, low exit latency
clock state that can be us ed for hardware controlled
“idle” computer states. The Deep Sleep state
provides an extremely low power state that can be
used for “Power-on Suspend” computer states,
which is an alt ernative to shut ting off the processor’s
power. Compared to the Pentium processor exit
latency of 1 msec, the exit latency of the Deep
Sleep state has been reduced to 30
sec in the
Mobile Pentium II processor. The Stop Grant and
Sleep states shown in Figure 2.1 are intended for
use in “Deep Green” desk top and s erver s yst em s —
not in mobile systems. Performing state transitions
not shown in Figure 2.1 i s neit her recomm ended nor
supported.
The clock control architecture consists of seven
different clock states: Normal, Auto Halt, Stop
Grant, Quick Start, HALT/Grant Snoop, Sleep and
Deep Sleep states . The Stop Grant and Quick Start
clock states are m utually exclusive, i.e. , a st rapping
option on signal A15# chooses which state is
entered when the STPCLK# signal is asserted.
Strapping the A15# signal to ground at Reset
enables the Quick Start state; otherwise, asserting
the STPCLK# signal puts the processor into the
Stop Grant s tate. The Stop Grant s tate has a hi gher
power level than the Quick Start state and is
designed for SMP platforms. The Quick Start state
has a much lower power level, but it can only be
used in uniprocessor platforms. Table 2.2 provides
clock state characteristics (power numbers based
on estimates for a Mobile Pentium II processor at
400 MHz and 366 MHz), which are described in
detail in the following sec tions.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 5
HALT/Grant
Snoop
Normal
HS=false
Stop
Grant
Auto
Halt
HS=true
Quick
Start
Sleep
Deep
Sleep
(!STPCLK#
and !HS) or
stop break
STPCLK# and
!QSE and SGA
Snoop
occurs
Snoop
serviced
STPCLK# and
QSE and SGA
(!STPCLK# and !HS)
or RESET#
Snoop
serviced Snoop
occurs
!STPCLK#
and HS
STPCLK# and
!QSE and SGA
HLT and
halt bus cycle
halt
break
Snoop
serviced
Snoop
occurs
STPCLK# and
QSE and SGA
!STPCLK#
and HS
!SLP# or
RESET#
SLP#
BCLK
stopped
BCLK on
and !QSE
BCLK
stopped
BCLK on
and QSE
V0001-00
NOTES: halt break - A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#
HLT - HLT instruc t i on executed
HS - Proc essor Halt State
QSE - Quic k Start State Enabl ed
SGA - Stop Grant Acknowledge bus cycle issued
Stop break - BINIT#, FLUSH#, RESET#
Figure 2.1 Clock Control States
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
6INTEL CORPORATION
2.2.2 Normal State
The Normal state of the processor is the normal
operating m ode where the proces sor’s internal c loc k
is running and the processor is actively executing
instructions.
2.2.3 Auto Hal t S tate
This is a low power mode entered by the processor
through the execution of the HLT instruction. The
power level of this mode is sim ilar to the Stop Grant
state. A transition to the Normal state is made by a
halt break event (one of the following signals going
active: NMI, INTR, BINIT#, INIT#, RESET#,
FLUSH# or SMI# ).
Assert ing the STPCLK # si gnal while in the A uto Hal t
state will cause the processor to transition to the
Stop Grant or Qui ck St art st ate, where a Stop Grant
Acknowledge bus cycle will be issued. Deasserting
STPCLK# will cause the processor to return to the
Auto Halt state without i s suing a new Halt bus c yc l e.
The SMI# interrupt is recognized in the Auto Halt
state. The return from the System Management
Interrupt (SMI) handler can be to either the Normal
state or the Auto Halt state. See the
Intel
®
Architecture Software Developer’s Manual, Volume
III: System Programmer’s Guide
for more
information. No Halt bus cycle is issued when
returning to the Auto Halt state from System
Management Mode (SMM).
The FLUSH# signal is serviced in the Auto Halt
state. After the on-chip and off-chip caches have
been flushed, the processor will return to the Auto
Halt state without issuing a Halt bus cycle.
Transitions in the A20M# and PREQ# signals are
recognized while in the Auto Halt s tate.
2.2.4 STOP GRANT State
The processor enters this mode with the assertion
of the STPCLK# signal when it is configured for
Stop Grant state (via the A15# strapping option).
The processor is still able to respond to snoop
requests and latch int errupts. Latched interrupts will
be serviced when the processor returns to the
Normal st ate. Only one occurrence of each i nterrupt
event will be latched. A transition back to the
Normal state can be made by the de-assertion of
the STPCLK# signal, or the occurrence of a stop
break event (a BINIT#, FLUSH# or RESET#
assertion).
The processor will return to the Stop Grant state
after the completion of a BINIT# bus initialization
unless STPCLK# has been de-asserted. RESET#
assertion will cause the processor to immediately
initialize itself, but the processor will stay in the Stop
Grant state after initialization until STPCLK# is
deasserted. If the FLUSH# signal is asserted, the
processor will flus h the on-c hip caches and ret urn t o
the Stop Grant state. A t ransiti on to the Sleep state
can be m ade by t he assertion of the SLP# signal.
While in the Stop Grant state, assertions of SMI#,
INIT#, INTR and NMI will be latched by the
processor. These latched events will not be serviced
until the process or returns to the Normal s tate. Only
one of each event will be recognized upon return to
the Norm al s tate.
2.2.5 QUICK START State
This is a mode entered by the processor with the
assertion of the STPCLK# signal when it is
configured for the Quick Start state (via the A15#
strapping option). In the Quick Start state the
processor is only capable of acting on snoop
transactions generated by the system bus priority
device. Because of its snooping behavior, Quick
Start can only be used in a Uniprocessor (UP)
configuration.
A transi tion to the Deep S l eep state can be made by
stopping the clock input to the processor. A
transition back to the Normal state (from the Quick
Start state) is made only if the STPCLK# signal is
deasserted.
While in this state the processor is limited in its
ability to respond to input. It is inc apable of latching
any interrupts, servicing snoop transactions from
symm et ric bus m as ters or respondi ng to FLUS H# or
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 7
BINIT# assertions. While the processor is in the
Quick Start state, it will not respond properly to any
input signal other than STPCLK#, RESET# or
BPRI#. If any other input signal changes, then the
behavior of the processor will be unpredictable. No
serial interrupt messages may begin or be in
progress while the processor is in the Quick Start
state.
RESET# assertion will cause the processor to
immediately initialize itself, but the processor will
stay in the Quick Start state after initialization until
STPCLK# i s deassert ed.
Table 2.2 Clock State Characteristics
Clock State Exit Latency Power Snooping? System Uses
Normal N/A Varies Yes Normal program execution
Auto Halt Approximatel y 10 bus clocks 1.25 W Yes S/W c ontrolled entry idl e
mode
Stop Grant Approximatel y 10 bus clocks 1.25 W Yes H/W controlled entry/ exit
mobile throttling
Quick S tart Through snoop, to
HALT/Grant Snoop stat e:
immediate
Through STPCLK#, to Norm al
state: 8 bus clocks
0.5 W Yes H/W controlled entry/ exit
mobile throttling
HALT/Grant
Snoop A few bus clocks after the end
of snoop ac tivity. Not spec i f i ed Yes Supports snoopi ng i n the low
power states
Sleep To Stop Grant state 10 bus
clocks 0.5 W No H/W cont rol l ed entry/exit
deskt op i dl e mode support
Deep Sleep 30
sec 150 mW No H/W controlled entry/exit
powered-on suspend support
NOTE: Not 100% tested. S pec i fied at 50°C by des i gn/charact eri zation.
2.2.6 HAL T/GRANT SNOOP State
The processor will respond to s noop trans act ions on
the system bus while in the Auto Halt, Stop Grant or
Quick Start state. When a snoop transaction is
presented on the system bus the processor will
enter the HALT/Grant Snoop state. The processor
will remain in this state until the snoop has been
serviced and the system bus is quiet. A fter the
snoop has been serviced, the processor will return
to its previous state. If the HALT/Grant Snoop state
is entered f rom the Quick S tart state, then the input
signal restrictions of the Quick Start state still apply
in the HALT/Grant Snoop state, except for those
signal transitions that are required to perform the
snoop.
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
8INTEL CORPORATION
2.2.7 SLEEP State
The Sleep state is a very low power state in which
the processor maintains its context and the phase-
locked loop (PLL) maintains phase lock. The Sleep
state c an only be ent ered from t he S top Grant s tat e.
After ent ering the Stop Grant state, the SLP # signal
can be asserted, causi ng t he processor to enter t he
Sleep state. The SLP# signal is not recognized in
the Norm al or A uto Halt states.
The processor can be reset by the RESET# signal
while in the Sleep state. If RESET# is driven active
while the processor is in the Sleep state then SLP#
and STPCLK# must immediately be driven inactive
to ensure that the processor correctly initializes
itself.
Input signals (other than RESET#) may not change
while the processor is in the Sleep state or
transitioning into or out of the Sleep state. Input
signal changes at these times will cause
unpredictable behavior. Thus, the processor is
incapable of snooping or latching any events in the
Sleep st ate.
W hile in t he Sleep st ate, t he process or can ent er its
lowest power state, the Deep Sleep state. Removing
the proces sor’s input cloc k put s t he proces sor in the
Deep Sleep state. PICCLK may be removed in the
Sleep st ate.
2.2.8 Deep Sleep State
The Deep Sleep state is the lowest power mode t he
processor can enter while maintaining its context.
The Deep Sleep state is entered by stopping the
BCLK input to the process or, while it is in the Sleep
or Quick S tart st ate. For proper operation, the BCLK
input shoul d be stopped in the l ow state.
The processor will return to t he Sleep or Quick Start
state from the Deep Sleep state when the BCLK
input is restart ed. Due to the P LL lock latency, there
is a 30
sec delay after the clocks have started
before this state transition happens. PICCLK may
be removed in the Deep Sleep state. PICCLK
should be designed to turn on when BCLK turns on
when transitioni ng out of the Deep Sleep state.
The input signal restrictions for the Deep Sleep
state are the same as for the Sleep state, except
that RESET# assertion will result in unpredictable
behavior.
2.2.9 Operating System Impl i cations of
Quick Start and Sl eep S tates
There are a number of architectural features of the
Mobile Pentium® II processor that are not available
when the Quick Start state is enabled or do not
functi on in the Quick Start or Sleep stat e as they do
in the Stop Grant state. These features are part of
the time-stamp counter and performance monitor
counters. The time-stamp counter and the
perform ance moni tor counters are not guarant eed to
count in t he Qui ck St art or Sleep st ates.
2.3 Low Power GTL+
The Mobile Pentium® II processor system bus
signals use a variation of t he low voltage swing GTL
signaling technology. The Mobile Pentium II
processor system bus specification is similar to the
Pentium II processor system bus specification,
which is a version of GTL with enhanced noise
margins and less ringing. The Mobile Pentium II
processor system bus specification reduces system
cost and power consumption by raising the
termination voltage and termination resistance and
changing the termination from dual ended to single
ended. Because the specification is different from
the standard GTL specification and from the
Pentium II processor GTL+ specification, it is
referred to as Low Power GTL+.
The Pentium II processor GTL+ system bus
depends on incident wave switching and uses flight
tim e for tim i ng calc ulat ions of t he GTL+ signal s. The
Low Power GTL+ system bus is short and lightly
loaded. With Low Power GTL+ signals, timing
calculations are based on capacitive derating.
Analog si gnal s i mulati on of the system bus includi ng
trace lengths is highly recommended to ensure that
there are no significant transmission line effects.
Contact your field sales representative to receive
the IBIS m odel s for the Mobile Pent i um II processor.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 9
The GTL+ system bus of the Pentium II processor
was designed to support high-speed data transfers
with mult iple l oads on a long bus that behaves l ik e a
transm ission line. However, in a mobile system, the
system bus only has two loads (the processor and
the chipset) and the bus traces are short enough
that trans mi ssion l ine effec ts are not s ignifi cant. It is
possibl e to change the layout and t ermination of the
system bus to take advantage of the mobile
environment using the same GTL+ I/O buffers. The
benefit is that it reduces the number of terminating
resistors in half and substantially reduces the AC
and DC power dissipation of the system bus. Low
Power GTL+ uses GTL+ I/O buffers but only two
loads are allowed. The trace length is limited and
the bus is terminated at one end only. Since the
system bus is small and lightly loaded, it behaves
like a capacitor, and the GTL+ I/O buffers behave
like high-speed open-drain buffers. With a 66-MHz
bus frequency, the pull-up would be 120
. If 100
termination resistors are used rather than 120
,
then 20% more power will be dissipated in the
termination resistors. 120
termination is
recom mended to c ons erve power.
Refer to the
Mobile Pentium
®
II Processor System
Bus Layout Guideline
(Order Number 243672-001)
for details on laying out the Low Power GTL+
system bus.
2.3.1 GTL+ Signals
Two signals of the system bus can potentially not
meet the Low Power GTL+ layout requirements:
PRDY# and RESET#. These two signals c onnect to
the debug port and might not meet the maximum
length requirements. If PRDY# or RESET# do not
meet the layout requirements for Low Power GTL+,
then they must be terminated using dual-ended
termination at 120
. Higher resistor values can be
used if simulations show that the signal quality
specificati ons in Section 4 are met .
2.4 Mobile Pentium® II Processor
CPUID
The Mobile Pentium
II processor has the same
CPUID family and model number as some
Celeron™ processors. The Mobile Pentium II
processor can be distinguished from these Celeron
processors by looking at the stepping number and
the CPUID cache descriptor information. A Mobile
Pentium II processor has a stepping number in the
range of 0AH t o 0FH (0AH to 0CH for t he 400 MHz,
0DH to 0FH for the 366 MHz and below) and an L2
cache descriptor of 042H (256-Kbyte L2 cache). If
the stepping number is less than 0AH or the L2
cache des cript or is not 042H t hen the proc ess or is a
Celeron processor. The L2 cache must be properly
initialized for the L2 cache descriptor information to
be correct. After a power-on RESET, or when the
CPUID instruction is executed, the EAX register
contains the values s hown in Table 2.3. Af ter the L2
cache is initialized, the CPUID cache/TLB
descriptors will be the values shown in Table 2.4.
Table 2.3 Mobile Pentium
II Processor CP UID
Reserved [31:14] Type [13:12] Family [11:8] Model [7:4] Stepping [3:0]
0DH– 0FH (400 MHz)
X066
0AH – 0CH (366 MHz and below)
Table 2.4 Mobile Pentium
II Processor CP UID Cache and TLB Descriptors
Cache and TLB Descriptors 01H, 02H, 03H, 04H, 08H, 0CH, 42H
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
10 INTEL CORPORATION
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 11
3. ELECTRICAL SPECIFICATIONS
3.1 Processor System Signals
Table 3.1 lis ts the proc essor system s i gnal s by type.
All Low Power GTL+ signals are synchronous with
the BCLK signal. All TAP signals are synchronous
with the TCK signal except TRST#. All CMOS input
signals can be applied async hronously.
Table 3.1 System Signal Groups
Group Name Signals
Low Power GTL+ Input BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
Low Power GTL+ Output PRDY#
Low Power GTL+ I/O A[35:3]#, ADS#, AERR#5, AP[1:0]#, BERR#, BINIT#, BNR#, BP [3:2]#,
BPM[1:0]#, BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HI T M#,
LOCK#, REQ[4:0]#, RP#
CMOS Input 1, 2 A20M#, BSEL, FLUSH#, IGNNE#, INIT#, INTR, NMI, PREQ#, PWRGOOD,
SLP#, SMI#, STPCLK#
Open Drain Output 2F ERR#, IE RR#, VTOL
Clock 3BCLK
API C Clock 2PICCLK
APIC I/O 2PICD[1:0]
Thermal Di ode THERMDA, THERMDC
TAP Input 2TCK, TDI, TMS, TRST#
TAP Output 2TDO
Power/Other 4EDGE CTRLN, NC, PLL1, PLL2, TEST HI, TEST HI 2, TESTHI 3, TESTLO, VCC,
VCCP, VREF, VSS
NOTES:
1. S ee Section 8 for inf ormation on the PWRGOOD signal.
2. E xcept for the 1.6V tolerant VTOL, these s i gnal s are tolerant t o 1.5V for the 400 MHz, and 2.5V tolerant
for the 366 MHz and below. See Table 3. 2 for the rec omm ended pul l -up res i stor.
3. B CLK is a 2.5V tolerant si gnal .
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
12 INTEL CORPORATION
4. VCC is the power supply for the c ore l ogi c.
PLL1 and PLL2 are the power supply for the PLL analog s ection.
VCCP is t he power supply for the CMOS voltage ref erences.
VREF is t he vol tage reference f or t he Low Power GTL+ input buf fers.
VSS is sys tem ground.
5. The A E RR# processor bus pin is removed as a processor feature f or t he 400 MHz. The pin must s till be
term i nat ed to VCC through a 120
pull-up resistor. But the proces sor mus t not be configured to drive or
observe the pin.
The CMOS and TAP inputs can be driven from
ground to VCMOS. The TAP outputs are open
drain and should be pulled up to VCMOS using
resistors with the values shown in Table 3.2. If
open drain drivers are used f or i nput si gnals, t hen
they should also be pulled up to VCMOS using
resistors with the values shown in Table 3.2.
Table 3.2 Recommended Resistors for Open Drai n S i gnals
Recommended
Resistor Valu e (
)Open Drain Signal 1
150 pull-up TDI, TDO, TE S T HI3 2
680 pull-up STPCLK #
1K pull-up INIT#, TCK , TESTHI , TESTHI 2, TESTHI 3 2, TMS
680 - 1K pull-down TRS T#
1.5K pull-up (400 MHz)
4.7K pull-up (366 MHz and
Below)
A20M#, FERR#, FLUSH#, IERR#, IGNNE#, INTR, NMI, PREQ#,
PWRGOOD, SLP#, SMI#, V TOL
NOTE:
1. Refer to Section 3.1.4 for the required pull-up or pul l -down resis tors for s i gnal s that are not bei ng used.
2. The TE STHI3 si gnal must be pul l ed up t o VCC using a 150
resistor on 400 MHz processors . On
366 MHz and below the resistor may be between 150
and 1K
.
3.1.1 Power Sequencing Requirements
The Mobile Pentium® II processor has no power
sequencing requirements. It is recommended that
all of the processor power planes rise to their
specified values within one second of eac h other.
The VCC power plane mus t not ris e too f ast. At leas t
200
sec (TR) mus t pass f rom the ti me t hat VCC is at
10% of it s nom inal value unti l the tim e that VCC is at
90% of its nom i nal val ue (See Figure 3.1).
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 13
90% Vcc (nominal)
Volts
TR
Vcc
10% Vcc (nominal)
Time
Figure 3.1 Ramp Rate Requirement
3.1.2 Test Access Po rt (TAP) Connection
The TAP interface is an implementation of the
IEEE 1149.1 (“JTAG”) standard. Due to the voltage
levels supported by the TAP interface, it is
recommended that the Mobile Pentium II processor
and the other 1.5V/2.5V JTAG specification
compliant devices be last in the JTAG chain after
any devices with 3.3V or 5V JTAG interfaces within
the system. A translation buffer should be used to
reduce the TDO output voltage of the last 3.3/5V
device down to the VCMOS range that the Mobile
Pentium II processor c an tolerat e. Multiple c opies of
TCK, TMS, and TRST# must be provided, one for
each voltage l evel .
A Debug Port and connector may be placed at the
start and end of the JTAG chain containing the
processor, with TDI to the first component coming
from the Debug Port and TDO from the last
component going to the Debug Port. There are no
requirement s for plac ement of the Mobile P entium II
processor in the JTAG chain, except for those that
are dictated by voltage requirements of the TAP
signals.
3.1.3 Catastrophic Thermal Protection
The Mobile Pentium II processor does not support
catas trophic therm al protect ion or the THE RMTRIP #
signal. An external thermal sensor should use the
thermal diode to protect the processor and the
system against excessive t emperatures.
3.1.4 Unused Signals
All signals named NC must be unconnected. All
signals named TESTLO must be pulled down to
VSS, or tied directly to VSS. All signals named
TESTHI or TESTHI3 must be pulled up to VCC with
a resistor. All signals named TESTHI2 must be
pulled up to VCCP with a resist or. Each TESTHI and
TESTHI2 signal must have an individual, 1k
pull-
up resistor. The TESTHI3 si gnals c an share a s ingle
pull-up of 150
for the 400 MHz processor and
150
to 1K
for 366 MHz and below.
Unused Low Power GTL+ inputs, outputs and bi-
directional signals should be individually connected
to VCC with 120
pull-up resistors. Unused CMOS
active low inputs should be connected to VCMOS.
Unused active high inputs should be connected to
VSS. Unused open-drain outputs should be
unconnected. If the processor i s configured to enter
the Quick Start state rather than the Stop Grant
state, then the SLP# signal should be connected to
VCMOS. When tying any signal to power or ground, a
resistor will allow for system testability. For unused
signals, it is suggested that 1k
resistors be used
for pull-ups and f or pul l -downs.
PICCLK and PICD[1:0] must be tied to VSS with a
1k
resistor. BSEL must be c onnected to VSS.
3.1.5 Signal S tate i n Low Pow er S tates
3.1.5.1 S ystem Bus Signals
All of t he sys tem bus si gnals have Low Power GTL+
input, output or input/output drivers. Except when
servicing snoops, the system bus signals are tri-
stated and pulled up by the termination resistors.
Snoops are not permitted in the Sleep and Deep
Sleep st ates.
3.1.5.2 CMOS and Open-Drain Si gnals
The CMOS input signals are allowed to be in either
the logic hi gh or l ow st at e when the process or is i n a
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
14 INTEL CORPORATION
low power state. In the Auto Halt and Stop Grant
states these signals are allowed to toggle. These
input buffers have no internal pull-up or pull-down
resistors and system logic can use CMOS or open-
drain drivers to dri ve t hem.
The open-drain output signals have open drain
drivers and external pull-up resistors are required.
One of the two output signals (IERR#) is a
catastrophic error indicator and is tri-stated (and
pulled-up) when the processor is functioning
normall y. The FERR# output can be ei ther tri-s tated
or driven to VSS when the processor is in a low
power state, depending on the condition of the
floating point unit. Since this signal is a DC current
path when it is driven to VSS, it is recom m ended t hat
the software clears or masks any floating point error
conditi on before putting t he processor int o the Deep
Sleep st ate.
3.1.5.3 Other Signals
The system bus clock (BCLK) must be driven in all
of the low power states except the Deep Sleep
state.
3.2 Power Supply Requirements
3.2.1 Decoupling Recommendations
The amount of bulk decoupli ng required to meet the
processor voltage tolerance requirements is a
strong function of the power supply design. Contact
your Intel Field Sales Representative for tools to
help determine how much decoupling is required.
The processor core power plane (VCC) should have
at least twenty-six 0.1
F high frequency decoupling
capacitors. The CMOS voltage reference power
plane (VCCP) requires 50 to 100
F of bulk
decoupling and at least eight 0.1
F high frequency
decoupling c apacitors.
For the Low Power GTL+ pull-up resistors, one
0.1
F high frequency decoupling capacitor is
recommended per resistor pack. There should be
no more than eight pull-up resistors per resistor
pack. The Low Power GTL+ voltage reference
power plane (VREF) should have at leas t t hree 0.1
F
high frequency dec oupl i ng capacitors.
3.2.2 Voltage Pl anes
All VCC and VSS balls /pins m ust be connec ted to the
appropriate voltage plane. All VCCP and VREF
balls/pins must be connected to the appropriate
traces on the syst em elect roni cs.
In addition to the main VCC, VCCP and VSS power
supply signals, PLL1 and PLL2 provide isolated
power to the PLL sec tion. PLL1 and PLL2 s hould be
connected according to Figure 3.2. Do not connect
PLL2 directly to VSS. A separate power supply
should be used to generate VCCP to isolate the PLL
from processor core noise. Table 3.3 contains the
requirements for C1 and L1.
PLL1
PLL2
VCCP
V0027-00
L1
C1
Figure 3.2 PLL LC Filter
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 15
Table 3.3 LC Filter Sp eci fications
Symbol Parameter Min Max Unit Notes
C1 LC Filter Capacit ance 47
F
30% tolerance, 1
max series res i stance,
~2nH series i nductance
L1 LC Filter I nduc tance 20 47
Hlow-Q type choke,
30% tolerance, 1.5
max series res i stance,
50mA current,
self-resonant frequency >10 MHz
3.3 System Bus Clock and
Processor Clocking
The 2.5V BCLK clock input directly controls the
operating speed of the system bus interface. All
system bus timing parameters are specified with
respect to the rising edge of the BCLK input. The
Mobile Pentium II processor core frequency is a
multiple of t he B CLK frequency.
The Mobile Pentium® II processor (0.18
m) at 400
MHz is implemented with the Bus Fraction Locking
scheme, which allows the processor to operate at
the marked core frequency only. The bus ratio
configuration signals are not effective. However, if
desired, t he signals can be set accordingly to Table
3.4.
Table 3.4 Core Frequency to System Bus Ratio Configuration
Processor Core Frequency to
System Bus Frequency Ratio NM I INTR IGNNE# A20M# Powerup Configuration
[25:22]
4/1 (266 MHz) L L L H 0010
9/2 (300 MHz) L H L H 0110
5/1 (333 MHz) L L H H 0000
11/2 (366 MHz) L H H H 0100
6/1 (400 MHz) H L L L 1011
The mobile Pentium II processors at 366 MHz and
below frequencies are implemented with a
Bus
fraction Limiting scheme
. A multiplexer is required
between the system electronics and the processor
to drive the bus ratio configuration signals during
Reset. Figure 3.6 and Table 3.18 describe the
timing requirements for this operation. The 443BX
CRESET# signal has suitable timing to control the
multiplexer. After RESET# and PWRGOOD are
asserted, the multiplexer logic must guarantee that
the bus rati o configurati on signals enc ode one of the
bus ratios in Table 3.4 and that the bus ratio
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
16 INTEL CORPORATION
corresponds to a core frequency at or below the
marked core frequency for the processor. The
selected bus ratio i s visible to software in the Power-
On configuration register, see Section 7.2 for
details.
Multiplying the bus clock frequency is necessary to
increase performance while allowing for easier
distribution of signals within the system. Clock
mult iplic ation within the processor is provided by the
internal Phase Lock Loop (PLL), which requires a
const ant frequency B CLK input. During Reset, or on
exit from the Deep Sleep state, the PLL requires
som e am ount of tim e t o acqui re t he phas e of BCLK .
This time is called the PLL lock latency, which is
specified in Section 3.6, AC timing parameters T18
and T47. Except for the 400 MHz processor, the
system bus frequency ratio can be changed when
RESET# is active, assuming that all Reset
specification are met. The BCLK frequency should
not be changed during Deep Sleep state (see
Secti on 2.2.8).
3.4 Maximum Ratings
Table 3.5 and Table 3.6 contains the Mobile
Pentium II processor stress ratings. Functional
operation at t he absolute m aximum and mi nimum i s
neither implied nor guaranteed. The processor
should not receive a clock while subjected to these
conditions. Functional operating conditions are
provided in the AC and DC tables. Extended
exposure to the m aximum ratings may affect device
reliability. Furthermore, although the processor
contains protective circuitry to resist damage from
static electric discharge, one should always take
precautions to avoid high static voltages or electric
fields.
Table 3.5 Absolute M axi mum Ratings for Mobile P enti u m
II Processor at 400 MHz
Symbol Parameter Min Max Unit Notes
TStorage Storage Temperature –40 85 °C Note1
VCC(Abs) Supply Volt age with respect t o VSS –0.5 2.0 V
VCCP CMOS Reference Vol tage with respect to VSS –0.3 2.0 V
VIN GTL+ Buffer DC Input Volt age with respect t o V SS –0.3 VCC + 0.5 V Note 2
VIN15 1. 5V Buffer DC Input Volt age with respect t o VSS –0.3 2.0 V Note 3
VBLCK BLCK Buf fer DC Input V ol tage with respect to VSS –0.3 3.3 V
NOTES:
1. The shipping cont ai ner i s only rated for 65° C.
2. P arameter appli es to the Low Power GTL+ signal groups onl y.
3. P arameter appli es to CMOS, Open-Drain, APIC and TAP bus s i gnal groups onl y.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 17
Table 3.6 Absolute M axi mum Ratings for Mobile P enti u m
II Processor at 366 MHz and Below
Symbol Parameter Min Max Unit Notes
TStorage Storage Temperature –40 85 °C Note1
VCC(Abs) Supply Volt age with respect t o VSS –0.5 3.0 V
VCCP CMOS Reference Vol tage with respect to VSS –0.3 3.0 V
VIN GTL+ Buffer DC Input Volt age with respect t o V SS –0.3 VCC + 0.7 V Note 2
VBLCK 2.5V Buffer DC Input Vol tage with respect to VSS –0.3 3.3 V Note 3
NOTES:
1. The shipping c ontainer is only rated for 65°C.
2. Param et er appl i es to the Low Power GTL+ signal groups onl y.
3. Param et er appl i es to CMOS, Open-Drain, APIC and TAP bus si gnal groups only.
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
18 INTEL CORPORATION
3.5 DC Specifications
Table 3.7 through Tabl e 3. 12 l i st the DC
specificati ons for the Mobile P ent i um II processor .
Specif i cations are val i d onl y while meeting
specificati ons for cas e t emperature, clock frequency
and input volt ages . Care should be taken to read all
notes as s ociated with each parameter.
Table 3.7 Pow er S p eci fications for Mobile Pentium® II Processor at 400 MHz
TCASE = 0 to TCASE,max; VCC = 1.5V ±115mV; VCCP = 1.5V ±90mV
Symbol Parameter Min Typ Max Unit Notes
VCC VCC for core logi c 1.385 1.500 1.615 V ±115 mV
VCCP VCC for CMOS voltage references 1.410 1.500 1.590 V ±90 mV
ICC ICC for VCC at core @ 400 MHz
frequency 7.10 A Note 3
ICCP Current for V CCP 100 m A Notes 1, 2, 3
ICC,SG Proc essor Stop Grant and
Auto Halt current 1.29 A Note 3
ICC,QS Processor Qui ck Start and
Sleep current 994 mA Note 3
ICC,DSLP P rocessor Deep Sl eep l eakage
current 700 mA Note 3
dICC/dt VCC power supply current s l ew rate 20 A/
s Notes 4, 5
NOTES:
1. ICCP i s the current s uppl y for the CMOS voltage references.
2. Not 100% tes t ed. Specified by design/ c haracterizati on.
3. ICCx,max specif i c ations are specified at VCC,max, VCCP,max and 100°C and under maximum s i gnal l oadi ng
conditions.
4. B ased on simulations and averaged over the duration of any change in current. Use to c ompute the
maxim um induct ance and reaction time of the voltage regul ator. This parameter is not test ed.
5. Maximum values specifi ed by design/characterizati on at nominal VCC and V CCP.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 19
Table 3.8 Power S peci fications for Mobi le Pentium® II P r ocessor at 366 MHz and Below
TCASE = 0 to TCASE,max; VCC = 1.6V ±135mV; V CCP = 1.8V ±90mV
Symbol Parameter Min Typ Max Unit Notes
VCC VCC of core logi c for regular volt age
processors 1.465 1.600 1.735 V ±135 mV
VCC,LP VCC when ICC < 300 m A 1.465 1.600 1.805 V +205/-135 mV 1
VCCP VCC for CMOS voltage references 1.710 1.800 1.890 V 1. 8V ±90 mV
ICC ICC for VCC at core @ 366 MHz
frequency @ 333 MHz
@ 300PE MHz
@ 266PE MHz
8.87
7.95
7.49
6.63
A
A
A
A
Note 4
ICCP Current for V CCP 75 mA Notes 2, 3, 4
ICC,SG Proc essor Stop Grant and
Auto Halt current 1190 m A Not e 4
ICC,QS Processor Qui ck Start and
Sleep current 880 mA Note 4
ICC,DSLP P rocessor Deep Sl eep l eakage
current 650 mA Note 4
dICC/dt VCC power supply current s l ew rate 20 A/
s Notes 5, 6
NOTES:
1. A higher VCC, MAX is all owed when the processor is in a l ow power state t o enabl e hi gh effici ency, low
current modes in t he power regulator.
2. ICCP i s the current s uppl y for the CMOS voltage references.
3. Not 100% tested. S pecified by des i gn/ characterization.
4. ICCx,max specif i c ations are specified at VCC,max, VCCP,max and 100°C and under maximum s i gnal l oadi ng
conditions.
5. Based on si mulati ons and averaged over the duration of any change in current. Use t o c ompute t he
maxim um induct ance and reaction time of the voltage regul ator. This parameter is not test ed.
6. Maximum values specified by design/ characterization at nominal VCC and VCCP.
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
20 INTEL CORPORATION
Table 3.9 Power S peci fications for Low Vo l tage P enti um® II Processor
TCASE = 0 to TCASE,max; VCC = 1.5V ±135mV; VCCP = 1.8V ±90mV
Symbol Parameter Min Typ Max Unit Notes
VCC Vcc of core logic for 266PE MHz at
low voltage 1.365 1.500 1.635 V ±135 mV
VCC,LP VCC when ICC < 300 A 1.365 1.500 1.705 V +205/-135 m V 1
VCCP VCC for CMOS voltage references 1.710 1.800 1.890 V 1.8V ±90 mV
ICC ICC for VCC at core frequency
@ 266PE MHz at low voltage 5.90 A Note 4
ICCP Current for V CCP 75 mA Notes 2, 3, 4
ICC,SG Proc essor Stop Grant and
Auto Halt current 940 mA Not e 4
ICC,QS Processor Qui ck Start and
Sleep current 630 m A Note 4
ICC,DSLP P rocessor Deep Sl eep l eakage
current 400 mA Not e 4
dICC/dt VCC power supply current s l ew rate 20 A /
s Notes 5, 6
NOTES:
1. A hi gher VCC,MAX is all owed when the processor is in a l ow power state t o enabl e hi gh effici ency, low
current modes in t he power regulator.
2. ICCP i s the current supply for the CMOS vol tage references .
3. Not 100% tes t ed. Specified by design/ c haracterizati on.
4. ICCx,max specif i c ations are specified at VCC,max, VCCP,max and 100°C and under maximum s i gnal l oadi ng
conditions.
5. B ased on simulations and averaged over the duration of any change in current. Use to c ompute the
maxim um induct ance and reaction time of the voltage regul ator. This parameter is not test ed.
6. Maximum values specifi ed by design/characterizati on at nominal VCC and V CCP.
The signals on the Mobile Pentium II processor
system bus are included in the Low Power GTL+
signal group. These signals are specified to be
terminated to VCC. The DC specifications for these
signals are listed in Table 3.10; the term ination and
reference voltage specifications for these
signals are list ed in Table 3.11. The Mobil e Pent ium
II processor requires external termination and a
VREF. Refer to
Mobile Pent ium
®
II Processor System
Bus Layout Guideline
(Order Number 243672-001)
for full det ai l s of sys t em VTT and VREF requirement s.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 21
Table 3.10 Low Power GTL+ Signal Group DC Specifications
TCASE = 0 to TCASE,max; VCC = 1.5V ± 115mV, VCC = 1.6V ± 135mV, or 1.5V ± 135mV; VCCP = 1.5V ± 90mV,
or VCCP = 1.8V ± 90mV
Symbol Parameter Min Max Unit Notes
VIL Input Low Voltage –0.3 5/9VTT – 0.2 V See Table 3.11 1
VIH Input High V ol tage 5/9VTT + 0. 2 VCC V Note 1
VOH Output High V ol tage — — V See VTT max in
Table 3.11.
RON Output Low Drive Strength 35 ohms
ILLeakage Current for i nputs ±100
A Note 2
ILO Leakage Current for outputs
& I/Os ±30
A 366 MHz and below 3
ILO Leakage Current for outputs
and I/Os ±100
A 400 MHz 3
NOTES:
1. VREF worst case, not nominal. Noi se on VREF shoul d be accounted f or.
2. (0
VIN
VCC).
3. (0
Vout
VCC).
Table 3.11. Low Power GTL+ Bus DC Specifications
TCASE = 0 to TCASE,max; VCC = 1.5V ± 115mV, VCC = 1.6V ± 135mV, or 1.5V ± 135mV; VCCP = 1.5V ± 90mV,
or VCCP = 1.8V ± 90mV
Symbol Parameter Min Typ Max Unit Notes
VTT Bus Termination V ol tage VCC,MIN VCC VCC,MAX V Note 1
VREF Input Reference Volt age 5/9VTT – 2% 5/9VTT 5/9VTT + 2% V ±2% 2
NOTES:
1. The i ntent is t o use the same power supply for VCC and V TT.
2. VREF for the system logi c should be created from VTT by a voltage divi der.
The CMOS, Open-Drain and TAP signals are
designed to interface at VCMOS to allow connection to other devices. BCLK is a 2.5V clock. The DC
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
22 INTEL CORPORATION
specifications for these signals are listed in Table 3.12.
Table 3.12 Clock, APIC, TAP, CMOS and Open-Drain Signal Group DC Specifications for
the Mobile Pentium® I I Processor at 400 M Hz
TCASE = 0 to TCASE,max; VCC = 1.5V ± 115mV, V CCP = 1.5V ± 90mV
Symbol Parameter Min Max Unit Notes
VIL Input Low Voltage –0.3 0.6 V
VIL,BCLK Input Low Voltage, BCLK –0.3 0.7 V
VIH Input High V ol tage 1.135 1.615 V
VIH,BCLK Input High Voltage, BCLK 1. 8 2.625 V
VOL Output Low Voltage 0.4 V Note 1
VOH Output High V ol tage N/A 1.615 V All outputs are open-drain
IOL Output Low Current 14 m A
ILLeakage Current for i nputs,
outputs, and I/Os ±100
A Note 2
NOTES:
1. P arameter measured at 14 mA.
2. (0
VIN/OUT
1.615V).
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 23
Table 3.13 Clock, APIC, TAP, CMOS and Open-Drain Signal Group DC Specifications for
the Mobil e P enti u m ® I I P rocessor at 366 MHz and Below
TCASE = 0 to TCASE,max; VCC = 1.6V ± 135mV, or V CC = 1.5V ± 115mV, VCCP = 1.8V ± 90mV
Symbol Parameter Min Max Unit Notes
VIL Input Low Voltage –0.3 0.7 V
VIL,BCLK Input Low Voltage, BCLK –0.3 0.7 V
VIH Input High V ol tage 1.700 2.625 V
VIH,BCLK Input High Voltage, BCLK 1.800 2.625 V
VOL Output Low Voltage 0.4 V Note 1
VOH Output High V ol tage N/A 2.625 V All outputs are open-drain
IOL Output Low Current 14 m A
ILInput Leakage Current ±100
A Note 2
ILO Output and I/O Leakage Current ±30
A Note 2
NOTES:
1. Parameter meas ured at 14 mA .
2. (0
VIN/OUT
2.625V).
3.6 AC Specifications
3.6.1 System Bus, Cl ock, APIC, TAP, CMOS
and Open-Drain AC Specifications
Table 3.14 through Table 3.21 provide AC
specif ications ass ociated with the Mobile P entium I I
processor. The AC specifications are divided into
the following categories: Table 3.14 contains the
system bus clock specifications; Table 3.15
contains the proces sor core f requencies; Table 3.16
contains the Low Power GTL+ specifications; Table
3.17 contains the CMOS and Open-Drain signal
groups specifications; Table 3.18 contains timings
for the reset conditions; Table 3.19 contains the
TAP specifications; and Table 3.20 and Table 3.21
contain the power management timing
specifications.
All syst em bus AC specificat ions for the Low Power
GTL+ signal group are relative to the rising edge of
the BCLK input at 1.25V. All Low Power GTL+
timings are referenced to VREF for both ‘0’ and ‘1’
logic level s unless otherwise specified.
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
24 INTEL CORPORATION
Table 3.14 System Bus Clock AC Specifications1
TCASE = 0 to TCASE,max; VCC = 1.5V ± 115mV, V CC = 1.6V ± 135mV, or 1. 5V ± 135mV ; V CCP = 1.5V ± 90mV,
or VCCP = 1.8V ± 90mV
Symbol Parameter Min Typ Max Unit Figure Notes
System Bus Frequency 66.67 MHz
T1 BCLK Period 15 ns 3.3 Note 2
T2 BCLK Period Stability ±250 ps Notes 3, 4
T3 BCLK High Time 5.0 ns 3.3 @>1.8V
T4 BCLK Low Time 5.0 ns 3.3 @<0.7V
T5 BCLK Rise Time 0.175 0.875 ns 3.3 (0.9V – 1. 6V) 4
T6 BCLK Fall Time 0.175 0.875 ns 3.3 (1.6V – 0.9V) 4
NOTES:
1. A l l AC timings for Low Power GTL+ and CMOS signals are referenced to the BCLK ris i ng edge at 1.25V.
All CMOS s i gnal s are referenced at VTRIP.
2. The B CLK period allows a +0.5ns tolerance for clock dri ver variation.
3. Not 100% tes t ed. Specified by design/ c haracterizati on.
4. Measured on the rising edge of adj acent BCLKs at 1.25V. The jitt er present m us t be account ed for as a
com ponent of BCLK skew between devices.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 25
Table 3.15 Valid Mobile Pentium
II Processor Frequenci es
TCASE = 0 to TCASE,max; VCC = 1.5V ± 115mV, VCC = 1.6V ± 135mV, or 1.5V ± 135mV; VCCP = 1.5V ± 90mV,
or VCCP = 1.8V ± 90mV
BCLK Frequency (MHz) Frequency Multiplier Core Frequency (M Hz)
66.67 4 266.67
66.67 9/2 300.00
66.67 5 333.33
66.67 11/2 366.67
66.67 6 400.00
NOTE: Because of the Bus Frac tion Locki ng schem e i mplemented in thi s process or, the frequency
multiplier is i nternally set to a fixed value of si x (6). The processor operates onl y at a core
frequency of 400 MHz.
Table 3.16 Low Power GTL+ Signal Groups AC Specifications1
RTT = 120
term i nat ed to VCC; VREF = 5/9 VCC; l oad = 0pF
TCASE = 0 to TCASE,max; VCC = 1.5V ± 115mV, V CC = 1.6V ± 135mV, or 1. 5V ± 135mV ; V CCP = 1.5V ± 90mV,
or VCCP = 1.8V ± 90mV
Symbol Parameter Min Max Unit Figure Notes
T7 Low Power GTL+ Output Valid Delay 0.00 7.78 ns 3.4
T8 Low Power GTL+ Input Setup Time 2.98 ns 3.5 Notes 2, 3
T9 Low Power GTL+ Input Hold Tim e 0. 90 ns 3.5 Note 4
T10 RESET# Pulse Width 1 ms 3.6 3.7 Note 5
NOTES:
1. A l l AC timings for Low Power GTL+ signals are referenced to the BCLK ris i ng edge at 1.25V. All Low
Power GTL+ signals are ref erenced at VREF.
2. RESET# c an be asserted (act ive) async hronous ly, but must be de-asserted s ync hronous ly.
3. S pecific ation is f or a minimum 0.40V swing.
4. S pecific ation is f or a maximum 1.0V s wing.
5. After VCC, VCCP and BCLK becom e stable and PWRGOOD is as serted.
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
26 INTEL CORPORATION
Table 3.17 CMOS and Open-Drain Signal Groups AC Specifications1, 2
TCASE = 0 to TCASE,max; VCC = 1.5V ± 115mV, V CC = 1.6V ± 135mV, or 1. 5V ± 135mV ; V CCP = 1.5V ± 90mV,
or VCCP = 1.8V ± 90mV
Symbol Parameter Min Max Unit Figure Notes
T14 CMOS Input P ul se Width, except
PWRGOOD 2BCLKs
3.4 Active and
Inactive
states
T15 PWRGOOD Inac t i ve Pulse Width 10 BCLKs 3.7 Notes 3, 4
NOTES:
1. A l l AC timings for CMOS and Open-Drai n signals are ref erenced to the BCLK ri sing edge at 1.25V . All
CMOS and Open-Drain signals are referenced at V TRIP.
2. Mini mum out put pulse width on CMOS outputs is 2 BCLKs.
3. When driven inactive, or after VCC, VCCP and BCLK bec ome st able. P WRGOOD must remain below
VIL,max from Tabl e 3.12 until all the voltage planes meet t he vol tage tolerance specifi cations i n Tabl e 3.7,
and BCLK has met the BCLK AC specifications in Table 3.14 f or at least 10 cl ock cycles. PWRGOOD
mus t ri se glitc h-free and monot oni cally to VCMOS.
4. I f the BCLK s i gnal meets it s AC specif ication within 150ns of t urning on t hen the PWRGOOD Inac t i ve
Pulse Widt h specific at ion (T15) is waived and BCLK may st art after PWRGOOD is as serted. PWRGOOD
must still remain below VIL,max unti l al l the voltage planes meet the vol tage tolerance specifi cations.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 27
Table 3.18 Reset Configuration AC Specifications
TCASE = 0 to TCASE,max; VCC = 1.5V ±115mV; VCCP = 1.5V ±90mV
Symbol Parameter Min Max Unit Figure Notes
T16 Reset Conf i guration Signals (A[15:5]#,
BREQ0#, FLUSH#, INIT#, PICD0)
Setup Tim e
4BCLKs
3.5 3.6 Before
deassert i on of
RESET#
T17 Reset Conf i guration Signals (A[15:5]#,
BREQ0#, FLUSH#, INIT#, PICD0)
Hold Time
220BCLKs
3.5 3.6 After clock that
deasserts
RESET#
T18 Reset Conf i guration Signals (A20M#,
IGNNE#, INTR, NMI) Setup Time 1ms
3.7 Before
deassert i on of
RESET# 1
T19 Reset Conf i guration Signals (A20M#,
IGNNE#, INTR, NMI) Delay Time 5BCLKs
3.7 After assertion of
RESET# 2
T20 Reset Conf i guration Signals (A20M#,
IGNNE#, INTR, NMI) Hold Time 220BCLKs
3.5 3.7 After clock that
deasserts
RESET#
NOTES:
1. A t least 1 ms must pas s after PWRGOOD rises above VIH,min from Tabl e 3.12, and BCLK meets i ts AC
tim ing specificat ion, until RESET# may be deasserted.
2. For a Reset, the clock rat i o defined by these signals must be a safe value (thei r f i nal val ue or a l ower
multiplier) within this delay after RESET# is asserted unless PWRGOOD is inactive (below VIL,max).
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
28 INTEL CORPORATION
Table 3.19 TAP Signal AC Specifi cations1
TCASE = 0 to TCASE,max; VCC = 1.5V ±115mV; VCCP = 1.5V ±90mV
Symbol Parameter Min Max Unit Figure Notes
T30 TCK Frequency — 16.67 MHz
T31 TCK Peri od 60 — ns 3.3
T32 TCK High Time 25.0 ns 3.3
1.135V 2
T33 TCK Low Time 25.0 ns 3.3
0.60V 2
T34 TCK Ri se Time 5.0 ns 3.3 (0.60V-1. 135V ) 2,3
T35 TCK Fall Time 5.0 ns 3.3 (1.135V-0.60V) 2,3
T36 TRST# Pul se Width 40.0 ns 3.9 A synchronous 2
T37 TDI, TMS Setup Time 5.0 ns 3.8 Note 4
T38 TDI, TMS Hold Time 14.0 ns 3.8 Note 4
T39 TDO Valid Delay 1.0 10.0 ns 3.8 Notes 5, 6
T40 TDO Float Delay 25.0 ns 3.8 Notes 2, 5, 6
T41 All Non-Tes t Outputs V al i d Del ay 2.0 25.0 ns 3.8 Notes 5, 7, 8
T42 All Non-Tes t Outputs Float Del ay 25.0 ns 3.8 Notes 2, 5, 7, 8
T43 All Non-Tes t Inputs Set up Ti me 5.0 ns 3.8 Notes 4, 7, 8
T44 All Non-Tes t Inputs Hold Time 13.0 ns 3.8 Notes 4, 7, 8
NOTES:
1. All AC tim i ngs for TAP signals are ref erenced to the TCK ri s i ng edge at VTRIP. All CMOS si gnal s are
referenced at VTRIP.
2. Not 100% tested. S pecified by des i gn/charact eri zat i on.
3. 1 ns c an be added to the m aximum TCK ri se and fall t i mes f or every 1 MHz below 16 MHz.
4. Referenc ed to TCK risi ng edge.
5. Referenc ed to TCK fall i ng edge.
6. Vali d del ay timi ng for this signal is specifi ed i nto 150
term i nat ed to VCMOS and 0pF of external load. For
real syst em timings these spec i ficati ons mus t be derated for external capac i t ance at 105 ps/ pF.
7. Non-Test Outputs and I nput s are the norm al output or input s i gnal s (except TCK, TRS T #, TDI, TDO and
TMS). These ti mings c orrespond to the res ponse of thes e s i gnal s due to boundary sc an operations.
8. Duri ng Debug P ort operation use the normal specifi ed timi ngs rather than the TAP signal timi ngs.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 29
Table 3.20 Quick Start/Deep Sleep AC Specificati ons
TCASE = 0 to TCASE,max; VCC = 1.5V ± 115mV, V CC = 1.6V ± 135mV, or 1. 5V ± 135mV ; V CCP = 1.5V ± 90mV,
or VCCP = 1.8V ± 90mV
Symbol Parameter Min Max Unit Figure
T45 Stop Grant Cycle Compl etion to Cloc k Stop 100 BCLKs 3.10
T46 Stop Grant Cycle Compl etion to Input Signals S t abl e 0 ns 3.10
T47 Deep Sleep PLL Lock Latenc y 30
s3.10
T48 STPCLK# Hol d Time from PLL Lock 0 ns 3.10
T49 Input S i gnal Hol d Ti me from STPCLK # Deassertion 8 BCLKs 3.10
NOTE: Input signals other than RESET# and BPRI# must be held constant in t he Quick Start s t at e.
Table 3.21 Stop Grant/Sleep/ Deep S l eep AC Specifications
TCASE = 0 to TCASE,max; VCC = 1.5V ± 115mV, V CC = 1.6V ± 135mV, or 1. 5V ± 135mV ; V CCP = 1.5V ± 90mV,
or VCCP = 1.8V ± 90mV
Symbol Parameter Min Max Unit Figure
T50 SLP# S i gnal Hol d Ti me from Stop Grant Cycle Com pl et i on 100 BCLKs 3.11
T51 SLP# A s sertion to Input Signal s Stable 0 ns 3.11
T52 SLP# A s sertion to Cl ock St op 10 BCLKs 3.11
T54 SLP# Hold Time from PLL Lock 0 ns 3.11
T55 STPCLK# Hold Time from SLP# Deassertion 10 BCLKs 3.11
T56 Input S i gnal Hol d Ti me from SLP# Deas sertion 10 BCLKs 3.11
NOTE: Input si gnals other than RESET# mus t be held constant in the Sleep stat e.
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
30 INTEL CORPORATION
Figure 3.3 through Fi gure 3.11 are to be used in conjuncti on with Tabl e 3.14 through Table 3.21.
CLK VIH VTRIP
Th
Tl
Tp
Tr1
D0003-02
VIL
Tf1
1.6V
0.9V
Tr2
Tf2
NOTES: Tr1 =T5, T
r2 = T34 (Rise Time)
Tf1 =T6, T
f2 = T35 (Fall Time)
Th= T3, T32 (Hi gh Ti m e)
Tl= T4, T33 (Low Ti m e)
Tp= T1, T31 (Period)
Figure 3.3 Generic Cl ock Waveform
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 31
CLK
Signal
TxTx
Tpw
V Valid Valid
D0004-00
NOTES: Tx= T7, T11 (V al i d Del ay)
Tpw = T14 (Pulse Widt h)
V= V
REF for Low Power GTL+ si gnal s ; VTRIP for CM OS, Open-Drain, and TA P signal groups
Figure 3.4 Valid Delay Timings
CLK
Signal V Valid
Th
Ts
D0005-0
0
NOTES: Ts= T8, T12 (Setup Time)
Th= T9, T13 (Hol d Ti m e)
V= V
REF for Low Power GTL+ si gnal s ; VTRIP for CM OS, Open-Drain, and TA P signal groups
Figure 3.5 Setup and Hold Timings
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
32 INTEL CORPORATION
BCLK
RESET#
Configuration
(A20M#, IGNNE#,
INTR, NMI)
Tv
Tx
Tt
Tu
Tz
Valid
D0006-01
Configuration
(A[15:5], BREQ0#,
FLUSH#, INIT#,
PICD0)
Tw
Valid
Safe
Ty
NOTES: Tt= T9 (Low Power GTL+ I nput Hol d Ti me)
Tu= T8 (Low P ower GTL+ Input Setup Tim e)
Tv= T10 (RESET# Pulse Width)
Tw= T16 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INI T #, PICD0)
Setup Time)
Tx= T17 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INI T #, PICD0)
Hold Time)
T20 (Reset Confi guration Signals (A20M#, IGNNE#, INTR, NMI) Hold Tim e)
Ty= T19 (Reset Configuration Signals (A20M#, I G NNE #, INTR, NMI ) Del ay Time)
Tz= T18 (Reset Configuration Signals (A20M#, I G NNE #, INTR, NMI ) Setup Time)
Figure 3.6 Reset and Configurati on Timings
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 33
BCLK
PWRGOOD
RESET#
TaTb
V ,
CC
VREF
D0007-01
V ,
CCP,
VIL,max
Configuration
(A20M#, IGNNE#,
INTR, NMI)
Tc
Valid Ratio
VIH,min
NOTES: Ta= T15 (PWRGOOD Inactive P uls e Width)
Tb= T10 (RESET# Pulse Width)
Tc= T20 (Reset Configuration Signals (A20M#, I G NNE #, INTR, NMI ) Hol d Ti m e)
Figure 3.7 Power-On Reset Timings
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
34 INTEL CORPORATION
TCK
TDI, TMS
Input
Signals
TDO
Output
Signals
VTRIP
TvTw
TrTs
TxTu
TyTz
D0008-02
NOTES: Tr= T43 (All Non-Test Input s Setup Time)
Ts= T44 (All Non-Test Inputs Hold Ti m e)
Tu= T40 (TDO Fl oat Del ay)
Tv= T37 (TDI , TMS Setup Tim e)
Tw= T38 (TDI, TMS Hold Time)
Tx= T39 (TDO Valid Delay)
Ty= T41 (All Non-Test Outputs Val i d Del ay)
Tz= T42 (All Non-Test Outputs Float Del ay)
Figure 3.8 Test Timings (Boundary Scan)
TRST# VTRIP
TqD0009-02
NOTE: Tq= T36 (TRST# Pulse Width)
Figure 3.9 Test Reset Timings
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 35
Tw
stpgnt
Running Running
BCLK
STPCLK#
CPU bus
SLP#
Compatibility
Signals Changing
Normal Quick Start Deep Sleep Quick Start Normal
Frozen
Tv
Ty
Tz
Tx
V0010-00
NOTES: Tv= T45 (St op Grant Acknowledge Bus Cyc l e Com pl etion to Cloc k Shut Off Delay)
Tw= T46 (Setup Time t o Input Signal Hol d Requi rement)
Tx= T47 (Deep Sleep PLL Lock Latency )
Ty= T48 (PLL lock to STPCLK# Hol d Ti me)
Tz= T49 (Input Signal Hol d Ti m e)
Figure 3.10 Quick Start/ Deep S leep Timing
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
36 INTEL CORPORATION
Tu
stpgnt
Running
BCLK
STPCLK#
CPU bus
SLP#
Compatibility
Signals FrozenChanging
Normal Stop
Grant Sleep Deep Sleep Sleep Stop
Grant Normal
Running
Tt
Tv
Ty
Tz
TwTx
V0011-00
Changing
NOTES: Tt= T50 (St op Grant Acknowledge Bus Cyc l e Com pl etion to SLP # A ssertion Del ay)
Tu= T51 (Setup Time t o Input Signal Hol d Requi rement)
Tv= T52 (SLP# ass ert i on to clock shut of f del ay)
Tw= T47 (Deep Sleep PLL loc k latency)
Tx= T54 (SLP# Hold Time)
Ty= T 55 (S T PCLK# Hold Ti m e)
Tz= T56 (Input Signal Hol d Ti m e)
Figure 3.11 Stop Grant/S l eep/Deep Sleep Timing
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 37
4. SYSTEM SIGNAL SIMULATIONS
Many scenarios have been s imulat ed to generat e
a set of Low Power GTL+ processor system bus
layout guidelines which are available in the
Mobile Pent ium
®
II Proc essor S yst em Bus Layout
Guideline
(Order Number 243672-001). Systems
must be simulated using the IBIS models to
determine if they are compliant with this
specification. There are different IBIS models for
the 400 MHz and for the 366 MHz and below
4.1 System Bus Clock (BCLK)
Signal Quality Specifications
Table 4.1 and Figure 4.1 show the signal quality
for the system bus clock (BCLK) signal as
measured at the processor. The timings
illustrated in Figure 4.1 are taken from Table
3.14. BCLK i s a 2.5V c l ock.
Table 4.1 BCLK Signal Qual ity S p eci fications
Symbol Parameter Min Max Unit Figure Notes
V1 VIL,BCLK 0.7 V 4.1 Note 1
V2 VIH,BCLK 1.8 V 4.1 Note 1
V3 VIN Absolute Voltage Range –0.7 3.5 V 4.1 Undershoot, Overshoot 2
V3 VIN Absol ute Voltage Range –0. 8 3.5 V 4.1 Unders hoot, Overshoot 3
V4 Rising E dge Ri ngback 1.8 V 4.1 Absolute Value 4
V5 Falling Edge Ringback 0.7 V 4.1 Absolute Value 4
BCLK ris i ng/ falling s l ew rate 0.8 4 V/ns 4.1
NOTES:
1. B CLK mus t ri se/fall monotonically between VIL,BCLK and VIH,BCLK.
2. 400 MHz proc essor only.
3. 366 MHz and below.
4. The ris i ng and falling edge ringback voltage s pecified is the minim um (rising) or maximum (falling)
absolute vol t age the BCLK si gnal can dip back to after pas sing the VIH,BCLK (rising) or VIL,BCLK (falling)
voltage li mits.
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
38 INTEL CORPORATION
V1
V3
V2
V4
V3
V5
V0012-00
T3
T6
T4
T5
Figure 4.1 BCLK Generic Cl ock Waveform
4.2 Low Power GTL+ Signal Quality
Specifications
Table 4.2 and Figure 4.2 illustrate the GTL+ signal
quality specifications for the Mobile Pentium II
processor. Refer to the
Pentium
®
II Processor
Developer’s Manual
for the GTL+ buffer
specification.
The Mobile Pentium ® II processor at 400 MHz also
has additional specif ications on m aximum allowable
overshoot and undershoot for a given duration of
time, as listed in Table 4.3. Contact your Intel Field
Sales representative for a copy of the
OVERSHOOT_CHECKER tool.
OVERSHOOT_CHECKER determines if a specific
waveform meets the overshoot/undershoot
specification. Figure 4.3 shows the overshoot/
undershoot waveform .
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 39
Table 4.2 Low Power GTL+ Signal Group Ringback Specification for
the Mobil e P enti u m ® I I P rocessor
Symbol Parameter Min Unit Figure Notes
Overshoot 100 mV 4.2 Notes 1, 2
Minimum Time at High 1 ns 4.2 Notes 1, 2
Ampl i tude of Ringback -100 mV 4.2 Notes 1, 2, 3
Final Sett l i ng V ol t age 100 mV 4.2 Notes 1, 2
Duration of S equential Ringback N/A ns 4.2 Notes 1, 2
NOTES:
1. Specifi ed for the edge rate of 0.3 – 0.8 V/ns. See Figure 4.2 for the generic waveform.
2. A l l val ues determ i ned by design/characterizati on.
3. Ri ngback below VREF +100 mV is not authorized during low to high t ransitions . Ri ngback above VREF -
100mV i s not authorized duri ng hi gh t o l ow trans i tions.
V
REF
+0.2V
Time
V
REF
-0.2V
V
REF
V
start
Clock
V
IL,BCLK
V
IH,BCLK
V0014-00
NOTE: High-to-low case i s analogous.
Figure 4.2 GTL+ Receiver Ringback Tolerance
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
40 INTEL CORPORATION
Table 4.3. GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core 1, 4, 5 for
the Mobile Pentium® I I Processor at 400 M Hz
Pulse Duration Allowed Overshoot 2 Allowed Undershoot 3
0.1 ns 2.0V -0.35V
0.3 ns 1.9V -0.25V
1.0 ns 1.8V -0.15V
NOTES:
1. Under no circumst ances should the GTL+ signal voltage ever exceed 2.0V m aximum with res pec t to
ground or -2.0V minim um with respec t to VCCT (i.e., VCCT - 2.0V) under operating conditions .
2. Ring-backs below VCCT c annot be subtrac t ed from overs hoots. Les s er undershoot does not al l ocate
longer or larger overshoot .
3. Ring-backs above ground cannot be s ubt racted from undershoots. Lesser overshoot does not al l ocate
longer or larger undershoot .
4. System designers are encouraged to f ol l ow Intel provi ded GTL+ l ayout guidelines.
5. All values are specified by design c haracterizati on, and are not test ed.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 41
Vtt
2.0v Max
1.9v
1.8v
Vss
Time Dependent Overshoot
Time Dependent Undershoot
-.15v
-.25v
-.35v Min
.1ns .3ns 1ns
.1ns .3ns 1ns
NOTE:
The total ov ershoot/unders hoot budget for one c l oc k cycle is fully consumed by the
,
or
waveforms.
Figure 4.3 M aximum Acceptable GTL+ Overshoot/Undershoot W aveform for
the Mobile Pentium® I I Processor at 400 MHz
4.3 Non-Low Power GTL+ Signal
Quality Specifications
Signals driven to the Mobile Pentium II processor
should meet signal quality specifications to ensure
that the processor reads data properly and that
incoming signals do not affect the long-term
reliability of the processor. There are three signal
quality parameters defined: overshoot/ undershoot,
ringback and s ettli ng lim it. The ri ngback and settl ing
limit signal quality parameters are shown in Figure
4.4 for non-GTL+ signal groups. The overshoot and
undershoot specifications for non-GTL+ signals are
the same as for GTL+ s i gnal s; see S ection 4.2.
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
42 INTEL CORPORATION
VLO
VCMOS
VSS
Time
Settling Limit
Settling Limit
Undershoot
Overshoot
Rising-Edge
Ringback
Falling-Edge
Ringback
V0015-01
Figure 4.4 Non-GTL+ Signal Ri ngback and S ettl ing Limit
4.3.1 Overshoot and Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of
the maximum voltage above the nominal high
voltage or below VSS. The overshoot/undershoot
guideline lim its t ransiti ons beyond VCC or V SS due to
the fast signal edge rates. The processor can be
damaged by repeated overshoot events on VCMOS
tolerant buffers if the charge is large enough (i.e., if
the overshoot i s great enough).
However, excessive ringback is the dominant
detrimental system timing effect resulting from
overshoot/undershoot (i.e., violating the
overshoot/undershoot guideline will make it difficult
to satisfy the ringback specification). The
overshoot/undershoot guideline is 0.7V for the 400
MHz, 0.8V for t he 366 MHz and below and ass um es
the absence of diodes on the input. These
guidelines should be verified in simulations
without
the on-chip E SD protection diodes present
because
the diodes will begin clamping the VCMOS tolerant
signals beginning at approximat ely 1.25V above V CC
and 0.5V below VSS. If the signals do not reach the
clamping voltage, then this will not be an issue. A
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 43
system should not rely on the diodes for
overshoot/undershoot protection as this will
negatively affect the life of the components and
make meeting the ringback specification very
difficult.
4.3.1 Ringback Specifi cation
Ringback refers to the amount of reflection seen
after a signal has switched. The ringback
specification is the voltage to which the signal rings
back after achieving its maximum absolute value.
Excessive ri ngback c an cause fal se signal detec tion
or extend the propagation delay. The ringback
specification applies to the input signal of each
receiving agent. Violations of the signal ringback
specification are not allowed under any
circumst ances for the non-GTL+ signals.
Ringback can be sim ulated with or without the input
protection diodes that can be added to the input
buffer model. However, signals that reach the
clamping voltage should be evaluated further. See
Table 4.4 for the signal ringback specifications for
non-GTL+ signals.
4.3.2 Settling Limit Guideline
Settling limit defines the maximum amount of
ringing at the receiving signal that a signal may
reach before its next transi tion. The am ount allowed
is 10% of the total signal swing (VHI – VLO) above
and below its final value. A signal should be within
the settling limit s of its final value, when either in i ts
high stat e or l ow st ate, before its next transition.
Signals that are not within their settling limit before
transitioning are at risk of unwanted oscillations that
could jeopardize signal integrity. Simulations to
verify settling limit may be done either with or
without the input protect ion diodes present . V iolat ion
of the settling limit guideline is acceptable if
simulations of 5 to 10 successive transitions do not
show the amplitude of the ringing increasing in the
subsequent t ransitions .
Table 4.4 Signal Ri ngback S pecifications for Non-GTL+ Signals for
the Mobile Pentium® I I Processor at 400 MHz
Input Signal Group Transition Maximum Ringback
(with I nput Di odes P r esent) Figure
Non-GTL+ Signals 0
1 1.135 V 4.4
Non-GTL+ Signals 1
0 0.600 V 4.4
Table 4.5 Signal Ri ngback S pecifications for Non-GTL+ Signals for
the Mobil e P enti u m ® I I P rocessor at 366 MHz and Below
Input Signal Group Transition Maximum Ringback
(with I nput Di odes P r esent) Figure
Non-GTL+ Signals 0
1 1.700 V 4.4
Non-GTL+ Signals 1
0 0.700 V 4.4
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
44 INTEL CORPORATION
5. MECHANICAL SPECIFICATIONS
The Mobile Pentium ® II process or are available i n a
PPGA-B 615 pack age (als o known as Mic ro-PGA ) or
in a PBGA-B615 package (also known as BGA).
The back of the processor die exposed on top of
both packages. This section contains information
describing the packages and the signal pin
assignments.
5.1 Dimensions of the Micro-PGA
Package
The Micro-PGA dimensions are given in Table 5.1,
and shown in Figure 5.1 and Figure 5.2. For
component handling, the substrate may only be
contacted within the region between the keepout
outline and t he edge of the subst rat e.
Table 5.1 Mi cro-PGA P ackage Mechanical S p eci fications
Symbol Parameter Min Max Unit
AOverall Height, top of die to seating plane of the
interposer 3.23 3.83 mm
A1Pin length 1.25 REF mm
A2Die Height 0.854 REF m m
B Pin Diameter 0.30 REF mm
D Die Subst rat e Width 30.85 31.15 mm
D1Die Width 10.36 REF m m
D2Package Width 32.60 REF m m
E Die Subst rat e Length 34.85 35.15 mm
E1Die Length 17.36 REF m m
E2Package Length 36.80 REF m m
e Pin pitch 1.27
Pin Tip Radial True P osition <=1.27
N Pin Count 615 each
S1Pin row A to short edge of interposer 2.220 REF m m
S2Pin column 1 to long edge of interposer 1.415 REF m m
PDIE Allowable Press ure on t he Di e for Thermal Solution — 689 k P a
W Pac kage Weight 7. 5 RE F grams
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 45
NOTE: Dimensions in parentheses are for reference only. All dimensions are in millimeters.
Figure 5.1 M icro-PGA Package-Top and Side View
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
46 INTEL CORPORATION
NOTE: Dimensions in parentheses are for reference only. All dimensions are in millimeters.
Figure 5.2 Micro-PGA Package - Bottom View
5.2 Dimensions of the BGA
Package
The mechanic al speci fic ati ons f or the s urfac e-m ount
package are provided in Table 5.2. Figure 5.3
shows the top and s i de vi ews of the surfac e-mount
package and, and Figure 5.4 s hows the bot tom view
of the surface-mount package. For component
handling, t he s ubstrate may only be cont acted within
the shaded region between the keepout outline and
the edge of the substrat e.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 47
Table 5.2 Surface-Mount BGA P ackage Specificati ons
Symbol Parameter Min Max Unit
A Overall Height, as delivered (USE THIS FOR 5.2) 2.29 2.79 mm
A1Substrate Height, as delivered 1.50 REF mm
A2Die Height 0.854 REF m m
b Ball Di ameter 0.78 REF mm
D Package Width 30.85 31.15 mm
D1Die Width 10.36 REF m m
E Package Length 34.85 35.15 mm
e Ball Pitch 1.27 m m
E1Die Length 17.36 REF m m
N Ball Count 615 each
S1Outer Ball Center to Short E dge of Substrate 1.625 REF m m
S2Outer Ball Center to Long Edge of S ubstrate 0.895 REF mm
PDIE Allowable Press ure on t he Di e for Thermal Solution — 689 k P a
W Pac kage Weight 3.71 4.52 grams
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
48 INTEL CORPORATION
D
1
E
1
V0026-00
(2x 1.800)
(2x 0.57)
(Ø 0.65)
(Ø 1.15)
D
(2x 2.032)
E
A
A
1
A
2
substrate
keepout
outline
die
(2x 1.50)
(5 .0 T YP )
(7 .0 T YP )
ink swatch
ink swatch
0.20 R EF
NOTE: Dimensions in parentheses are for reference only. All dimensions are in millimeters.
Figure 5.3 Surface-Mount BGA Package - Top and Side View
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 49
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
H
G
F
E
D
C
3 4 5 6 9 10111213 15161718192021222324
B
2V0025-01
K
J
A
7 81 14
S2
e
Øb
eS1
NOTE: Dimensions in parentheses are for reference only. All dimensions are in millimeters.
Figure 5.4 Surface-Mount BGA Package - Bottom Vi ew
5.3 Signal Listings
Figure 5.5 is a topside vi ew of the ball/pin m ap of
the Mobile Pentium ® I I proc ess or with the volt age
pins/balls call ed out. Table 5.3 list s the signals i n
pin/ball number order. Table 5.4 and Table 5.5 list
the signal s in signal name order.
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
50 INTEL CORPORATION
V0024-04
VCC OtherVCCP VSS Analog
Decou
p
lin
g
NCVSSD16#D18#VSSD3#D5#VSSVSSD0#VSSNCNCVSSNCVSSVSSA34#A26#VSSA29#VSSVSS
VSSVSSD31#D26#D13#D7#D2#D17#D15#D6#NCNCNCNCNCNCTESTHIA24#A30#A22#A19#A35#
EDG
CTRLN
VSS
D35#D29#D27#D24#D21#D19#D14#D10#D1#D4#NCNCNCNCNCBERR#RESET#A33#A31#A17#A25#NCNCVSS
D33#VSSD28#D32#VSSD22#D20#VSSD9#VREFVSSNCNCVSSVREFA27#VSSA20#A23#VSSTESTLOTESTLOVSSA28#
NCD39#D34#VREFVSSD25#D23#D30#D11#D12#D8#NCNCNCA32#A18#VREFA21#NCVSSTESTLOA13#A12#A16#
VCCPNCD43#D36#D37A10#A5#A15#A3#A11#
NCD44#VSSD38A14#VSSA6#A8#
D49#D51#D42#D45#AP0#A9#A4#A7#
D40#D52#D41#D47#D48#VREFAP1#RSP#BNR#TESTHI3
VSSD57#VSSVSSD59#TESTHI3VSSVSSTESTHI3VSS
D53#D46#D55#VREFD54#TESTHIREQ0#REQ4#BPRI#REQ1#
D60#D58#D50#D56#D61#TRDY#LOCK#TESTHI3REQ2#DEFER#
VSSD62#D63#VSSDEP7#VREFVSSHITM#REQ3#VSS
VSSDEP6#DEP5#DEP3#DEP0#HIT#DRDY#RP#DBSY#VSS
DEP4#DEP2#DEP1#VREFBPM1#PWRGOODRS1#RS2#RS0#BREQ0#
VSSBINIT#PRDY#VSSBP3#SLP#VSSTHERMDAADS#VSS
BPM0#BP2#TESTHI3PICCLKPICD1TDINCTHERMDCVCCPAERR#
TESTHIPREQ#INTRNCVCCPTMSNCBSEL
PICD0VSSVSSNCVCCPVSSVSSTRST#
VSSVCCPVCCPNCNCTESTLOFERR#SMI#TCKVSS
NMINCNCNCNCNCIERR#INIT#A20M#STPCLK#
NCNCNCNCNCNCNCIGNNE#TDO
VSSVSSNCVTOLNCTESTLONCTESTHI2FLUSH#
NCTESTHI2VCCPVSS NC
VSSVSS
VSSVSSBCLKVSSNC
242322212019181716151413121110987654321
PLL1PLL2
NC NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS VSS VSS VSSVSS
NCNCNCVCCVSSVCCVSSVCCVSSVCCVSSNCNCNC
NCNCNCVSSVCCVSSVCCVSSVCCVSSVCCNCNCNC
NCNCNCVCCVSSVCCVSSVCCVSSVCCVSSNCNCNC
NCNCNCVSSVCCVSSVCCVSSVCCVSSVCCNCNCNC
NCNCNCVCCVSSVCCVSSVCCVSSVCCVSSNCNCNC
NCNCNCVSSVCCVSSVCCVSSVCCVSSVCCNCNCNC
NCNCNCVCCVSSVCCVSSVCCVSSVCCVSSNCNCNC
NCNCNCVSSVCCVSSVCCVSSVCCVSSVCCNCNCNC
NCNCNCVCCVSSVCCVSSVCCVSSVCCVSSNCNCNC
NCNCNCVSSVCCVSSVCCVSSVCCVSSVCCNCNCNC
NCNCNCVCCVSSVCCVSSVCCVSSVCCVSSNCNCNC
NCNCNCVSSVCCVSSVCCVSSVCCVSSVCCNCNCNC
NCNCNCVCCVSSVCCVSSVCCVSSVCCVSSNCNCNC
NCNCNCVSSVCCVSSVCCVSSVCCVSSVCCNCNCNC
NCNCNCNCNCNCNCNCNCNCNCNCNCNC
NCNCNCNCNCNCNCNCNCNCNCNCNCNC
NCNCNCNCNCNCNCNCNCNCNCNCNCNC
NCNCNCNCNCNCNCNCNCNCNCNCNCNC
NCNCNCNCNCNCNCNCNCNCNCNCNCNC
NCNCNCNCNCNCNCNCNCNCNCNCNCNC
NCNCNCNCNCNCNCNCNCNCNCNCNCNC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
VCC
VSS
VCCP
Figure 5.5 Pin/Ball Map - Top View
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 51
Table 5.3 Signal Listing in Order by Pin/Ball Number
No. Signal Name No. S ignal Name No . Sig n al Name No. Signal Name
A2 VSS B8 TESTHI C14 NC D20 VSS
A3 VSS B9 NC C15 D4# D21 D32#
A4 A29# B10 NC C16 D1# D22 D28#
A5 VSS B11 NC C17 D10# D23 VSS
A6 A26# B12 NC C18 D14# D24 D33#
A7 A34# B13 NC C19 D19# E1 A16#
A8 VSS B14 NC C20 D21# E2 A12#
A9 VSS B15 D6# C21 D24# E3 A13#
A10 NC B16 D15# C22 D27# E4 TESTLO
A11 VSS B17 D17# C23 D29# E5 VSS
A12 NC B18 D2# C24 D35# E6 NC
A13 NC B19 D7# D1 A28# E7 A21#
A14 VSS B20 D13# D2 VSS E8 VREF
A15 D0# B21 D26# D3 TESTLO E9 A18#
A16 VSS B22 D31# D4 TESTLO E10 A32#
A17 VSS B23 VSS D5 VSS E11 NC
A18 D5# B24 VSS D6 A23# E12 NC
A19 D3# C1 VSS D7 A20# E13 NC
A20 VSS C2 NC D8 VSS E14 D8#
A21 D18# C3 NC D9 A27# E15 D12#
A22 D16# C4 A25# D10 VREF E16 D11#
A23 VSS C5 A17# D11 VSS E17 D30#
A24 NC C6 A31# D12 NC E18 D23#
B1 VSS C7 A33# D13 NC E19 D25#
B2 EDGCTRLN C8 RESET# D14 VSS E20 VSS
B3 A35# C9 BERR# D15 VREF E21 VREF
B4 A19# C10 NC D16 D9# E22 D34#
B5 A22# C11 NC D17 VSS E23 D39#
B6 A30# C12 NC D18 D20# E24 NC
B7 A24# C13 NC D19 D22# F1 A11#
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
52 INTEL CORPORATION
Table 5.3 Signal Listing in Order by Pin/Ball Number
No. Signal Name No. S ignal Name No . Sig n al Name No. Signal Name
F2 A3# G8 NC H15 VCC J21 D47#
F3 A15# G9 VSS H16 VSS J22 D41#
F4 A5# G10 VCC H17 NC J23 D52#
F5 A10# G11 VSS H18 NC J24 D40#
F6 NC G12 VCC H19 NC K1 VSS
F7 NC G13 VSS H20 D45# K2 TESTHI3
F8 NC G14 VCC H21 D42# K3 VSS
F9 NC G15 VSS H22 D51# K4 VSS
F10 NC G16 VCC H23 D49# K5 TESTHI3
F11 NC G17 NC J1 TESTHI3 K6 NC
F12 NC G18 NC J2 BNR# K7 NC
F13 NC G19 NC J3 RSP# K8 NC
F14 NC G20 D38# J4 AP1# K9 VCC
F15 NC G21 VSS J5 VREF K10 VSS
F16 NC G22 D44# J6 NC K11 VCC
F17 NC G23 NC J7 NC K12 VSS
F18 NC H2 A7# J8 NC K13 VCC
F19 NC H3 A4# J9 VSS K14 VSS
F20 D37# H4 A9# J10 VCC K15 VCC
F21 D36# H5 AP0# J11 VSS K16 VSS
F22 D43# H6 NC J12 VCC K17 NC
F23 NC H7 NC J13 VSS K18 NC
F24 VCCP H8 NC J14 VCC K19 NC
G2 A8# H9 VCC J15 VSS K20 D59#
G3 A6# H10 VSS J16 VCC K21 VSS
G4 VSS H11 VCC J17 NC K22 VSS
G5 A14# H12 VSS J18 NC K23 D57#
G6 NC H13 VCC J19 NC K24 VSS
G7 NC H14 VSS J20 D48# L1 REQ1#
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 53
Table 5.3 Signal Listing in Order by Pin/Ball Number
No. Signal Name No. S ignal Name No . Sig n al Name No. Signal Name
L2 BPRI# M8 NC N14 VCC P20 DEP0#
L3 REQ4# M9 VCC N15 VSS P21 DEP3#
L4 REQ0# M10 VSS N16 VCC P22 DEP5#
L5 TESTHI M11 VCC N17 NC P23 DEP6#
L6 NC M12 VSS N18 NC P24 VSS
L7 NC M13 VCC N19 NC R1 BREQ0#
L8 NC M14 VSS N20 DEP7# R2 RS0#
L9 VSS M15 VCC N21 VSS R3 RS2#
L10 VCC M16 VSS N22 D63# R4 RS1#
L11 VSS M17 NC N23 D62# R5 PWRGOOD
L12 VCC M18 NC N24 VSS R6 NC
L13 VSS M19 NC P1 VSS R7 NC
L14 VCC M20 D61# P2 DBSY# R8 NC
L15 VSS M21 D56# P3 RP# R9 VSS
L16 VCC M22 D50# P4 DRDY# R10 VCC
L17 NC M23 D58# P5 HIT# R11 VSS
L18 NC M24 D60# P6 NC R12 VCC
L19 NC N1 VSS P7 NC R13 VSS
L20 D54# N2 REQ3# P8 NC R14 VCC
L21 VREF N3 HITM# P9 VCC R15 VSS
L22 D55# N4 VSS P10 VSS R16 VCC
L23 D46# N5 VREF P11 VCC R17 NC
L24 D53# N6 NC P12 VSS R18 NC
M1 DEFER# N7 NC P13 VCC R19 NC
M2 REQ2# N8 NC P14 VSS R20 BPM1#
M3 TESTHI3 N9 VSS P15 VCC R21 VREF
M4 LOCK# N10 VCC P16 VSS R22 DEP1#
M5 TRDY# N11 VSS P17 NC R23 DEP2#
M6 NC N12 VCC P18 NC R24 DEP4#
M7 NC N13 VSS P19 NC T1 VSS
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
54 INTEL CORPORATION
Table 5.3 Signal Listing in Order by Pin/Ball Number
No. Signal Name No. S ignal Name No . Sig n al Name No. Signal Name
T2 ADS# U8 NC V15 VCC W23 PICD0
T3 THERMDA U9 VSS V16 VSS Y1 VSS
T4 VSS U10 VCC V17 NC Y2 TCK
T5 SLP# U11 VSS V18 NC Y3 SMI#
T6 NC U12 VCC V19 NC Y4 FERR#
T7 NC U13 VSS V20 NC Y5 TESTLO
T8 NC U14 VCC V21 INTR Y6 NC
T9 VCC U15 VSS V22 PREQ# Y7 NC
T10 VSS U16 VCC V23 TESTHI Y8 NC
T11 VCC U17 NC W2 TRST# Y9 VCC
T12 VSS U18 NC W3 VSS Y10 VSS
T13 VCC U19 NC W4 VSS Y11 VCC
T14 VSS U20 PICD1 W5 VCCP Y12 VSS
T15 VCC U21 PICCLK W6 NC Y13 VCC
T16 VSS U22 TESTHI3 W7 NC Y14 VSS
T17 NC U23 BP2# W8 NC Y15 VCC
T18 NC U24 BPM0# W9 VSS Y16 VSS
T19 NC V2 BSEL W10 VCC Y17 NC
T20 BP3# V3 NC W11 VSS Y18 NC
T21 VSS V4 TMS W12 VCC Y19 NC
T22 PRDY# V5 VCCP W13 VSS Y20 NC
T23 BINIT# V6 NC W14 VCC Y21 NC
T24 VSS V7 NC W15 VSS Y22 VCCP
U1 AERR# V8 NC W16 VCC Y23 VCCP
U2 VCCP V9 VCC W17 NC Y24 VSS
U3 THERMDC V10 VSS W18 NC AA1 STPCLK#
U4 NC V11 VCC W19 NC AA2 A20M#
U5 TDI V12 VSS W20 NC AA3 INIT#
U6 NC V13 VCC W21 VSS AA4 IERR#
U7 NC V14 VSS W22 VSS AA5 NC
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 55
Table 5.3 Signal Listing in Order by Pin/Ball Number
No. Signal Name No. S ignal Name No . Sig n al Name No. Signal Name
AA6 NC AB12 NC AC18 NC AD24 NC
AA7 NC AB13 NC AC19 NC AE1 VSS
AA8 NC AB14 NC AC20 NC AE2 VSS
AA9 NC AB15 NC AC21 VTOL AE3 VSS
AA10 NC AB16 NC AC22 NC AE4 VSS
AA11 NC AB17 NC AC23 VSS AE5 VSS
AA12 NC AB18 NC AC24 VSS AE6 VSS
AA13 NC AB19 NC AD1 VSS AE7 VSS
AA14 NC AB20 NC AD2 VCCP AE8 NC
AA15 NC AB21 NC AD3 VCC AE9 NC
AA16 NC AB22 NC AD4 TESTHI2 AE10 NC
AA17 NC AB23 NC AD5 NC AE11 NC
AA18 NC AB24 NC AD6 NC AE12 NC
AA19 NC AC1 FLUSH# AD7 NC AE13 NC
AA20 NC AC2 TESTHI2 AD8 NC AE14 NC
AA21 NC AC3 NC AD9 NC AE15 NC
AA22 NC AC4 VSS AD10 NC AE16 NC
AA23 NC AC5 TESTLO AD11 NC AE17 NC
AA24 NMI AC6 NC AD12 NC AE18 NC
AB1 TDO AC7 NC AD13 NC AE19 NC
AB2 IGNNE# AC8 NC AD14 NC AE20 NC
AB3 NC AC9 NC AD15 NC AE21 NC
AB4 VCCP AC10 NC AD16 NC AE22 NC
AB5 NC AC11 NC AD17 NC AE23 NC
AB6 NC AC12 NC AD18 NC AE24 NC
AB7 NC AC13 NC AD19 NC AF1 NC
AB8 NC AC14 NC AD20 NC AF2 VSS
AB9 NC AC15 NC AD21 NC AF3 BCLK
AB10 NC AC16 NC AD22 NC AF4 VSS
AB11 NC AC17 NC AD23 NC AF5 PLL2
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
56 INTEL CORPORATION
Table 5.3 Signal Listing in Order by Pin/Ball Number
No. Signal Name No. S ignal Name No . Sig n al Name No. Signal Name
AF6 PLL1 AF11 NC AF16 NC AF21 NC
AF7 VSS AF12 NC AF17 NC AF22 NC
AF8 NC AF13 NC AF18 NC AF23 NC
AF9 NC AF14 NC AF19 NC AF24 NC
AF10 NC AF15 NC AF20 NC
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 57
Table 5.4 Signal Listing in Order by Signal Name
No. Signal
Name Signal Buffer Type No. Signal
Name Signal Buffer Type
F2 A3# Low Power GTL+ I/O C7 A33# Low Power GTL+ I/O
H3 A4# Low Power GTL+ I/O A7 A34# Low Power GTL+ I/O
F4 A5# Low Power GTL+ I/O B3 A35# Low Power GTL+ I/O
G3 A6# Low Power GTL+ I/O AA2 A20M# CMOS Input
H2 A7# Low Power GTL+ I/O T2 ADS# Low Power GTL+ I/O
G2 A8# Low Power GTL+ I/O U1 AERR# Low Power GTL+ I/O
H4 A9# Low Power GTL+ I/O H5 AP0# Low Power GTL+ I/O
F5 A10# Low Power GTL+ I/O J4 AP1# Low Power GTL+ I/O
F1 A11# Low Power GTL+ I/O AF3 B CLK Proc es sor Clock I nput
E2 A12# Low Power GTL+ I/O C9 BE RR# Low Power GTL+ I/O
E3 A13# Low Power GTL+ I/O T23 BINIT# Low Power GTL+ I/O
G5 A14# Low Power GTL+ I/O J2 BNR# Low Power GTL+ I/O
F3 A15# Low Power GTL+ I/O U23 BP2# Low Power GTL+ I/O
E1 A16# Low Power GTL+ I/O T20 BP3# Low Power GTL+ I/O
C5 A17# Low Power GTL+ I/O U24 B P M0# Low Power GTL+ I/O
E9 A18# Low Power GTL+ I/O R20 B P M1# Low Power GTL+ I/O
B4 A19# Low Power GTL+ I/O L2 BPRI# Low Power GTL+ Input
D7 A20# Low Power GTL+ I/O R1 BREQ0# Low Power GTL+ I/O
E7 A21# Low Power GTL+ I/O V2 BSEL CMOS Input
B5 A22# Low Power GTL+ I/O A15 D0# Low Power GTL+ I/O
D6 A23# Low Power GTL+ I/O C16 D1# Low Power GTL+ I/O
B7 A24# Low Power GTL+ I/O B18 D2# Low Power GTL+ I/O
C4 A25# Low Power GTL+ I/O A19 D3# Low Power GTL+ I/O
A6 A26# Low Power GTL+ I/O C15 D4# Low Power GTL+ I/O
D9 A27# Low Power GTL+ I/O A18 D5# Low Power GTL+ I/O
D1 A28# Low Power GTL+ I/O B15 D6# Low Power GTL+ I/O
A4 A29# Low Power GTL+ I/O B19 D7# Low Power GTL+ I/O
B6 A30# Low Power GTL+ I/O E14 D8# Low Power GTL+ I/O
C6 A31# Low Power GTL+ I/O D16 D9# Low Power GTL+ I/O
E10 A32# Low Power GTL+ I/O C17 D10# Low Power GTL+ I/O
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
58 INTEL CORPORATION
Table 5.4 Signal Listing in Order by Signal Name
No. Signal
Name Signal Buffer Type No. Signal
Name Signal Buffer Type
E16 D11# Low Power GTL+ I/O J22 D41# Low Power GTL+ I/O
E15 D12# Low Power GTL+ I/O H21 D42# Low Power GTL+ I/O
B20 D13# Low Power GTL+ I/O F22 D43# Low Power GTL+ I/O
C18 D14# Low Power GTL+ I/O G22 D44# Low Power GTL+ I/O
B16 D15# Low Power GTL+ I/O H20 D45# Low Power GTL+ I/O
A22 D16# Low Power GTL+ I/O L23 D46# Low Power GTL+ I/O
B17 D17# Low Power GTL+ I/O J21 D47# Low Power GTL+ I/O
A21 D18# Low Power GTL+ I/O J20 D48# Low Power GTL+ I/O
C19 D19# Low Power GTL+ I/O H23 D49# Low Power GTL+ I/O
D18 D20# Low Power GTL+ I/O M22 D50# Low Power GTL+ I/O
C20 D21# Low Power GTL+ I/O H22 D51# Low Power GTL+ I/O
D19 D22# Low Power GTL+ I/O J23 D52# Low Power GTL+ I/O
E18 D23# Low Power GTL+ I/O L24 D53# Low Power GTL+ I/O
C21 D24# Low Power GTL+ I/O L20 D54# Low Power GTL+ I/O
E19 D25# Low Power GTL+ I/O L22 D55# Low Power GTL+ I/O
B21 D26# Low Power GTL+ I/O M21 D56# Low Power GTL+ I/O
C22 D27# Low Power GTL+ I/O K23 D57# Low Power GTL+ I/O
D22 D28# Low Power GTL+ I/O M23 D58# Low Power GTL+ I/O
C23 D29# Low Power GTL+ I/O K20 D59# Low Power GTL+ I/O
E17 D30# Low Power GTL+ I/O M24 D60# Low Power GTL+ I/O
B22 D31# Low Power GTL+ I/O M20 D61# Low Power GTL+ I/O
D21 D32# Low Power GTL+ I/O N23 D62# Low Power GTL+ I/O
D24 D33# Low Power GTL+ I/O N22 D63# Low Power GTL+ I/O
E22 D34# Low Power GTL+ I/O P2 DBSY# Low Power GTL+ I/O
C24 D35# Low Power GTL+ I/O M1 DEFE R# Low Power GTL+ Input
F21 D36# Low Power GTL+ I/O P20 DEP0# Low Power GTL+ I/O
F20 D37# Low Power GTL+ I/O R22 DEP1# Low Power GTL+ I/O
G20 D38# Low Power GTL+ I/O R23 DEP2# Low Power GTL+ I/O
E23 D39# Low Power GTL+ I/O P21 DEP3# Low Power GTL+ I/O
J24 D40# Low Power GTL+ I/O R24 DEP4# Low Power GTL+ I/O
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 59
Table 5.4 Signal Listing in Order by Signal Name
No. Signal
Name Signal Buffer Type No. Signal
Name Signal Buffer Type
P22 DEP5# Low Power GTL+ I/O R2 RS0# Low Power GTL+ Input
P23 DEP6# Low Power GTL+ I/O R4 RS1# Low Power GTL+ Input
N20 DEP7# Low Power GTL+ I/O R3 RS2# Low Power GTL+ Input
P4 DRDY# Low Power GTL+ I/O J3 RSP# Low Power GTL+ Input
B2 EDGCTRLN Low Power GTL+ Control T5 SLP# CMOS I nput
Y4 FERR# Open Drain Output Y3 SMI# CMOS Input
AC1 FLUSH# CMOS Input AA1 STP CLK # CMOS Input
P5 HIT# Low Power GTL+ I/O Y2 TCK JTAG Clock I nput
N3 HITM# Low Power GTL+ I/O U5 TDI JTAG I nput
AA4 IERR# Open Drain Output AB1 TDO JTAG Output
AB2 IGNNE# CMOS Input B8 TEST HI GTL+ Test Input
AA3 INIT# CMOS Input L5 TESTHI GTL+ Test Input
V21 INTR CMOS Input V23 TESTHI GTL+ Test Input
M4 LOCK# Low Power GTL+ I/O AC2 TES THI2 CMOS Test I nput
AA24 NMI CMOS Input AD4 TESTHI2 CMOS Test Input
U21 PICCLK APIC Clock Input J1 TESTHI3 GTL+ Test Input
W23 PICD0 Open Drai n I/O K2 TEST HI 3 GTL+ Test Input
U20 PICD1 Open Drain I/O K5 TESTHI 3 GTL+ Test Input
AF6 PLL1 PLL Analog Voltage M3 TES T HI 3 GTL+ Test Input
AF5 PLL2 PLL Analog Voltage U22 TE STHI3 GTL+ Test Input
T22 PRDY# Low Power GTL+ Output D3 TES TLO Test Input
V22 PREQ# CMOS Input D4 TE S T LO Test Input
R5 PWRGOOD CMOS Input E4 TE S T LO Test Input
L4 REQ0# Low Power GTL+ I/O Y5 TEST LO Test Input
L1 REQ1# Low Power GTL+ I/O AC5 TES TLO Test Input
M2 REQ2# Low Power GTL+ I/O T3 THERMDA T hermal Diode A node
N2 REQ3# Low Power GTL+ I/O U3 THERMDC T hermal Diode Cat hode
L3 REQ4# Low Power GTL+ I/O V4 TMS JTAG Input
C8 RESET# Low Power GTL+ Input M5 TRDY# Low Power GTL+ Input
P3 RP# Low Power GTL+ I/O J5 VRE F GTL+ Referenc e Voltage
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
60 INTEL CORPORATION
Table 5.4 Signal Listing in Order by Signal Name
No. Signal
Name Signal Buffer Type No. Signal
Name Signal Buffer Type
D10 VREF GTL+ Reference Volt age L21 VREF GTL+ Reference Vol t age
D15 VREF GTL+ Referenc e V ol tage N5 VREF GTL+ Reference Volt age
E8 VREF GTL+ Referenc e V ol tage R21 VREF GTL+ Reference Vol tage
E21 VREF GTL+ Reference V ol t age AC21 V T OL Voltage Toleranc e
W2 TRST# JTAG Input
NOTE: Except f or BCLK, the CMOS signals are 1. 5V tolerant for 400 MHz; and 2.5V tolerant for 366 MHz
and below.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 61
Table 5.5 Voltage and No-Connect Ball/Pin Locations
Signal
Name Ball Nu mbers
NC A10, A12, A13, A24, B9, B10, B11, B12, B13, B14, C2, C3, C10, C11, C12, C13, C14, D12, D13,
E6, E11, E 12, E13, E24, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F23,
G6, G7, G8, G17, G18, G19, G23, H6, H7, H8, H17, H18, H19, J6, J7, J8, J17, J18, J19, K 6, K7,
K8, K17, K18, K19, L6, L7, L8, L17, L18, L19, M6, M7, M8, M17, M18, M19, N6, N7, N8, N17, N18,
N19, P6, P7, P8, P17, P18, P19, R6, R7, R8, R17, R18, R19, T6, T7, T8, T17, T18, T19, U4, U6,
U7, U8, U17, U18, U19, V3, V6, V7, V8, V17, V18, V19, V20, W6, W7, W 8, W17, W18, W19,
W 20, Y6, Y7, Y8, Y17, Y18, Y19, Y20, Y21, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13,
AA14, AA15, AA16, AA17, AA18, AA19, AA20, AA21, AA22, AA23, AB3, AB5, AB6, AB7, AB8,
AB9, A B10, AB11, AB12, AB13, AB 14, AB15, AB16, AB17, AB18, AB19, A B20, AB21, AB22,
AB23, A B24, AC3, AC6, AC7, A C8, AC9, AC10, A C11, AC12, AC13, A C14, AC15, AC16, A C17,
AC18, AC19, A C20, AC22, AD5, AD6, AD7, A D8, AD9, AD10, A D11, AD12, AD13, A D14, AD15,
AD16, AD17, A D18, AD19, AD20, AD21, AD22, A D23, AD24, AE8, AE9, AE10, AE11, AE12,
AE13, A E14, AE15, AE16, AE17, AE 18, AE19, AE20, AE21, AE22, AE23, A E24, AF1, AF8, AF9,
AF10, A F 11, AF12, AF13, AF14, A F 15, AF16, A F17, AF18, A F 19, AF20, A F 21, AF22, AF23, AF24
VCC G10, G12, G14, G16, H9, H11, H13, H15, J 10, J12, J14, J16, K9, K11, K13, K15, L10, L12, L14,
L16, M9, M11, M13, M15, N10, N12, N14, N16, P9, P11, P13, P15, R10, R12, R14, R16, T9, T11,
T13, T15, U10, U12, U14, U16, V9, V11, V13, V15, W10, W12, W14, W16, Y9, Y11, Y13, Y15,
AD3
VCCP F24, U2, V5, W5, Y22, Y23, AB4, AD2
VSS A2, A3, A5, A8, A9, A11, A14, A16, A17, A20, A23, B1, B23, B24, C1, D2, D5, D8, D11, D14, D17,
D20, D23, E5, E20, G4, G9, G11, G13, G15, G21, H10, H12, H14, H16, J9, J11, J13, J15, K 1, K3,
K4, K10, K12, K14, K16, K21, K22, K24, L9, L11, L13, L15, M10, M12, M14, M16, N1, N4, N9,
N11, N13, N15, N21, N24, P1, P10, P12, P14, P16, P24, R9, R11, R13, R15, T1, T4, T10, T12,
T14, T16, T21, T24, U9, U11, U13, U15, V10, V12, V14, V16, W3, W4, W9, W11, W13, W15,
W21, W22, Y 1, Y10, Y12, Y14, Y16, Y24, AC4, AC23, AC24, A D1, AE1, A E2, AE3, AE4, AE5,
AE6, AE7, AF2, AF4, AF7
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
62 INTEL CORPORATION
6. THERMAL SPECIFICATIONS
In order to achieve proper cooling of the processor,
a thermal solut ion (e.g., heat spreader, heat pipe, or
other heat transfer system) must m ake firm contact
to the exposed processor die. The processor die
must be clean before the thermal solution is
attached or the process or may be dam aged.
During all operating environments, the processor
case temperature, TCASE, must be within the
specified range of 0°C to 100°C. An A/D converter
attached to the thermal diode can be used to
measure the processor core temperature to ensure
compliance with this specification. The designer is
responsible for insuring that the thermal diode and
A/D converter accurately track the processor
temperature. The designer should verify this by
correlating “sensor” output temperature with a
thermocouple placed directly on the die surface.
Refer to Section 6.2 for more det ai l s .
Table 6.1 Mobile Pentium
II Processor (0. 18
m) Pow er S p ecifications
Symbol Parameter Min Typ1Max Unit Notes
TDP Thermal Design Power @ 400 MHz
@ 366 MHz
@ 333 MHz
@ 300PE MHz
@ 266PE MHz
@ 266PE MHz Low Voltage
—
—
—
—
—
—
9.80
13.10
11.80
11.10
9.80
7.90
W
W
W
W
W
W
at 100 °C 2, 3
PSGNT Stop Grant and Auto Halt power 1.25 W at 50°C 3
PQS Quick S tart and Sleep power 500 mW at 50°C 3
PDSLP Deep Sl eep power 150 mW at 50°C 3
TCASE Case Temperat ure 0 100 °C
NOTES:
1. TDPTYP is a recommendation bas ed on the power dissipati on of the proces s or while executi ng publ i cly
available software under normal operat i ng conditions at nominal vol t ages. Contac t your Intel Fiel d Sales
Representati ve for further inf ormation.
2. TDPMAX i s a specificati on of the total power dis s i pation of the processor while executing a worst -case
instruction mix under normal operati ng c ondi tions at nominal voltages. I t i ncludes the power dis s i pated by
all of t he c omponents withi n the process or. Specif i ed by design/characterizati on.
3. Not 100% tes t ed or guaranteed. The power specif i cations are compos ed of the current of t he processor
on the various vol tage planes. These currents are measured and s pecified at hi gh temperature in Table
3.10. These 50°C power specifications are determined by characterizat i on of the proces sor currents at
higher temperatures.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 63
6.1 Thermal Diode
The Mobile Pentium II processor has an on-die
diode that can be used to monitor the die
temperature. A thermal sensor located on the
system elec tronic s m ay use t he diode to m oni tor t he
die temperature of the processor for thermal
management purposes. Table 6.2 and Table 6.3
provide the diode interface and s pec i ficati ons.
Table 6.2 Thermal Diode I n terface
Signal Name Ball/Pin Number Signal Description
THERMDA T3 Thermal diode anode
THERMDC U3 Thermal di ode cathode
Table 6.3. Thermal Di ode S p ecifications
Symbol Parameter Min Typ Max Unit Notes
IFW Forward Bias Current 5 500
A Note 1
n Diode Ideality Factor 1.0057 1.0080 1.0125 Notes 2, 4, 5
n Diode Ideality Factor 1.0000 1.0065 1.0173 Notes 3, 4, 5
NOTES:
1. Intel does not support or recommend operation of the thermal di ode under reverse bias. I ntel does not
support or rec omm end operat i on of the thermal diode when the proces sor power supplies are not withi n
their specified t ol eranc e range.
2. For the 400 MHz processor. Characterized at 100° C.
3. For the 366 MHz processor and below. Charac terized at 35°C.
4. Not 100% tes t ed. Specified by design/ c haracterizati on.
5. The i deal i ty factor, n, represent s the deviati on f rom ideal diode behavi or as exemplifi ed by the diode I/V
equation:
1
q
nkT
V
e
II D
O
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
64 INTEL CORPORATION
6.2 Case Temperature
To verify that the proper TCASE (cas e tem perat ure) is
maint ained f or the proc ess or, it shoul d be m eas ured
at the cent er of the die on the pack age top surfac e.
To minimize any measurement errors, the following
techniques are recom mended:
Use 36 gauge or finer diameter K, T or J type
thermocouples. Intel’s laboratory testing was
done using a thermocouple made by Omega
(part num ber: 5TC-TTK-36-36).
Attach the thermocouple bead or junction to
the center of the die on the top package
surface using highly thermally conductive
cements. Intel’s laboratory testing was done
using Omega Bond (part number: OB100).
Thermal grease provides equivalent
temperature measurement results when used
correctly but is not as mec hanically resilient as
cement.
The therm ocouple should be att ached at a 90°
angle as shown in Figure 6.1. A horizontal
therm oc oupl e mount is accept abl e.
V0028-00
Figure 6.1 Technique for M easuri ng Case Temperature
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 65
7. PROCESSOR INITIALIZATION
AND CONFIGURATION
7.1 Description
The Mobile Pentium® II processor has some
configuration options that are determined by
hardware and some that are determined by
software. The processor samples its hardware
configuration at reset, on the active-to-inactive
transition of RESET#. Most of the configuration
options for the Mobile Pentium II processor are
identic al t o those of t he P entium II processor. The
Pentium
®
II Proc essor Developer’s Manual
(order
number 243502) describes these configuration
options. New configuration options for the Mobile
Pentium II processor are described in the
remainder of this section.
7.1.1 Quick Start Enabl e
The processor normally enters the Stop Grant
state when the S TPCLK # signal is ass erted, but it
will enter the Quick Start state instead if A15# is
sampled ac tive on the RESET# signal’s ac tive-to-
inacti ve transition. The Quick St art state s upports
snoops from the bus priority device like the Stop
Grant state, but it does not support symmetric
master snoops, nor is the latching of interrupts
supported. A ‘1’ in bit position 5 of the Power-On
Configuration register indicates that the Quick
Start state has been enabl ed.
7.1.2 System Bus Frequency
The current generation Mobile Pentium II
processor will only function with a system bus
frequency of 66 MHz, but future generations may
operate at 100 MHz. Bit posi tion 19 of the P ower-
On Configuration register indicates at which
speed a processor will run. A ‘0’ in bit 19
indicates a 66-MHz bus frequency and a ‘1’
indicates a 100-MHz bus frequency.
7.1.3 APIC Disabl e
The APIC has been removed as a feature of the
Mobile Pentium II processor. The PICCLK and
PICD[1: 0] signals must be t ied to VSS with a 1K
resist or to disable the A PIC. Driving PI CD0 low at
reset has the effect of clearing the APIC Global
Enable bit in the APIC Base MSR. This bit is
normally set when the processor is reset, but
when it is cl eared the APIC i s com pl etely dis abl ed
until t he next reset.
7.2 Clock Frequencies and
Ratios
The Mobile Pentium II processor uses a clock
design in which the bus clock is multiplied by a
ratio to produce the processor’s internal (or
“core”) clock. The Bus Fraction Locking scheme
implemented in the processor permanently sets
the clock ratio multiplier to the corresponding
processor marked frequency. Section 3.3
describes how this is done. The bus ratio
programmed into the processor is visible in bit
positions 22 to 25 of the Power-On Configuration
register. Table 3.4 shows the 4-bit codes in the
Power-On Configuration register and their
corresponding bus ratios.
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
66 INTEL CORPORATION
8. PROCESSOR INTERFACE
8.1 Alphabetical Signal Reference
Except for BCLK, the 1.5V Tolerant signals are for
the 400 MHz; the 2.5V tolerant signals are for the
366 MHz and below.
A[35:3]# (I/O - Low Power GTL+)
The A[35:3]# (Address) signals define a 236-byte
physical memory address space. When ADS# is
active, these signals transmit the address of a
transaction; when ADS# is inactive, these signals
transmit transaction i nformat i on. These signals must
be connected to the appropriate balls/pins of both
agents on the system bus. The A[35:24]# signals
are protected with the AP1# parity signal, and the
A[23:3]# signals are protected with the AP0# parity
signal.
On the active-to-inactive transition of RESET#, each
processor bus agent samples A[35:3]# signals to
determ ine its power-on configurat ion. See Sect ion 7
of this document and the
Pentium
®
II Processor
Developer’s Manual
for detail s .
A20M# (I - 1. 5V /2.5V tolerant)
If the A20M# (Address-20 Mask) input signal is
asserted, the processor masks physical address bit
20 (A20#) before looking up a line in any internal
cache and before driving a read/write transac tion on
the bus. Asserting A20M# emulates the 8086
processor's address wrap-around at the 1-Mbyte
boundary. Assertion of A20M# is only supported in
real mode.
ADS# (I/O - Low Power GTL+)
The ADS# (Address Strobe) signal is asserted to
indicate the validity of a transaction address on the
A[35:3]# signals. Both bus agents observe the
ADS# activation to begin parity checking, protocol
checking, address decode, internal snoop or
deferred reply ID match operations associated with
the new transact ion. This signal must be connected
to the appropriate balls/pins on both agents on the
system bus.
AERR# (I/O - Low Power GTL+)
The AERR# (Address Parity Error) signal is
observed and driven by both system bus agents,
and if used, must be connected to the appropriate
balls of both agents on the system bus. AERR#
observation is optionally enabled during power-on
configurat ion; if enabl ed, a vali d ass ertion of AE RR#
aborts the current trans action.
If AERR# observation is disabled during power-on
configuration, a central agent may handle an
assertion of AERR# as appropriate to the error
handling architecture of t he system.
The AERR# processor bus pin is removed as a
processor feature for mobile Pentium® II processor
at 400 MHz. The pin must st ill be terminated to Vc c
through a 120
pull-up resistor. But the processor
mus t not be configured to drive or observe the pi n.
AP[1:0]# (I/ O - L o w Power GTL+)
The AP[1:0]# (Address Parity) signals are driven by
the request initiator along with ADS#, A[35:3]#,
REQ[4:0]# and RP#. AP1# covers A[35:24]#. AP0#
covers A[23:3]#. A correct parity signal is high if an
even number of covered signals are low and low if
an odd number of covered signals are low. This
allows parity t o be high when all the covered s ignals
are high. AP[1:0]# should be connected to the
appropriate balls /pins on both agent s on the syst em
bus.
BCLK (I - 2.5V tolerant)
The BCLK (Bus Clock) signal determines the
system bus frequency. Both system bus agents
must receive this signal to drive their outputs and
latch their inputs on the BCLK rising edge. All
external timing parameters are specified with
respect t o the BCLK si gnal .
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 67
BERR# (I/O - Low Power GTL+)
The BERR# (Bus Error) signal is asserted to
indicate an unrecoverable error without a bus
protocol vi olation. It m ay be driven by either sys tem
bus agent, and must be connected to the
appropriate balls/pins of both agents, if used.
However, the Mobile Pentium® II processor does
not observe as s ertions of the BERR# si gnal .
BERR# assertion conditions are defined by the
system configuration. Configuration options enable
the BERR# driver as foll ows:
Enabled or dis abl ed
Asserted optionally for internal errors along with
IERR#
Asserted optionally by the request initiator of a
bus transaction after it observes an error
A ss erted by any bus agent when it obs erves an
error in a bus trans action
BINIT# (I/O - Low Power GTL+)
The BINIT# (Bus Initialization) signal may be
observed and driven by both system bus agents,
and mus t be connect ed to t he appropriat e balls /pins
of both agents, if used. If the BINIT# driver is
enabled during the power-on configuration, BINIT#
is ass erted to s ignal any bus c ondition that prevents
reliable future information.
If BINIT# is enabled during power-on configuration,
and BINIT# is sampled asserted, all bus state
machines are reset and any data which was in
transit is lost. All agents reset their rotating ID for
bus arbitration to the state after reset, and internal
count inform ation is lost. The L1 and L2 caches are
not affected.
If BINIT# is disabled during power-on configuration,
a central agent may handle an assertion of BINIT#
as appropriate to the Machine Check Architecture
(MCA) of the s ystem .
BNR# (I/O - Lo w Pow er GTL+)
The BNR# (Block Next Request) signal is used to
assert a bus stall by any bus agent that is unable to
accept new bus trans actions. Duri ng a bus stall, the
current bus owner cannot issue any new
transactions.
Since multiple agents may need to request a bus
stall simultaneously, BNR# is a wired-OR signal
which must be connected to the appropriate
balls/ pi ns of both agents on the sys t em bus. In order
to avoid wire-OR glitches associated with
simultaneous edge transitions driven by multiple
drivers, BNR# is activated on specific clock edges
and sam pl ed on specifi c clock edges.
BP[3:2]# (I / O - L ow Power GTL+)
The BP[3:2]# (Breakpoint) signals are the System
Support group Break point signals. They are outputs
from the processor that indicate the status of
breakpoints.
BPM[1:0]# (I/O - Low Power GTL+)
The BPM[1:0]# (Breakpoint Monitor) signals are
breakpoint and performance monitor signals. They
are outputs from the processor that indicate the
status of breakpoints and programmable counters
used for monitoring processor perf ormance.
BPRI# (I - Low Power GTL+)
The BPRI# (Bus Priority Request) signal is used to
arbitrate f or ownership of t he sys tem bus . I t m ust be
connected to the appropriate balls/pins on both
agents on the system bus. Observing BPRI# active
(as asserted by the priority agent) causes the
process or to stop iss uing new requests , unl ess suc h
requests are part of an ongoing locked operation.
The priority agent keeps BPRI# asserted until all of
its requests are completed, and then releases the
bus by deass ert i ng BPRI#.
BREQ0# (I/O - Low Power GTL+)
The BREQ0# (Bus Request) signal is a processor
Arbitration Bus signal. The processor indicates that
it wants ownership of the system bus by asserting
the BREQ0# signal.
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
68 INTEL CORPORATION
During power-up configuration, the central agent
must assert the BREQ0# bus signal. The processor
sam ples B REQ0# on t he act ive-to-i nact ive trans iti on
of RESET#.
BSEL (I - 1.5V/2.5V tolerant)
The BSEL (System Bus Speed Select) signal is
used to configure the processor for the system bus
frequency. A ‘1’ on this signal configures the
processor for 100 MHz operation and a ‘0’
configures it for 66 MHz operation. Thi s signal mus t
be connect ed t o VSS.
D[63:0]# (I/O - Low Pow er GTL+)
The D[63:0]# (Data) signals are the data signals.
These signals provide a 64-bit data path between
both syst em bus agents, and must be connected to
the appropriate balls/pins on both agents. The data
driver asserts DRDY# to indicate a valid data
transfer.
DBSY# (I/O - Low Power GTL+)
The DBSY# (Data Bus Busy) signal is asserted by
the agent respons ible for dri ving data on t he sys tem
bus to indi cate that t he data bus is in use. The data
bus is released after DBSY# is deasserted. This
signal must be connected to the appropriate
balls/ pi ns on both agents on the syst em bus.
DEFER# (I - Low Power GTL+)
The DEFER# (Defer) s ignal is ass erted by an agent
to indicate that the transaction cannot be
guaranteed in-order completion. Assertion of
DEFER# is normally the responsibility of the
addressed memory agent or I/O agent. This signal
must be connected to the appropriate balls/pins on
both agents on the syst em bus.
DEP[7:0]# (I /O - Low Power GTL+)
The DEP[7:0]# (Data Bus ECC Protection) signals
provide optional ECC protection for the data bus.
They are driven by the agent res ponsible for driving
D[63:0]#, and must be connect ed to the appropriate
balls/pins on both agents on the system bus if they
are used. During power-on c onfiguration, DE P[7:0]#
signals can be enabled for ECC checking or
disabled f or no checking.
DRDY# (I/O - Lo w Pow er GTL+)
The DRDY# (Data Ready) signal is asserted by the
data driver on each data transfer, indicating valid
data on the data bus. In a multi-cycle data transfer,
DRDY# can be deas sert ed to i nsert idl e cl ocks. This
signal must be connected to the appropriate
balls/ pi ns on both agents on the syst em bus.
EDGCTRLN (analog)
This si gnal is used to c onfigure the edge rate of the
Low Power GTL+ output buffers. Connect the
EDGCTRLN (Edge Rate Control N-FET) signal to
VCC with a 51
, 1% resistor.
FERR# (O - 1.5V/2.5V tolerant open-drain)
The FERR# (Floating-point Error) signal is asserted
when the processor detects an unmasked floating-
point error. FE RR# is similar to the ERROR# s ignal
on the Intel387 coprocessor, and is included for
compatibility with systems using DOS-type floating-
point error reporti ng.
FLUSH# (I - 1.5V/2.5V tolerant)
When the FLUSH# (Flush) input signal is asserted,
the processor writes back all internal cache lines in
the Modified state and invalidates all internal cache
lines. At the completion of a flush operation, the
processor issues a Flush Acknowledge transaction.
The process or stops c ac hi ng any new data while the
FLUSH# signal remains asserted.
On the active-to-inactive transition of RESET#, each
process or bus agent sam ples FLUSH# to determi ne
its power-on conf i gurat i on.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 69
HIT# (I/O - Low Power GTL+), HITM#
(I/O - Low Power GTL+)
The HIT# (Snoop Hit) and HITM# (Hit Modified)
signals convey transaction snoop operation results,
and mus t be connect ed to t he appropriat e balls /pins
on both agents on the system bus. Either bus agent
can assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be
continued by reasserting HI T# and HITM# together.
IERR# (O - 1.5V/2.5V tolerant open-drain)
The IERR# (Int ernal Error) signal is as serted by t he
processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the system bus. This
transaction may optionally be converted to an
external error signal (e.g., NMI) by sys t em logic. The
processor will keep IERR# asserted until it is
handled in software or with the assertion of
RESET#, BINIT or INIT#.
IGNNE# (I - 1.5V/2.5V tolerant)
The IGNNE# (Ignore Numeric Error) signal is
asserted to force the processor to ignore a num eric
error and continue to execute non-control floating-
point instructions. If IGNNE# is deasserted, the
processor freezes on a non-control floating-point
instruction if a previous instruction caused an error.
IGNNE# has no effect when the NE bit in control
register 0 (CR0) i s set.
During active RESET#, the processor begins
sampling the A20M#, IGNNE#, INTR and NMI
values to determine the ratio of core-clock
frequency to bus-clock frequency (see Table 3.4).
On the active-to-inactive transition of RESET#, the
processor latches these signals and freezes the
frequency ratio internally. System logic must then
release these signals for normal operation.
INIT# (I - 1.5V/2.5V tolerant)
The INIT# (Initialization) signal is asserted to reset
integer registers inside the processor without
affecting the internal (L1 or L2) caches or the
floating-point registers. The processor begins
execution at the power-on reset vector configured
during power-on configuration. The processor
continues to handle snoop requests during INIT#
assert i on. INIT# is an as ynchronous input.
If INIT# is sampled active on RESET#'s active-to-
inactive transition, then the processor executes its
built-in self test (BIST).
INTR (I - 1.5V/2.5V tolerant)
The INTR (Interrupt) signal indicates that an
external interrupt has been generated. The interrupt
is m ask able us ing the I F bit in the EFLA GS regis ter.
If the IF bit is set, the processor vectors to the
interrupt handler after completing the current
instruc tion execution. Upon recognizing t he interrupt
request, the processor issues a single Interrupt
Acknowledge (INTA) bus transaction. INTR must
remain active until the INTA bus transaction to
guarantee its recognition. I NTR mus t be deas serted
for a minimum of two clocks to guarantee its
inacti ve recognition.
LOCK# (I/O - Low Power GTL+)
The LOCK# (Lock) signal indicates to the system
that a sequence of transactions must occur
atomically. This signal must be connected to the
appropriate balls /pins on both agent s on the syst em
bus. For a lock ed sequence of trans actions, LOCK#
is asserted from the beginning of the first
transaction through the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate
for bus ownership, it waits until it observes LOCK#
deasserted. This enables the processor to retain
bus ownership throughout the bus locked operation
and guarantee the atomici ty of lock.
NMI (I - 1.5V/2.5V tolerant)
The NMI (Non-Maskable Interrupt) indicates that an
external interrupt has been generated. Asserting
NMI causes an interrupt with an internally supplied
vector value of 2. An external int errupt-acknowledge
transaction is not generated. If NMI is asserted
during the execution of an NMI service routine, it
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
70 INTEL CORPORATION
remains pending and is recognized aft er the IRET is
executed by the NMI service routine. At most, one
assert ion of NMI is held pending. NMI i s rising-edge
sensitive. Active and inactive pulse widths must be
a minimum of two clocks.
PICCLK (I - 1.5V/2.5V tolerant)
The PICCLK (APIC Cl ock ) signal is an i nput c loc k t o
the processor and system logic or I/O APIC that is
required for operati on of the proc ess or, sys tem logi c
and I/O APIC components on the APIC bus.
PICD[1:0] (I/O - 1.5V/2.5V tolerant open-drain)
The PICD[1:0] (APIC Data) signals are used for
bidirectional serial message passing on the APIC
bus. They must be connected to the appropriate
balls/pins of all APIC bus agents, including the
processor and the system logic or I/O APIC
components. If the PICD0 signal is sampled low on
the active-to-inactive transition of the RESET#
signal, t hen the APIC i s hardware disabled.
PRDY# (O - Low Power GTL+)
The PRDY# (Probe Ready) signal is a processor
output used by debug tools to determine processor
debug readiness.
PREQ# (I - 1.5V/2.5V tolerant)
The PREQ# (Probe Request) signal is used by
debug tools to request debug operation of the
processor.
PWRGOOD (I - 2.5V/2.5V tolerant)
PWRGOOD (Power Good) is a 1.5V tolerant input
for the 400 MHz, and 2.5V tolerant for the 366 MHz
and below. The processor requires this signal to be
a clean indication that clocks and the power
supplies (VCC, VCCP, etc.) are s table and within their
specifications. Clean implies that the signal will
remain low, (capable of s ink ing leak age current ) and
without glitches, from the time that the power
supplies are turned on, until they come within
specification. The signal will then transition
monot onically to a high (1.5V or 2.5V) st ate. Figure
8.1 illustrates the relationship of PWRGOOD to
other system signals. PWRGOOD can be driven
inactive at any time, but clocks and power must
again be stable before the rising edge of
PWRGOOD. It must also meet the minimum pulse
width specified in Table 3.16 (Section 3.5), and be
followed by a 1 ms RESET# pulse.
BCLK
PWRGOOD
RESET#
D0026-00
1 msec
VIH,min
VCC,
VCCP,
VREF
Figure 8.1 PWRGOOD Relationshi p at P o wer-On
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 71
The PWRGOOD signal, which must be supplied to
the processor, is used to protect internal circuits
against voltage sequencing issues. The P WRGOOD
signal should be driven high throughout boundary
scan operat i on.
REQ[4:0]# (I/O - Low Power GTL+)
The REQ[4:0]# (Request Command) signals must
be connected to the appropriate balls/pins on both
agents on the s yst em bus. They are as sert ed by t he
current bus owner when it drives A[35:3]# to define
the currentl y active trans action type.
RESET# (I - Low Power GTL+)
Asserting the RESET# signal resets the processor
to a known state and invalidates the L1 and L2
caches without writing bac k Modified (M st ate) lines .
For a power-on type reset, RESET# must stay
active for at least 1 m sec after VCC and BCLK have
reached their proper DC and AC specifications and
after PWRGOOD has been asserted. When
observing active RESET#, all bus agents will
deassert their outputs within two clocks.
A number of bus signals are sampled at the active-
to-inactive transition of RESET# for the power-on
configuration. The configuration options are
described in Section 7 and in the
Pentium
®
II
Processor Developer’s Manual
.
Unless its outputs are tri-stated during power-on
configurat ion, after an acti ve-to-inactive t ransition of
RESET#, the process or optionally executes its built-
in self-test (BIST) and begins program execution at
reset-vector 000FFFF0H or FFFFFFF0H. RESET#
must be connected to the appropriate balls/pins on
both agents on the syst em bus.
RP# (I/O - Low Power GTL+)
The RP# (Request Parity) signal is driven by the
request initiator, and provides parity protection on
ADS# and REQ[4:0]#. RP# should be connected to
the appropriate balls/pins on both agents on the
system bus.
A correct parity signal is high if an even number of
covered signals are low, and low if an odd number
of covered signals are low. This definition allows
parity to be hi gh when all c overed signals are high.
RS[2:0]# (I - L ow Power GTL+)
The RS[2:0]# (Response Status) signals are driven
by the response agent (the agent responsible for
completion of the current transaction), and must be
connected to the appropriate balls/pins on both
agents on the system bus.
RSP# (I - Low Power GTL+)
The RSP# (Response P arity) signal is driven by t he
response agent (the agent responsible for
completion of the current transaction) during
assertion of RS[2:0]#. RSP# provides parity
protection for RS[2:0]#. RSP# should be connected
to the appropriate balls/pins on both agents on the
system bus.
A correct parity signal is high if an even number of
covered signals are low, and low if an odd number
of covered signals are low. During Idle state of
RS[2:0] # (RS[2:0] #=000), RSP# is als o high since it
is not driven by any agent guaranteeing correct
parity.
SLP# (I - 1.5V/2.5V tolerant)
The SLP# (Sl eep) signal, when ass erted i n the Stop
Grant state, caus es the proces sor to enter the Sleep
state. During the Sleep state, the processor stops
providing internal clock signals to all units, leaving
only the Phase-Loc ked Loop (PLL) st ill running. The
processor will not recognize snoop and interrupts in
the Sleep state. The processor will only recognize
changes in the SLP#, STPCLK# and RESET#
signals while in the Sleep state. If SLP# is
deasserted, the processor exits Sleep state and
returns to t he St op Grant s tat e in which it rest arts its
internal c l ock to the bus and API C proc essor units.
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
72 INTEL CORPORATION
SMI# (I - 1.5V/2.5V tolerant)
The SMI# (System Management Interrupt) is
asserted asynchronously by system logic. On
accepting a System Management Interrupt, the
processor saves the current state and enters
System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the
processor begins program execution from the SMM
handler.
STPCLK# (I - 1.5V/2.5V tolerant)
The STPCLK# (Stop Clock) signal, when asserted,
causes the processor to enter a low-power Stop
Grant state. The processor issues a Stop Grant
Acknowledge special transaction, and stops
providing internal clock signals to all units except
the bus and API C units. The proc essor continues to
snoop bus transactions and service interrupts while
in the Stop Grant state. When STPCLK# is
deasserted, the processor restarts its internal clock
to all unit s and resum es execution. The ass ertion of
STPCLK# has no effec t on the bus c l oc k.
TCK (I - 1.5V/2.5V tolerant)
The TCK (Test Clock) signal provides the clock
input for t he tes t bus (als o known as t he t est ac ces s
port).
TDI (I - 1.5V/2.5V tolerant)
The TDI (Test Data In) signal transfers serial test
data to the processor. TDI provides the serial input
needed for JTA G support.
TDO (O - 1.5V/2.5V tolerant open-drain)
The TDO (Test Data Out ) si gnal t ransfers serial tes t
data from the processor. TDO provides the serial
output needed for JTAG support.
THERMDA, THERMDC (analog)
The THERMDA (Thermal Diode Anode) and
THERMDC (Thermal Diode Cathode) signals
connect to the anode and cathode of the on-die
therm al di ode.
TMS (I - 1.5V/2.5V tolerant)
The TMS (Test Mode Select) signal is a JTAG
support s i gnal us ed by debug tools.
TRDY# (I - Low Power GTL+)
The TRDY# (Target Ready) signal is asserted by
the target to indicate that the target is ready to
receive write or implicit writeback data transfer.
TRDY# must be connected to the appropriate
balls/ pi ns on both agents on the syst em bus.
TRST# (I - 1.5V/2.5V tolerant)
The TRST# (Test Port Reset) signal resets the Tes t
Access Port (TAP) logic. The Mobile Pentium® II
processor does not self-reset during power-on;
therefore, it is necessary to drive this signal low
during power-on reset.
VTOL (O – 1.6V tolerant open-drain)
The VTOL (Voltage Tolerance) signal indicates
whether the processor has 2.5V tolerant CMOS
signals or 1.5V tolerant CMOS signals. This signal
is a high impedance pin on the 2.5V tolerant Mobile
Pentium® II processor at 366 MHz and below, and
is shorted to VSS on the 1.5V tolerant Mobile
Pentium® II processor at 400 MHz. It is safe to
connect t hi s signal t o 1.6V with a pull-up res i stor..
8.2 Signal Summaries
Table 8.1 through Table 8.4 list the attributes of the
process or i nput , output, and I /O signals.
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 73
Table 8.1 Input Signals
Name Active Level Clock Si gnal Group Qualified
A20M# Low Asynch CMOS Always
BCLK High — System B us Always
BPRI# Low BCLK System Bus Always
BSEL High Asynch Implementation Always
DEFER# Low BCLK System B us Always
FLUSH# Low Asynch CMOS Always
IGNNE# Low Asynch CMOS Always
INIT# Low Async h Sys tem B us Always
INTR Hi gh Asynch CMOS APIC disabled mode
NMI High Asynch CMOS API C di sabled mode
PICCLK High — APIC Always
PREQ# Low Asynch Implementation Always
PWRGOOD High Asynch Implementation Always
RESET# Low BCLK System Bus Always
RS[2: 0]# Low BCLK S ystem Bus Al ways
RSP# Low BCLK System Bus Always
SLP# Low Asynch Implementation Stop Grant state
SMI# Low Asynch CMOS Always
STPCLK# Low Asynch Implementation Always
TCK High — JTAG
TDI TCK JTAG
TMS TCK JTAG
TRDY# Low B CLK System Bus Response phase
TRST# Low Asynch JTAG
MOBILE PENTIUM® II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHz, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ
74 INTEL CORPORATION
Table 8.2 Output Signals
Name Active Level Clock Signal Group
FERR# Low Asynch Open-Drain
IERR# Low Asynch Open-Drain
PRDY# Low BCLK Implementation
TDO High TCK JTAG
VTOL High Asynch Implementation
Table 8.3 Input/Output Signals (Single Driver)
Name Active Level Clock S i gnal Group Quali fi ed
A[35:3]# Low BCLK S ys tem Bus A DS#, ADS#+1
ADS# Low BCLK System Bus Always
AP[1:0]# Low BCLK System Bus ADS#, A DS #+1
BREQ0# Low B CLK System B us A l ways
BP[3:2]# Low BCLK System Bus Always
BPM[1:0]# Low BCLK System Bus Always
D[63:0] # Low BCLK System B us DRDY#
DBSY# Low BCLK System Bus Always
DEP[7:0]# Low BCLK System B us DRDY #
DRDY# Low BCLK System Bus Always
LOCK# Low BCLK System B us Al ways
REQ[4:0]# Low B CLK System B us A DS #, ADS#+1
RP# Low BCLK System Bus ADS#, ADS#+1
MOBILE PENTIUM
II PROCESSOR IN MICRO-PGA AND BGA PACKAGES
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ
INTEL CORPORATION 75
Table 8.4 Input/Output Signals (Multiple Driver)
Name Active Level Clock Si gnal Group Quali fi ed
AERR# Low BCLK System Bus ADS#+3
BERR# Low BCLK System Bus Always
BINIT# Low B CLK System Bus Always
BNR# Low BCLK S ystem Bus Always
HIT# Low B CLK S ystem Bus Always
HITM# Low BCLK System Bus A l ways
PICD[1:0] High PICCLK APIC Always
UNITED STATES, I nt e l Corpor a t ion
2200 Mi ssi on Col l ege Bl vd. , P.O. Box 58119, Sant a Clar a, CA 95052-8119
Tel: +1 408 765- 8080
JAPAN, Intel Japan K. K.
5-6 Tokodai , Tsukuba- shi , Ibar aki - ken 300- 26
Tel: + 81- 29847- 8522
FRANCE, Inte l Corporati on S. A.R. L.
1, Q uai de G r enel l e, 75015 Par i s
Tel: +33 1- 45717171
UNITED KING DO M, Inte l Corpor a t ion ( U. K.) Lt d.
Piper s W ay, Swindon, Wi ltshire, England SN3 1RJ
Tel: +44 1- 793- 641440
GERMANY, Intel GmbH
Dornacher Strasse 1
85622 Feldki r chen/ M uenchen
Tel: +49 89/99143-0
HONG KONG, Inte l Semiconductor Ltd.
32/F Tw o Paci f i c Pl ace, 88 Queensway, Cent r al
Tel: +852 2844- 4555
CANADA, I ntel Sem iconductor of Canada, Ltd.
190 Attw el l Drive, Sui t e 500
Rexdale, Ontar i o M 9W 6H8
Tel: +416 675- 2438
BRAZIL, Intel Semicondutor es do Br asi l
Centro Empresar i al Nações Unidas - Edif ício Tor r e O est e
Av. das Nações Unidas, 12. 901 - 18o. andar - Brookl in Novo
04578.000 São Paulo - S. P. – Brasil
Tel: +55- 11-5505-2296
