HV7131RP CMOS Image Sensor with Image Signal Processing HV7131RP MagnaChip Semiconductor Ltd. Version 1.5 2005/ 02 / 04 V1.5 -12005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Revision History Revision Script Date Comments V1.0 2003/10/15/Wed - HV7131RP Preliminary is released V1.1 2004/01/20/Tue - register information is updated V1.2 2004/03/22/Mon - register information is updated V1.3 2004/08/16/Mon - register information is updated. (AE Anti-Flicker Step, AE Maximum Limit) - ENB setting is updated. V1.4 2004/10/04/Mon V1.5 2005/02/04/Fri - MagnaChip Logo Changed - Spectral response is updated. (p.13) - Anti-Banding Configuration is updated.(p.62) - Output Data according to Video Mode is updated.(p. 63) - Electro-Optical Characteristics is updated.(p.75) Copyright by MagnaChip Semiconductor Ltd., all right reserved 2003, 2004, 2005 Disclaimer This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd., assumes no responsibility or liability arising from use of circuit described, and no patent licenses are implied. 2005/ 02 / 04 V1.5 -22005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP CONTENTS General Description ...........................................................................................................................4 Features ..............................................................................................................................................4 Block Diagram ....................................................................................................................................5 40LD Pin Diagram...............................................................................................................................7 Pin Description ...................................................................................................................................8 Functional Description.......................................................................................................................9 Pixel Architecture ................................................................................................................. 9 ENB Setting guide information for normal stand-by mode ............................................... 9 Sensor Imaging Operation..................................................................................................10 10bit on-chip ADC ...............................................................................................................10 Gamma Correction ..............................................................................................................11 Color Interpolation ..............................................................................................................11 Color Correction & Color Space Conversion.....................................................................12 Image Enhancement............................................................................................................12 Edge Enhancement .............................................................................................................12 Output Formatting...............................................................................................................12 Auto Exposure Control .......................................................................................................13 Auto White Balance .............................................................................................................13 Spectral Characteristics......................................................................................................13 Register Description ........................................................................................................................14 Frame Timing.....................................................................................................................................57 Anti-Banding Configuration.................................................................................................................63 Data Output Timing and Interface ...................................................................................................63 Output Data according to Video Mode............................................................................................64 I2C Chip Interface.............................................................................................................................72 AC/DC Characteristics......................................................................................................................73 Electro-Optical Characteristics........................................................................................................77 CLCC Package Specification ..............................................................................................78 2005/ 02 / 04 V1.5 -32005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP General Description HV7131RP is a highly integrated single chip CMOS color image sensor implemented by proprietary MagnaChip 0.30um CMOS sensor process realizing high sensitivity and wide dynamic range. Total Pixel Array are 660x507 pixels. Each active pixel composed of 4 transistors has a micro-lens to enhance sensitivity, and converts photon energy to analog pixel voltage. On-chip 10bit Analog to Digital Converter (ADC) digitizes analog pixel voltage, and on-chip Correlated Double Sampling (CDS) scheme reduces Fixed Pattern Noise (FPN) dramatically. General image processing functions such as gamma correction, color interpolation, color correction, color space conversion, H/V Edge Enhancement, Image Enhancement, auto exposure, and auto white balance are implemented to diversify its applications, and various output formats are supported for the sensor to easily interface with different video codec chips. The integration of sensor function and image processing functions make HV7131RP especially very suitable for mobile imaging systems such as IMT-2000 phone's video part that requires very low power and system compactness. Features n 1/4.5 inch optical format n Total pixel array : 660x507 n Active pixel array : 640x480 n 5.04um x 5.04um active square pixel n Micro-lens for high sensitivity n RGB mosaic color filter array n On-chip 10 bit ADC n Correlated double sampling for reduction of Fixed Pattern Noise n Black Level Compensation n Gamma correction by programmable piecewise linear approximation n 3x3 Color interpolation n Color correction by programmable 3x3 matrix operation n Image Enhancement : Contrast, Hue, Saturation, Brightness n Edge Enhancement n Color space conversion from RGB to YCbCr n Inverse Color Space conversion YCbCr to RGB n Sub-sampling Modes : 2x2, 2x6, CIF, QCIF n Various output formats : YCbCr 4:2:2, RGB 5:6:6, Bayer 2005/ 02 / 04 V1.5 -42005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP n 8bit Data Bus Mode n Automatic Exposure Control n Automatic White Balance Control n Frame Rate : 30 f/s at 25Mhz, HBLANK = 208, VBLANK = 8 n Power Consumption: 86mW @ 30f/s and 2.8V, 68mW @ 15f/s and 2.8V, 336uW @ power down n Operation Voltage Range : 2.6V ~ 3.0V, Operation Temperature : -10 ~ +50 degrees Celsius n Package Types : CLCC 40 PIN, COB(Chip-on-Board), COF(Chip-on-Flex) Block Diagram Analog Analog Pre R/G/B Gain Amp. Gain Amp. Integration Time & Pre-Amp Gain Control (AE) Bayer Dark Noise Cancellation SCK SDA 10Bit ADC RGB Gamma Correction Strobe Sensor Core Auto Black Level Compensation MCLK Sensor Control Logic CEN RESETB Auto Exposure Color Space Conversion & Color Correction Anti Flicker R(G)B (Analog) Gain Control (AWB) HSYNC VSYNC VCLK YCbCr or RGB Output Stream 3x3 Color Interpolation to 24bit RGB Auto White Balance Color Suppression Output Formatter & Inverse conversion Image Enhancement (Hue, Saturation, Contrast, Brightness) H/V Edge Enhancement 2005/ 02 / 04 V1.5 -52005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Pixel Array Structure Metal Shielded Black Level Array [2 line] G R G R .... GG R G R B G B G .... BG G B G G R G R .... GG R G R B G B G .... BG G B G Metal Shielded Black Level Array [2 line] Note: If black level data output is enabled& ABLC enabled(SCTRC[1:0] set to 2'b11) with Bayer mode select(SCTRC[7] set to high), data output in the areas of Metal Shielded Black Level Array can be monitored during 4 line period of HSYNC right after VSYNC goes from high state to low state. 2005/ 02 / 04 V1.5 -62005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP 40LD Pin Diagram NC NC 1 NC NC 2 NC NC 3 NC NC 4 NC NC 5 40 39 38 3 7 36 GND_IO 6 35 GND_D Y[7] 7 34 VDD_D Y[6] 8 33 GND_A HV7131GP HV7131RP CLCC 40 PIN Y[5] 9 Y[4] 10 32 VDD_A 31 GND_A CLCC 40 PIN Top View Top View Y[3] 11 Y[2] 12 30 VDD_A 29 CEN Y[1] 13 28 RESETB Y[0] 14 27 NC 26 VDD_IO VDD_IO 15 16 17 18 19 20 21 22 23 24 25 GND_IO STROBE SCK SDA VCLK HSYNC VSYNC MCLK VDD_D GND_D 2005/ 02 / 04 V1.5 -72005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Pin Description Symbol Description Pin Type 1-5 N NC No Connection 6 G GND_IO Ground for I/O Buffer 7~14 O Y[7:0] 8Bits Video Data output 15 P VDD_IO Power for I/O Buffer 16 G GND_D Ground for Internal Digital Block 17 P VDD_D Power for Internal Digital Block 18 I MCLK Master Input Clock 19 O VSYNC Video Frame Synchronization signal. VSYNC is active at start of image data frame. 20 O HSYNC Video Horizontal Line Synchronization signal. Image data is valid, when HSYNC is high. 21 O VCLK Video Output Clock 22 B SDA I2C Standard data I/O port 23 I SCK I2C Clock Input 24 O STROBE Strobe Signal Output 25 G GND_IO Ground for I/O Buffer 26 P VDD_IO Power for I/O Bufrfer 27 N NC No Connection 28 I RESETB Sensor Reset, Low Active 29 I CEN Chip Enable, High Active CEN low : sleep mode, CEN high : normal operation mode 30 P VDD_A Power for Internal Analog Block 31 G GND_A Ground for Internal Analog Block 32 P VDD_A Power for Internal Analog Block 33 G GND_A Ground for Internal Analog Block 34 P VDD_D Power for Internal Digital Block 35 G GND_D Ground for Internal Digital Block 36-40 N NC No Connection 2005/ 02 / 04 V1.5 -82005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Functional Description Pixel Architecture Pixel architecture is a 4 transistor NMOS pixel design. The additional use of a dedicated transfer transistor in the architecture reduces most of reset level noise so that fixed pattern noise is not visible. Furthermore, micro-lens is placed upon each pixel in order to increase fill factor so that high pixel sensitivity is achieved. ENB Setting guide information for normal stand-by mode It is necessary that this kind of initialization sequence for the normal stand-by mode of HV7131RP after system power on Sensor operation sequence System power On Sensor Power down sequence More than 4cycle DVDD/AVDD RESETB Low MCLK Low 1'st VSYNC out VSYNC Low ENB Low 2.0 [Mcycle] for 1'st VSYNC out 2.086 [Mcycle] for logic stable time I2C Video stream Don't care Initialization sequence Don't care Camera Mode ex) If MCLK = 25[Mhz] => 2.086[Mcycle] / 25[MHz] = 83.44 ms The time period of ENB high value have to keep for 83.44[ms] or more 2005/ 02 / 04 V1.5 -92005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Sensor Imaging Operation Imaging operation is implemented by the offset mechanism of integration domain and scan domain (rolling shutter scheme). First integration plane is initiated, and after the programmed integration time is elapsed, scan plane is initiated, Time then image data start being produced. Integration Integration Plane Time Frame 0 Scan Integration Plane Frame 0 Plane Frame 0 Time Frame 1 Scan Plane Frame 1 Frame 1 Time 10bit on-chip ADC On-chip ADC converts analog pixel voltage to 10bit digital data. 2005/ 02 / 04 V1.5 - 10 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Gamma Correction Piecewise linear gamma approximation method is implemented. Ten piece linear segments are supported and user-programmable. Gamma Slope Registers are programmed as the integer value of real slope value that is multiplied by 64. Out Start 9 : : Start 3 Start 2 Slope 1 Start 1 Slope 0 Start 0 0 4 16 32 64 128 192 256 512 768 1023 In Gamma Transfer Function Color Interpolation 3x3 linear color interpolation is done by moving 3x3 interpolation window by one pixel horizontally and vertically B G B G R G B G B R B G 2005/ 02 / 04 V1.5 - 11 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Color Correction & Color Space Conversion Both of Color Correction and Color Space conversion are implemented by 3x3 matrix operation, so that two stages may be merged into one matrix stage. Color correction matrix may be resolved by measuring sensor's color spread characteristics for primary color source and calculating the inverse matrix of color spread matrix. For color space conversion matrix, the equation from CCIR-601 standard is normally used. Therefore, the intended single matrix for color correction and color space conversion may be resolved as below. Intended single matrix = Color Space Conversion Matrix * Color Correction Matrix Intended single matrix coefficients are programmable from -127/64 to 127/64. Programming register value for intended single matrix coefficients should be resolved by the following equations. For positive values, CMAxx = Integer (Real Coefficient Value x 64); For negative values, CMAxx = Two Complement(Integer (Real Coefficient Value x 64)); Real Coefficient Value values from -127/64 to 127/64 can be programmed. CCIR-601 YCbCr color space conversion equation < Conversion Equation > Y = (77R + 150G + 29B)/256 Range: 16 ~ 235 Cb = (-44R -87G + 131B)/256 + 128 Range: 16 ~ 240 Cr = (131R - 110G - 21B)/256 + 128 Range: 16 ~ 240 < Reverse Conversion > R = Y + 1.371(Cr - 128) G = Y - 0.698(Cr - 128) - 0.336(Cb - 128) B = Y + 1.732(Cb - 128) In the above equations, R, G, and B are gamma-corrected values. Image Enhancement Contrast, brightness, hue and saturation are programmable. Contrast and saturation factor range is 0.0 ~ 1.99. Brightness factor range is -127 ~ + 128. Hue factor range is -30~ + 30. Edge Enhancement Edge enhancement is performed for increasing sharpness of image. Edge weight range is 0.5 ~ 8.0. Output Formatting The output formats such as Bayer Raw Data, RGB 5:6:5, and YCbCr 4:2:2 are supported and the sequence of Cb and Cr are programmable. 2005/ 02 / 04 V1.5 - 12 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Auto Exposure Control Y mean value is continuously calculated every frame, and the integration time value is increased or decreased according to difference between target Y mean value and current frame Y mean value. Auto White Balance Cb/Cr frame mean value is calculated every frame and according to Cb/Cr frame mean values' displacement from Cb/Cr white target point. Spectral Characteristics 2005/ 02 / 04 V1.5 - 13 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Register Description Register Symbol Add. Default (Hex) (Hex) Description Device ID DEVID 00 42 Product ID, Revision No. Sensor Control A SCTRA 01 23 Xflip, Yflip, CIF mode, SSSel, Vmode[1:0] Sensor Control B SCTRB 02 00 Power down, Clock division Sensor Control C SCTRC 03 01 Sensor Internal control Register Row Start Address High RSAU 08 00 Row Start Address Upper Byte Row Start Address Low RSAL 09 02 Row Start Address Lower Byte Column Start Address High CSAU 0a 00 Column Start Address Upper Byte Column Start Address Low CSAL 0b 02 Column Start Address Lower Byte Window Height High WIHU 0c 01 Window Height Address Upper Byte Window Height Low WIHL 0d e0 Window Height Address Lower Byte Window Width High WIWU 0e 02 Window Width Address Upper Byte Window Width Low WIWL 0f 80 Window Width Address Lower Byte HBLANK Time High HBLU 10 00 HBLANK Time HBLANK Time Low HBLL 11 d0 208 clocks VBLANK Time High VBLU 12 00 VBLANK Time VBLANK Time Low VBLL 13 08 5 Lines Red Color Gain RCG 14 18 0.5 to 2 64 step 6bit resolution Green Color Gain GCG 15 18 0.5 to 2 64 step 6bit resolution Blue Color Gain BCG 16 18 0.5 to 2 64 step 6bit resolution Preamp Gain PgaVal 17 20 0.5 to 16.5 256 step 8bit resolution Preamp Gain Min PgaMIN 18 14 0.5 to 16.5 256 step 8bit resolution Preamp Gain Max PgaMAX 19 ff 0.5 to 16.5 256 step 8bit resolution Preamp Gain Nominal PgaNOM 1a 20 0.5 to 16.5 256 step 8bit resolution Analog control A ACTRA 1b 37 Amp Bias[3:0], CDS bias[6:4] Reset Clamp ACTRB 1c 7f Reset Clamping[7:4], ADC bias[3:0] Red Pixel Black Offset ORedl 21 3f -127 to +127 256 step Green Pixel Black Offset OGrnl 22 3f MSB = `0' mean "-" {1'b0, [4:0]} Blue Pixel Black Offset OBlul 23 3f LSB = `1' mean "+" {1'b0, [4:0]} Red Pixel Active Offset ORedU 24 RO ADC Offset Value for Active Red Pixel Green Pixel Active Offset OGrnU 25 RO ADC Offset Value for Active Green Pixel 2005/ 02 / 04 V1.5 - 14 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Blue Pixel Active Offset OBluU 26 RO ADC Offset Value for Active Blue Pixel Black Level Threshold BLCTH 27 3f Black Level Threshold Value(256) ISP Function Enable IspFen 30 02 Functions Enable & Edge Eh ISP Output Format OutFmT 31 60 Image data output formatting & Inversion Dark Noise Cancellation DncMode 33 41 Dnc Blocking[7:4], Dnc Th[3:2], Dnc Mode[1:0] Dnc Enable Gain DncGain 34 3e Dnc enable at Pgain 4.3x Dnc Enable Int. Time DncIntH 35 13 Dnc enable at DncIntM 36 12 Int time > {DncIntH, DncIntM, 8'h00} Color Matrix Coefficient 11 CMA11 37 2f Color matrix coefficient 11 Color Matrix Coefficient 12 CMA12 38 db Color matrix coefficient 12 Color Matrix Coefficient 13 CMA13 39 F6 Color matrix coefficient 13 Color Matrix Coefficient 21 CMA21 3a 0f Color matrix coefficient 21 Color Matrix Coefficient 22 CMA22 3b 28 Color matrix coefficient 22 Color Matrix Coefficient 23 CMA23 3c 08 Color matrix coefficient 23 Color Matrix Coefficient 31 CMA31 3d f5 Color matrix coefficient 31 Color Matrix Coefficient 32 CMA32 3e ce Color matrix coefficient 32 Color Matrix Coefficient 33 CMA33 3f 3d Color matrix coefficient 33 Gamma Segment Point 0 GmaP0 40 00 Start point for gamma line segment 0 Gamma Segment Point 1 GmaP1 41 04 Start point for gamma line segment 1 Gamma Segment Point 2 GmaP2 42 12 Start point for gamma line segment 2 Gamma Segment Point 3 GmaP3 43 21 Start point for gamma line segment 3 Gamma Segment Point 4 GmaP4 44 37 Start point for gamma line segment 4 Gamma Segment Point 5 GmaP5 45 55 Start point for gamma line segment 5 Gamma Segment Point 6 GmaP6 46 6b Start point for gamma line segment 6 Gamma Segment Point 7 GmaP7 47 7d Start point for gamma line segment 7 Gamma Segment Point 8 GmaP8 48 B4 Start point for gamma line segment 8 Gamma Segment Point 9 GmaP9 49 dd Start point for gamma line segment 9 Gamma Segment Slope 0 GmaS0 4a 40 Slope value for gamma line segment 0 Gamma Segment Slope 1 GmaS1 4b 4b Slope value for gamma line segment 1 Gamma Segment Slope 2 GmaS2 4c 3c Slope value for gamma line segment 2 Gamma Segment Slope 3 GmaS3 4d 2c Slope value for gamma line segment 3 Gamma Segment Slope 4 GmaS4 4e 1e Slope value for gamma line segment 4 Gamma Segment Slope 5 GmaS5 4f 16 Slope value for gamma line segment 5 2005/ 02 / 04 V1.5 - 15 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Gamma Segment Slope 6 GmaS6 50 12 Slope value for gamma line segment 6 Gamma Segment Slope 7 GmaS7 51 0e Slope value for gamma line segment 7 Gamma Segment Slope 8 GmaS8 52 0a Slope value for gamma line segment 8 Gamma Segment Slope 9 GmaS9 53 09 Slope value for gamma line segment 9 Invers Color constant for R RCrconst 54 57 Invers Color Constant for R Invers Color constant for G GCrconst 55 d4 Invers Color Constant for G Invers Color constant for G GCbconst 56 eb Invers Color Constant for G Invers Color constant for B BCbconst 57 6e Invers Color Constant for B Hue Value 1 HUE1 58 00 Hue value 1 Hue Value 2 HUE2 59 80 Hue value 2 Contrast Value Contrast 5a 80 Contrast Value Brightness Value Brightness 5b 00 Brightness Value Saturation Value Saturation 5c 80 Saturation Value Edge Weight Control Value EgWtCon 5d 00 Edge Weight Control Value 5e 10 Edge Enhancement Vth Low 60 24 Suppression Pre Amp Gain Min 61 24 Saturation Pre Amp Gain Min Edge Enhancement Vth EdThLo Low Suppression Pre Amp Gain SupGMin Min Saturation Pre Amp Gain SatGMin Min Edge Pre Amp Gain Min EdgGMin 62 24 Edge Gain Min AE Mode 1 AeMode1 70 29 Auto exposure mode selection 1 AE Mode 2 AeMode2 71 ed Auto exposure mode selection 2 AE Windows weight AeWinWgt 72 cd AE Windows weigth Integration Time High INTH 73 02 Integration Time High Integration Time Middle INTM 74 71 Integration Time Middle Integration Time Low INTL 75 00 Integration Time Low AE Target OutDoor LuTarget1 76 5a AE Target OutDoor AE Target InDoor LuTarget2 77 5a AE Target InDoor AE Lock Boundary AeLockFineBn 78 f6 AE Lock Boundary d AE Unlock Boundary AeUnlockBnd 79 2a AE Unlock Boundary AE Anti-Flicker Step High AeintStepH 7a 01 AE Anti-Flicker Step High AE Anti-Flicker Step Middle AeintStepM 7b 38 AE Anti-Flicker Step Middle 2005/ 02 / 04 V1.5 - 16 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP AE Anti-Flicker Step Low AeintStepL 7c 80 AE Anti-Flicker Step Low AE Maximum Limit High AeIntLimitH 7d 09 AE Maximum Limit High AE Maximum Limit Middle AeIntLimitM 7e c4 AE Maximum Limit Middle AE Maximum Limit Low AeIntLimitL 7f 00 AE Maximum Limit Low AWB Mode AWBMode 80 18 AWB mode AWB Windows Weight AwbWinWgt 82 00 AWB Windows Weight AWB Cb Target Position CbTarget 83 80 AWB Cb Target Position AWB Cr Target Position CrTarget 84 80 AWB Cr Target Position AWB Lock Boundary AwbLockBnd 85 02 AWB Lock Boundary AWB Unlock Boundary AwbUnlockBnd 86 20 AWB Unlock Boundary AWB Cb White Pixel CbWhiteBnd 87 30 AWB White Pixel Boundary White Pixel CrWhiteBnd 88 30 AWB White Pixel Boundary AWB C Boundary AwbCBnd 89 30 AWB Cb+Cr Boundary R/B Gain Max AwbGainMax 8a 3f R/B Gain Max R/B Gain Min AwbGainMin 8b 00 R/B Gain Min AE State Machine AeFSM 8c RO AE State Machine AWB State Machine AwbFSM 8d RO AWB State Machine Lu Frame Mean LuFMean 8e RO Lu Frame Mean Value Cb Frame Mean CbFMean 8f RO Cb Frame Mean Value Cr Frame Mean CrFMean 90 RO Cr Frame Mean Value Anti Banding Gain Min KlBndMin 91 14 Anti Banding Pre Amp Gain Min Anti Banding Gain Max KlBndMax 92 3d Anti Banding Pre Amp Gain Max Awb White Pixel Boundary AwbWhite 93 ff Awb White Pixel Boundary Awb Black Pixel Boundary AwbBlack 94 00 Awb Black Pixel Boundary Awb Valid Number AwbNumber 95 02 Awb Valid Number Plane IntScnOfsH 96 R0 Integration-Scan Plane Offset High Plane IntScnOfsM 97 R0 Integration-Scan Plane Offset Middle Plane IntScnOfsL 98 R0 Integration-Scan Plane Offset Low Boundary AWB Cr Boundary Integreation-Scan Offset High Integreation-Scan Offset Middle Integreation-Scan Offset Low 2005/ 02 / 04 V1.5 - 17 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Device ID [DEVID : 00h : 42h] 7 6 5 4 3 Product ID 0 1 2 1 0 Revision Number 0 0 0 0 1 0 High nibble represents Sensor Array Resolution, Low Nibble represents Revision Number. Sensor Control A [SCTRA : 01h : 23h] 7 6 Reserved 0 5 4 3 2 X-Flip Y-Flip CifMode SSSel 1 0 0 0 0 X-Flip Image is horizontally flipped Y-Flip Image is vertically flipped CifMode 1 0 Video Mode 1 1 When this register set to high and video mode(SCTRA[1:0]) set to "11" or "00", output data is CIF format. And if this register set to high and video mode(SCTRA[1:0]) set to "10", output data is QCIF format. SSSel 0 ISP Sub-Sampling( High Image Quality, 1x Core Frame Rate) 1 Bayer Sub Sampling( Low Image Quality, 2x Core Frame Rate) * only applicable Row, Column is always ISP Video Mode 11 No Scaling mode 10 2x2 subsampling mode (1/4 subsampling) 01 2x6 subsampling mode (1/16 subsampling) 00 No Scaling mode * More detailed information is available on page 63 2005/ 02 / 04 V1.5 - 18 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Sensor Control B [SCTRB : 02h : 00h] 7 6 5 4 3 2 AE/AWB Data path Analog All Strobe Block Block Block Internal Signal Sleep Sleep Sleep Block Enable 1 0 Clock Division Sleep 0 0 0 0 0 0 0 0 < Clock Acronym Definition > MCF : Master Clock Frequency DCF : Divided Clock Frequency SCF : Sensor Clock Frequency ICF : Image Processing Clock Frequency VCF : Video Clock Frequency LCF : Line Clock Frequency < Clock Frequency Relation > MCF : MCF DCF : MCF/Clock Division SCF : DCF/2 ICF SCF for 3x3 interpolation, SCF/2 for 1/4 subsampling mode SCF/4 for 1/16 subsampling mode VCF : ICF*2 for 8bit output AE/AWB Block Sleep LCF : 1/(HBLANK Period + HSYNC Period) AE/AWB block goes into sleep mode with this bit set to high. Data path Block Sleep Image processing data path block goes into sleep mode with this bit set to high. Analog Block Sleep all internal analog block goes into sleep mode with this bit set to high. With All Digital Block Sleep active, sensor goes into power down mode. All Internal Block all internal digital and analog block goes into sleep with this bit set to high. Sleep Strobe Signal Enable When strobe signal is enabled by this bit, STROBE pin will indicates when strobe light should be splashed in the dark environment to get adequate lighted image. Clock Division divides input master clock(IMC) for internal use. Internal divided clock frequency (DCF) is defined as master clock frequency (MCF) divided by specified clock divisor. Internal divided clock frequency (DCF) is as follows. 000 : MCF, 001 : MCF/2, 010 : MCF/4, 011 : MCF/8 2005/ 02 / 04 V1.5 - 19 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP 100 : MCF/16, 101 : MCF/32, 110 : MCF/64, 111 : MCF/128 2005/ 02 / 04 V1.5 - 20 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Sensor Control C [SCTRC : 03h : 01h] 7 6 5 4 3 2 1 0 Bayer Single Black HSYNC in reserved Unit Gain Black ABLC Output Shot level VBLANK Mode Level enable Enable Mode average Data output Enable 0 0 Bayer Output Enable 0 0 0 0 0 0 1 Output format is set to RGB565 or YCbCr 4:2:2 by ISP Output Format [31h] value. 1 Single Shot Mode Black Level Average Bayer Raw data which does not pass ISP function is printed out. With this register set to high, single video image is streamed out 0 Output This bit enable R/G/B Active Offset registers[24h-26h] to represent updated active offset values 1 This bit enable R/G/B Active Offset registers[24h-26h] to represent black level average value HSYNC in VBLANK VBLANK is equivalent to VSYNC, and HSYNC is the inversion of HBLANK, and this bit control whether HSYNC is active or not when VBLANK unit is LCF. VSYNC (VBLANK) HSYNC Unit Gain Mode If set to HIGH, the value of R Gain and B Gain will become equal to G Gain. Black Level Data HSYNC is generated for light-shielded pixels in 4 lines. Enable Auto Black Level Compensation Black level average values of light-shielded pixels are compensated when active image data is produced. 2005/ 02 / 04 V1.5 - 21 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Row Start Address High [RSAU : 08h : 00h] 7 6 5 4 3 2 1 0 reserved Row Start Address High 0 0 0 0 0 0 0 0 3 2 1 0 0 1 0 Row Start Address Low [RSAL : 09h : 02h] 7 6 5 4 Row Start Address Low 0 0 0 0 0 Row Start Address register defines the row start address of image read out operation. Column Start Address High [CSAU : 0ah : 00h] 7 6 5 4 3 2 reserved 1 0 Column Start Address High 0 0 0 0 0 0 0 0 3 2 1 0 0 1 0 Column Start Address Low [CSAL : 0bh : 02h] 7 6 5 4 Column Start Address Low 0 0 0 0 0 Column Start Address register defines the column start address of image read out operation. 2005/ 02 / 04 V1.5 - 22 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Window Height High [WIHU : 0ch : 01h] 7 6 5 4 3 2 1 reserved 0 Window Height High 0 0 0 0 0 0 0 1 4 3 2 1 0 0 0 0 2 1 0 Window Height Low [WIHL : 0dh : e0h] 7 6 5 Window Height Low 1 1 1 0 0 Window Height register defines the height of image to be read out. Window Width High [WIWU : 0eh : 02h] 7 6 5 4 3 reserved 0 0 0 Window Width High 0 0 0 1 0 4 3 2 1 0 0 0 0 Window Width Low [WIWL : 0fh : 80h] 7 6 5 Window Width Low 1 0 0 0 0 Window Width Address register defines the width of image to be read out. 2005/ 02 / 04 V1.5 - 23 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP HBLANK Time High [HBLU : 10h : 00h] 7 6 5 4 3 2 1 0 HBLANK Time High 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 HBLANK Time Low [HBLL : 11h : d0h] 7 6 5 HBLANK Time Low 1 1 0 1 0 HBLANK Time register defines data blank time between current line and next line by using Sensor Clock Period unit (1/SCF), and should be larger than 208(d0h). VBLANK Time High[VBLU : 12h : 00h] 7 6 5 4 3 2 1 0 VBLANK Time High 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 VBLANK Time Low[VBLL : 13h : 08h] 7 6 5 VBLANK Time Low 0 0 0 0 1 VBLANK Time register defines active high duration of VSYNC output. Active high VSYNC indicates frame boundary between continuous frames. For VSYNC-HSYNC timing relation in the frame transition, please refer to Frame Timing section. 2005/ 02 / 04 V1.5 - 24 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Each sensor has a little different photo-diode characteristics so that the sensor provides internal adjustment registers that calibrate internal sensing circuit in order to get optimal performance. Sensor characteristics adjustment registers are as below. Red Color Gain [RCG : 14h : 18h] 7 6 5 4 3 reserved 0 2 1 0 R Color Gain 0 0 1 1 0 0 0 4 3 2 1 0 Green Color Gain [RCG : 15h : 18h] 7 6 5 reserved 0 G Color Gain 0 0 1 1 0 0 0 4 3 2 1 0 0 0 Blue Color Gain [RCG : 16h : 18h] 7 6 5 reserved 0 B Color Gain 0 0 1 1 0 There are three color gain registers for R, G, B pixels, respectively. Programmable range is from 0.5X ~ 2.5X. Effective Gain = 0.5 + B<5:0>/32. These registers may be used for white balance and color effect with independent R,G,B color control. Default gain is 1.25X. Preamp Gain [PgaVal : 17h : 20h] 7 6 5 4 3 2 1 0 Preamp Gain 0 0 1 0 0 0 0 0 Preamp Gain is common gain for R, G, B channel and used for auto exposure control. Programmable range is from 0.5X ~ 16.5X. Default gain is 2.5X. Gain = 0.5 + B<7:0>/16 2005/ 02 / 04 V1.5 - 25 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Preamp Gain Min [PgaMin : 18h : 14h] 7 6 5 4 3 2 1 0 1 0 0 Preamp Gain Min 0 0 0 1 0 Preamp Gain Min is minimum value of preamp gain when sensor adjusts pre-amplifier gain for auto exposure control. Programmable range is same as preamp gain. Recommended value is 0.5X. Preamp Gain Max [PgaMax : 19h : ffh] 7 6 5 4 3 2 1 0 1 1 1 Preamp Gain Max 1 1 1 1 1 Preamp Gain Max is maximum value of preamp gain when sensor adjusts preamp gain for auto exposure control. Programmable range is same as preamp gain. Recommended value is 16.5X. Preamp Gain Normal [PgaNom : 1ah : 20h] 7 6 5 4 3 2 1 0 0 0 0 Preamp Gain Normal 0 0 1 0 0 Preamp Gain Normal is reference value of preamp gain when sensor adjusts preamp gain for auto exposure control. First, sensor controls integration time before adjusting preamp gain for auto exposure control. After integration time is changed to the minimum or maximum value, sensor adjusts preamp gain from this register value. Programmable range is same as preamp gain. Recommended value is 1.5X. Analog control A [ACTRA : 1bh : 37h] 7 6 reserved 0 5 4 3 2 CDS Bias[6:4] 1 0 1 1 Amp Bias Pixel Bias 0 1 1 0 1 controls the amount of current in CDS bias circuit to amplify CDS output effectively. The larger register value increases the amount of current. controls the amount of current in internal amplifier bias circuit to amplify Amplifier Bias[3:0] pixel output effectively. The larger register value increases the amount of current. 2005/ 02 / 04 V1.5 - 26 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Reset Clamp [ACTRB : 1ch : 7fh] 7 6 5 4 3 2 Reset Level Clamp 0 1 Reset Clamping[7:4] 1 1 0 ADC Bias 1 1 1 1 1 Because extremely bright image like sun affects reset data voltage of pixel to lower, bright image is captured as black image in image sensor regardless of correlated double sampling. To solve this extraordinary phenomenon, we adopt the method to clamp reset data voltage. Reset Level Clamp controls the reset data voltage to prevent inversion of extremely bright image. The larger register value clamps the reset data level at highest voltage level. Default value is 7 to clamp the reset data level at appropriate voltage level. ADC Bias[3:0] ADC Bias controls the amount of current in ADC bias circuit to operate ADC effectively. The larger register value increases the amount of current. Red Pixel Black Offset [ORedl : 21h : 3fh] 7 6 5 4 3 2 1 0 1 1 1 1 3 2 1 0 1 1 1 Red Pixel Black Offset 0 0 1 1 Green Pixel Black Offset [OGrnl : 22h : 3fh] 7 6 5 4 Green Pixel Black Offset 0 0 1 1 1 2005/ 02 / 04 V1.5 - 27 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Blue Pixel Black Offset [OBlul : 23h : 3fh] 7 6 5 4 3 2 1 0 1 1 1 Blue Pixel Black Offset 0 0 1 1 1 These registers control the offset voltage of ADC that changes the black level value for active pixels, red, green and blue pixel respectively. The registers are internally updated by black level compensation logic, and are read-only registers. Register bit functions are composed as follows. Pixel Black Offset[7] The bit specifies whether to subtract or add offset voltage in ADC input for light-shielded pixels. Pixel Black Offset[6:0] This value specifies the amount of offset voltage for light-shielded pixels. Red Pixel Active Offset [ORedU : 24h : RO] 7 6 5 4 3 2 1 0 RO RO RO RO 3 2 1 0 RO RO RO Red Pixel Active Offset RO RO RO RO Green Pixel Active Offset [OGrnU : 25h : RO] 7 6 5 4 Green Pixel Active Offset RO RO RO RO RO 2005/ 02 / 04 V1.5 - 28 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Blue Pixel Active Offset [OBluU : 26h : RO] 7 6 5 4 3 2 1 0 RO RO RO Blue Pixel Active Offset RO RO RO RO RO These registers control the offset voltage of ADC that changes the black level value for active pixels, red, green and blue pixel respectively. The registers are internally updated by black level compensation logic, and are read-only registers. Register bit functions are composed as follows. Pixel Active Offset[7] Pixel Active The bit specifies whether to subtract or add offset voltage in ADC input for active pixels. This value specifies the amount of offset voltage for active pixels. Offset[6:0] Black Level Threshold [BLCTH : 27h : 3fh] 7 6 5 4 3 2 1 0 0 1 1 Black Level Threshold 1 1 1 1 0 The register specifies the maximum value which determines whether light-shielded pixel output is valid. When light-shielded pixel output exceeds this limit, the pixel is not accounted for black level calculation. 2005/ 02 / 04 V1.5 - 29 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP ISP Function Enable [IspFen : 30h : 02h] 7 6 5 4 3 2 1 0 Saturation Color IspFen[5] Smooth Filter Edge Edge Gamma IspFen[0] Suppression Suppression Enable Enhance Algorithm Correction Enable Enable Enable Select 0 0 0 0 0 0 0 1 0 Disable It always comes to apply the same Saturation [5ch] value in a certain environment. Saturation Suppression Enable 1 Enable. If preamp gain[17h] exceeds saturation preamp gain min[60h], saturation value[5ch] is suppressed. Color Suppression 0 Disable Enable 1 Enable. Chroma Suppressed U, V output IspFen[5] Smooth Filter Enable Set `0' 0 Disable. 1 Enable. If Edge Enhancement is carried out, a image will become very sharp so by using smooth filter we can obtain a slightly soft image. Edge Enhance Enable 0 Disable. 1 Enable. In order to generate sharper image edge emphasizes and difference of the section of edge increases. This bit selects edge enhancement algorithm. Edge Algorithm Select Gamma Correction IspFen[0] 0 Use the algorithm which makes the line of edge vivid. 1 Use the algorithm which makes the line of edge embossing. 0 Disable. Normal Bayer Output 1 Enable. Gamma Corrected Bayer Output Set `0' 2005/ 02 / 04 V1.5 - 30 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP ISP Output Format [OutFmt : 31h : 60h] 7 6 5 4 3 2 1 0 reserved UFirst YFirst RGB565 Clk Inv Inv Inv Enable HSC VSC HSC VCLK 0 0 0 0 0 - 1 1 U First U pixel in front of V pixel for output data sequence. Y First Y pixel in front of U and V pixels for output data sequence. RGB 565 Enable Data format of RGB 565 mode is composed with {R[7:3]/G[7:5]}, {G[4:2]/B[7:3]} or {B[7:3]/G[7:5]}, {G[4:2]/R[7:3]}. If OutFmt[5](YFirst) register set to low, data format changes to BGR 565. Clk HSC In HSYNC, VCLK is embedded, that is, HSYNC is toggling at VCLK rate during normal HSYNC time Inv VSC VSYNC output polarity is inverted Inv HSC Do not support. Inv VCLK VCLK output polarity is inverted Dark Noise Cancellation [DncMode : 33h : 41h] 7 6 5 4 3 DNC always performing zone 0 1 DNC always 0 2 Dnc Threshold 0 0 0 1 0 Dnc Mode Select 0 1 Dark Noise always performed when 2 neighborhood pixel values are Less performing zone then this value x8. DNC Threshold Determines the grade judged to be noise. (Tight)11 - 10 - 01 - 00(Loose) DNC Mode Select 10 Dark Noise Cancellation is always performed 01 Dark Noise Cancellation is performed when Integration Time (73h- 75h) exceeds (DNC enable integration Time[35h-36h] *256) or Pre-Amp Gain[17h] > Dnc Gain[34h] 11, 00 Dark Noise Cancellation is turned off 2005/ 02 / 04 V1.5 - 31 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP DNC Enable Gain [DncGain : 34h : 3eh] 7 6 5 4 3 2 1 0 Dnc Mode Select 0 0 1 1 1 1 1 0 If Dnc mode[33h] set to "01" and Dnc enable gain exceeds preamp gain[17h], Dnc is enabled. DNC Enable Int. Time High [DncIntH : 35h : 13h] 7 6 5 4 3 2 1 0 0 0 1 1 3 2 1 0 0 1 0 Dark Noise Cancellation 0 0 0 1 DNC Enable Int. Time Mid [DncIntM : 36h : 12h] 7 6 5 4 Dark Noise Cancellation 0 0 0 1 0 For Dnc mode [1:0] at "01", if {DncIntH, DncIntM, and 8'h00} value is smaller than Integration Time[73h - 75 h] , Dnc will operate. 2005/ 02 / 04 V1.5 - 32 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Color Matrix Coefficients Both of Color Correction and Color Space conversion are implemented by 3x3 matrix operation, so that two stages may be merged into one matrix stage. Color correction matrix may be resolved by measuring sensor's color spread characteristics for primary color source and calculating the inverse matrix of color spread matrix. For color space conversion matrix, the equation from CCIR-601 standard is normally used. Therefore, the intended single matrix for color correction and color space conversion may be resolved as below. Intended single matrix = Color Space Conversion Matrix * Color Correction Matrix Intended single matrix coefficients are programmable from -127/64 to 127/64. Programming register value for intended single matrix coefficients should be resolved by the following equations. For positive values, CMAxx = Integer(RealCoefficientValue x 64); For negative values, CMAxx = TwoComplement(Integer(RealCoefficientValue x 64)); RealCoefficientValue values from -127/64 to 127/64 can be programmed. CCIR-601 YCbCr color space conversion equation < Conversion Equation > Y = (77R + 150G + 29B)/256 Range: 16 ~ 235 Cb = (-44R -87G + 131B)/256 + 128 Range: 16 ~ 240 Cr = (131R - 110G - 21B)/256 + 128 Range: 16 ~ 240 < Reverse Conversion > R = Y + 1.371(Cr - 128) G = Y - 0.698(Cr - 128) - 0.336(Cb - 128) B = Y + 1.732(Cb - 128) In the above equations, R, G, and B are gamma-corrected values Color Matrix Coefficient 11 [CMA11 : 37h : 2fh] 7 6 5 4 3 2 1 0 1 1 1 1 3 2 1 0 0 1 1 Color Matrix Coefficient 11 0 0 1 0 Color Matrix Coefficient 12 [CMA12 : 38h : dbh] 7 6 5 4 Color Matrix Coefficient 12 1 1 0 1 1 2005/ 02 / 04 V1.5 - 33 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Color Matrix Coefficient 13 [CMA13 : 39h : f6h] 7 6 5 4 3 2 1 0 0 1 1 0 3 2 1 0 1 1 1 1 3 2 1 0 1 0 0 0 3 2 1 0 1 0 0 0 3 2 1 0 0 1 0 1 3 2 1 0 1 1 1 0 3 2 1 0 1 0 1 Color Matrix Coefficient 13 1 1 1 1 Color Matrix Coefficient 21 [CMA21 : 3ah : 0fh] 7 6 5 4 Color Matrix Coefficient 21 0 0 0 0 Color Matrix Coefficient 22 [CMA22 : 3bh : 28h] 7 6 5 4 Color Matrix Coefficient 22 0 0 1 0 Color Matrix Coefficient 23 [CMA23 : 3ch : 08h] 7 6 5 4 Color Matrix Coefficient 23 0 0 0 0 Color Matrix Coefficient 31 [CMA31 : 3dh : f5h] 7 6 5 4 Color Matrix Coefficient 31 1 1 1 1 Color Matrix Coefficient 32 [CMA32 : 3eh : ceh] 7 6 5 4 Color Matrix Coefficient 32 1 1 0 0 Color Matrix Coefficient 33 [CMA33 : 3fh : 3dh] 7 6 5 4 Color Matrix Coefficient 33 0 0 1 1 1 2005/ 02 / 04 V1.5 - 34 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Gamma Segment Start Points Gamma Segment Start Points specify the start points of nine line segments for piecewise gamma approximation. Current default gamma curve is very selected for optimum gray gradation. Gamma Segment Point 0 [GmaP0 : 40h : 00h] 7 6 5 4 3 2 1 0 0 0 0 0 3 2 1 0 0 1 0 0 3 2 1 0 0 0 1 0 3 2 1 0 0 0 0 1 3 2 1 0 0 1 1 1 3 2 1 0 1 0 1 Gamma Segment Point 0 0 0 0 0 Gamma Segment Point 1 [GmaP1 : 41h : 04h] 7 6 5 4 Gamma Segment Point 1 0 0 0 0 Gamma Segment Point 2 [GmaP2 : 42h : 12h] 7 6 5 4 Gamma Segment Point 2 0 0 0 1 Gamma Segment Point 3 [GmaP3 : 43h : 21h] 7 6 5 4 Gamma Segment Point 3 0 0 1 0 Gamma Segment Point 4 [GmaP4 : 44h : 37h] 7 6 5 4 Gamma Segment Point 4 0 0 1 1 Gamma Segment Point 5 [GmaP5 : 45h : 55h] 7 6 5 4 Gamma Segment Point 5 0 1 0 1 0 2005/ 02 / 04 V1.5 - 35 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Gamma Segment Point 6 [GmaP6 : 46h : 6bh] 7 6 5 4 3 2 1 0 1 0 1 1 3 2 1 0 1 1 0 1 3 2 1 0 0 1 0 0 3 2 1 0 1 0 1 Gamma Segment Point 6 0 1 1 0 Gamma Segment Point 7 [GmaP7 : 47h : 7dh] 7 6 5 4 Gamma Segment Point 7 0 1- 1 1 Gamma Segment Point 8 [GmaP8 : 48h : b4h] 7 6 5 4 Gamma Segment Point 8 1 0 1 1 Gamma Segment Point 9 [GmaP9 : 49h : ddh] 7 6 5 4 Gamma Segment Point 9 1 1 0 1 1 Gamma Slope Values Gamma Slope Registers are programmed as the integer value of real slope value that is multiplied by 64. Gamma Segment Slope 0 [GmaS0 : 4ah : 40h] 7 6 5 4 3 2 1 0 0 0 0 0 3 2 1 0 0 1 1 Gamma Segment Slope 0 0 1 0 0 Gamma Segment Slope 1 [GmaS1 : 4bh : 4bh] 7 6 5 4 Gamma Segment Slope 1 0 1 0 0 1 2005/ 02 / 04 V1.5 - 36 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Gamma Segment Slope 2 [GmaS2 : 4ch : 3ch] 7 6 5 4 3 2 1 0 1 1 0 0 3 2 1 0 1 1 0 0 3 2 1 0 1 1 1 0 3 2 1 0 0 1 1 0 3 2 1 0 0 0 1 0 3 2 1 0 1 1 0 Gamma Segment Slope 1 0 0 1 1 Gamma Segment Slope 3 [GmaS3 : 4dh : 2ch] 7 6 5 4 Gamma Segment Slope 3 0 0 1 0 Gamma Segment Slope 4 [GmaS4 : 4eh : 1eh] 7 6 5 4 Gamma Segment Slope 4 0 0 0 1 Gamma Segment Slope 5 [GmaS5 : 4fh : 16h] 7 6 5 4 Gamma Segment Slope 5 0 0 0 1 Gamma Segment Slope 6 [GmaS6 : 50h : 12h] 7 6 5 4 Gamma Segment Slope 6 0 0 0 1 Gamma Segment Slope 7 [GmaS7 : 51h : 0eh] 7 6 5 4 Gamma Segment Slope 7 0 0 0 0 1 2005/ 02 / 04 V1.5 - 37 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Gamma Segment Slope 8 [GmaS8 : 52h : 0ah] 7 6 5 4 3 2 1 0 1 0 1 0 3 2 1 0 0 0 1 Gamma Segment Slope 8 0 0 0 0 Gamma Segment Slope 9 [GmaS9 : 53h : 09h] 7 6 5 4 Gamma Segment Slope 9 0 0 0 0 1 Inverse Color Space Conversion Inverse color space conversion transforms YCbCr by RGB. It is a function only about RGB565 format. Default setting value is from CCIR-601 standard. R = Y + A(Cr-128) G = Y - B(Cr-128) - C(Cb-128) B = Y + D(Cb-128) A : Inverse Color constant for R[54h] B : Inverse Color constant for G[55h] C : Inverse Color constant for G[56h] D : Inverse Color constant for B[57h] Inverse Color constant for R [RCrconst : 54h : 57h] 7 6 5 4 3 2 1 0 1 1 1 Inverse Color constant for R 0 1 0 1 0 For inverse color space conversion matrix, this register defines the constant(A) of following equation(CCIR-601 standard). R = Y + A(Cr-128) 2005/ 02 / 04 V1.5 - 38 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Inverse Color constant for G [Gcrconst : 55h : d4h] 7 6 5 4 3 2 1 0 1 0 0 Inverse Color constant for G 1 1 0 1 0 For inverse color space conversion matrix, this register defines the constant(A) of following equation(CCIR-601 standard). G = Y - A(Cr-128) - B(Cb-128) Inverse Color constant for G [Gcrconst : 56h : ebh] 7 6 5 4 3 2 1 0 0 1 1 Inverse Color constant for G 1 1 1 0 1 For inverse color space conversion matrix, this register defines the constant(B) of following equation(CCIR-601 standard). G = Y - A(Cr-128) - B(Cb-128) Inverse Color constant for B [Bcrconst : 57h : 6eh] 7 6 5 4 3 2 1 0 1 1 0 Inverse Color constant for B 0 1 1 0 1 For inverse color space conversion matrix, this register defines the constant(A) of following equation(CCIR-601 standard). B = Y + A(Cb-128) Hue value 1 [HUE1 : 58h : 00h] 7 6 5 4 3 2 1 0 Hue value 1 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 Hue value 2 [HUE2 : 59h : 80h] 7 6 5 Hue value 2 1 0 0 0 0 Hue factor for hue adjustment. Rotate angle range : -30 ~ +30 <Hue Reg Setting Parameter> 2005/ 02 / 04 V1.5 - 39 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP * HUE1 or HUE2 value is multiplied by 128 Angle HUE1 HUE2 Angle HUE1 HUE2 Angle HUE1 HUE2 () (hex) (hex) () (hex) (hex) () (hex) (hex) -30 C0 6E -9 EC 7E 12 1A 7D -29 C2 6F -8 EF 7E 13 1C 7C -28 C4 71 -7 F1 7F 14 1E 7C -27 C6 72 -6 F3 7F 15 21 7B -26 C8 73 -5 F5 7F 16 23 7B -25 CA 74 -4 F8 7F 17 25 7A -24 CC 74 -3 FA 7F 18 27 79 -23 CE 75 -2 FC 7F 19 29 79 -22 D1 76 -1 FE 7F 20 2B 78 -21 D3 77 0 00 80 21 2D 77 -20 D5 78 1 02 7F 22 2F 76 -19 D7 79 2 04 7F 23 32 75 -18 D9 79 3 06 7F 24 34 74 -17 DB 7A 4 08 7F 25 36 74 -16 DD 7B 5 0B 7F 26 38 73 -15 DF 7B 6 0D 7F 27 3A 72 -14 E2 7C 7 0F 7F 28 3C 71 -13 E4 7C 8 11 7E 29 3E 6F -12 E6 7D 9 14 7E 30 40 6E -11 E8 7D 10 16 7E -10 EA 7E 11 18 7D Contrast value [Contrast : 5ah : 80h] 7 6 5 4 3 2 1 0 0 0 0 Contrast value 1 0 0 0 0 Contrast factor for contrast adjustment. Programmable range of Contrast value is 0.1 ~ 1.99. The Contrast value is same as Saturation value. 2005/ 02 / 04 V1.5 - 40 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Brightness value [Brightness : 5bh : 00h] 7 6 5 4 3 2 1 0 0 0 0 Brightness value 0 0 0 0 0 Brightness adjustment is performed for summing Y data and brightness value. Brightness value is two's complement and its range is -127 ~ +128. Bright Y = Y data + brightness value. For positive value, Brightness[7:0] = Two's complement(integer) Saturation value [Saturation : 5ch : 80h] 7 6 5 4 3 2 1 0 0 0 0 Saturation value 1 0 0 0 0 Saturation adjustment is performed for multiplying Cr,Cb data by saturation value. Programmable range of saturation value is 0.1 ~ 1.99. For instance, Sat Cb,Cr = Cb,Cr data * Satuation[7:0] / 256 < Contrast & Saturation parameter > * Contrast or Saturation Value is multiplied by 128 Number Contrast & Saturation (hex) Number Contrast & Saturation (hex) 0.1 0D 1.1 8D 0.2 1A 1.2 9A 0.3 26 1.3 A6 0.4 33 1.4 B3 0.5 40 1.5 C0 0.6 4D 1.6 CD 0.7 5A 1.7 DA 0.8 66 1.8 E6 0.9 73 1.9 F3 1.0 80 1.99 FF 2005/ 02 / 04 V1.5 - 41 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Edge Weight Control value [EgWtCon : 5dh : 00h] 7 6 5 4 3 2 Reserved 0 0 Edge weight : 0 -> 0.5 ~ 1 0 Edge Weight 0 0 f -> 8 0. 0 0 0 0 Weight increases by 0.5 step and divides into 16 step. Edge Enhancement Vth Low [EdThLo : 5eh : 10h] 7 6 5 4 3 2 1 0 0 0 0 2 1 0 1 0 0 Edge Enhancement Vth Low 0 0 0 1 0 If edge value is higher than this register value, edge enhancement is enabled. Suppression Pre Amp Gain Min [SupGMin : 60h : 24h] 7 6 5 4 3 Suppression Pre Amp Gain Min 0 0 1 0 0 If preamp gain value is higher than this register value and Color Suppression Enable[30h] is HIGH, color suppression is enabled. Saturation Pre Amp Gain Min [SatGMin : 61h : 24h] 7 6 5 4 3 2 1 0 1 0 0 Saturation Pre Amp Gain Min 0 0 1 0 0 If preamp gain value is higher than this register value and Saturation Suppression Enable[30h] is HIGH, saturation suppression is enabled. Edge Pre Amp Gain Min [EgeGMin : 62h : 24h] 7 6 5 4 3 2 1 0 1 0 0 Edge Pre Amp Gain Min 0 0 1 0 0 If preamp gain value is higher than this register value and Edge Enhancement Enable[30h] is HIGH, edge suppression is enabled. Edge suppression is a function that edge weight decreases in dark 2005/ 02 / 04 V1.5 - 42 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP environment automatically. 2005/ 02 / 04 V1.5 - 43 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Auto Exposure Y mean value is continuously calculated every frame, and the integration time value is increased or decreased according to the displacement between current frame Y mean value and target Y mean value. FFh AE Unlock Boundary [79h] AE Lock Boundary [78h] 80h AE Target [76,77h] AE Lock Boundary [78h] AE Unlock Boundary [79h] 0h Y Frame Mean AE Mode 1 [AEMODE1 : 70h : 29h] 7 6 5 4 AEMODE1 Anti- Anti- AeWinEn [7] Banding Banding Enable Minimum 3 2 1 Time Speed 0 AE Mode Break 0 0 AEMODE1[7] 1 0 1 0 0 1 Set `0' 2005/ 02 / 04 V1.5 - 44 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Anti-Banding Enable When Anti-Banding is enabled, AE initializes Integration Time registers to 4 x Anti-Banding Step value, and integration increment/decrement amount is set to Anti-Banding Step value in order to remove banding noise caused by intrinsic energy waveform of light sources. Banding noise is inherent in CMOS image sensor that adopts rolling shutter scheme for image acquisition. In this mode, AE operates with very large unit, typically a reciprocal of (2 x power line frequency), so that minute integration time tuning is not liable. Therefore, this mode is recommended for only indoor use. Anti-Banding Minimum When AE is still of out lock state despite that AE preamp analog gain Break update value exceeds preamp minimum gain value(18h) and integration time(73h-75h) is reached to AE Anti-Banding Step(7ah-7ch), integration time(73h-75h) is broken to less than AE Anti-Banding Step(7ah-7ch). AeWinEn This bit uses during calculating the average of Y value at present frame for AE. When this bit is HIGH, AE Window Weight is equal. If not, calculate the average of Y using AE Window Weight. Time Speed (fast)11 - 10 - 01 - 00(slow) AE Mode 11 Gain-Only control mode. Only preamp gain is controlled to get optimum exposure state. 10 Time-Only control mode. Only integration time is controlled to get optimum exposure state. 01 Time-Gain control mode. integration time and preamp gain are controlled to get optimum exposure state. 00 AE function is disabled AE Mode 2 [AEMODE2 : 71h : edh] 7 6 Gain Speed 1 1 1 Gain Speed1 5 4 Gain Speed 2 1 3 2 1 0 Time Gain EnDGain EnAGain Fine Fine 1 1 0 1 0 This Speed Only worked from dark luminance condition to white luminance condition rapidly. (fast)11 - 10 - 01 - 00(slow) 2005/ 02 / 04 V1.5 - 45 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Gain Speed2 It's about situation except the case of Gain Speed 1. Gain update speed is specified as follows. (fast)11 - 10 - 01 - 00(slow) Integration Time Fine Tune Integration time fine tuning is performed when AE arrive around AE Fine Tune Boundary to settle into AE lock state smoothly. Preamp Gain Fine Tune Preamp gain fine tuning is performed when AE arrive around AE Fine Tune Boundary to settle into AE lock state smoothly. Enable Digital Gain If Pre-Amp Gain(17h) is less then Anti-Banding Gain Min(91h), Bayer pixel value are gained by ratio of Anti-Banding Gain Min / Pre-Amp Gain when this register value set to high. AE Analog Gain Control AE updates preamp gain register(17h) in order to reach optimum exposure state AE Windows Weight [AEWINWGT : 72h : cdh] 7 6 Top window 1 1 5 4 3 2 Center window Bottom window 0 1 0 1 0 Side window 1 0 1 When calculate the average of Y, each window is able to have different weight. Bottom Window in sensor means Top Window in display. Value Weight `Zro 1 `One 1/4 `Two 1/8 `Tri 1/16 VEnd VStart Top(1/16) Side(1/4) Center(1) Side(1/4) Bottom(1/16) HStart HEnd 2005/ 02 / 04 V1.5 - 46 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Integration Time High [INTH: 73h : 02h] 7 6 5 4 3 2 1 0 0 0 1 0 3 2 1 0 Integration Time High [23:16] 0 0 0 0 Integration Time Middle [INTM: 74h: 71h] 7 6 5 4 Integration Time Middle[15:8] 0 1 1 1 0 0 0 1 4 3 2 1 0 0 0 0 Integration Time Low [INTL: 75h: 00h] 7 6 5 Integration Time Low[7:0] 0 0 0 0 0 Integration time value register defines the time during which active pixel element evaluates photon energy that is converted to digital data output by internal ADC processing. Integration time is equivalent to exposure time of general camera so that integration time need to be increased in dark environment and decreased according to lighting condition. Maximum integration time is register maximum value(224-1) x sensor clock period(80ns, SCF 12.5Mhz @ DCF 25Mhz) = 1.34sec. AE Target OutDoor [LuTarget1 : 76h : 5ah] 7 6 5 4 3 2 1 0 0 1 0 2 1 0 0 1 0 AE Target OutDoor 0 1 0 1 1 This register defines the target luminance value for AE operation in outdoor. AE Target InDoor[LuTarget2 : 77h : 5ah] 7 6 5 4 3 AE Target InDoor 0 1 0 1 1 This register defines the target luminance value for AE operation in indoor. 2005/ 02 / 04 V1.5 - 47 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP AE Lock Boundary [AeLockFineBnd : 78h : f6h] 7 6 5 4 3 2 AE Fine Boundary 1 1 1 0 AE Lock Boundary 1 1 0 1 1 0 AE Lock Boundary specifies the displacement of Y Frame Mean value(8eh) from AE Target in which AE goes into LOCK state. With Anti-Banding is enabled, this displacement condition is discarded, and instead AE Speed Unlock Boundary is used as Lock boundary. AE Fine Boundary specifies the displacement of Y Frame Mean value(8eh) from AE Target in which AE start to tune fine integration time or preamp gain in order to goes into lock state smoothly. AE Unlock Boundary [AeUnlockBnd : 79h : 2ah] 7 6 5 4 3 2 1 0 0 1 0 AE Unlock Boundary 0 0 1 0 1 AE Unlock Boundary specifies Y Frame Mean displacement from AE Target in which AE goes into UNLOCK state. In this state, integration time increment/decrement speed changes from 2x (integration unit step) to 1x (integration unit step). In anti-banding mode, this boundary is used as lock boundary for exposure control. AE Anti-Flicker Step High [AeIntStepH : 7ah : 01h] 7 6 5 4 3 2 reserved 0 0 0 1 0 AE Anti-Flicker Step High 0 0 0 0 1 2 1 0 0 0 0 AE Anti-Flicker Step Middle [AeIntStepM : 7bh : 38h] 7 6 5 4 3 AE Anti-Flicker Step High 0 0 1 1 1 2005/ 02 / 04 V1.5 - 48 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP AE Anti-Flicker Step Low [AeIntStepL : 7ch : 80h] 7 6 5 4 3 2 1 0 0 0 0 AE Anti-Flicker Step Low 1 0 0 0 0 AE Anti-Banding Step specifies integration time unit value that AE uses when Anti-Banding is enabled. Anti-Banding Step value is resolved by the following equation. Anti-Banding Step Value = Sensor Operation Frequency (SCF) / (2x power line frequency) The default value is set with SCF 12.5Mhz, 50Hz power line, that is, Anti-Banding Step Value = 12.5Mhz / (2 x 50) = 125000d = 1e848h To operate stably, AE Anti-Flicker Step Low [1:0] bits have to `00'. So, Anti-Banding Step Value at HV7131RP is (1e848h & fffffch = 1e848h) AE Maximum Limit High [AeIntLimitH : 7dh : 09h] 7 6 5 4 3 2 1 0 1 0 0 1 3 2 1 0 0 1 0 0 3 2 1 0 0 0 0 AE Maximum Limit High 0 0 0 0 AE Maximum Limit Middle [AeIntLimitM : 7eh : c4h] 7 6 5 4 AE Maximum Limit Middle 1 1 0 0 AE Maximum Limit Low [AeIntLimitL : 7fh : 00h] 7 6 5 4 AE Maximum Limit Low 0 0 0 0 0 These three registers define the maximum integration time value that is allowed to sensor operation. It is desirable to set the value to multiples of AE Anti-Banding Step to easily operate with Anti-banding mode enabled. The default value is set to 1/8sec with SCF set to 25Mhz 12.5Mhz / 8 = 1,562,500 = 17d784 To operate stably, AE Maximum Limit Low [1:0] bits have to `11'. So, AE Maximum Limit at HV7131RP is (17d784h | 000003h = 17d787h) 2005/ 02 / 04 V1.5 - 49 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Auto White Balance Cb/Cr frame mean value is calculated every frame and according to Cb/Cr frame mean values' displacement from Cb/Cr white target point, R/B scaling values for R/B data are resolved. FFh Cb/Cr AWVB White Pixel Boundary [87h, 88h] AWB Unlock Boundary [86h] AWB Lock Boundary [85h] 80h Cb/Cr Target [83h, 84h] AWB Lock Boundary [85h] AWB Unlock Boundary [86h] Cb/Cr AWB White Pixel Boundary [87h, 88h] 0h Cb/Cr Frame Mean AWB Mode [AWBMode : 80h : 18h] 7 6 reserved AtoTstEn 5 4 3 2 Csp Val Awb AWB En Enable Window 1 0 AWB Speed AWB Mode[0] Enable - 0 AtoTstEn Csp Val En 0 1 1 0 0 0 This value is using at only simulation or test. When this bit set to high, color matrix coefficient [CMA11 ~ CMA33] is used for for color space conversion matrix. And if this bit set to low, the equation from CCIR-601 is used. 2005/ 02 / 04 V1.5 - 50 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Auto White Balance Control Enabled. Awb Enable AWB is carried out only when satisfying all the following cases. - the displacement of Cb/Cr Frame Mean value from AWB Target is larger than AWB Lock Boundary - the displacement of Cb/Cr Frame Mean value from AWB Target is smaller than AWB White Pixel Boundary - the displacement of the sum of Cb target and Cr target from the sum of average of Cb and Cr is smaller than AWB C Boundary AWB Window Enable This bit uses during calculating the average of Cb/Cr value at present frame for AWB. When this bit is HIGH, AWB Window Weight is equal. If not, calculate the average of Cb/Cr using AWB Window Weight. AWB Speed (Fast)11 - 10 - 01 - 00(slow) AWB Mode[0] Set `0' AWB Windows Weight [AwbWinWgt : 82h : 00h] 7 6 Top window 0 0 5 4 3 2 Center window Bottom window 0 0 0 1 0 Side window 0 0 0 When calculate the average of Cb/Cr, each window is able to have different weight. Bottom Window in sensor means Top Window in display. Value Weight `Zro 1 `One 1/4 `Two 1/8 `Tri 1/16 VEnd VStart Top(1) Side(1) Center(1) Side(1) Bottom(1) HStart HEnd 2005/ 02 / 04 V1.5 - 51 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP AWB Cb Target Position [CbTarget : 83h : 80h] 7 6 5 4 3 2 1 0 0 0 0 2 1 0 0 0 0 1 0 AWB Cb Target Position 1 0 0 0 0 This register defines Cb target frame mean value for AWB operation. AWB Cr Target Position [CbTarget : 84h : 80h] 7 6 5 4 3 AWB Cr Target Position 1 0 0 0 0 This register defines Cr target frame mean value for AWB operation. AWB Lock Boundary [AwbLockBnd : 85h : 02h] 7 6 5 4 3 reserved 0 0 2 AWB Lock Boundary 0 0 0 0 1 0 It specifies Cb/Cr frame mean values' displacement from Cb/Cr Target (83h-84h) value where AWB goes into LOCK state. AWB Unlock Boundary [AwbUnlockBnd : 86h : 20h] 7 6 5 4 3 2 1 0 0 0 0 AWB Unlock Boundary 0 0 1 0 0 It specifies Cb/Cr frame mean values' displacement from Cb/Cr Target (83h-84h) where AWB is released from LOCK state. AWB operation retains LOCK state unless Cb/Cr frame mean values' displacement value exceeds this boundary. The value should be larger AWB Lock Boundary. AWB Cb White Pixel Boundary [CbWhiteBnd : 87h : 30h] 7 6 5 4 3 2 1 0 0 0 0 AWB Cb White Pixel Boundary 0 0 1 1 0 When Cb frame mean values' displacement from Cb Target exceeds AWB White Pixel Boundary value, AWB accept frame color as it is and does not try to correct white balance deviation. 2005/ 02 / 04 V1.5 - 52 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP AWB Cr White Pixel Boundary [CrWhiteBnd : 88h : 30h] 7 6 5 4 3 2 1 0 0 0 0 AWB Cr White Pixel Boundary 0 0 1 1 0 When Cr frame mean values' displacement from Cr Target exceeds AWB White Pixel Boundary value, AWB accept frame color as it is and does not try to correct white balance deviation. AWB C Boundary [AwbCBnd : 89h : 30h] 7 6 5 4 3 2 1 0 0 0 0 AWB C Boundary 0 0 1 1 0 In case of the single color which is not a light source, this register uses in order not to operate AWB. R/B Gain Max [AwbGainMax : 8ah : 3f] 7 6 5 4 3 2 1 0 1 1 1 2 1 0 0 0 0 2 1 0 R/B Gain Max 0 0 1 1 1 The register specifies maximum boundary of AWB R/B gain R/B Gain Min [AwbGainMin : 8bh : 00] 7 6 5 4 3 R/B Gain Min 0 0 0 0 0 The register specifies minimum boundary of AWB R/B gain AE State Machine [AeFSM : 8ch : RO] 7 6 5 4 3 AE Mode State RO AE State RO RO AE Lock state RO RO RO RO RO Mode This nibble represents the mode where internal Y plane FSM is currently placed among time-gain control, time-only control, or gain-only control modes. "0000" : outdoor exposure control in anti-banding enabled "0001" : gain negative control mode 2005/ 02 / 04 V1.5 - 53 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP "0010" : exposure bidirectional control state "0011" : gain positive control mode "0100" : exposure only control mode "0101" : gain only control mode AE Lock State Y channel FSM status "0000" means that AE Y plane is in lock state "0001" means that AE Y plane is in unlock state "0010" means that AE Y plane is in far state AWB State Machine [AwbFSM : 8dh : RO] 7 6 5 reserved 4 3 AE/AWB 2 Cb Lock State 1 0 Cr Lock State Lock RO AE/AWB Lock RO RO RO RO RO RO RO This single status bit indicates that AE and AWB are in lock state for optimum still image capture. Cb Lock State Cb channel FSM status. "00" means that AWB Cb plane is in lock state. Cr Lock State Cr channel FSM status. "00" means that AWB Cr plane is in lock state Lu Frame Mean [LuFMean : 8eh : RO] 7 6 5 4 3 2 1 0 RO RO RO 2 1 0 RO RO RO Lu Frame Mean RO RO RO RO RO The register reports current Y plane frame mean value. Cb Frame Mean [CbFMean : 8fh : RO] 7 6 5 4 3 Cb Frame Mean RO RO RO RO RO The register reports current Cb plane frame mean value. 2005/ 02 / 04 V1.5 - 54 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Cr Frame Mean [CrFMean : 90h : RO] 7 6 5 4 3 2 1 0 RO RO RO 2 1 0 1 0 0 Cr Frame Mean RO RO RO RO RO The register reports current Cr plane frame mean value. Anti-Banding Gain Min [KlBndMin : 91h : 14h] 7 6 5 4 3 Anti-Banding Gain Min 0 0 0 1 0 The register specifies the minimum limit to which AE may decrease preamp gain or Y digital gain in order to get optimum exposure value while Anti-Banding Mode is enabled and the following condition is met. AE Lock Boundary < (Y Frame Mean - AE Target) < AE Unlock Boundary. Anti-Banding Gain Max [KlBndMax : 92h : 3dh] 7 6 5 4 3 2 1 0 1 0 1 Anti-Banding Gain Max 0 0 1 1 1 The register specifies the maximum limit to which AE may increase preamp gain or Y digital gain in order to get optimum exposure value while Anti-Banding Mode is enabled and the following condition is met. AE Lock Boundary < (AE Target - Y Frame Mean) < AE Unlock Boundary. AWB White Pixel Boundary [AwbWhite : 93h : ffh] 7 6 5 4 3 2 1 0 1 1 1 AWB White Pixel Boundary 1 1 1 1 1 During Cb, Cr frame mean value calculation, AWB discards pixel of which luminance is larger than this register value. 2005/ 02 / 04 V1.5 - 55 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP AWB Black Pixel Boundary [AwbBlack : 94h : 00h] 7 6 5 4 3 2 1 0 0 0 0 AWB Black Pixel Boundary 0 0 0 0 0 During Cb, Cr frame mean value calculation, AWB discards pixel of which luminance is smaller than this register value. AWB Valid Number [AwbNumber : 95h : 02h] 7 6 5 4 3 2 1 0 0 1 0 AWB Valid Number 0 0 0 0 0 AWB update when the number of valid color pixel is larger than (this valid value x 64). Integration-Scan Plane Offset High [IntScn0fsH : 96h : RO] 7 6 5 4 3 2 1 0 RO RO RO 2 1 0 RO RO RO 2 1 0 RO RO RO Integration-Scan Offset High RO RO RO RO RO Integration-Scan Plane Offset Middle [IntScn0fsM : 97h : RO] 7 6 5 4 3 Integration-Scan Offset Middle RO RO RO RO RO Integration-Scan Plane Offset Low [IntScn0fsL : 98h : RO] 7 6 5 4 3 Integration-Scan Offset Low RO RO RO RO RO The register represents time offset between integration plane and scan plane. The value should be the same as the value specified by integration time register(73h - 75h). 2005/ 02 / 04 V1.5 - 56 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Frame Timing For clear description of frame timing, clocks' acronym and relation are reminded in here again. < Clock Acronym Definition > MCF : Master Clock Frequency DCF : Divided Clock Frequency SCF : Sensor Clock Frequency ICF : Image Processing Clock Frequency VCF : Video Clock Frequency LCF : Line Clock Frequency < Clock Frequency Relation > MCF : MCF DCF : MCF/Clock Division SCF : DCF/2 ICF SCF for No Scale Image mode, SCF/2 for 2 X 2 subsampling mode SCF/4 for 2 X 6 subsampling mode VCF : ICF*2 for 8bit output LCF : 1/(HBLANK Period + HSYNC Period) HBLANK Period : HBLANK Time register value * (1/SCF) HSYNC Period : HSYNC Active Time < Frame Time Calculation > Core Frame Time is (IDLE SLOT + Video Height * LCP) and Real Frame Time is resolved as follows. When Integration Time > Core Frame Time, Real Frame Time is (Integration Time + VBLANK * LCP), otherwise is (Core Frame Time + VBLANK * LCP). 1. No Scale Image Timing No Scale Image Frame Timing Related Parameters Master Clock Frequency(MCF) 20Mhz Divided Clock Frequency(DCF) MCF/1 = 20Mhz Sensor Clock Frequency(SCF) DCF/2 = 10Mhz Sensor Clock Period(SCP) 1/10Mhz = 100ns Window Width 640 Window Height 480 HBLANK Value 208 VBLANK Value 8 VSYNC Mode Line Mode Line Clock Period(LCP) 848 SCPs Output Bus Width 8bit VGA Video Output Frequency SCF * 2 = 20Mhz Final Video Output Size 640x480 . . 2005/ 02 / 04 V1.5 - 57 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP If Integration Time < Core Frame Time, Real Frame Time is 2 * (208 + 640) SCPs + 480 * (208 + 640) SCPs + 8 * (208 + 640) SCPs = 415520 SCPs = 0.041552sec else Real Frame Time is Integration Time * SCPs + 8 * (208 + 640) SCPs. HOLD SLOT in frame timing appears only if integration time is larger than core frame time. Core Frame IDLE SLOT(2LCPs + (512+HBLANK)*4) Time HBLANK HSYNC (640 SCPs) Video Lines is (208 SCPs) Active Data: 640 EA active every LCP, that is, 480 Video Lines LCP(848 SCPs) for 480 LCPs HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] Real Frame (8 LCPs) Time 2005/ 02 / 04 V1.5 - 58 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP 480 line data // HSYNC // HSYNC Idle Slot HBLK 208 SCPs One active video line is equal to one line clock period(LCP) = 848 SCPs VCLK(20Mhz) Y[7:0] 640 SCPs // Y Cb Y Cr // Y Cb Y Hold Slot VSYNC VSYNC 2005/ 02 / 04 V1.5 - 59 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP 2. 2x2 Subsampling Timing 2 X 2 Subsampling Frame Timing Related Parameters Master Clock Frequency(MCF) 20Mhz Divided Clock Frequency(DCF) MCF/1 = 20Mhz Sensor Clock Frequency(SCF) DCF/2 = 10Mhz Sensor Clock Period(SCP) 1/10Mhz = 100ns Window Width 640 Window Height 480 HBLANK Value 208 VBLANK Value 8 VSYNC Mode Line Mode Line Clock Period(LCP) 848 * 2 SCPs Output Bus Width 8bit SIF Video Output Frequency SCF * 1 = 10Mhz Final Video Output Size 320x240 In 2 X 2sub-sampling mode, valid video data is produced every other line, i.e. for 480 LCPs, active video lines are 240. HSYNC active time is equal to HSYNC active time of No Scale Image mode, but video clock frequency is half of No Scale Image mode's to produce half size output in horizontal direction. IDLE SLOT ((512+HBLANK)*4) Core Frame Time Video Lines is 1 IDLE LINE (848SCPs) active every other LCP, that is, HBLANK HSYNC (640 SCPs) 240 Video Lines (208 SCPs) Active Data: 320 EA for 480 LCPs HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] Real Frame (8 LCPs) Time 2005/ 02 / 04 V1.5 - 60 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP 240 line data // HSYNC // HSYNC Idle Slot HBLK 208 SCPs 1 Idle Line One active video line is equal to one line clock period(LCP) = 848 SCPs 320SCPs VCLK=MCLK/4 // Y Y[7:0] Cb Y Cr // Y Cb Y VSYNC Hold Slot VSYNC 3. 2 X 6 Subsampling Timing 2 X 6 Subsampling Frame Timing Related Parameters Master Clock Frequency(MCF) 20Mhz Divided Clock Frequency(DCF) MCF/1 = 20Mhz Sensor Clock Frequency(SCF) DCF/2 = 10Mhz Sensor Clock Period(SCP) 1/10Mhz = 100ns Window Width 640 Window Height 480 HBLANK Value 208 VBLANK Value 8 VSYNC Mode Line Mode Line Clock Period(LCP) 848 * 4 SCPs Output Bus Width 8bit QSIF Video Output Frequency SCF / 2 = 5Mhz Final Video Output Size 160x120 In 2 X 6 subsampling mode, valid video data is produced every four line, i.e. for 480 LCPs, active video lines are 120. HSYNC active time is equal to HSYNC active time of No Scale Image mode, but video clock frequency is a quarter of No Scale Image mode's to produce a quarter size output in horizontal direction. 2005/ 02 / 04 V1.5 - 61 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Core Frame IDLE SLOT ( (512+HBLANK)*4) Time Video data is active at last 1 LCP period of every 4 LCPs 3 IDLE LINES (3 * 848 SCPs) period, that is, HBLANK HSYNC (640 SCPs) 120 Video Lines (208 SCPs) Active Data: 160 EA for 480 LCPs HOLD SLOT (Integration Time - Core Frame Time) VBLANK[VSYNC] Real Frame (8 LCPs) Time 120 line data // HSYNC // HSYNC Idle Slot HBLK 208 SCPs 3 Idle Line One active video line is equal to one line clock period(LCP) = 848 SCPs 160SCPs VCLK=MCLK / 8 Y[7:0] // Y Cb Y Cr // Y Cb Y VSYNC Hold Slot VSYNC 2005/ 02 / 04 V1.5 - 62 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Anti-Banding Configuration For Anti-Banding mode to work correctly, the following registers should be configured to the appropriate values. AE Mode 70h Anti-Banding Enable[7] AE Anti-Banding Step 7a-7ch SCF / (2 x power line frequency) AE Integration Time Limit 7d-7fh The value should be multiples of AE Anti-Banding Step When Anti-Banding is enabled, AE initializes Integration Time registers[73-75h] to 4 x Anti-Banding Step value[7a-7ch], and integration increment/decrement amount is set to Anti-Banding Step value in order to remove anti-banding noise caused by intrinsic energy waveform of light sources. Banding noise is inherent in CMOS image sensor that adopts rolling shutter scheme for image acquisition. Data Output Timing and Interface 14 ns ~ 15 ns M CLK V C LK HSYNC Y [7 :0 ] X Y0 Y1 Y2 4ns ~ 5ns As specified in the above data output timing diagram, the timing margin between video clock pin (VCLK) and data pins (Y[7:0]) is about 4ns ~ 5ns. This margin may be sufficient or not according to how much video clock and data pins are delayed internally in the backend chip, respectively. To safely latch the data output in the backend chip, it is recommended that data be latched at negative edge of VCLK. 2005/ 02 / 04 V1.5 - 63 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Output Data according to Video Mode Output Data according to Video Mode is controlled by configuring Sensor Control A[01h]. Configurable options are specified again for your reference. < Video Mode Setting > Row Sub- YCbCr 4:2:2 RGB 5:6:5 Bayer Sampling OUTFMT[6:4] = OUTFMT[6:4] = SCTRC[7] = 1 6h 7h VGA(640x480) ISP(SSSel = 0) Support Support None SCTRA[2:0] = 0h Bayer(SSSel = 1) Support Support Support QVGA(320x240) ISP(SSSel = 0) Support Support None SCTRA[2:0] = 2h Bayer(SSSel = 1) Support Support Support QQVGA(160x120 ISP(SSSel = 0) Support Support None ) Bayer(SSSel = 1) Support Support Support CIF(236x288) ISP(SSSel = 0) Support Support Not Support SCTRA[2:0] = 8h Bayer(SSSel = 1) Support Support Not Support QCIF(178x144) ISP(SSSel = 0) Support Support Not Support SCTRA[2:0] = Ah Bayer(SSSel = 1) Support Support Not Support or 3h SCTRA[2:0] = 1h or Bh 2005/ 02 / 04 V1.5 - 64 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP < Video Mode Setting > Output Format VGA Sensor Control A Sensor Control C [0x01] [0x05] (640 x 480) 0x00, YCbCr422 QVGA (320 x 240) ISP Subsampling 0x03 Output Format [0x31] 0x00 0x60 0x02 0x00 0x60 QQVGA (160 x 120) 0x01 0x00 0x60 CIF (356 x 288) 0x08, 0x00 0x60 QCIF (178 x 144) 0x0a 0x00 0x60 VGA (640 x 480) 0x04, 0x07 0x00 0x60 0x0b YCbCr422 QVGA (320 x 240) 0x06 0x00 0x60 Bayer QQVGA (160 x 120) 0x05 0x00 0x60 CIF (356 x 288) 0x0c, 0x0f 0x00 0x60 QCIF (178 x 144) 0x0e 0x00 0x60 VGA (640 x 480) 0x00, 0x03 0x00 0x10 Sub-sampling RGB565 QVGA (320 x 240) 0x02 0x00 0x10 ISP Sub- QQVGA (160 x 120) 0x01 0x00 0x10 sampling CIF (356 x 288) 0x08, 0x0b 0x00 0x10 QCIF (178 x 144) 0x0a 0x00 0x10 VGA (640 x 480) 0x04, 0x07 0x00 0x10 RGB565 QVGA (320 x 240) 0x06 0x00 0x10 Bayer QQVGA (160 x 120) 0x05 0x00 0x10 CIF (356 x 288) 0x0c, 0x0f 0x00 0x10 QCIF (178 x 144) 0x0e 0x00 0x10 VGA (640 x 480) 0x04, 0x07 0x80 0x00 QVGA (320 x 240) 0x06 0x80 0x00 QQVGA (160 x 120) 0x05 0x80 0x00 Sub-sampling Bayer Sub- sampling 2005/ 02 / 04 V1.5 - 65 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Output timings for general configurations are described below. Slot named as "X" means that it is has no meaningful value and should be discarded. No Scale Image Mode or Sub-sampling (2x2, 2x6) Mode 1. YCbCr 4:2:2 Mode or Sub-sampling (2x2, 2x6) Mode Register bit configurations Sensor Control A : No Scale Mode or Sub-sampling Mode Output Format : 8bit Output, Y First, U First. 2005/ 02 / 04 V1.5 - 66 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP VCLK HSYNC No Scale Mode Video Clock & Output Data CLK Y[7:0] X X Y0 Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1 Y4 Cb2 Y5 Cr2 Y5 Cb3 Y6 Cr3 C[7:0] X X X X X X X X X X X X X X X X X X 2 X 2 Video Clock & Output Data CLK Y[7:0] X Y0 Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1 2 X 6 Video Clock & Output Data CLK Y[7:0] X Y0 Cb0 Y1 Cr0 2005/ 02 / 04 V1.5 - 67 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP 2. RGB565 Mode or Sub-sampling (2x2, 2x6) Mode Register bit configurations Sensor Control A : No Scale Mode or Sub-sampling Mode Output Format : 8bit Output, Y First, U First and RGB565 enable. VCLK HSYNC No Scale Mode Video Clock & Output Data CLK Y[7:0] X X RG0 GB0 {R0[7:3] G0[7:5]} RG1 GB1 RG2 GB2 RG3 GB3 RG4 GB4 RG5 GB5 RG6 GB6 RG7 GB7 {G0[4:2] B0[7:3]} 2 X 2 Video Clock & Output Data CLK Y[7:0] X RG0 GB0 RG2 GB2 RG4 GB4 RG6 GB6 2 X 6 Video Clock & Output Data CLK Y[7:0] X RG0 GB0 RG4 GB4 2005/ 02 / 04 V1.5 - 68 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP 3. Bayer Mode or Sub-sampling (2x2, 2x6) Mode Register bit configurations Sensor Control A : Bayer Mode( SSSel enable) or Sub-sampling Mode Output Format : 8bit Output, Y First, U First VCLK HSYNC Bayer Mode Video Clock & Output Data Y[7:0] Even Line X B G B G B G B G B G B Y[7:0] Odd Line X G R G R G R G R G R G 2 X 2 Video Clock & Output Data HSYNC Y[7:0] Even Line X B G B G B G B G B G B Y[7:0] Odd Line X G R G R G R G R G R G 2 X 6 Video Clock & Output Data 6 Line Data HSYNC // Y[7:0] Even Line X B G B G B G B G B G B Y[7:0] Odd Line X G R G R G R G R G R G 2005/ 02 / 04 V1.5 - 69 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP CIF or QCIF Mode 1. YCbCr 4:2:2 with 8bit Output Register bit configurations Sensor Control A : No Scale Mode and CIF Mode Output Format : 8bit Output, Y First, U First CIF HSYNC VCLK Y[7:0] Y0 Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1 // Y0 Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1 // Y12 Cb6 Y13 Cr6 QCIF HSYNC VCLK Y[7:0] Y12 Cb6 Y13 Cr6 2. RGB565 with 8bit Output Register bit configurations Sensor Control A : No Scale Mode or CIF Mode Output Format : 8bit Output, Y First, U First and RGB565 enable. 2005/ 02 / 04 V1.5 - 70 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP CIF HSYNC VCLK Y[7:0] RG0 GB0 RG1 GB1 RG2 GB2 RG3 GB3 // RG0 GB0 RG1 GB1 RG2 GB2 RG3 GB3 // RG12 GB12 RG13 GB13 QCIF HSYNC VCLK Y[7:0] RG6 GB6 RG7 GB7 2005/ 02 / 04 V1.5 - 71 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP I2C Chip Interface Register Write Sequences One Byte Write S 22H A 01H A 03H A P *1 *2 *3 *4 *5 *6 *7 *8 Set "Sensor Control A" register into Window mode *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor *4. Drive: 01H [sub-address] *5. Read: acknowledge from sensor *6. Drive: 03H [Video Mode : CIF *7. Read: acknowledge from sensor *8. Drive: I2C stop condition Multiple Byte Write using Auto Address Increment S *1 22H A 6aH A 51H A 61H A P *2 *3 *4 *5 *6 *7 *8 *9 *10 Set "AE Integration Step High/Low" register as 5161H with auto address increment *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor *4. Drive: 6aH [sub-address] *5. Read: acknowledge from sensor *6. Drive: 51H [AE Integration Step High] *7. Read: acknowledge from sensor *8. Drive: 61H [AE Integration Step Low] *9. Read: acknowledge from sensor *10. Drive: I2C stop condition 2005/ 02 / 04 V1.5 - 72 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Register Read Sequence S *1 22H A 50H A S 23H A Data of 50H *2 *3 *4 *5 *6 *7 *8 *9 A P *10 *11 Read "Reset Level Control" register from HV7131RP *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit(be careful. R/W=0)] *3. Read: acknowledge from sensor *4. Drive: 50H [sub-address] *5. Read: acknowledge from sensor *6. Drive: I2C start condition *7. Drive: 23H(001_0001 + 1) [device address + R/W bit(be careful. R/W=1)] *8. Read: acknowledge from sensor *9. Read: Read "Reset Level Control Value" from sensor *10. Drive: acknowledge to sensor. If there is more data bytes to read, SDA should be driven to low and data read states(*9, *10) is repeated. Otherwise SDA should be driven to high to prepare for the read transaction end. *11. Drive: I2C stop condition AC/DC Characteristics Absolute Maximum Ratings Symbol Parameter Units Min. Max. Vdpp Digital supply voltage Volts -0.3 7.0 Vapp Analog supply voltage Volts -0.3 7.0 Vipp Input signal voltage Volts -0.3 7.0 Top Operating Temperature C -10 50 Tst Storage Temperature C -30 80 Caution: Stresses exceeding the absolute maximum ratings may induce failure. 2005/ 02 / 04 V1.5 - 73 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP DC Operating Conditions Symbol Parameter Units Min. Max. Vdd Internal operation supply voltage Volt 2.6 3.0 Vih Input voltage logic "1" Volt 2.0 3.0 6.5 Vil Input voltage logic "0" Volt 0 0.8 6.5 Voh Output voltage logic "1" Volt 2.15 Vol Output voltage logic "0" Volt 0.4 60 Ioh Output High Current mA -4 60 Iol Output Low Current mA 4 60 Ta Ambient operating temperature Celsius -10 Load[pF] 60 Notes at Ioh = -1mA 50 AC Operating Conditions Symbol Parameter Max Operation Frequency Units Notes MCLK Main clock frequency 25 MHz 1,2 SCK I2C clock frequency 400 KHz 3 1. MCLK may be divided by internal clock division logic for easy integration with high speed video codec system. 2. Frame Rate : 30 frames/sec at 25Mhz, HBLANK = 208, VBLANK = 8 3. SCK is driven by host processor. For the detail serial bus timing, refer to I2C chip interface section Output AC Characteristics All output timing delays are measured with output load 60[pF]. Output delay includes the internal clock path delay and output driving delay that changes in respect to the output load, the operating environment, and a board design. Due to the variable valid time delay of the output, video output signals Y[7:0], C[7:0], HSYNC, and VSYNC may be latched in the negative edge of VCLK for the stable data transfer between the image sensor and video codec. 2005/ 02 / 04 V1.5 - 74 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP V C LK HSY NC Y /C [7:0] X D ata 0 D ata 1 D a ta 2 D a ta 3 4 ns ~ 5n s 2005/ 02 / 04 V1.5 - 75 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP I2C Bus Timing stop start start stop SDA tr tbuf thd;sta tf tlow SCK thd;sta thd;dat thigh tsu;d at tsu;sta tsu;sto Parameter Symbol Min. Max. Unit SCK clock frequency f sck 0 400 KHz tbuf 1.2 - us Hold time for a START thd;sta 1.0 - us LOW period of SCK tlow 1.2 - us HIGH period of SCK thigh 1.0 - us Setup time for START tsu;sta 1.2 - us Data hold time thd;dat 100 - ns Data setup time tsu;dat 250 - ns Rise time of both SDA and SCK tr - 250 ns tf - 300 ns Setup time for STOP tsu;sto 1.2 - us Capacitive load of SCK/SDA Cb - - pf Time that I2C bus must be free before a new transmission can start Fall time of both SDA and SCK 2005/ 02 / 04 V1.5 - 76 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP Electro-Optical Characteristics Parameter Units Min. Typical Max. Note Sensitivity mV / luxsec 2200 Green Pixel Dark Signal mV 12 1/10" , 60 Output Saturation Signal mV 780 - Color temperature of light source: 3200K / IR cut-off filter (CM-500S, 1mm thickness) is used. Soldering Infrared(IR) / Convection solder reflow condition Parameter Peak Temperature Range Note: Units Min. Typical Max. Note Celsius - 230 240 1) 1) Time within 5 Celsius of actual peak temperature, 10sec 2005/ 02 / 04 V1.5 - 77 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP CLCC Package Specification 2005/ 02 / 04 V1.5 - 78 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com HV7131RP MagnaChip Semiconductor Ltd. * Contact Point * CIS Marketing Team 15Floor, MagnaChip Youngdong Bldg. 891 Daechi-Dong Kangnam-Gu Seoul 135-738 Republic of Korea Tel: 82-2-3459-3374 Fax: 82-2-3459-5580 E-mail : jungjin.jeong@MagnaChip.com 2005/ 02 / 04 V1.5 - 79 2005 MagnaChip Semiconductor Ltd. PDF created with FinePrint pdfFactory Pro trial version www.pdffactory.com