Am29LV400BB90WAD - Advanced Micro Devices

July 2003

The follo wing document specifies Spansi on memory p roducts t hat are now of fered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the re sult of normal datasheet improvement and are noted in the

document revis ion summary, where suppo rted. Future routine revisions will occur whe n appropriate,

and changes will be noted in a revision su mmary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support e xisting part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Or dering Part Number s lis ted in this docu ment.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory soluti ons.

Am29LV400B

Data Sheet

Publication Number 21523 Revision DAmendment +2 Issue Date October 30, 2003

THIS PAGE LEFT INTENTIONALLY BLANK.

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 21523 Rev: DAmendment/+2

Issue Date: October 30, 2003

Am29LV400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read and

write operations for compatibility with high

performance 3.3 volt microprocessors

■Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm Am29LV400 device

■High performance

— Full voltage range: access times as fast as 70 ns

— Regulated voltage range: access times as fast as

55 ns

■Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 7 mA read current

— 15 mA program/erase current

■Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

seven 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

seven 32 Kword sectors (word mode)

— Supports full chip erase

— Sector Protection features:

— A hardware method of locking a sector to prevent

any program or erase operations within that sector

— Sectors can be locked in-system or via

programming equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■Unlock Bypass Program Command

— Reduces overall programming time when issuing

multiple program command sequences

■Top or bottom boot block configurations

available

■Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■Minimum 1,000,000 write cycle guarantee per sector

■20-year data retention at 125°C

— Reliable operation for the life of the system

■Package option

— 48-ball FBGA

— 48-pin TSOP

— 44-pin SO

— Lead (Pb) - Free Packaging Available

■Compatibility with JEDEC standards

— Pinout and software compatible with

single-power supply Flash

— Superior inadvertent write protection

■Data# Polling and toggle bits

— Provides a software method of detecting program

or erase operation completion

■Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

■Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

10/30/03 Am29LV400B 2

GENERAL DESCRIPTION

The Am29LV400B is a 4 Mbit, 3.0 volt-only Flash

memory organized as 524,288 bytes or 262,144 words.

The device is offered in 48-ball FBGA, 44-pin SO, and

48-pin TSOP packages. The word-wide data (x16)

appears on DQ15–DQ0; the byte-wide (x8) data

appears on DQ7–DQ0. This device is designed to be

programmed in-system using only a single 3.0 volt VCC

supply. No VPP is required for write or erase operations.

The device can also be programmed in standard

EPROM programmers.

This device is manufactured using AMD’s 0.32 µm

process technology, and offers all the features and ben-

efits of the Am29LV400, which was manufactured using

0.5 µm process technology. In addition, the

Am29LV400B features unlock bypass programming

and in-system sector protection/unprotection.

The standard device offers access times of 55, 70, 90

and 120 ns, allowing high speed microprocessors to

operate without wait states. To eliminate bus contention

the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using stan-

dard microprocessor write timings. Register contents

serve as input to an internal state-machine that con-

trols the erase and programming circuitry. Write cycles

also internally latch addresses and data needed for the

programming and erase operations. Reading data out

of the device is similar to reading from other Flash or

EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

Device erasure occurs by executing the erase

command sequence. This initiates the Embedded

Erase algorithm—an internal algorithm that automatically

pre-programs the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data

or accept another command.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write operations

during power transitions. The hardware sector pro-

tection feature disables both program and erase oper-

ations in any combination of the sectors of memory.

This can be achieved in-system or via programming

equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the standby

mode. Power consumption is greatly reduced in both

these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effectiveness.

The device electrically erases all bits within a sector simul-

taneously via Fowler-Nordheim tunneling. The data is

programmed using hot electron injection.

3 Am29LV400B 10/30/03
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .   4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . .   5
Special Handling Instructions for Fine Pitch 
Ball Grid Array (FBGA) ...................................................................7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .   8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .   9
Table 1. Am29LV400B Device Bus Operations  ......................................9
Word/Byte Configuration  ................................................................ 9
Requirements for Reading Array Data  ...........................................9
Writing Commands/Command Sequences  ..................................10
Program and Erase Operation Status  ..........................................10
Standby Mode  ..............................................................................10
Automatic Sleep Mode  .................................................................10
RESET#: Hardware Reset Pin  .....................................................10
Output Disable Mode  ...................................................................11
Table 2. Am29LV400BT Top Boot Sector Address Table .....................11
Table 3. Am29LV400BB Bottom Boot Sector Address Table  ...............11
Autoselect Mode  .......................................................................... 12
Table 4. Am29LV400B Autoselect Codes (High Voltage Method)  ........12
Sector Protection/Unprotection  .................................................... 12
Figure 1. In-System Sector Protect/Unprotect Algorithms .................... 13
Temporary Sector Unprotect ........................................................ 14
Figure 2. Temporary Sector Unprotect Operation................................. 14
Hardware Data Protection ............................................................ 14
Low VCC Write Inhibit .................................................................... 14
Write Pulse “Glitch” Protection  .....................................................14
Logical Inhibit  ...............................................................................14
Power-Up Write Inhibit  .................................................................14
Command Definitions . . . . . . . . . . . . . . . . . . . . .   15
Reading Array Data ......................................................................15
Reset Command  .......................................................................... 15
Autoselect Command Sequence ..................................................15
Word/Byte Program Command Sequence ...................................15
Unlock Bypass Command Sequence ...........................................16
Figure 3. Program Operation ................................................................ 16
Chip Erase Command Sequence .................................................16
Sector Erase Command Sequence ..............................................17
Erase Suspend/Erase Resume Commands  ................................17
Figure 4. Erase Operation..................................................................... 18
Table 5. Am29LV400B Command Definitions .......................................19
Write Operation Status  . . . . . . . . . . . . . . . . . . . .   20
DQ7: Data# Polling  ...................................................................... 20
Figure 5. Data# Polling Algorithm ......................................................... 20
RY/BY#: Ready/Busy#  .................................................................21
DQ6: Toggle Bit I ..........................................................................21
DQ2: Toggle Bit II .........................................................................21
Reading Toggle Bits DQ6/DQ2  ....................................................21
DQ5: Exceeded Timing Limits ...................................................... 22
DQ3: Sector Erase Timer ............................................................. 22
Figure 6. Toggle Bit Algorithm ..............................................................  22
Table 6. Write Operation Status  ........................................................... 23
Absolute Maximum Ratings. . . . . . . . . . . . . . . . .  24
Figure 7. Maximum Negative Overshoot Waveform .............................  24
Figure 8. Maximum Positive Overshoot Waveform ..............................  24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .  25
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic 
Sleep Currents).....................................................................................  26
Figure 10. Typical ICC1 vs. Frequency...................................................  26
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .  27
Figure 11. Test Setup ...........................................................................  27
Table 7. Test Specifications .................................................................. 27
Figure 12. Input Waveforms and Measurement Levels ........................  27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .  28
Read Operations  .......................................................................... 28
Figure 13. Read Operations Timings....................................................  28
Hardware Reset (RESET#) .......................................................... 29
Figure 14. RESET# Timings .................................................................  29
Word/Byte Configuration (BYTE#)   .............................................30
Figure 15. BYTE# Timings for Read Operations ..................................  30
Figure 16. BYTE# Timings for Write Operations ..................................  30
Erase/Program Operations  .......................................................... 31
Figure 17. Program Operation Timings ................................................  32
Figure 18. Chip/Sector Erase Operation Timings .................................  33
Figure 19. Data# Polling Timings (During Embedded Algorithms) .......  34
Figure 20. Toggle Bit Timings (During Embedded Algorithms) ............  34
Figure 21. DQ2 vs. DQ6 .......................................................................  35
Figure 22. Temporary Sector Unprotect Timing Diagram.....................  35
Figure 23. Sector Protect/Unprotect Timing Diagram ...........................  36
Figure 24. Alternate CE# Controlled Write Operation Timings .............  38
Erase And Programming Performance. . . . . . . .  39
BGA Ball Capacitance  . . . . . . . . . . . . . . . . . . . . .  40
TS 048—48-Pin Standard TSOP  ................................................. 41
TSR048—48-Pin Reverse TSOP .................................................42
FBA048—48-ball Fine-Pitch Ball Grid Array (FBGA) 
6 x 8 mm package ........................................................................ 43
SO 044—44-Pin Small Outline Package  .....................................44
Revision A (January 1998) ...........................................................45
Revision B (July 1998)  .................................................................45
Revision B+1 (August 1998)  ........................................................ 45
Revision C (January 1999) ...........................................................45
Revision C+1 (July 2, 1999)  ......................................................... 45
Revision D (January 3, 1999) .......................................................45
Revision D+1 (November 8, 2000) ...............................................45
Revision D+2 (October 30, 2003)  ................................................ 45

10/30/03 Am29LV400B 4

PRODUCT SELECTOR GUIDE

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

Family Part Number Am29LV400B

Speed Options

Regulated Voltage Range: 3.0 – 3.6 V 55R

Full Voltage Range: 2.7 – 3.6 V 70 90 120

Max access time, ns (tACC) 55 70 90 120

Max CE# access time, ns (tCE) 55 70 90 120

Max OE# access time, ns (tOE)30303550

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

BYTE#

CE#

OE#

STB

DQ0

–

DQ15 (A-1)

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A17

5 Am29LV400B 10/30/03

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A17

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

A15

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A17

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

Reverse TSOP

Standard TSOP

10/30/03 Am29LV400B 6

CONNECTION DIAGRAMS

RY/BY#

A17

CE#

OE#

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

RESET#

WE#

A10

A11

A12

A13

A14

A15

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

A1 B1 C1 D1 E1 F1 G1 H1

A2 B2 C2 D2 E2 F2 G2 H2

A3 B3 C3 D3 E3 F3 G3 H3

A4 B4 C4 D4 E4 F4 G4 H4

A5 B5 C5 D5 E5 F5 G5 H5

A6 B6 C6 D6 E6 F6 G6 H6

DQ15/A-1 VSS

BYTE#A16A15A14A12A13

DQ13 DQ6DQ14DQ7A11A10A8A9

VCC DQ4DQ12DQ5NCNCRESET#WE#

DQ11 DQ3DQ10DQ2NCNCNCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE# VSS

CE#A0A1A2A4A3

FBGA

Top View, Balls Facing Down

7 Am29LV400B 10/30/03

Special Handling Instructions for Fine

Pitch Ball Grid Array (FBGA)

Special handling is required for Flash Memory products

in FBGA packages.

The package and/or data integrity may be compro-

mised if the package body is exposed to temperatures

above 150°C for prolonged periods of time.

PIN CONFIGURATION

A0–A17 =18 addresses

DQ0–DQ14 =15 data inputs/outputs

DQ15/A-1 =DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

BYTE# =Selects 8-bit or 16-bit mode

CE# =Chip enable

OE# = Output enable

WE# =Write enable

RESET# =Hardware reset pin, active low

RY/BY# = Ready/Busy# output

VCC =3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

VSS =Device ground

NC =Pin not connected internally

LOGIC SYMBOL

16 or 8

DQ0–DQ15

(A-1)

A0–A17

CE#

OE#

WE#

RESET#

BYTE# RY/BY#

10/30/03 Am29LV400B 8

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

Am29LV400B T -55R E C

TEMPERATURE RANGE

D = Commercial (0°C to +70°C); Lead (Pb)-Free Package

C = Commercial (0°C to +70°C)

F = Industrial (-40°C to 85°C); Lead (Pb)-Free Package

I = Industrial (–40°C to +85°C)

K = Extended (–55°C to +125°C); Lead (Pb)-Free Package

E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)

S = 44-Pin Small Outline Package (SO 044)

WA=48-Ball Fine Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 8 mm package (FBA048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top sector

B = Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29LV400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP and SO Packages

AM29LV400BT55R,

AM29LV400BB55R

ED, EF, EK, EC, EI, FC, FD, FF, FK,

FI, SC, SI, SD, SF, SK

AM29LV400BT70,

AM29LV400BB70 EC, EI, EE,

FC, FI, FE,

SC, SI, SE,

ED, EF, EK, FD, FF, FK

SD, SF, SK

AM29LV400BT90,

AM29LV400BB90

AM29LV400BT120,

AM29LV400BB120

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29LV400BT55R,

AM29LV400BB55R

WAC,WAI,

WAD,WAF,

WAK

L400BT55R,

L400BB55R

C, I, D,

F, K

AM29LV400BT70,

AM29LV400BB70

WAC, WAI,

WAE,WAD,

WAF,WAK

L400BT70V,

L400BB70V

C, I, E,

D, F, K

AM29LV400BT90,

AM29LV400BB90

L400BT90V,

L400BB90V

AM29LV400BT120,

AM29LV400BB120

L400BT12V,

L400BB12V

9 Am29LV400B 10/30/03

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state

machine. The state machine outputs dictate the func-

tion of the device. Table 1 lists the device bus opera-

tions, the inputs and control levels they require, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29LV400B Device Bus Operations

Legend:

L = Logic Low = V

, H = Logic High = V

, V

= 12.0

0.5 V, X = Don’t Care, A

= Addresses In, D

= Data In, D

OUT

= Data Out

Notes:

1. Addresses are A17:A0 in word mode (BYTE# = V

A17:A-1 in byte mode (BYTE# = V

2. The sector protect and sector unprotect functions may

also be implemented via programming equipment. See

the “Sector Protection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output

control and gates array data to the output pins. WE#

should remain at VIH. The BYTE# pin determines

whether the device outputs array data in words or

bytes.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert

valid addresses on the device address inputs produce

valid data on the device data outputs. The device

remains enabled for read access until the command

Address access time (tACC) is the delay from stable

addresses to valid output data. The chip enable access

time (tCE) is the delay from stable addresses and stable

CE# to valid data at the output pins. The output enable

Operation CE# OE#

# RESET#

Addresses

(Note 1)

DQ0–

DQ7

DQ8–DQ15

BYTE#

= VIH

BYTE#

= VIL

Read L L H H AIN DOUT DOUT DQ8–DQ14 =

High-Z, DQ15 = A-1

Write L H L H AIN DIN DIN

Standby VCC ±

0.3 V XXVCC ±

0.3 V X High-Z High-Z High-Z

Output Disable L H H H X High-Z High-Z High-Z

Reset X X X L X High-Z High-Z High-Z

Sector Protect (Note 2) L H L VID

Sector Address, A6 = L,

A1 = H, A0 = L DIN XX

Sector Unprotect (Note 2) L H L VID

Sector Address, A6 = H,

A1 = H, A0 = L DIN XX

Temporary Sector

Unprotect XXX V

ID AIN DIN DIN High-Z

10/30/03 Am29LV400B 10
access time (tOE) is the delay from the falling edge of
OE# to valid data at the output pins (assuming the
addresses have been stable for at least tACC–tOE time). 
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. ICC1 in the
DC Characteristics table represents the active current
specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information. 
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command
sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
section has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input. 
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification. 
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC4 in the DC
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The

11 Am29LV400B 10/30/03

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during Embedded Algo-

rithms). The system can read data tRH after the

RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET#

parameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

Table 2. Am29LV400BT Top Boot Sector Address Table

Table 3. Am29LV400BB Bottom Boot Sector Address Table

Note for Tables 2 and 3: Address range is A17:A-1 in byte

mode and A17:A0 in word mode. See “Word/Byte

Configuration” section.

Sector A17 A16 A15 A14 A13 A12

Sector Size

(Kbytes/

Kwords)

Address Range (in hexadecimal)

(x8)

Address Range

(x16)

Address Range

SA0 0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh

SA1 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh

SA2 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh

SA3 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh

SA4 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh

SA5 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh

SA6 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh

SA71110XX 32/16 70000h–77FFFh38000h–3BFFFh

SA8111100 8/4 78000h–79FFFh3C000h–3CFFFh

SA9111101 8/4 7A000h–7BFFFh3D000h–3DFFFh

SA1011111X 16/8 7C000h–7FFFFh3E000h–3FFFFh

Sector A17 A16 A15 A14 A13 A12

Sector Size

(Kbytes/

Kwords)

Address Range (in hexadecimal)

(x8)

Address Range

(x16)

Address Range

SA000000X 16/8 00000h–03FFFh00000h–01FFFh

SA1000010 8/4 04000h–05FFFh02000h–02FFFh

SA2000011 8/4 06000h–07FFFh03000h–03FFFh

SA30001XX 32/16 08000h–0FFFFh04000h–07FFFh

SA4 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh

SA5 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh

SA6 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh

SA7 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh

SA8 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh

SA9 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh

SA10 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh

10/30/03 Am29LV400B 12
Autoselect Mode
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 4. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t care.
When all necessary bits have been set as required, the
programming equipment may then read the corre-
sponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
Table 4. Am29LV400B Autoselect Codes (High Voltage Method)
L = Logic Low = V
IL
, H = Logic High = V
IH
,  SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods. 
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 1 shows the algo-
rithms and Figure 23 shows the timing diagram. This
method uses standard microprocessor bus cycle
timing. For sector unprotect, all unprotected sectors
must first be protected prior to the first sector unprotect
write cycle. 
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD flash devices. Pub-
lication number 20873 contains further details; contact
an AMD representative to request a copy. 
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Description Mode CE# OE# WE#
A17
to 
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X VID XLXLL X 01h
Device ID: 
Am29LV400B
(Top Boot Block)
Word L L H
XXV
ID XLXLH
22h B9h
Byte L L H X B9h
Device ID: 
Am29LV400B
(Bottom Boot Block)
Word L L H
XXV
ID XLXLH
22h BAh
Byte L L H X BAh
Sector Protection Verification L L H SA X VID XLXHL
X01h 
(protected)
X00h 
(unprotected)

13 Am29LV400B 10/30/03

Figure 1. In-System Sector Protect/Unprotect Algorithms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm

Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

10/30/03 Am29LV400B 14

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the

RESET# pin to VID. During this mode, formerly pro-

tected sectors can be programmed or erased by

selecting the sector addresses. Once VID is removed

from the RESET# pin, all the previously protected

sectors are protected again. Figure 2 shows the algo-

rithm, and Figure 22 shows the timing diagrams, for this

feature.

Figure 2. Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 5 for

command definitions). In addition, the following hard-

ware data protection measures prevent accidental

erasure or programming, which might otherwise be

caused by spurious system level signals during VCC

power-up and power-down transitions, or from system

noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept

any write cycles. This protects data during VCC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until VCC

is greater than VLKO. The system must provide the

proper signals to the control pins to prevent uninten-

tional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

15 Am29LV400B 10/30/03
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 5 defines the valid register command
sequences. Writing incorrect address and data
values or writing them in the improper sequence may
place the device in an unknown state. A reset
command is then required to return the device to
reading array data. 
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system 
must
 issue the reset command to
re-enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command. 
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is com-
plete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command 
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies during Erase Sus-
pend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements. This
method is an alternative to that shown in Table 4, which
is intended for PROM programmers and requires VID
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A read cycle at address XX00h retrieves the
manufacturer code. A read cycle at address XX01h in
word mode (or 02h in byte mode) returns the device
code. A read cycle containing a sector address (SA)
and the address 02h in word mode (or 04h in byte
mode) returns 01h if that sector is protected, or 00h if it
is unprotected. Refer to Tables 2 and 3 for valid sector
addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up command.
The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The
system is 
not
 required to provide further controls or tim-
ings. The device automatically generates the program
pulses and verifies the programmed cell margin. Table
5 shows the address and data requirements for the
byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can

10/30/03 Am29LV400B 16
determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits. 
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes or words to the device faster than using
the standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 5 shows the require-
ments for the command sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
program address and the data 90h. The second cycle
need only contain the data 00h. The device then
returns to reading array data.
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 17 for
timing diagrams.
Note: See Table 5 for program command sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does 
not
 require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation imme-
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
START
Write Program
Command Sequence
Data Poll 
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
 Completed
Increment Address
Embedded
Program
algorithm
 in progress

17 Am29LV400B 10/30/03
device has returned to reading array data, to ensure
data integrity.
The system can determine the status of the erase oper-
ation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. 
Figure 4 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 18 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements for the sector erase command sequence.
The device does 
not
 require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations. 
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. (Refer to “Write Operation Status” for infor-
mation on these status bits.)
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 18 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is erase-sus-
pended. See “Write Operation Status” for information
on these status bits.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more informa-
tion.

10/30/03 Am29LV400B 18

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the

device has resumed erasing.

Notes:

1. See Table 5 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 4. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

19 Am29LV400B 10/30/03
Command Definitions
Table 5. Am29LV400B Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read. 
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. 
Addresses latch on the falling edge of the WE# or CE# pulse, 
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the 
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or 
erased. Address bits A17–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles 
are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and 
command cycles.
5. Address bits A17–A11 are don’t cares for unlock and 
command cycles, except when SA or PA required.
6. No unlock or command cycles required when reading array 
data.
7. The Reset command is required to return to reading array 
data when device is in the autoselect mode, or if DQ5 goes 
high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a 
read cycle.
9. The data is 00h for an unprotected sector and 01h for a 
protected sector. See “Autoselect Command Sequence” for 
more information.
10. The Unlock Bypass command is required prior to the Unlock 
Bypass Program command.
11. The Unlock Bypass Reset command is required to return to 
reading array data when the device is in the unlock bypass 
mode.
12. The system may read and program in non-erasing sectors, or 
enter the autoselect mode, when in the Erase Suspend 
mode. The Erase Suspend command is valid only during a 
sector erase operation.
13. The Erase Resume command is valid only during the Erase 
Suspend mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third  Fourth Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Manufacturer ID Word 4555 AA 2AA 55 555 90 X00 01
Byte AAA 555 AAA
Device ID, 
Top Boot Block 
Word 4555 AA 2AA 55 555 90 X01 22B9
Byte AAA 555 AAA X02 B9
Device ID,
Bottom Boot Block
Word 4555 AA 2AA 55 555 90 X01 22BA
Byte AAA 555 AAA X02 BA
Sector Protect Verify 
(Note 9)
Word
4
555
AA
2AA
55
555
90
(SA)
X02
XX00
XX01
Byte AAA 555 AAA (SA)
X04
00
01
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 10) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 11) 2 XXX 90 XXX 00
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 12) 1 XXX B0
Erase Resume (Note 13) 1 XXX 30
Autoselect (Note 8)

10/30/03 Am29LV400B 20

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a write operation: DQ2, DQ3, DQ5, DQ6,

DQ7, and RY/BY#. Table 6 and the following subsec-

tions describe the functions of these bits. DQ7,

RY/BY#, and DQ6 each offer a method for determining

whether a program or erase operation is complete or in

progress. These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in progress

or completed, or whether the device is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the

final WE# pulse in the program or erase command

sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status

information on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 100 µs, then

the device returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores

the selected sectors that are protected.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ7–DQ0 on the

following

read cycles. This is

because DQ7 may change asynchronously with

DQ0–DQ6 while Output Enable (OE#) is asserted low.

Figure 19, Data# Polling Timings (During Embedded

Algorithms), in the “AC Characteristics” section illus-

trates this.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

21 Am29LV400B 10/30/03
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel
with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. Figures 14, 17
and 18 shows RY/BY# for reset, program, and erase
operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. The system may use either OE#
or CE# to control the read cycles. When the operation
is complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles
for approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are pro-
tected. 
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the
system must also use DQ2 to determine which sectors
are erasing or erase-suspended. Alternatively, the
system can use DQ7 (see the subsection on DQ7:
Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
Table 6 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 20 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 21 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6. 
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 20 shows the toggle bit timing diagram. Figure
21 shows the differences between DQ2 and DQ6 in
graphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the

10/30/03 Am29LV400B 22

program or erase operation. If it is still toggling, the

device did not completed the operation successfully,

and the system must write the reset command to return

to reading array data.

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to

determine the status of the operation (top of Figure 6).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire

time-out also applies after each additional sector erase

command. When the time-out is complete, DQ3

switches from “0” to “1.” If the time between additional

sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also the “Sector Erase Command

Sequence” section.

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure the device has

accepted the command sequence, and then read DQ3.

If DQ3 is “1”, the internally controlled erase cycle has

begun; all further commands (other than Erase Sus-

pend) are ignored until the erase operation is complete.

If DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been

accepted. Table 6 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle?

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1” . See text.

Figure 6. Toggle Bit Algorithm

(Notes

1, 2)

(Note 1)

23 Am29LV400B 10/30/03

Table 6. Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

Operation

DQ7

(Note 2) DQ6

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

Standard

Mode

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Reading within Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Reading within Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

10/30/03 Am29LV400B 24

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1). . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–0.5 V to +12.5 V

All other pins (Note 1) . . . . . .–0.5 V to VCC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may overshoot V

–2.0 V for periods of up to 20 ns. See Figure 7. Maximum

DC voltage on input or I/O pins is V

+0.5 V. During

voltage transitions, input or I/O pins may overshoot to V

+2.0 V for periods up to 20 ns. See Figure 8.

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

RESET# may overshoot V

to –2.0 V for periods of up to

20 ns. See Figure 7. Maximum DC input voltage on pin A9

is +12.5 V which may overshoot to 14.0 V for periods up

to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . . –55°C to +125°C

VCC Supply Voltages

VCC for regulated voltage range . . . . .+3.0 V to +3.6 V

VCC for full voltage range . . . . . . . . . .+2.7 V to +3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

Figure 7. Maximum Negative

Overshoot Waveform

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

Figure 8. Maximum Positive

Overshoot Waveform

25 Am29LV400B 10/30/03

DC CHARACTERISTICS

CMOS Compatible

Notes:

1. The I

current listed is typically less than 2 mA/MHz, with

OE# at V

. Typical V

is 3.0 V.

2. Maximum I

specifications are tested with V

= V

CCmax

3. I

active while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t

ACC

+ 30 ns.

5. Not 100% tested.

Parameter Description Test Conditions Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC,

VCC = VCC max

±1.0 µA

ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA

ILO Output Leakage Current VOUT = VSS to VCC,

VCC = VCC max

±1.0 µA

ILR RESET Input Load Current VCC = VCC max, RESET# = 12.5 V 35 µA

ICC1

VCC Active Read Current

(Note 1)

CE# = VIL, OE# = VIH,

Byte Mode

5 MHz 7 12

1 MHz 2 4

CE# = VIL, OE# = VIH,

Word Mode

5 MHz 7 12

1 MHz 2 4

ICC2

VCC Active Write Current

(Notes 2, 3, 5) CE# = VIL, OE# = VIH 15 30 mA

ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC±0.3 V 0.2 5 µA

ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 5 µA

ICC5

Automatic Sleep Mode

(Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 x VCC VCC + 0.3 V

VID

Voltage for Autoselect and

Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V

VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V

VOH1 Output High Voltage

IOH = –2.0 mA, VCC = VCC min 0.85 VCC V

VOH2 IOH = –100 µA, VCC = VCC min V

CC–0.4

VLKO

Low VCC Lock-Out Voltage

(Note 4) 2.3 2.5 V

10/30/03 Am29LV400B 26

DC CHARACTERISTICS

Zero Power Flash

0 500 1000 1500 2000 2500 3000 3500 4000

Supply Current in mA

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

12345

Frequency in MHz

Supply Current in mA

Note: T = 25

Figure 10. Typical ICC1 vs. Frequency

2.7 V

3.6 V

27 Am29LV400B 10/30/03

TEST CONDITIONS

Table 7. Test Specifications

Key To Switching Waveforms

2.7 kΩ

CL6.2 kΩ

3.3

Device

Under

Te s t

Figure 11. Test Setup

Note:Diodes are IN3064 or equivalent

Test Condition

55R,

70,

90,

120 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig capacitance) 30 100 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–3.0 V

Input timing measurement

reference levels 1.5 V

Output timing measurement

reference levels 1.5 V

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V 1.5 V OutputMeasurement LevelInput

Figure 12. Input Waveforms and Measurement Levels

10/30/03 Am29LV400B 28

AC CHARACTERISTICS

Read Operations

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test specifications.

Parameter

Description

Speed Options

JEDEC Std Test Setup 55R 70 90 120 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 55 70 90 120 ns

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL

Max 55 70 90 120 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 ns

tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 ns

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns

tOEH

Output Enable

Hold Time (Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

tAXQX tOH

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 1) Min 0 ns

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output Valid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

0 V

RY/BY#

RESET#

tDF

tOH

Figure 13. Read Operations Timings

29 Am29LV400B 10/30/03

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

tREADY

RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note) Max 20 µs

tREADY

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH RESET# High Time Before Read (See Note) Min 50 ns

tRPD RESET# Low to Standby Mode Min 20 µs

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

Figure 14. RESET# Timings

10/30/03 Am29LV400B 30

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter Speed Options

JEDEC Std Description 55R 70 90 120 Unit

tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 16 ns

tFHQV BYTE# Switching High to Output Active Min 55 70 90 120 ns

DQ15

Output

Data Output

(DQ0–DQ7)

CE#

OE#

BYTE#

tELFL

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFLQZ

BYTE#

Switching

from word

to byte

mode

DQ15

Output

Data Output

(DQ0–DQ7)

BYTE#

tELFH

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFHQV

BYTE#

Switching

from byte

to word

mode

Figure 15. BYTE# Timings for Read Operations

Note: Refer to the Erase/Program Operations table for t

and t

specifications.

Figure 16. BYTE# Timings for Write Operations

CE#

WE#

BYTE#

The falling edge of the last WE# signal

tHOLD (tAH)

tSET

(tAS)

31 Am29LV400B 10/30/03

AC CHARACTERISTICS

Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter Speed Options

JEDEC Std Description 55R 70 90 120 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns

tAVWL tAS Address Setup Time Min 0 ns

tWLAX tAH Address Hold Time Min 45 45 45 50 ns

tDVWH tDS Data Setup Time Min 35 35 45 50 ns

tWHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHWL tGHWL

Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 35 35 35 50 ns

tWHWL tWPH Write Pulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation (Note 2)

Byte Typ 9

µs

Word Typ 11

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

tVCS VCC Setup Time (Note 1) Min 50 µs

tRB Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

10/30/03 Am29LV400B 32

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

WHWH1

WPH

VCS

555h PA PA

Read Status Data (last two cycles)

A0h

Status D

OUT

Program Command Sequence (last two cycles)

RY/BY#

tBUSY

Notes:

1. PA = program address, PD = program data, D

OUT

is the

true data at the program address.

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

33 Am29LV400B 10/30/03

AC CHARACTERISTICS

OE#

CE#

Addresses

WE#

Data

2AAh SA

WPH

555h for chip erase

10 for Chip Erase

30h

VCS

55h

Progress Complete

WHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

BUSY

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address

for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

10/30/03 Am29LV400B 34

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

DQ6/DQ2

RY/BY#

BUSY

Addresses VA

OEH

VA VA

ACC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

35 Am29LV400B 10/30/03

AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Note: The system may use OE# and CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 21. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

Parameter

All Speed OptionsJEDEC Std Description Unit

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

tRSP

RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

RESET#

tVIDR

12 V

0 or 3 V

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 3 V

Figure 22. Temporary Sector Unprotect Timing Diagram

10/30/03 Am29LV400B 36

AC CHARACTERISTICS

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

RESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Protect/Unprotect Verify

VID

VIH

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Protect/Unprotect Timing Diagram

37 Am29LV400B 10/30/03

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program

Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter Speed Options

JEDEC Std Description 55R 70 90 120 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 45454550ns

tDVEH tDS Data Setup Time Min 35354550ns

tEHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHEL tGHEL

Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 35 35 35 50 ns

tEHEL tCPH CE# Pulse Width High Min 30 ns

tWHWH1 tWHWH1

Programming Operation

(Note 2)

Byte Typ 9

µs

Word Typ 11

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

10/30/03 Am29LV400B 38

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. PA = program address, PD = program data, DQ7# =

complement of the data written to the device, DOUT = data

written to the device.

2. Figure indicates the last two bus cycles of the command sequence.

3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

39 Am29LV400B 10/30/03

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following

conditions: 25

C, 3.0 V V

, 1,000,000 cycles.

Additionally, programming typicals assume checkerboard

pattern.

2. Under worst case conditions of 90°C, V

= 2.7 V (3.0 V for regulated speed options), 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 5 for further information on command definitions.

6. The device has a minimum erase and program cycle en-

durance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Includes all pins except V

. Test conditions: V

= 3.0 V, one

pin at a time.

TSOP AND SO PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 15 s Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time 11 s

Byte Programming Time 9 300 µs

Excludes system level

overhead (Note 5)

Word Programming Time 11 360 µs

Chip Programming Time

(Note 3)

Byte Mode 4.5 13.5 s

Word Mode 2.9 8.7 s

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(including A9, OE#, and RESET#) –1.0 V 12.5 V

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

10/30/03 Am29LV400B 40

BGA BALL CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 4.2 5.0 pF

COUT Output Capacitance VOUT = 0 5.4 6.5 pF

CIN2 Control Pin Capacitance VIN = 0 3.9 4.7 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C 10 Years

125°C 20 Years

41 Am29LV400B 10/30/03

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP

Dwg rev AA; 10/99

10/30/03 Am29LV400B 42

PHYSICAL DIMENSIONS

TSR048—48-Pin Reverse TSOP

* For reference only. BSC is an ANSI standard for Basic Space Centering.

Dwg rev AA; 10/99

43 Am29LV400B 10/30/03

PHYSICAL DIMENSIONS

FBA048—48-ball Fine-Pitch Ball Grid Array (FBGA)

6x8mm package

Dwg rev AF; 10/99

10/30/03 Am29LV400B 44

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package

Dwg rev AC; 10/99

45 Am29LV400B 10/30/03

REVISION SUMMARY

Revision A (January 1998)

First release.

Revision B (July 1998)

Expanded data sheet from Advanced Information to

Preliminary version.

Distinctive Characteristics

Changed “Manufactured on 0.35 µm process technology”

to “Manufactured on 0.32 µm process technology”.

General Description

Second paragraph:

Changed “This device is manufac-

tured using AMD’s 0.35 µm process technology” to

“This device is manufactured using AMD’s 0.32 µm

process technology”.

Revision B+1 (August 1998)

Global

Added the 55 ns speed option.

Connection Diagrams

Corrected the orientation identifiers on the reverse

TSOP package. Changed the FBGA drawing to top

view, balls facing down.

Revision C (January 1999)

Global

Added -50R speed option.

Ordering Information

Valid Combinations

: Deleted the Am29LV400BT80 and

Am29LV400BB80 entries.

Erase and Programming Performance

Note 2: Changed “(3.0 V for 55R)’ to “(3.0 V for regu-

lated speed options)”.

Revision C+1 (July 2, 1999)

Global

Deleted references to the 50R speed option.

Revision D (January 3, 1999)

AC Characteristics—Figure 17. Program

Operations Timing and Figure 18. Chip/Sector

Erase Operations

Deleted tGHWL and changed OE# waveform to start at

high.

Physical Dimensions

Replaced figures with more detailed illustrations. The

FBGA package OPN designation is now FBA048.

Revision D+1 (November 8, 2000)

Global

Added table of contents. Deleted burn-in option from

Ordering Information section.

Revision D+2 (October 30, 2003)

Package Options

Added Lead (Pb) - Free Packaging Available option.

Special Handling Instructions for Fine Pitch Ball

Grid Array (FBGA)

Removed first sentence of second paragraph.

Standard Products - Temperature Range

Added new D, F, and K temperature ranges, and

included this new information in the valid combinations

for TSOP, SO, and FBGA Packages

DC Characteristics - CMOS Compatible

Added ILR.

AC Characteristics - Read Operations

Modified speed options for tEHQZ and tGHQZ.

AC Characteristics - Word/Byte Configuration

(BYTE#)

Modified speed options for tFLQZ.

BGA Capacitance

Added new table with specified information.

Trademarks

Updated.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

01/03

Printed in USA

One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 408-732-2400

TWX 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com

Advanced Micro Devices reserves the right to make changes in its product without notice

in order to improve design or performance characteristics.The performance

characteristics listed in this document are guaranteed by specific tests, guard banding,

design and other practices common to the industry. For specific testing details, contact

your local AMD sales representative.The company assumes no responsibility for the use of

any circuits described herein.

AMD, the AMD Arrow logo and combination thereof, are trademarks of

Advanced Micro Devices, Inc. Other product names are for informational purposes only

and may be trademarks of their respective companies.

North America

ALABAMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (256)830-9192

ARIZONA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (602)242-4400

CALIFORNIA,

Irvine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .( 949)450-7500

Sunnyvale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(408)732-2400

COLORADO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (303)741-2900

CONNECTICUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(203)264-7800

FLORIDA,

Clearwater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 27)793-0055

Miami (Lakes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (305)820-1113

GEORGIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(770)814-0224

ILLINOIS,

Chicago . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (630)773-4422

MASSACHUSETTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (781)213-6400

MICHIGAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 248)471-6294

MINNESOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (612)745-0005

NEW JERSEY,

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NEW YORK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(716)425-8050

NORTH CAROLINA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(919)840-8080

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PENNSYLVANIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (215)340-1187

SOUTH DAKOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (605)692-5777

TEXAS,

Austin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (512)346-7830

Dallas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 7 2)985-1344

Houston . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (281)376-8084

VIRGINIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (703)736-9568

International

AUSTRALIA, North Ryde . . . . . . . . . . . . . . . . . . . . . . .TEL(61)2-88-777-222

BELGIUM,Antwerpen . . . . . . . . . . . . . . . . . . . . . . . .TEL(32)3-248-43-00

BRAZIL, San Paulo . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(55)11-5501-2105

CHINA,

Beijing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(86)10-6510-2188

Shanghai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(86)21-635-00838

Shenzhen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(86)755-246-1550

FINLAND, Helsinki . . . . . . . . . . . . . . . . . . . . . . TEL(358)881-3117

FRANCE, Paris . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(33)-1-49751010

GERMANY,

Bad Homburg . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(49)-6172-92670

Munich . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(49)-89-450530

HONG KONG, Causeway Bay . . . . . . . . . . . . . . . . . . . TEL(85)2-2956-0388

ITALY, Milan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(39)-02-381961

INDIA, New Delhi . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(91)11-623-8620

JAPAN,

Osaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(81)6-6243-3250

Tokyo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(81)3-3346-7600

KOREA, Seoul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(82)2-3468-2600

RUSSIA, Moscow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(7)-095-795-06-22

SWEDEN, Stockholm . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(46)8-562-540-00

TAIWAN,Taipei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(886)2-8773-1555

UNITED KINGDOM,

Frimley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(44)1276-803100

Haydock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(44)1942-272888

Representatives in U.S. and Canada

ARIZONA,

Tempe - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (480)839-2320

CALIFORNIA,

Calabasas - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (818)878-5800

Irvine - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 49)261-2123

San Diego - Centaur. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (858)278-4950

Santa Clara - Fourfront. . . . . . . . . . . . . . . . . . . . . . . . . . . . (408)350-4800

CANADA,

Burnaby, B.C. - Davetek Marketing. . . . . . . . . . . . . . . . . . . . (604)430-3680

Calgary, Alberta - Davetek Marketing. . . . . . . . . . . . . . . . . (403)283-3577

Kanata, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . . . . (613)592-9540

Mississauga, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . . (905)672-2030

St Laurent, Quebec - J-Squared Tech. . . . . . . . . . . . . . . . (514)747-1211

COLORADO,

Golden - Compass Marketing . . . . . . . . . . . . . . . . . . . . . . (303)277-0456

FLORIDA,

Melbourne - Marathon Technical Sales . . . . . . . . . . . . . . . . (321)728-7706

Ft. Lauderdale - Marathon Technical Sales . . . . . . . . . . . . . . (954)527-4949

Orlando - Marathon Technical Sales . . . . . . . . . . . . . . . . . . (407)872-5775

St. Petersburg - Marathon Technical Sales . . . . . . . . . . . . . . (7 2 7)894-3603

GEORGIA,

Duluth - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . ( 6 78)584-1128

ILLINOIS,

Skokie - Industrial Reps, Inc. . . . . . . . . . . . . . . . . . . . . . . . . (8 4 7)967-8430

INDIANA,

Kokomo - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .( 765)457-7241

IOWA,

Cedar Rapids - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . (319)294-1000

KANSAS,

Lenexa - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . (913)469-1312

MASSACHUSETTS,

Burlington - Synergy Associates . . . . . . . . . . . . . . . . . . . . . (781)238-0870

MICHIGAN,

Brighton - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (810)227-0007

MINNESOTA,

St. Paul - Cahill, Schmitz & Cahill, Inc. . . . . . . . . . . . . . . . . .(651)699-0200

MISSOURI,

St. Louis - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . . (314)997-4558

NEW JERSEY,

Mt. Laurel - SJ Associates . . . . . . . . . . . . . . . . . . . . . . . . . (856)866-1234

NEW YORK,

Buffalo - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . .(716)741-7116

East Syracuse - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . (315)437-8343

Pittsford - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . (716)586-3660

Rockville Centre - SJ Associates . . . . . . . . . . . . . . . . . . . .(516)536-4242

NORTH CAROLINA,

Raleigh - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . . (919)846-5728

OHIO,

Middleburg Hts - Dolfuss Root & Co. . . . . . . . . . . . . . . . . (440)816-1660

Powell - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . . . (614)781-0725

Vandalia - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . .(937)898-9610

Westerville - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . (614)523-1990

OREGON,

Lake Oswego - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . . (503)670-0557

UTAH,

Murray - Front Range Marketing . . . . . . . . . . . . . . . . . . . . (801)288-2500

VIRGINIA,

Glen Burnie - Coherent Solution, Inc. . . . . . . . . . . . . . . . . (410)761-2255

WASHINGTON,

Kirkland - I Squared,Inc. . . . . . . . . . . . . . . . . . . . . . . . . . .(425)822-9220

WISCONSIN,

Pewaukee - Industrial Representatives . . . . . . . . . . . . . . . . ( 2 6 2)574-9393

Representatives in Latin America

ARGENTINA,

Capital Federal Argentina/WW Rep. . . . . . . . . . . . . . . . . . . .54-11)4373-0655

CHILE,

Santiago - LatinRep/WWRep. . . . . . . . . . . . . . . . . . . . . . . . . .(+562)264-0993

COLUMBIA,

Bogota - Dimser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(571)410-4182

MEXICO,

Guadalajara - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . ( 5 23)817-3900

Mexico City - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . ( 5 25)752-2727

Monterrey - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . .(528)369-6828

PUERTO RICO,

Boqueron - Infitronics. . . . . . . . . . . . . . . . . . . . . . . . . . . .(787)851-6000

Sales Offices and Representatives