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Technical Support Line:
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DSNEXP-ABL-RM Rev 8.0.2
ABEL Design Manual
ABEL Design Manual 2
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Generic Array Logic, ISP, ispANALYZER, ispATE, ispCODE, ispDCD,
ispDOWNLOAD, ispDS, ispDS+, ispEXPERT, ispGDS, ispGDX, ispHDL, ispJTAG,
ispSmartFlow, ispStarter, ispSTREAM, ispSVF, ispTA, ispTEST, ispTURBO,
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March 2003
ABEL Design Manual 3
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ABEL Design Manual 4
Table of Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
What is in this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Where to Look for Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 1 ABEL-HDL Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Programmable Design in ispDesignExpert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
What is Programmable Designing? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
What is ABEL-HDL?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Overview of Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Projects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Project Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Design Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Design Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Device Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2 ABEL-HDL Hierarchical Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Why Use Hierarchical Design? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Approaches to Hierarchical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Creating a new Hierarchical Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Top-down Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bottom-up Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Inside-out (Mixed) Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Specifying a Lower-level Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 3 Compiling ABEL-HDL Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Overview of ABEL-HDL Compiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Design Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Creating a Design Using ABEL-HDL Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Design Compliation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Keeping Track of Process: Auto-update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Compiling an ABEL-HDL Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Using Properties and Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Design Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ABEL Design Manual 5
Chapter 4 ABEL-HDL Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Overview of ABEL-HDL Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Hierarchy in ABEL-HDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Instantiating a Lower-level Module in an ABEL-HDL Source. . . . . . . . . . . . . . . . . . . . . . . 39
Identifying I/O Ports in the Lower-level Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Declaring Lower-level Modules in the Top-level Source. . . . . . . . . . . . . . . . . . . . . . . . 40
Instantiating Lower-level Modules in Top-level Source. . . . . . . . . . . . . . . . . . . . . . . . . 40
Hierarchy and Retargeting and Fitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Redundant Nodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Merging Feedbacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Post-linked Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Hierarchical Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Prevent Node Collapsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Node Collapsing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Selective Collapsing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Pin-to-pin Language Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Device-independence vs. Architecture-independence. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Signal Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Signal Dot Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Pin-to-pin vs. Detailed Descriptions for Registered Designs . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Using := for Pin-to-pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Resolving Ambiguities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Detailed Circuit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Detailed Descriptions: Designing for Macrocells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Examples of Pin-to-pin and Detailed Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Pin-to-pin Module Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Detailed Module Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Detailed Module with Inverted Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
When to Use Detailed Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Using := for Alternative Flip-flop Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Using Active-low Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Polarity Control with Istype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Using Istype ‘neg’, ‘pos’, and ‘dc’ to Control Equation and Device Polarity . . . . . . . . . 53
Using ‘invert’ and ‘buffer’ to Control Programmable Inversion . . . . . . . . . . . . . . . . . . . 54
Flip-flop Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Feedback Considerations — Dot Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Dot Extensions and Architecture-Independence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Dot Extensions and Detail Design Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Using Don’t Care Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Exclusive OR Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Optimizing XOR Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Using XOR Operators in Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Using Implied XORs in Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Using XORs for Flip-flop Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
JK Flip-Flop Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
ABEL Design Manual 6
State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Use Identifiers Rather Than Numbers for States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Powerup Register States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Unsatisfied Transition Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
D-Type Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Other Flip-flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Precautions for Using Don’t Care Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Number Adjacent States for One-bit Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Use State Register Outputs to Identify States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
State Register Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Using Symbolic State Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Symbolic Reset Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Symbolic Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Using Complement Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ABEL-HDL and Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Basic Syntax - Simple Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Influence of Signal polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Using .X. in Truth tables conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Using .X. on the right side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Special case: Empty ON-set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Registered Logic in Truth tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ABEL Design Manual 7
Preface
This manual provides information on ABEL-HDL design sources, hierarchical
structure, compiling, and design considerations. It is assumed that you have a basic
understanding of ABEL-HDL design.
What is in this Manual
ABEL Design Manual 8
What is in this Manual
This manual contains the following information:
■Introduction to ABEL-HDL design
■Hierarchical design in ABEL-HDL
■ABEL-HDL compiling
■ABEL-HDL design considerations
Where to Look for Information
Chapter 1, ABEL-HDL Overview – Provides an overview of ABEL-HDL designs.
Chapter 2, ABEL-HDL Hierarchical Designs – Discusses the hierarchical structure
in ABEL-HDL designs.
Chapter 3, Compiling ABEL-HDL Designs – Provides information on the compiling
of ABEL-HDL designs.
Chapter 4, ABEL-HDL Design Considerations – Discusses the design
considerations in ABEL-HDL designs.
Documentation Conventions
ABEL Design Manual 9
Documentation Conventions
This user manual follows the typographic conventions listed here:
Convention Definition and Usage
Italics
Italicized text represents variable input. For example:
design
.1
This means you must replace
design
with the file name you used for all the files
relevant to your design.
Valuable information may be italicized for emphasis. Book titles also appear in
italics.
The beginning of a procedure appears in italics. For example:
To run the functional simulation:
Bold Valuable information may be boldfaced for emphasis. Commands are shown in
boldface. For example:
SelectFile⇒ Open from the Waveform Viewer.
Courier
Font Monospaced (Courier) font indicates file and directory names and text that the
system displays. For example:
TheC:\isptools\ispsys\config subdirectory contains...
Bold
Courier Bold Courier font indicates text you type in response to system prompts. For
example: SET YBUS [Y0..Y6];
|...| Verticalbarsindicateoptionsthataremutuallyexclusive;youcanselectonlyone.
For example:
INPUT|OUTPUT|BIDI
“Quotes” Titles of chapters or sections in chapters in this manual are shown in quotation
marks. For example: See Chapter 1, “Introduction.”
✍
NOTE
Indicates a special note.
▲
CAUTION
Indicates a situation that could cause loss of data or other problems.
❖
TIP
Indicates a special hint that makes using the software easier.
⇒ Indicates a menu option leading to a submenu option. For example:
File⇒ New
Related Documentation
ABEL Design Manual 10
Related Documentation
In addition to this manual, you might find the following reference material helpful:
■
ispDesignExpert User Manual
■
ispDesignExpert Tutorial
■
ABEL-HDL Reference Manual
■
Schematic Entry User Manual
■
Design Verification Tools User Manual
■
ispLSI Macro Library Reference Manual
■
ispLSI 5K/8K Macro Library Supplement
■
ISP Daisy Chain Download User Manual
■
ispEXPERT Compiler User Manual
■
VHDL and Verilog Simulation User Manual
These books provide technical specifications for the LSC device families and give
helpful information on device use and design development.
ABEL Design Manual 11
Chapter 1
ABEL-HDL Overvie w
This chapter covers the following topics:
■Programmable Design in ispDesignExpert
■Overview of Design
Programmable Design in ispDesignExpert
ABEL Design Manual 12
Programmable Design in ispDesignExpert
What is Programmable Designing?
Programmable designing is creating a design that can be implemented into a
programmable device. PLDs (Programmable Logic Devices) and CPLDs (Complex
PLDs) are a few examples of programmable devices.
Figure1-1 shows an example Design. This design has lower-level ABEL-HDL files
(not shown).
Figure 1-1. Example of a Top-level ABEL-HDL source for a Design
MODULE twocnt
TITLE 'two counters having a race'
"DemonstratesabilitytousemultiplelevelsofABEL-HDLHierarchy,
"andtocollapselower-levelmodulenodesintoupperlevelmodules.
"Forexample,eachcounterhasfourREGISTERnodes,andthismodule
"has four COMBINATORIAL pins. The lower-level registers are
“correctly flattened into the top-level combinatorial outputs. No
“dotextensionsareused,allowingthesystemtodeterminethebest
“feedbackpathtouse.Thisdesignusestheadvancedfitproperties
“REMOVE REDUNDANT NODES and MERGE EQUIVALENT FEEDBACK NODES.
"Constants
c,x = .c.,.x.;
"Inputs clk, en1, en2, rst pin ;
"Outputs a3, a2, a1, a0, b3, b2, b1, b0 pin ;
ov1, ov2 pin istype
'reg,buffer';
"Submodule declarations
hiercnt interface (clk,rst,en -> q3, q2, q1, q0);
"Submodule instances
cnt1 functional_block hiercnt;
cnt2 functional_block hiercnt;
Programmable Design in ispDesignExpert
ABEL Design Manual 13
Figure 1-1. Example of a Top-level ABEL-HDL source for an Design (Continued)
Equations cnt1.clk = clk;
cnt2.clk = clk;
cnt1.rst = rst;
cnt2.rst = rst;
cnt1.en = en1;
cnt2.en = en2;
"Each counter may be enabled independent of the other. This module
may be used as a Sub-module for a higher-level design, as these
counters may be cascaded by feeding the ovoutputs to the en inputs
of the next stage.
ov1.clk = clk;
ov2.clk = clk;
ov1 := a3 & a2 & a1 & !a0 & en1; "look-ahead carry -
overflow ov2 := b3 & b2 & b1 & !b0 & en2; "indicator
a3 = cnt1.q3; a2 = cnt1.q2; a1 = cnt1.q1; a0 =
cnt1.q0; b3 = cnt2.q3; b2 = cnt2.q2; b1 = cnt2.q1; b0 =
cnt2.q0;
test_vectors
([clk,rst,en1,en2] -> [a3,a2,a1,a0,b3,b2,b1,b0,ov1,ov2])
[ 0 , 0, 0 , 0 ] -> [ x, x, x, x, x, x, x, x, x, x ];
[ c , 1, 0 , 0 ] -> [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ];
[ c , 0, 1 , 0 ] -> [ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 ];
[ c , 0, 1 , 0 ] -> [ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 ];
[ c , 0, 1 , 0 ] -> [ 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 ];
[ c , 0, 0 , 1 ] -> [ 0, 0, 1, 1, 0, 0, 0, 1, 0, 0 ];
[ c , 0, 0 , 1 ] -> [ 0, 0, 1, 1, 0, 0, 1, 0, 0, 0 ];
END
Programmable Design in ispDesignExpert
ABEL Design Manual 14
What is ABEL-HDL?
ABEL-HDL is a hierarchical logic description language. ABEL-HDL design
descriptions are contained in an ASCII text file in the ABEL Hardware Description
Language (ABEL-HDL). For example, the following ABEL-HDL code describes a
one-bit counter block:
MODULE obcb
TITLE 'One Bit Counter Block'
"Inputs
clk, rst, ci pin ;
"Outputs
co pin istype 'com';
q pin istype 'reg';
Equations
q.clk = clk;
q := !q.fb & ci & !rst "toggle if carry in and not reset
# q.fb & !ci & !rst "hold if not carry in and not reset
# 0 & rst; "go to 0 if reset
co = q.fb & ci; "carry out is carry in and q = 1
END
For detailed information about the ABEL-HDL language, refer to the
ABEL-HDL
Reference Manual
and the online help of ispDesignExpert. An online version of the
ABEL-HDL Reference Manual
is provided in the ispDesignExpert CD (accessible by
selecting Help ⇒Manuals from the ispDesignExpert Project Navigator).
Overview of Design
ABEL Design Manual 15
Overview of Design
With ispDesignExpert, you can create and test designs that will be physically
implemented into Programmable devices. ispDesignExpert uses the Project
Navigator interface (Figure 1-2) as the front-end to all the design tools which creates
an integrated design environment that links together design, simulation, and
place-and-route tools.
Figure 1-2. ispDesignExpert Project Navigator
ProjectsIn ispDesignExpert, a single design is represented by a single project that is created
and modified using the Project Navigator. The project contains all the logical
descriptions for the design. In addition, the project can contain documentation files,
and test files.
A project represents one design, but you have the option of targeting your design to a
specific device. When you switch the target device, the processes and design flow in
the Project Navigator changes to one that is appropriate for the new target device.
The Sources in Project Window (Sources window)
shows all the design files associated with a project. The Processes for Current Source Window
(Processes window)
Overview of Design
ABEL Design Manual 16
Project Sources
In ispDesignExpert, a project (design) consists of one or more source files.
Each type of source is identified by an icon and name in the Sources in Project
window. The Sources in Project window is the large scrollable window on the left side
of the Project Navigator display. The Sources in Project window lists all of the sources
that are part of the project design.
In addition to the sources that describe the function of the design, every project
contains at least two special types of sources: the project notebook and the device.
Project Notebook – The project notebook is where you enter the title and name of the
project. You can also use the project notebook to keep track of external files (such as
document files) that are related to your project.
Device – The device is a source that includes information about the currently selected
device.
The supported sources are:
■ABEL-HDL module (.abl)
■schematic module(.sch)
■VHDL module (.vhd)
■Verilog HDL module (.v)
■test vector file (.abv)
■graphic waveform stimulus (.wdl)
■VHDL test bench (.vhd)
■Verilog test fixture (.tf)
Figure 1-3 shows the sources as they appear in the Project Navigator. The top-level
ABEL-HDL file RM12PS6K contains INTERFACE statements that instantiate (links to)
the lower-level ABEL-HDL files PSSR8X16 and RAM12.
Figure 1-3. Sources in a Design Project
Project Title
Targeted Device
ABEL-HDL Test Vectors
Lower-level ABEL-HDL Files
Top-level ABEL-HDL File
Overview of Design
ABEL Design Manual 17
Design Hierarchy
When designs can be broken into multiple levels, this is called hierarchical designing.
ispDesignExpert supports full hierarchical design, which permits you to create a
design that is divided into multiple levels, either to clarify its function or permit the
easy reuse of functional blocks. For instance, a large complex design does not have
to be created as a single module. By using hierarchical designing, each component
or piece of a complex design could be created as a separate module. Figure 1-3
shows a two-level hierarchy.
For more information on hierarchical designing, refer to Chapter 2, “ABEL-HDL
Hierarchical Designs”.
Design Compilation
After design entry, you can compile your design using the ispEXPERT Compiler. The
compiler first verifies designs for correct syntax, then optimizes and parittions
designs, and fits logic and performs place-and-route to map the logic to specific
devices, it finally generates a JEDEC fusemap file used to program the device and a
netlist file for post-route simulation.
The compiler gathers all compilation results and writes this information to the
ispEXPERT Compiler report that can be read using Process ⇒View from the
Project Navigator.
If an error occurs, the compiler stops and issues the auto-make log file
(automake.log) in the Report Viewer. Using the log file information, you can
change your design and recompile it.
Design Simulation
In ispDesignExpert, functional and timing simulation is available using ABEL-HDL
Test Vector (.abv) files or Waveform Description Language (.wdl) files. The
functional and timing simulator and Waveform Viewer enable you to verify your design
before implementing it into a specific device. For more information on simulation, refer
to the
Design Verification Tools User Manual
.
Device Programming
After the compiler produces a fusemap of your finished design, the integrated ISP
Download System in ispDesignExpert enables you to download the JEDEC device
programming file to an ispLSI device using an ispDOWNLOAD cable. See the
ISP
Daisy Chain Download User Manual
for more details.
ABEL Design Manual 18
Chapter 2
ABEL-HDL Hierar chical Designs
ispDesignExpert supports full hierarchical design. Hierarchical structuring permits a
design to be broken into multiple levels, either to clarify its function or permit the easy
reuse of lower-level sources. For instance, a large complex design does not have to
be created as a single module. By using hierarchical design, each component or
piece of a complex design could be created as a separate module.
A design is hierarchical when it is broken up into modules. For example, you could
create a top-level ABEL-HDL describing a design. In the ABEL-HDL file, you could
interface to lower-level modules that describe pieces of the design.
The module represented by the ABEL-HDL interface is said to be at one level below
the ABEL-HDL file in which the INTERFACE statement appears. Regardless of how
you refer to the levels, any design with more than one level is called a hierarchical
design. In ispDesignExpert, there is no limit to the number of hierarchical levels a
design can contain.
This chapter covers the following topics:
■Why Use Hierarchical Design?
■Approaches to Hierarchical Design
■Specifying a Lower-level Module in an ABEL-HDL Module
Why Use Hierarchical Design?
ABEL Design Manual 19
Why Use Hierarchical Design?
The primary advantage of hierarchical design is that it encourages modularity. For
instance, a careful choice of the circuitry you select to be a module will give you a
module that can be reused.
Another advantage of hierarchical design is the way it lets you organize your design
into useful levels of abstraction and detail.
Approaches to Hierarchical Design
Hierarchical designs consists of ONE top-level. The lower-level modules can be of
any supported source (ABEL-HDL sources) and are represented in the top-level
module by a place-holder. You can create the top-level module first or create it after
creating the lower-level modules. Figure 2-1 illustrates a two-level hierarchical
project.
Figure 2-1. Example of a Hierarchical Project in the Project Navigator
Creating a new Hierarchical Design
Hierarchical entry is a convenient way to enter a large design one piece at a time. It is
also a way of organizing and structuring your design and the design process. The
choice of the appropriate methodology can speed the design process and reduce the
chance of design or implementation errors.
There are three basic approaches to creating a multi-module hierarchical design:
■Top-down
■Bottom-up
■Inside-out (mixed)
Regardless of the approach you choose, you start from those parts of the design that
are clearly defined and move up or down to those parts of the design that need
additional definition.
The following sections explain the philosophy and techniques of each approach.
Project Title
Lower-level ABEL-HDL Sources
Top-level ABEL-HDL Source
Specifying a Lower-level Module
ABEL Design Manual 20
Top-down Design
In top-down design, you do not have to know all the details of your project when you
start. You can begin at the top, with a general description of the circuit’s functionality,
then break the design into modules with the appropriate functions. This approach is
called “stepwise refinement” – you move in order from a general description to
modularized functions and to the specific circuits that perform those functions.
In a top-down design, the uppermost schematic usually consists of nothing but Block
symbols representing modules (plus any needed power, clocking, or support
circuitry). These modules are repeatedly broken down into simpler modules (or the
actual circuitry) until the entire design is complete.
Bottom-up Design
In bottom-up design you start with the simplest modules, then combine them in
schematics at increasingly higher levels. Bottom-up design is ideal for projects in
which the top-level behavior cannot be defined until the low-level behavior is
established.
Inside-out (Mixed) Design
Inside-out design is a hybrid of top-down and bottom-up design, combining the
advantages of both. You start wherever you want in the project, building up and down
as required.
ispDesignExpert fully supports the mixed approach to design. This means that you
can work bottom-up on those parts of the project that must be defined in hardware
first, and top-down on those parts with clear functional definitions.
Specifying a Lower-level Module
The following steps outline how to specify a lower-level module in a design module.
1. In a Text Editor, open your ABEL-HDL file (File ⇒Open) or create a new
ABEL-HDL file (File ⇒New).
2. In the ABEL-HDL file, use the INTERFACE and FUNCTIONAL_BLOCK keywords
to instantiate lower-level files.
❖
TIP
You can also use the INTERFACE keyword in lower-level files
to link to upper-level ABEL-HDL modules (not upper-level
schematics).
You can place multiple instances of the same interface in the
same design by using the FUNCTIONAL_BLOCK statement.
Refer to the
ABEL-HDL Reference Manual
for more
information.
Specifying a Lower-level Module
ABEL Design Manual 21
3. The interface must have same names as the pin names (ABEL-HDL) in the
lower-level module.
Figure 2-2, Figure 2-3 and Figure 2-4 show one upper-level ABEL-HDL module
and different ways to implement the lower-level modules:
Figure 2-2. Top-level ABEL-HDL Module for NAND1
Figure 2-3. Lower-level Schematic for AND1 Interface
MODULE nand1
TITLE 'Hierarchical nand gate -
Instantiates an and gate and a not gate.'
I1, I2, O1 pin;
" The following code defines the interfaces (components)
" and1 and not1. And1 corresponds to the lower-
" level module AND1.vhd, AND1.ABL, or AND1.SCH.
" For component AND1, the IN1, IN2, and OUT1 interface names
" correspond to IN1, IN2, and OUT1 in the lower-level module.
and1 INTERFACE(IN1, IN2 -> OUT1);
not1 INTERFACE(IN1 -> OUT1);
" The following code defines the instances for the interfaces
" using the functional_block statement. For the and1 interface,
" there is one instance named my_and.
my_and functional_block and1;
my_not functional_block not1;
EQUATIONS
my_and.IN1 = I1;
my_and.IN2 = I2;
my_not.IN1 = andinst.OUT1;
O1 = my_not.OUT1;
END
Specifying a Lower-level Module
ABEL Design Manual 22
The name of the lower-level schematic must match the Block Name (schematic), or
the interface name (ABEL-HDL) in the upper-level module. This associates the
lowe-level module with the symbol representing it. The schematic (Figure 2-3) must
be named AND.sch.
The nets in the lower-level schematic correspond to the pin names (schematics), or
pine names (ABEL-HDL) in the upper-level module.
Figure 2-4. Lower-level ABEL-HDL Module for AND1 Interface
❖
TIP
If you are in a lower-level schematic, you can click the Use
Data From This Block button in the New Block Symbol dialog
box (Add ⇒New Block Symbol) to automatically create a
functional block symbol for the current schematic.
MODULE and1
TITLE 'and1 gate -
Instantiated by nand1 - Simple hierarchy example'
" The pins must match the Symbol pins (schematic),
" or interface names (ABEL-HDL) in the upper-level module.
IN1, IN2, OUT1 pin;
EQUATIONS
OUT1 = IN1 & IN2;
TEST_VECTORS
([ IN1, IN2] -> [OUT1])
[ 0, 0] -> [ 0];
[ 0, 1] -> [ 0];
[ 1, 0] -> [ 0];
[ 1, 1] -> [ 1];
END
❖
TIP
It is best to create the lowest-level sources first and then
import or create the higher-level sources.
ABEL Design Manual 23
Chapter 3
Compiling ABEL-HDL Designs
This chapter provides information on what the ispEXPERT Compiler functions during
compiling ABEL-HDL designs. It covers the following topics:
■Design Entry
■Design Compilation
■Design Simulation
Overview of ABEL-HDL Compiling
ABEL Design Manual 24
Overview of ABEL-HDL Compiling
Design Entry
In ispDesignExpert, when you create an ABEL-HDL module and import that module
into a design, this is called design entry. Design entry for ABEL-HDL modules is
primarily a function of the Project Navigator and a Text Editor (used to enter the
ABEL-HDL code). The following sections use a sample to describe how to enter the
design in a project.
Creating a Design Using ABEL-HDL Sources
Follow the steps to describe the design using ABEL-HDL.
To start a new project and set up a new directory for this tutorial:
1. Start ispDesignExpert. The Project Navigator window appears.
2. Select File ⇒New Project. The Create New Project dialog box (Figure 3-1)
appears.
Figure 3-1. Create New Project Dialog Box
3. Select Schematic/ABEL in the Project Type field. This specifies the design source
in ispDesignExpert.
4. Navigate to a directory where you want to save your project files, enter a project
name and_ff2.syn in the Project Name field.
5. Click Save to exit the Create New Project dialog box. The Project Navigator
displays the new project with the defalut device ispLSI5384E-125LB388.
Overview of ABEL-HDL Compiling
ABEL Design Manual 25
To change the name of the project:
1. Double-click on the project notebook icon or project name Untitled that appears at
the top of the Sources in Project window. The Project Properties dialog box
(Figure 3-2) appears.
Figure 3-2. Project Properties Dialog Box
2. Enter a descriptive title AND gate with a flip-flop in the Title field.
3. Click OK to save the change.
4. Select File ⇒Save from the Project Navigator to save the changes to your new
project.
To enter the ABEL-HDL description:
1. Select Source ⇒New to create a new design source. The New Source dialog
box (Figure 3-3) appears.
Figure 3-3. New Source Dialog Box
2. Select ABEL-HDL Module in the New field.
3. Click OK to close the dialog box. The Text Editor loads and the New ABEL-HDL
dialog box (Figure 3-4) appears prompting you for a module name, file name, and
title.
Overview of ABEL-HDL Compiling
ABEL Design Manual 26
Figure 3-4. New ABEL-HDL Source Dialog Box
4. In the Module Name field, enter and_ff2.
5. In the File Name field, enter and_ff2.abl (the file extension can be omitted).
6. If you like, enter a descriptive title AND gate with a flip-flop in the Title
text box.
7. When you have finished entering the information, click the OK button. You now
have a template ABEL-HDL source file as shown in Figure 3-5.
✍
NOTE
The module name and file name should have the same base
name as demonstrated above. (The base name is the name
without the 3 character extension.) If the module and file
names are different, some automatic functions in the Project
Navigator might fail to run properly.
Overview of ABEL-HDL Compiling
ABEL Design Manual 27
Figure 3-5. Template ABEL-HDL Source File
For detailed syntax on ABEL-HDL language, refer to the
ABEL-HDL Reference
Manual
.
To enter the logic description:
8. Add declarations for the three inputs (two AND gate inputs and the clock) and the
output by entering the following statements in the ABEL-HDL source file. If a
TITLE statement exists in the template file, enter these statements after the TITLE
statement:
input_1, input_2, Clk pin;
output_q pin istype 'reg';
These two statements declare four signals (input_1, input_2, Clk, and output_q).
9. To describe the actual behavior of this design, enter two equations in the following
manner:
Equations
output_q := input_1 & input_2;
output_q.clk = Clk;
These two equations define the data to be loaded on the registered output, and
define the clocking function for the output.
✍
NOTE
ABEL-HDL does not have an explicit declaration for inputs and
outputs; whether a given signal is an input or an output
depends on how it is used in the design description that
follows. The signal output_q is declared to be type 'reg’,
which implies that it is a registered output pin. The actual
behavior of output_q, however, is specified using one or
more equations.
Overview of ABEL-HDL Compiling
ABEL Design Manual 28
Specifying Test Vectors
The method for testing ABEL-HDL designs is to use test vectors. Test vectors are
sets of input stimulus values and corresponding expected outputs that can be used
with the functional and timing simulator. Test vectors can be specified in two ways.
They can be specified in the ABEL-HDL source, or they can be specified in an
external Test Vector file (.abv). When you specify the test vectors in the ABEL-HDL
source, the system will create a dummy ABV file (
design
-vectors) that points to
the ABEL-HDL source containing the vectors.
As the test vectors in this sample is very short, we just add them to the ABEL-HDL
source file.
To add the test vectors to the ABEL-HDL source file:
10.Type the following test vectors before the END statement in the and_ff2.abl file.
Test_vectors
([Clk, input_1 , input_2] -> output_q)
[ 0 , 0 , 0 ] -> 0;
[.C., 0 , 0 ] -> 0;
[.C., 0 , 1 ] -> 0;
[.C., 1 , 1 ] -> 1;
Figure 3-6 shows the complete ABEL-HDL source file.
Figure 3-6. Sample ABEL-HDL Source File and_ff2.abl
11.Select File ⇒Save from the Text Editor to save the ABEL-HDL source file.
12.Select File ⇒Exit to exit the Text Editor.
Overview of ABEL-HDL Compiling
ABEL Design Manual 29
After creating the ABEL-HDL source file, the Project Navigator updates the Sources
window to include the new ABEL-HDL source (notice the ABEL-HDL source icon).
The Project Navigator also updates the Processes window to reflect the steps
necessary to process this source file.
Design Compliation
In general, compiling involves every process after Design Entry that prepares your
design for simulation and implementation. These processes include compiling and
optimizing steps which can be done at the level of a single module or for the entire
design.
However, which processes are available for your design depends entirely on which
device architecture you want to implement your design.
This chapter discusses some of the general considerations and processes used in
ABEL-HDL compiling. For more information about design considerations, refer to
Chapter 4, “ABEL-HDL Design Considerations.”
Keeping Track of Process: Auto-update
Figure 3-7 shows the Project Naviagor window for the and_ff2 ABEL-HDL module.
Figure 3-7. Project Naviagtor Window with and_ff2.syn Loaded
Overview of ABEL-HDL Compiling
ABEL Design Manual 30
There are more processes required for an ABEL-HDL source file than for a
schematic, because the ABEL-HDL source file requires compilation and optimization
before you can run a simulation. And the Project Navigator knows what processes
are required to generate a simulation file from an ABEL-HDL source, you can
double-click on the end process you want. The auto-update feature automatically
runs any processes required to complete the process you request.
Device-related processes, such as mapping the selected ABEL-HDL source file to a
JEDEC file, will be available in the Processes for Current Source window after you
select a device for the design.
Compiling an ABEL-HDL Source File
The Project Navigator’s auto-updating reprocesses sources when they are needed to
perform the process you request. You do not need to worry about when to recompile
ABEL-HDL source files.
However, you can compile an individual source file by highlighting the file in the
Sources window and double-clicking on Compile Logic in the Processes window.
Alternatively, you can double-click on a report in the Processes window and compile
automatically.
To compile an ABEL-HDL file and view the report:
1. Highlight a ABEL-HDL source file (and_ff2.abl) in the Sources window.
2. Double-click Compiled Equations in the Processes window.
The source file is compiled and the resulting compiled equations are displayed in
the Report Viewer (Figure 3-8). If the ABEL-HDL file contains syntax errors, the
errors are displayed in a view window and an error indication appears in the
Processes window.
Overview of ABEL-HDL Compiling
ABEL Design Manual 31
Figure 3-8. Compiled Equations for and_ff2
In this example, the compiled equations are identical to the equations that you
entered in the ABEL-HDL source file. This is because the equations were simple
Boolean equations that did not require any advanced compiling in order to be
processed.
Using Properties and Strategies
For many processes (such as the compiling and optimizing steps shown above),
there are processing options you can specify. These options include compiler options
(such as custom arguments or processing changes) and optimization options (such
as node collapsing). You can use properties to specify these options.
Properties
The properties available at any given time depend on the following conditions:
■The selected type of source file in the Sources window (for example, ABEL-HDL).
■The selected process in the Processes window
Overview of ABEL-HDL Compiling
ABEL Design Manual 32
To see how properties are set:
1. Highlight the ABEL-HDL source file in the Sources window (by clicking on the
and_ff2 ABEL-HDL source).
2. Highlight (do not double-click) Compile Logic in the Processes window.
3. Click the Properties button below the Processes window.
The Properties dialog box (Figure 3-9) appears with a menu of properties. This
properties menu is specific to the Compile Logic process for an ABEL-HDL
source.
Figure 3-9. Properties Dialog Box
4. In the Properties dialog box, select the Generate Listing property.
5. Click on the arrow to the right of the text box (at the top of the properties menu),
and select the Expanded option from the list.
6. Click on the Close button to accept the setting and exit the Properties dialog box.
To get information on a property:
1. Click on a property in the Properties Dialog box.
2. Press the Help button.
Strategies
Another way to set options in your project is to use strategies. A strategy is a set of
properties (processing options) that you have specified for some or all of the sources
in your project. Strategies can be useful as your processing requirements change,
depending on factors such as size and speed tradeoffs in synthesis, or whether your
design is being processed for simulation or final implementation.
With strategies, you do not have to modify the properties for every source in the
design if you want to change the processing options. Strategies allow you to set up
properties once, then associate a strategy with a source to which you want to apply
the properties. You can create new strategies that reflect different properties for the
entire project, and then associate one or more custom strategies with the sources in
your project.
Overview of ABEL-HDL Compiling
ABEL Design Manual 33
To see how strategies work:
1. Select Source ⇒Strategy from the Project Navigator. The Define Strategies
dialog box (Figure 3-10) appears.
Figure 3-10. Define Strategies Dialog Box
2. Click the New button, the New Strategy dialog box (Figure 3-11) appears.
Figure 3-11. New Strategy Dialog Box
3. Enter a name for the strategy in the New strategy Name field.
4. Click the OK button. The new strategy appears in the Strategy drop-down list box
in the Define Strategies dialog box.
To associate a source with a new strategy:
1. Select a strategy in the Strategy field of the Define Stratigies dialog box.
2. Click the Associate button.
3. Highlight the ABEL-HDL source and_ff2 in the Source to Associate with
Strategy field.
4. Click the Associate with Strategy button.
The and_ff2 source appears in the Associated Sources list box (Figure 3-12).
Overview of ABEL-HDL Compiling
ABEL Design Manual 34
Figure 3-12. Expanded Define Strategies Dialog Box
Design Sim